12 lines
790 B
Plaintext
12 lines
790 B
Plaintext
<BaliSimProject version="1.3" path="." stage="1" language="1" name="tb_RelayConTop" simType="QuestaSim">
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<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.vo" type="VERILOG" langstandard="" include="none"/>
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<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
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<Source worklib="work" path="RelayConTop_tf.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
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<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf" type="VERILOG" langstandard="" include="none"/>
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<Sdf path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf"/>
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<SimLib value="pmi_work ovi_machxo2"/>
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<GlbInc value=""/>
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<Macro value=""/>
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<TopModule instance="/DUT" language="" name="tb_RelayConTop"/>
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</BaliSimProject>
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