293 lines
11 KiB
Systemverilog
293 lines
11 KiB
Systemverilog
//------------------------------------------------------------------------------
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//
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// Testbench: CPLD1 - SPI Register R/W (Simplified)
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// Project: NewCalBoard DIG
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// Tool: Lattice Diamond Verilog-2001 simulator
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// Purpose: Verify SPI register read/write using only i_sclk, i_cs, i_mosi, o_miso
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//
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// Protocol:
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// Write: [1][Addr:7b][Data:24b] = 32 bits
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// Read: [0][Addr:7b][Don'tCare:24b] -> MISO returns [8'h00][24-bit rdata]
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//
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`define SYS_CLK_PERIOD 20 // 50 MHz system clock
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`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock
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module tb_SPI_RegRW;
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// Clock & reset
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reg i_sys_clk;
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reg i_rst_n;
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// SPI interface - only 4 signals used in reality
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reg i_sclk;
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reg i_mosi;
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reg i_cs;
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wire o_miso;
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// Clock generation
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initial begin
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i_sys_clk = 0;
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forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
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end
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initial begin
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i_sclk = 0;
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forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
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end
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// DUT instantiation - only essential pins
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RelayConTop DUT (
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.i_sys_clk(i_sys_clk),
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.i_rst_n (i_rst_n),
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.i_sclk (i_sclk),
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.i_mosi (i_mosi),
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.i_cs (i_cs),
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.o_miso (o_miso)
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);
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//==========================================================================
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// SPI Helper Tasks - Mode 0 (CPOL=0, CPHA=0), MSB first, 32 bits
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//==========================================================================
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// Build 32-bit write frame: {1'b1, addr[6:0], data[23:0]}
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function [31:0] mk_write;
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input [6:0] addr;
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input [23:0] data;
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begin
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mk_write = {1'b1, addr, data};
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end
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endfunction
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// Build 32-bit read frame: {1'b0, addr[6:0], 24'b0}
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function [31:0] mk_read;
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input [6:0] addr;
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begin
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mk_read = {1'b0, addr, 24'b0};
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end
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endfunction
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// Drive a 32-bit word out through MOSI
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// SPI Mode 0: data prepared on falling edge, sampled on rising edge
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task spi_send;
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input [31:0] data;
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integer i;
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begin
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@(negedge i_sclk); // Wait for any negedge to enter
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i_cs = 1'b0;
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i_mosi = data[31]; // Drive first bit on SAME edge as CS
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for (i = 31; i >= 0; i = i - 1) begin
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@(posedge i_sclk); // DUT samples MOSI on rising edge
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if (i > 0) begin
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@(negedge i_sclk); // Next falling edge
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i_mosi = data[i - 1];// Setup next bit for next rising edge
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end
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end
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@(negedge i_sclk);
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i_cs = 1'b1;
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i_mosi = 1'b0;
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@(negedge i_sclk);
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end
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endtask
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// Send command, capture response on MISO
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// SPI Mode 0: data prepared on falling edge, sampled on rising edge
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// DUT shifts MISO out on falling edge → read MISO on falling edge
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task spi_read;
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input [31:0] cmd;
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output [31:0] rdata;
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integer i;
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begin
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@(negedge i_sclk); // Wait for any negedge to enter
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i_cs = 1'b0;
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i_mosi = cmd[31]; // Drive first bit on SAME edge as CS
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rdata = 32'b0;
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for (i = 31; i >= 0; i = i - 1) begin
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@(posedge i_sclk); // DUT samples MOSI on rising edge
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@(negedge i_sclk); // DUT shifts MISO out on falling edge
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#1; // clock-to-Q timing margin
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rdata[i] = o_miso; // Read shifted-out bit
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if (i > 0) begin
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i_mosi = cmd[i - 1]; // Setup next bit for next rising edge
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end
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end
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@(negedge i_sclk);
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i_cs = 1'b1;
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i_mosi = 1'b0;
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@(negedge i_sclk);
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end
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endtask
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// Send a write command
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task spi_write;
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input [31:0] data;
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begin
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spi_send(data);
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end
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endtask
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//==========================================================================
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// Main Test Sequence
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//==========================================================================
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initial begin
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// Initialize
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i_rst_n = 1'b0;
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i_cs = 1'b1;
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i_mosi = 1'b0;
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#(`SYS_CLK_PERIOD * 4);
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i_rst_n = 1'b1;
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#(`SYS_CLK_PERIOD * 10);
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$display("");
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$display("=============================================================");
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$display(" CPLD1 SPI Register R/W Testbench (Simplified)");
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$display(" System clock: %d MHz | SPI clock: %d MHz",
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1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
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$display("=============================================================");
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$display("");
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test_read_registers();
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test_write_registers();
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test_write_then_read();
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$display("");
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$display("=============================================================");
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$display(" *** ALL TESTS COMPLETED ***");
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$display("=============================================================");
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$display("");
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#(`SYS_CLK_PERIOD * 20);
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$finish;
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end
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//==========================================================================
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// Test 1: Read different registers
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//==========================================================================
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task test_read_registers;
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reg [31:0] rdata;
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begin
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$display("");
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$display("-------------------------------------------------------------");
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$display(" Test 1: Read Different Registers");
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$display("-------------------------------------------------------------");
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// Read IDENT register (ADDR 0) - must return 24'h200010
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$display(" 1a. Read IDENT register (ADDR 0)");
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spi_read(mk_read(7'd0), rdata);
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$display(" ADDR 0 (IDENT) = 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h200110 ? " [OK]" : " [FAIL]");
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// Read same register again (should be identical)
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$display(" 1b. Read IDENT register again");
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spi_read(mk_read(7'd0), rdata);
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$display(" ADDR 0 (IDENT) = 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h200110 ? " [OK]" : " [FAIL]");
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// Read ADDR 1 (STATE_REG)
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$display(" 1c. Read STATE register (ADDR 1)");
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spi_read(mk_read(7'd1), rdata);
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$display(" ADDR 1 (STATE) = 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h800000 ? " [OK]" : " [FAIL]");
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// Read ADDR 2 (Freq_Slot1)
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$display(" 1d. Read Freq_Slot1 register (ADDR 2)");
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spi_read(mk_read(7'd2), rdata);
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$display(" ADDR 2 (FreqSlot1) = 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'd0 ? " [OK]" : " [FAIL]");
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#(`SPI_CLK_PERIOD);
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end
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endtask
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//==========================================================================
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// Test 2: Write registers (verify via read-back)
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//==========================================================================
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task test_write_registers;
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reg [31:0] rdata;
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begin
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$display("");
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$display("-------------------------------------------------------------");
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$display(" Test 2: Write Registers (verify via read-back)");
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$display("-------------------------------------------------------------");
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// Write to ADDR 2, then read back
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$display(" 2a. Write 0x000005 to ADDR 2, read back");
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spi_write(mk_write(7'd2, 24'h000005));
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spi_read(mk_read(7'd2), rdata);
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$display(" Wrote 0x000005, read 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h000005 ? " [OK]" : " [FAIL]");
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// Write to ADDR 3, then read back
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$display(" 2b. Write 0x003001 to ADDR 3, read back");
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spi_write(mk_write(7'd3, 24'h003001));
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spi_read(mk_read(7'd3), rdata);
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$display(" Wrote 0x003001, read 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h003001 ? " [OK]" : " [FAIL]");
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// Write to ADDR 4, then read back
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$display(" 2c. Write 0xABCDEF to ADDR 4, read back");
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spi_write(mk_write(7'd4, 24'hABCDEF));
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spi_read(mk_read(7'd4), rdata);
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$display(" Wrote 0xABCDEF, read 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'hABCDEF ? " [OK]" : " [FAIL]");
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// Write 0 to ADDR 5, then read back
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$display(" 2d. Write 0x000000 to ADDR 5, read back");
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spi_write(mk_write(7'd5, 24'h000000));
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spi_read(mk_read(7'd5), rdata);
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$display(" Wrote 0x000000, read 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h000000 ? " [OK]" : " [FAIL]");
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#(`SPI_CLK_PERIOD);
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end
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endtask
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//==========================================================================
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// Test 3: Write then Read / Read then Write (interleaved)
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//==========================================================================
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task test_write_then_read;
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reg [31:0] rdata;
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begin
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$display("");
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$display("-------------------------------------------------------------");
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$display(" Test 3: Write-Then-Read / Read-Then-Write (Interleaved)");
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$display("-------------------------------------------------------------");
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// 3a. Write, delay, then read (verify persistence)
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$display(" 3a. Write 0x112233 to ADDR 6, read after delay");
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spi_write(mk_write(7'd6, 24'h112233));
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#(`SPI_CLK_PERIOD * 3);
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spi_read(mk_read(7'd6), rdata);
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$display(" Wrote 0x112233, read 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h112233 ? " [OK]" : " [FAIL]");
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// 3b. Read current value, then write new value, then read again
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$display(" 3b. Read ADDR 7, write 0x445566, read again");
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spi_read(mk_read(7'd7), rdata);
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$display(" Before write: ADDR 7 = 0x%06h", rdata[23:0]);
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spi_write(mk_write(7'd7, 24'h445566));
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spi_read(mk_read(7'd7), rdata);
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$display(" After write: ADDR 7 = 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h445566 ? " [OK]" : " [FAIL]");
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// 3c. Rapid successive writes to multiple registers
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$display(" 3c. Rapid writes to ADDR 8, 9, then read-back");
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spi_write(mk_write(7'd8, 24'h8899AA));
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spi_write(mk_write(7'd9, 24'hBBCCDD));
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spi_read(mk_read(7'd8), rdata);
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$display(" ADDR 8 = 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'h8899AA ? " [OK]" : " [FAIL]");
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spi_read(mk_read(7'd9), rdata);
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$display(" ADDR 9 = 0x%06h %s", rdata[23:0],
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rdata[23:0] === 24'hBBCCDD ? " [OK]" : " [FAIL]");
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#(`SPI_CLK_PERIOD);
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end
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endtask
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endmodule
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