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base: yuysh/NewInstrCalBoard_CPLD:v1.1.2
Branches Tags
yuysh/NewInstrCalBoard_CPLD:master
yuysh/NewInstrCalBoard_CPLD:v1.1.2 yuysh/NewInstrCalBoard_CPLD:v1.1.0
..
compare: yuysh/NewInstrCalBoard_CPLD:master
Branches Tags
yuysh/NewInstrCalBoard_CPLD:master
yuysh/NewInstrCalBoard_CPLD:v1.1.2 yuysh/NewInstrCalBoard_CPLD:v1.1.0
4 Commits
v1.1.2 .. master
Author SHA1 Message Date
yuysh 040f20075c Increased version code 2026-06-18 11:02:23 +08:00
yuysh 0d459342ae Add Support for RLoad Open 2026-06-18 10:50:39 +08:00
yuysh 2431906630 Fix: CPLD3: Fix PMU4 AD5522 Reset Pin defination 
Note: Add AD5522 Reset function to fix the unintended power-up state
 2026-06-16 16:50:40 +08:00
yuysh 8554c0aac3 Feat: CPLD3: Add AD5522 Reset 2026-06-16 16:20:53 +08:00
16 changed files with 55899 additions and 44960 deletions
Expand all files Collapse all files
CPLD1/CPLD1_Debug.svf
+1063 -14
View File
File diff suppressed because one or more lines are too long
CPLD1/CPLD_Con.v
+4 -4
View File
@@ -305,7 +305,7 @@ module CPLD_Con (
RC_LOFS <= 2'b10; RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18)) begin if (i_DC_Con1[21:17] > 18) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
@@ -347,7 +347,7 @@ module CPLD_Con (
RC_LOFS <= 2'b10; RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18)) begin if (i_DC_Con2[21:17] > 18) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
@@ -389,7 +389,7 @@ module CPLD_Con (
RC_LOFS <= 2'b10; RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18)) begin if (i_DC_Con3[21:17] > 18) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
@@ -431,7 +431,7 @@ module CPLD_Con (
RC_LOFS <= 2'b10; RC_LOFS <= 2'b10;
end end
//Sanity Check //Sanity Check
if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18)) begin if (i_DC_Con4[21:17] > 18) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
CPLD1/NewExtIns_CPLD1.ldf
+1 -1
View File
@@ -2,7 +2,7 @@
<BaliProject version="3.2" title="NewExtIns_CPLD1" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1"> <BaliProject version="3.2" title="NewExtIns_CPLD1" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/> <Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1"> <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop" top="RelayConTop"/> <Options top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog"> <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/> <Options top_module="RelayConTop"/>
</Source> </Source>
CPLD1/Reg_file.v
+1 -1
View File
@@ -35,7 +35,7 @@ module Reg_file (
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h200000 | 12'b0001_0001_0010, //CPLD1==1,version=1.1.2 IDENT = 24'h200000 | 12'b0001_0001_0011, //CPLD1==1,version=1.1.2
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
CPLD1/debug.rvl
+155 -75
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-06-16"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-06-18">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="698409536" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="698655953" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="1024"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="1024"/>
@@ -12,6 +12,159 @@
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Bus Name="CPLD_Con_1/RC_RLShifter1">
<Sig Type="SIG" Name="CPLD_Con_1/RC_RLShifter1:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/RC_RLShifter1:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/RC_RLShifter1:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/RC_RLShifter1:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/RC_RLShifter1:4"/>
</Bus>
<Bus Name="RC_RLSel">
<Sig Type="SIG" Name="RC_RLSel:0"/>
<Sig Type="SIG" Name="RC_RLSel:1"/>
<Sig Type="SIG" Name="RC_RLSel:2"/>
<Sig Type="SIG" Name="RC_RLSel:3"/>
<Sig Type="SIG" Name="RC_RLSel:4"/>
<Sig Type="SIG" Name="RC_RLSel:5"/>
<Sig Type="SIG" Name="RC_RLSel:6"/>
<Sig Type="SIG" Name="RC_RLSel:7"/>
<Sig Type="SIG" Name="RC_RLSel:8"/>
<Sig Type="SIG" Name="RC_RLSel:9"/>
<Sig Type="SIG" Name="RC_RLSel:10"/>
<Sig Type="SIG" Name="RC_RLSel:11"/>
<Sig Type="SIG" Name="RC_RLSel:12"/>
<Sig Type="SIG" Name="RC_RLSel:13"/>
<Sig Type="SIG" Name="RC_RLSel:14"/>
<Sig Type="SIG" Name="RC_RLSel:15"/>
<Sig Type="SIG" Name="RC_RLSel:16"/>
<Sig Type="SIG" Name="RC_RLSel:17"/>
</Bus>
<Bus Name="DC_Con1">
<Sig Type="SIG" Name="DC_Con1:0"/>
<Sig Type="SIG" Name="DC_Con1:1"/>
<Sig Type="SIG" Name="DC_Con1:2"/>
<Sig Type="SIG" Name="DC_Con1:3"/>
<Sig Type="SIG" Name="DC_Con1:4"/>
<Sig Type="SIG" Name="DC_Con1:5"/>
<Sig Type="SIG" Name="DC_Con1:6"/>
<Sig Type="SIG" Name="DC_Con1:7"/>
<Sig Type="SIG" Name="DC_Con1:8"/>
<Sig Type="SIG" Name="DC_Con1:9"/>
<Sig Type="SIG" Name="DC_Con1:10"/>
<Sig Type="SIG" Name="DC_Con1:11"/>
<Sig Type="SIG" Name="DC_Con1:12"/>
<Sig Type="SIG" Name="DC_Con1:13"/>
<Sig Type="SIG" Name="DC_Con1:14"/>
<Sig Type="SIG" Name="DC_Con1:15"/>
<Sig Type="SIG" Name="DC_Con1:16"/>
<Sig Type="SIG" Name="DC_Con1:17"/>
<Sig Type="SIG" Name="DC_Con1:18"/>
<Sig Type="SIG" Name="DC_Con1:19"/>
<Sig Type="SIG" Name="DC_Con1:20"/>
<Sig Type="SIG" Name="DC_Con1:21"/>
<Sig Type="SIG" Name="DC_Con1:22"/>
<Sig Type="SIG" Name="DC_Con1:23"/>
</Bus>
<Bus Name="DC_Con2">
<Sig Type="SIG" Name="DC_Con2:0"/>
<Sig Type="SIG" Name="DC_Con2:1"/>
<Sig Type="SIG" Name="DC_Con2:2"/>
<Sig Type="SIG" Name="DC_Con2:3"/>
<Sig Type="SIG" Name="DC_Con2:4"/>
<Sig Type="SIG" Name="DC_Con2:5"/>
<Sig Type="SIG" Name="DC_Con2:6"/>
<Sig Type="SIG" Name="DC_Con2:7"/>
<Sig Type="SIG" Name="DC_Con2:8"/>
<Sig Type="SIG" Name="DC_Con2:9"/>
<Sig Type="SIG" Name="DC_Con2:10"/>
<Sig Type="SIG" Name="DC_Con2:11"/>
<Sig Type="SIG" Name="DC_Con2:12"/>
<Sig Type="SIG" Name="DC_Con2:13"/>
<Sig Type="SIG" Name="DC_Con2:14"/>
<Sig Type="SIG" Name="DC_Con2:15"/>
<Sig Type="SIG" Name="DC_Con2:16"/>
<Sig Type="SIG" Name="DC_Con2:17"/>
<Sig Type="SIG" Name="DC_Con2:18"/>
<Sig Type="SIG" Name="DC_Con2:19"/>
<Sig Type="SIG" Name="DC_Con2:20"/>
<Sig Type="SIG" Name="DC_Con2:21"/>
<Sig Type="SIG" Name="DC_Con2:22"/>
<Sig Type="SIG" Name="DC_Con2:23"/>
</Bus>
<Bus Name="DC_Con3">
<Sig Type="SIG" Name="DC_Con3:0"/>
<Sig Type="SIG" Name="DC_Con3:1"/>
<Sig Type="SIG" Name="DC_Con3:2"/>
<Sig Type="SIG" Name="DC_Con3:3"/>
<Sig Type="SIG" Name="DC_Con3:4"/>
<Sig Type="SIG" Name="DC_Con3:5"/>
<Sig Type="SIG" Name="DC_Con3:6"/>
<Sig Type="SIG" Name="DC_Con3:7"/>
<Sig Type="SIG" Name="DC_Con3:8"/>
<Sig Type="SIG" Name="DC_Con3:9"/>
<Sig Type="SIG" Name="DC_Con3:10"/>
<Sig Type="SIG" Name="DC_Con3:11"/>
<Sig Type="SIG" Name="DC_Con3:12"/>
<Sig Type="SIG" Name="DC_Con3:13"/>
<Sig Type="SIG" Name="DC_Con3:14"/>
<Sig Type="SIG" Name="DC_Con3:15"/>
<Sig Type="SIG" Name="DC_Con3:16"/>
<Sig Type="SIG" Name="DC_Con3:17"/>
<Sig Type="SIG" Name="DC_Con3:18"/>
<Sig Type="SIG" Name="DC_Con3:19"/>
<Sig Type="SIG" Name="DC_Con3:20"/>
<Sig Type="SIG" Name="DC_Con3:21"/>
<Sig Type="SIG" Name="DC_Con3:22"/>
<Sig Type="SIG" Name="DC_Con3:23"/>
</Bus>
<Bus Name="DC_Con4">
<Sig Type="SIG" Name="DC_Con4:0"/>
<Sig Type="SIG" Name="DC_Con4:1"/>
<Sig Type="SIG" Name="DC_Con4:2"/>
<Sig Type="SIG" Name="DC_Con4:3"/>
<Sig Type="SIG" Name="DC_Con4:4"/>
<Sig Type="SIG" Name="DC_Con4:5"/>
<Sig Type="SIG" Name="DC_Con4:6"/>
<Sig Type="SIG" Name="DC_Con4:7"/>
<Sig Type="SIG" Name="DC_Con4:8"/>
<Sig Type="SIG" Name="DC_Con4:9"/>
<Sig Type="SIG" Name="DC_Con4:10"/>
<Sig Type="SIG" Name="DC_Con4:11"/>
<Sig Type="SIG" Name="DC_Con4:12"/>
<Sig Type="SIG" Name="DC_Con4:13"/>
<Sig Type="SIG" Name="DC_Con4:14"/>
<Sig Type="SIG" Name="DC_Con4:15"/>
<Sig Type="SIG" Name="DC_Con4:16"/>
<Sig Type="SIG" Name="DC_Con4:17"/>
<Sig Type="SIG" Name="DC_Con4:18"/>
<Sig Type="SIG" Name="DC_Con4:19"/>
<Sig Type="SIG" Name="DC_Con4:20"/>
<Sig Type="SIG" Name="DC_Con4:21"/>
<Sig Type="SIG" Name="DC_Con4:22"/>
<Sig Type="SIG" Name="DC_Con4:23"/>
</Bus>
<Bus Name="DMM_EN">
<Sig Type="SIG" Name="DMM_EN:0"/>
<Sig Type="SIG" Name="DMM_EN:1"/>
<Sig Type="SIG" Name="DMM_EN:2"/>
<Sig Type="SIG" Name="DMM_EN:3"/>
<Sig Type="SIG" Name="DMM_EN:4"/>
<Sig Type="SIG" Name="DMM_EN:5"/>
<Sig Type="SIG" Name="DMM_EN:6"/>
<Sig Type="SIG" Name="DMM_EN:7"/>
<Sig Type="SIG" Name="DMM_EN:8"/>
<Sig Type="SIG" Name="DMM_EN:9"/>
<Sig Type="SIG" Name="DMM_EN:10"/>
<Sig Type="SIG" Name="DMM_EN:11"/>
<Sig Type="SIG" Name="DMM_EN:12"/>
<Sig Type="SIG" Name="DMM_EN:13"/>
<Sig Type="SIG" Name="DMM_EN:14"/>
<Sig Type="SIG" Name="DMM_EN:15"/>
<Sig Type="SIG" Name="DMM_EN:16"/>
<Sig Type="SIG" Name="DMM_EN:17"/>
<Sig Type="SIG" Name="DMM_EN:18"/>
</Bus>
<Sig Type="SIG" Name="DPSFS_RC1"/>
<Bus Name="DPS_FS_1"> <Bus Name="DPS_FS_1">
<Sig Type="SIG" Name="DPS_FS_1:0"/> <Sig Type="SIG" Name="DPS_FS_1:0"/>
<Sig Type="SIG" Name="DPS_FS_1:1"/> <Sig Type="SIG" Name="DPS_FS_1:1"/>
@@ -98,79 +251,6 @@
<Sig Type="SIG" Name="FSMMC:4"/> <Sig Type="SIG" Name="FSMMC:4"/>
<Sig Type="SIG" Name="FSMMC:5"/> <Sig Type="SIG" Name="FSMMC:5"/>
</Bus> </Bus>
<Sig Type="SIG" Name="DPSFS_RC1"/>
<Bus Name="o_PMU_OC_1">
<Sig Type="SIG" Name="o_PMU_OC_1:0"/>
<Sig Type="SIG" Name="o_PMU_OC_1:1"/>
<Sig Type="SIG" Name="o_PMU_OC_1:2"/>
<Sig Type="SIG" Name="o_PMU_OC_1:3"/>
<Sig Type="SIG" Name="o_PMU_OC_1:4"/>
<Sig Type="SIG" Name="o_PMU_OC_1:5"/>
<Sig Type="SIG" Name="o_PMU_OC_1:6"/>
<Sig Type="SIG" Name="o_PMU_OC_1:7"/>
<Sig Type="SIG" Name="o_PMU_OC_1:8"/>
<Sig Type="SIG" Name="o_PMU_OC_1:9"/>
<Sig Type="SIG" Name="o_PMU_OC_1:10"/>
<Sig Type="SIG" Name="o_PMU_OC_1:11"/>
<Sig Type="SIG" Name="o_PMU_OC_1:12"/>
<Sig Type="SIG" Name="o_PMU_OC_1:13"/>
<Sig Type="SIG" Name="o_PMU_OC_1:14"/>
<Sig Type="SIG" Name="o_PMU_OC_1:15"/>
</Bus>
<Bus Name="o_PMU_OC_2">
<Sig Type="SIG" Name="o_PMU_OC_2:0"/>
<Sig Type="SIG" Name="o_PMU_OC_2:1"/>
<Sig Type="SIG" Name="o_PMU_OC_2:2"/>
<Sig Type="SIG" Name="o_PMU_OC_2:3"/>
<Sig Type="SIG" Name="o_PMU_OC_2:4"/>
<Sig Type="SIG" Name="o_PMU_OC_2:5"/>
<Sig Type="SIG" Name="o_PMU_OC_2:6"/>
<Sig Type="SIG" Name="o_PMU_OC_2:7"/>
<Sig Type="SIG" Name="o_PMU_OC_2:8"/>
<Sig Type="SIG" Name="o_PMU_OC_2:9"/>
<Sig Type="SIG" Name="o_PMU_OC_2:10"/>
<Sig Type="SIG" Name="o_PMU_OC_2:11"/>
<Sig Type="SIG" Name="o_PMU_OC_2:12"/>
<Sig Type="SIG" Name="o_PMU_OC_2:13"/>
<Sig Type="SIG" Name="o_PMU_OC_2:14"/>
<Sig Type="SIG" Name="o_PMU_OC_2:15"/>
</Bus>
<Bus Name="o_PMU_OC_3">
<Sig Type="SIG" Name="o_PMU_OC_3:0"/>
<Sig Type="SIG" Name="o_PMU_OC_3:1"/>
<Sig Type="SIG" Name="o_PMU_OC_3:2"/>
<Sig Type="SIG" Name="o_PMU_OC_3:3"/>
<Sig Type="SIG" Name="o_PMU_OC_3:4"/>
<Sig Type="SIG" Name="o_PMU_OC_3:5"/>
<Sig Type="SIG" Name="o_PMU_OC_3:6"/>
<Sig Type="SIG" Name="o_PMU_OC_3:7"/>
<Sig Type="SIG" Name="o_PMU_OC_3:8"/>
<Sig Type="SIG" Name="o_PMU_OC_3:9"/>
<Sig Type="SIG" Name="o_PMU_OC_3:10"/>
<Sig Type="SIG" Name="o_PMU_OC_3:11"/>
<Sig Type="SIG" Name="o_PMU_OC_3:12"/>
<Sig Type="SIG" Name="o_PMU_OC_3:13"/>
<Sig Type="SIG" Name="o_PMU_OC_3:14"/>
<Sig Type="SIG" Name="o_PMU_OC_3:15"/>
</Bus>
<Bus Name="o_PMU_OC_4">
<Sig Type="SIG" Name="o_PMU_OC_4:0"/>
<Sig Type="SIG" Name="o_PMU_OC_4:1"/>
<Sig Type="SIG" Name="o_PMU_OC_4:2"/>
<Sig Type="SIG" Name="o_PMU_OC_4:3"/>
<Sig Type="SIG" Name="o_PMU_OC_4:4"/>
<Sig Type="SIG" Name="o_PMU_OC_4:5"/>
<Sig Type="SIG" Name="o_PMU_OC_4:6"/>
<Sig Type="SIG" Name="o_PMU_OC_4:7"/>
<Sig Type="SIG" Name="o_PMU_OC_4:8"/>
<Sig Type="SIG" Name="o_PMU_OC_4:9"/>
<Sig Type="SIG" Name="o_PMU_OC_4:10"/>
<Sig Type="SIG" Name="o_PMU_OC_4:11"/>
<Sig Type="SIG" Name="o_PMU_OC_4:12"/>
<Sig Type="SIG" Name="o_PMU_OC_4:13"/>
<Sig Type="SIG" Name="o_PMU_OC_4:14"/>
<Sig Type="SIG" Name="o_PMU_OC_4:15"/>
</Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/> <TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/>
CPLD1/debug.rvs
+154 -74
View File
@@ -1,4 +1,4 @@
<Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-06-16"> <Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-06-18">
<Core Name="RelayConTop_LA0"> <Core Name="RelayConTop_LA0">
<Setting> <Setting>
<Capture SamplesPerTrig="1" NumTrigsCap=""/> <Capture SamplesPerTrig="1" NumTrigsCap=""/>
@@ -7,6 +7,159 @@
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Bus Name="CPLD_Con_1/RC_RLShifter1" Radix="0">
<Sig Name="CPLD_Con_1/RC_RLShifter1:0"/>
<Sig Name="CPLD_Con_1/RC_RLShifter1:1"/>
<Sig Name="CPLD_Con_1/RC_RLShifter1:2"/>
<Sig Name="CPLD_Con_1/RC_RLShifter1:3"/>
<Sig Name="CPLD_Con_1/RC_RLShifter1:4"/>
</Bus>
<Bus Name="RC_RLSel" Radix="0">
<Sig Name="RC_RLSel:0"/>
<Sig Name="RC_RLSel:1"/>
<Sig Name="RC_RLSel:2"/>
<Sig Name="RC_RLSel:3"/>
<Sig Name="RC_RLSel:4"/>
<Sig Name="RC_RLSel:5"/>
<Sig Name="RC_RLSel:6"/>
<Sig Name="RC_RLSel:7"/>
<Sig Name="RC_RLSel:8"/>
<Sig Name="RC_RLSel:9"/>
<Sig Name="RC_RLSel:10"/>
<Sig Name="RC_RLSel:11"/>
<Sig Name="RC_RLSel:12"/>
<Sig Name="RC_RLSel:13"/>
<Sig Name="RC_RLSel:14"/>
<Sig Name="RC_RLSel:15"/>
<Sig Name="RC_RLSel:16"/>
<Sig Name="RC_RLSel:17"/>
</Bus>
<Bus Name="DC_Con1" Radix="0">
<Sig Name="DC_Con1:0"/>
<Sig Name="DC_Con1:1"/>
<Sig Name="DC_Con1:2"/>
<Sig Name="DC_Con1:3"/>
<Sig Name="DC_Con1:4"/>
<Sig Name="DC_Con1:5"/>
<Sig Name="DC_Con1:6"/>
<Sig Name="DC_Con1:7"/>
<Sig Name="DC_Con1:8"/>
<Sig Name="DC_Con1:9"/>
<Sig Name="DC_Con1:10"/>
<Sig Name="DC_Con1:11"/>
<Sig Name="DC_Con1:12"/>
<Sig Name="DC_Con1:13"/>
<Sig Name="DC_Con1:14"/>
<Sig Name="DC_Con1:15"/>
<Sig Name="DC_Con1:16"/>
<Sig Name="DC_Con1:17"/>
<Sig Name="DC_Con1:18"/>
<Sig Name="DC_Con1:19"/>
<Sig Name="DC_Con1:20"/>
<Sig Name="DC_Con1:21"/>
<Sig Name="DC_Con1:22"/>
<Sig Name="DC_Con1:23"/>
</Bus>
<Bus Name="DC_Con2" Radix="0">
<Sig Name="DC_Con2:0"/>
<Sig Name="DC_Con2:1"/>
<Sig Name="DC_Con2:2"/>
<Sig Name="DC_Con2:3"/>
<Sig Name="DC_Con2:4"/>
<Sig Name="DC_Con2:5"/>
<Sig Name="DC_Con2:6"/>
<Sig Name="DC_Con2:7"/>
<Sig Name="DC_Con2:8"/>
<Sig Name="DC_Con2:9"/>
<Sig Name="DC_Con2:10"/>
<Sig Name="DC_Con2:11"/>
<Sig Name="DC_Con2:12"/>
<Sig Name="DC_Con2:13"/>
<Sig Name="DC_Con2:14"/>
<Sig Name="DC_Con2:15"/>
<Sig Name="DC_Con2:16"/>
<Sig Name="DC_Con2:17"/>
<Sig Name="DC_Con2:18"/>
<Sig Name="DC_Con2:19"/>
<Sig Name="DC_Con2:20"/>
<Sig Name="DC_Con2:21"/>
<Sig Name="DC_Con2:22"/>
<Sig Name="DC_Con2:23"/>
</Bus>
<Bus Name="DC_Con3" Radix="0">
<Sig Name="DC_Con3:0"/>
<Sig Name="DC_Con3:1"/>
<Sig Name="DC_Con3:2"/>
<Sig Name="DC_Con3:3"/>
<Sig Name="DC_Con3:4"/>
<Sig Name="DC_Con3:5"/>
<Sig Name="DC_Con3:6"/>
<Sig Name="DC_Con3:7"/>
<Sig Name="DC_Con3:8"/>
<Sig Name="DC_Con3:9"/>
<Sig Name="DC_Con3:10"/>
<Sig Name="DC_Con3:11"/>
<Sig Name="DC_Con3:12"/>
<Sig Name="DC_Con3:13"/>
<Sig Name="DC_Con3:14"/>
<Sig Name="DC_Con3:15"/>
<Sig Name="DC_Con3:16"/>
<Sig Name="DC_Con3:17"/>
<Sig Name="DC_Con3:18"/>
<Sig Name="DC_Con3:19"/>
<Sig Name="DC_Con3:20"/>
<Sig Name="DC_Con3:21"/>
<Sig Name="DC_Con3:22"/>
<Sig Name="DC_Con3:23"/>
</Bus>
<Bus Name="DC_Con4" Radix="0">
<Sig Name="DC_Con4:0"/>
<Sig Name="DC_Con4:1"/>
<Sig Name="DC_Con4:2"/>
<Sig Name="DC_Con4:3"/>
<Sig Name="DC_Con4:4"/>
<Sig Name="DC_Con4:5"/>
<Sig Name="DC_Con4:6"/>
<Sig Name="DC_Con4:7"/>
<Sig Name="DC_Con4:8"/>
<Sig Name="DC_Con4:9"/>
<Sig Name="DC_Con4:10"/>
<Sig Name="DC_Con4:11"/>
<Sig Name="DC_Con4:12"/>
<Sig Name="DC_Con4:13"/>
<Sig Name="DC_Con4:14"/>
<Sig Name="DC_Con4:15"/>
<Sig Name="DC_Con4:16"/>
<Sig Name="DC_Con4:17"/>
<Sig Name="DC_Con4:18"/>
<Sig Name="DC_Con4:19"/>
<Sig Name="DC_Con4:20"/>
<Sig Name="DC_Con4:21"/>
<Sig Name="DC_Con4:22"/>
<Sig Name="DC_Con4:23"/>
</Bus>
<Bus Name="DMM_EN" Radix="0">
<Sig Name="DMM_EN:0"/>
<Sig Name="DMM_EN:1"/>
<Sig Name="DMM_EN:2"/>
<Sig Name="DMM_EN:3"/>
<Sig Name="DMM_EN:4"/>
<Sig Name="DMM_EN:5"/>
<Sig Name="DMM_EN:6"/>
<Sig Name="DMM_EN:7"/>
<Sig Name="DMM_EN:8"/>
<Sig Name="DMM_EN:9"/>
<Sig Name="DMM_EN:10"/>
<Sig Name="DMM_EN:11"/>
<Sig Name="DMM_EN:12"/>
<Sig Name="DMM_EN:13"/>
<Sig Name="DMM_EN:14"/>
<Sig Name="DMM_EN:15"/>
<Sig Name="DMM_EN:16"/>
<Sig Name="DMM_EN:17"/>
<Sig Name="DMM_EN:18"/>
</Bus>
<Sig Name="DPSFS_RC1"/>
<Bus Name="DPS_FS_1" Radix="0"> <Bus Name="DPS_FS_1" Radix="0">
<Sig Name="DPS_FS_1:0"/> <Sig Name="DPS_FS_1:0"/>
<Sig Name="DPS_FS_1:1"/> <Sig Name="DPS_FS_1:1"/>
@@ -93,79 +246,6 @@
<Sig Name="FSMMC:4"/> <Sig Name="FSMMC:4"/>
<Sig Name="FSMMC:5"/> <Sig Name="FSMMC:5"/>
</Bus> </Bus>
<Sig Name="DPSFS_RC1"/>
<Bus Name="o_PMU_OC_1" Radix="0">
<Sig Name="o_PMU_OC_1:0"/>
<Sig Name="o_PMU_OC_1:1"/>
<Sig Name="o_PMU_OC_1:2"/>
<Sig Name="o_PMU_OC_1:3"/>
<Sig Name="o_PMU_OC_1:4"/>
<Sig Name="o_PMU_OC_1:5"/>
<Sig Name="o_PMU_OC_1:6"/>
<Sig Name="o_PMU_OC_1:7"/>
<Sig Name="o_PMU_OC_1:8"/>
<Sig Name="o_PMU_OC_1:9"/>
<Sig Name="o_PMU_OC_1:10"/>
<Sig Name="o_PMU_OC_1:11"/>
<Sig Name="o_PMU_OC_1:12"/>
<Sig Name="o_PMU_OC_1:13"/>
<Sig Name="o_PMU_OC_1:14"/>
<Sig Name="o_PMU_OC_1:15"/>
</Bus>
<Bus Name="o_PMU_OC_2" Radix="0">
<Sig Name="o_PMU_OC_2:0"/>
<Sig Name="o_PMU_OC_2:1"/>
<Sig Name="o_PMU_OC_2:2"/>
<Sig Name="o_PMU_OC_2:3"/>
<Sig Name="o_PMU_OC_2:4"/>
<Sig Name="o_PMU_OC_2:5"/>
<Sig Name="o_PMU_OC_2:6"/>
<Sig Name="o_PMU_OC_2:7"/>
<Sig Name="o_PMU_OC_2:8"/>
<Sig Name="o_PMU_OC_2:9"/>
<Sig Name="o_PMU_OC_2:10"/>
<Sig Name="o_PMU_OC_2:11"/>
<Sig Name="o_PMU_OC_2:12"/>
<Sig Name="o_PMU_OC_2:13"/>
<Sig Name="o_PMU_OC_2:14"/>
<Sig Name="o_PMU_OC_2:15"/>
</Bus>
<Bus Name="o_PMU_OC_3" Radix="0">
<Sig Name="o_PMU_OC_3:0"/>
<Sig Name="o_PMU_OC_3:1"/>
<Sig Name="o_PMU_OC_3:2"/>
<Sig Name="o_PMU_OC_3:3"/>
<Sig Name="o_PMU_OC_3:4"/>
<Sig Name="o_PMU_OC_3:5"/>
<Sig Name="o_PMU_OC_3:6"/>
<Sig Name="o_PMU_OC_3:7"/>
<Sig Name="o_PMU_OC_3:8"/>
<Sig Name="o_PMU_OC_3:9"/>
<Sig Name="o_PMU_OC_3:10"/>
<Sig Name="o_PMU_OC_3:11"/>
<Sig Name="o_PMU_OC_3:12"/>
<Sig Name="o_PMU_OC_3:13"/>
<Sig Name="o_PMU_OC_3:14"/>
<Sig Name="o_PMU_OC_3:15"/>
</Bus>
<Bus Name="o_PMU_OC_4" Radix="0">
<Sig Name="o_PMU_OC_4:0"/>
<Sig Name="o_PMU_OC_4:1"/>
<Sig Name="o_PMU_OC_4:2"/>
<Sig Name="o_PMU_OC_4:3"/>
<Sig Name="o_PMU_OC_4:4"/>
<Sig Name="o_PMU_OC_4:5"/>
<Sig Name="o_PMU_OC_4:6"/>
<Sig Name="o_PMU_OC_4:7"/>
<Sig Name="o_PMU_OC_4:8"/>
<Sig Name="o_PMU_OC_4:9"/>
<Sig Name="o_PMU_OC_4:10"/>
<Sig Name="o_PMU_OC_4:11"/>
<Sig Name="o_PMU_OC_4:12"/>
<Sig Name="o_PMU_OC_4:13"/>
<Sig Name="o_PMU_OC_4:14"/>
<Sig Name="o_PMU_OC_4:15"/>
</Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Operator="6" Name="TU1" ID="1" Value="0" Radix="0"/> <TU Operator="6" Name="TU1" ID="1" Value="0" Radix="0"/>
CPLD1/impl1/NewExtIns_CPLD1_impl1.jed
+3968 -3968
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CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo
+48018 -38358
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File diff suppressed because it is too large Load Diff
CPLD3/AD5522_Con.v
+20
View File
@@ -0,0 +1,20 @@
module AD5522_Con (
input i_sys_clk,
input i_rst_n,
output o_AD5522_Reset
);
reg AD5522_Reset;
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
AD5522_Reset <= 'd0;
end else begin
AD5522_Reset <= 'd1;
end
end
assign o_AD5522_Reset = AD5522_Reset;
endmodule
CPLD3/NewExtIns_CPLD3.lpf
+39 -29
View File
@@ -1,29 +1,39 @@
rvl_alias "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK RESETPATHS ; RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK ASYNCPATHS ; BLOCK RESETPATHS ;
LOCATE COMP "i_sys_clk" SITE "B9" ; BLOCK ASYNCPATHS ;
LOCATE COMP "i_rst_n" SITE "Y14" ; LOCATE COMP "i_sys_clk" SITE "B9" ;
LOCATE COMP "i_sclk" SITE "AA10" ; LOCATE COMP "i_rst_n" SITE "Y14" ;
LOCATE COMP "i_cs" SITE "AB11" ; LOCATE COMP "i_sclk" SITE "AA10" ;
LOCATE COMP "i_mosi" SITE "AB12" ; LOCATE COMP "i_cs" SITE "AB11" ;
LOCATE COMP "o_miso" SITE "AA14" ; LOCATE COMP "i_mosi" SITE "AB12" ;
IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ; LOCATE COMP "o_miso" SITE "AA14" ;
IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
LOCATE COMP "o_err" SITE "AB16" ; IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_PMU_RC[0]" SITE "V2" ; LOCATE COMP "o_err" SITE "AB16" ;
LOCATE COMP "o_PMU_RC[1]" SITE "N18" ; LOCATE COMP "o_PMU_RC[0]" SITE "V2" ;
LOCATE COMP "o_PMU_RC[2]" SITE "P19" ; LOCATE COMP "o_PMU_RC[1]" SITE "N18" ;
LOCATE COMP "o_PMU_RC[3]" SITE "P18" ; LOCATE COMP "o_PMU_RC[2]" SITE "P19" ;
IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 ; LOCATE COMP "o_PMU_RC[3]" SITE "P18" ;
IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
BLOCK JTAGPATHS ; IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
BLOCK JTAGPATHS ;
LOCATE COMP "o_PMU1_AD5522_Reset" SITE "H17" ;
LOCATE COMP "o_PMU2_AD5522_Reset" SITE "L20" ;
LOCATE COMP "o_PMU3_AD5522_Reset" SITE "C21" ;
LOCATE COMP "o_PMU4_AD5522_Reset" SITE "B15" ;
IOBUF PORT "o_PMU1_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU2_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU3_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU4_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_con_done" IO_TYPE=LVCMOS25 ;
CPLD3/Reg_file.v
+1 -1
View File
@@ -33,7 +33,7 @@ module Reg_file (
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h800000 | 12'b0001_0001_0000, //CPLD3==1,version=1.1.0 IDENT = 24'h800000 | 12'b0001_0010_0000, //CPLD3==1,version=1.2.0
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
CPLD3/RelayConTop.v
+42
View File
@@ -11,6 +11,11 @@ module RelayConTop (
input i_wvalid, input i_wvalid,
output [3:0]o_PMU_RC, output [3:0]o_PMU_RC,
output o_PMU1_AD5522_Reset,
output o_PMU2_AD5522_Reset,
output o_PMU3_AD5522_Reset,
output o_PMU4_AD5522_Reset,
output o_wready, output o_wready,
output o_err, output o_err,
@@ -42,6 +47,11 @@ module RelayConTop (
wire [23:0]DC_Con3 ; wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ; wire [23:0]DC_Con4 ;
//PMU AD5522
wire [3:0]PMU_AD5522_Reset ;
//DPS AD5522
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
@@ -105,9 +115,41 @@ module RelayConTop (
.o_err(cpld_err_flag) .o_err(cpld_err_flag)
); );
AD5522_Con PMU1_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[0])
);
AD5522_Con PMU2_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[1])
);
AD5522_Con PMU3_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[2])
);
AD5522_Con PMU4_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[3])
);
assign o_con_done = con_done; assign o_con_done = con_done;
assign o_PMU_RC = PMU_RC; assign o_PMU_RC = PMU_RC;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag; assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
assign o_PMU1_AD5522_Reset = PMU_AD5522_Reset[0];
assign o_PMU2_AD5522_Reset = PMU_AD5522_Reset[1];
assign o_PMU3_AD5522_Reset = PMU_AD5522_Reset[2];
assign o_PMU4_AD5522_Reset = PMU_AD5522_Reset[3];
endmodule endmodule
CPLD3/debug.rvl
+7 -10
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-06-16">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695936675" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="698419671" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -16,17 +16,14 @@
<Sig Type="SIG" Name="Bus_Con_3/err_flag"/> <Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/> <Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/> <Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/> <Sig Type="SIG" Name="o_PMU1_AD5522_Reset"/>
<Bus Name="o_PMU_RC"> <Sig Type="SIG" Name="o_PMU2_AD5522_Reset"/>
<Sig Type="SIG" Name="o_PMU_RC:0"/> <Sig Type="SIG" Name="o_PMU3_AD5522_Reset"/>
<Sig Type="SIG" Name="o_PMU_RC:1"/> <Sig Type="SIG" Name="o_PMU4_AD5522_Reset"/>
<Sig Type="SIG" Name="o_PMU_RC:2"/>
<Sig Type="SIG" Name="o_PMU_RC:3"/>
</Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/> <TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_3/i_con_exec,"/> <TU Serialbits="0" Type="0" ID="2" Sig="con_exec,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/> <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/> <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger> </Trigger>
CPLD3/debug.rvs
+26 -29
View File
@@ -1,30 +1,27 @@
<Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvs" Date="2026-05-29"> <Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-06-16">
<Core Name="RelayConTop_LA0"> <Core Name="RelayConTop_LA0">
<Setting> <Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/> <Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/> <Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/> <TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Name="i_rst_n"/> <Sig Name="i_rst_n"/>
<Sig Name="Bus_Con_3/err_flag"/> <Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/> <Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/> <Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/> <Sig Name="o_PMU1_AD5522_Reset"/>
<Bus Name="o_PMU_RC" Radix="0"> <Sig Name="o_PMU2_AD5522_Reset"/>
<Sig Name="o_PMU_RC:0"/> <Sig Name="o_PMU3_AD5522_Reset"/>
<Sig Name="o_PMU_RC:1"/> <Sig Name="o_PMU4_AD5522_Reset"/>
<Sig Name="o_PMU_RC:2"/> </Trace>
<Sig Name="o_PMU_RC:3"/> <Trigger>
</Bus> <TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
</Trace> <TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/>
<Trigger> <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/> <TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
<TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/> </Trigger>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/> </Dataset>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/> </Core>
</Trigger>
</Dataset>
</Core>
</Project> </Project>
CPLD3/impl1/NewExtIns_CPLD3_impl1.bit
BIN
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CPLD3/impl1/NewExtIns_CPLD3_impl1.jed
+2400 -2396
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