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CPLD2: Add DPS Function
This commit is contained in:
Jeremy Shen
2026-06-15 17:50:08 +08:00
parent 1ab71827c7
commit fd5ac5eae0
2 changed files with 71 additions and 17 deletions
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CPLD2/CPLD_Con.v
+33 -3
View File
@@ -25,6 +25,11 @@ module CPLD_Con (
output [31:0]o_PMU_OC_3 , output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4 , output [31:0]o_PMU_OC_4 ,
output [15:0]o_DPS_FS_1 ,
output [15:0]o_DPS_FS_2 ,
output [15:0]o_DPS_FS_3 ,
output [15:0]o_DPS_FS_4 ,
//Output FLAGs //Output FLAGs
output o_err, output o_err,
output o_con_done output o_con_done
@@ -45,6 +50,12 @@ module CPLD_Con (
reg [31:0]PMU_OC_3 ; reg [31:0]PMU_OC_3 ;
reg [31:0]PMU_OC_4 ; reg [31:0]PMU_OC_4 ;
reg [31:0]DPS_FS_1 ;
reg [31:0]DPS_FS_2 ;
reg [31:0]DPS_FS_3 ;
reg [31:0]DPS_FS_4 ;
//Flags //Flags
reg exec_done_flag; reg exec_done_flag;
reg exec_flag; reg exec_flag;
@@ -111,10 +122,17 @@ module CPLD_Con (
exec_flag <= 1'b0; exec_flag <= 1'b0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
freq_slot_flag <= 'd0; freq_slot_flag <= 'd0;
PMU_OC_1 <= 'd0; PMU_OC_1 <= 'd0;
PMU_OC_2 <= 'd0; PMU_OC_2 <= 'd0;
PMU_OC_3 <= 'd0; PMU_OC_3 <= 'd0;
PMU_OC_4 <= 'd0; PMU_OC_4 <= 'd0;
DPS_FS_1 <= 32'hffffffff;
DPS_FS_2 <= 32'hffffffff;
DPS_FS_3 <= 32'hffffffff;
DPS_FS_4 <= 32'hffffffff;
dc_slot_flag<='d0; dc_slot_flag<='d0;
err_flag <= 'd0; err_flag <= 'd0;
end end
@@ -525,7 +543,7 @@ module CPLD_Con (
end end
end end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
//TODO: TBD DPS_FS_1 <= ~(32'b1 << ( Channel_1 - 1));
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
@@ -814,7 +832,7 @@ module CPLD_Con (
end end
end end
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
//TODO: TBD DPS_FS_2 <= ~(32'b1 << ( Channel_2 - 1));
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
@@ -1102,7 +1120,7 @@ module CPLD_Con (
end end
end end
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
//TODO: TBD DPS_FS_3 <= ~(32'b1 << ( Channel_3 - 1));
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
@@ -1389,6 +1407,7 @@ module CPLD_Con (
end end
end end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
DPS_FS_4 <= ~(32'b1 << ( Channel_4 - 1));
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
@@ -1399,6 +1418,12 @@ module CPLD_Con (
PMU_OC_2 <= 'd0 ; PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ; PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ; PMU_OC_4 <= 'd0 ;
DPS_FS_1 <= 32'hffffffff;
DPS_FS_2 <= 32'hffffffff;
DPS_FS_3 <= 32'hffffffff;
DPS_FS_4 <= 32'hffffffff;
relay_l1 <= 'd0 ; relay_l1 <= 'd0 ;
relay_l2 <= 'd0 ; relay_l2 <= 'd0 ;
relay_l3 <= 'd0 ; relay_l3 <= 'd0 ;
@@ -1419,6 +1444,11 @@ module CPLD_Con (
assign o_PMU_OC_3 = PMU_OC_3; assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4; assign o_PMU_OC_4 = PMU_OC_4;
assign o_DPS_FS_1 = DPS_FS_1[31:16];
assign o_DPS_FS_2 = DPS_FS_2[31:16];
assign o_DPS_FS_3 = DPS_FS_3[31:16];
assign o_DPS_FS_4 = DPS_FS_4[31:16];
assign o_err = err_flag; assign o_err = err_flag;
endmodule endmodule
CPLD2/RelayConTop.v
+29 -5
View File
@@ -14,19 +14,25 @@ module RelayConTop (
output [7:0]o_RC_F, //Ref: Schematic output [7:0]o_RC_F, //Ref: Schematic
output [15:0]o_RC_S, output [15:0]o_RC_S,
output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1) output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1)
//output [3:0] o_OC_x09, //PMU OC Control
//output [3:0] o_OC_x25,
output [31:0]o_PMU_OC_1 , output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 , output [31:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_3 , output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4 output [31:0]o_PMU_OC_4 ,
//DPS OC Control
output [15:0]o_DPS_F_1 ,
output [15:0]o_DPS_S_1 ,
output [15:0]o_DPS_F_2 ,
output [15:0]o_DPS_S_2 ,
output [15:0]o_DPS_F_3 ,
output [15:0]o_DPS_S_3 ,
output [15:0]o_DPS_F_4 ,
output [15:0]o_DPS_S_4
); );
wire [7:0] RC_F; wire [7:0] RC_F;
wire [15:0] RC_S; wire [15:0] RC_S;
wire [31:0] RC_T; wire [31:0] RC_T;
wire [3:0]OC_x09 ;
wire [3:0]OC_x25 ;
wire [23:0]r_data ; wire [23:0]r_data ;
wire [23:0]w_data ; wire [23:0]w_data ;
@@ -57,6 +63,12 @@ module RelayConTop (
wire [31:0]PMU_OC_3 ; wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ; wire [31:0]PMU_OC_4 ;
//DPS PerChannel Force/Sense Control
wire [15:0]DPS_FS_1 ;
wire [15:0]DPS_FS_2 ;
wire [15:0]DPS_FS_3 ;
wire [15:0]DPS_FS_4 ;
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
@@ -120,6 +132,10 @@ BUS_Con BUS_Con_2(
.o_PMU_OC_2(PMU_OC_2), .o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3), .o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4), .o_PMU_OC_4(PMU_OC_4),
.o_DPS_FS_1(DPS_FS_1),
.o_DPS_FS_2(DPS_FS_2),
.o_DPS_FS_3(DPS_FS_3),
.o_DPS_FS_4(DPS_FS_4),
.o_con_done(con_done), .o_con_done(con_done),
.o_RC_F(RC_F), .o_RC_F(RC_F),
.o_RC_S(RC_S), .o_RC_S(RC_S),
@@ -137,6 +153,14 @@ BUS_Con BUS_Con_2(
assign o_PMU_OC_3 = PMU_OC_3 ; assign o_PMU_OC_3 = PMU_OC_3 ;
assign o_PMU_OC_4 = PMU_OC_4 ; assign o_PMU_OC_4 = PMU_OC_4 ;
assign o_DPS_F_1 = DPS_FS_1;
assign o_DPS_S_1 = DPS_FS_1;
assign o_DPS_F_2 = DPS_FS_2;
assign o_DPS_S_2 = DPS_FS_2;
assign o_DPS_F_3 = DPS_FS_3;
assign o_DPS_S_3 = DPS_FS_3;
assign o_DPS_F_4 = DPS_FS_4;
assign o_DPS_S_4 = DPS_FS_4;
assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag; assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag;