Fix the SPI MISO logic

Modify the tb to make it easier from all aspects
2026-06-02 11:23:34 +08:00
parent 070ad1c768
commit ed3fbd7cf5
5 changed files with 252 additions and 791 deletions
@@ -74,7 +74,6 @@ module Reg_file (
        else begin
            case (state)
                IDLE: begin
-                    rvalid_flag <= 1'b0;
                    err_flag    <= 1'b0;
                    
                    // Priority Check: Did we crash/reset while EXEC bit was still 1?
@@ -99,6 +98,7 @@ module Reg_file (
                end  

                BUSY: begin
+                    rvalid_flag <= 1'b0;
                    if (err_flag) begin
                        state <= IDLE;
                    end
@@ -133,6 +133,7 @@ module Reg_file (
                // Wait for Controller to register the command and pull 'done' LOW (Busy)
                EXEC_ACK: begin
                    busy_flag <= 1'b1;
+                    rvalid_flag <= 1'b0;
                    if (i_con_done == 1'b0) begin
                        state <= EXEC_WAIT;
                    end