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Change MISO logic

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This commit is contained in:
Jeremy Shen
2026-06-01 14:44:18 +08:00
parent 5b949c6b63
commit e60d56dd26
3 changed files with 54 additions and 18 deletions
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CPLD1/BUS_Con.v
+16 -4
View File
@@ -76,18 +76,31 @@ module BUS_Con (
localparam DONE = 2'b11;
always @(posedge i_sys_clk) begin
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
recv_reg <= 32'd0;
bit_cnt <= 6'd0;
data_ready <= 1'b0;
err_flag <= 1'b0;
end
else begin
else begin
// Clear data_ready when FSM has consumed the command
if (state == CMD_SENT) begin
data_ready <= 1'b0;
end
if (cs_active) begin
if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data};
if (bit_cnt == 6'd31) begin
if (bit_cnt == 6'd7) begin
// 8th bit received: check if read (MSB=0) or write (MSB=1)
if (recv_reg[0] == 1'b0) begin
// Read command: set data_ready after 8 bits
data_ready <= 1'b1;
end
end
else if (bit_cnt == 6'd31) begin
// 32nd bit received: write command complete
data_ready <= 1'b1;
end
bit_cnt <= bit_cnt + 1'b1;
@@ -187,7 +200,6 @@ module BUS_Con (
CMD_SENT: begin
cmd_valid_out <= 1'b0;
data_ready <= 1'b0; // Clear data_ready when FSM consumes it
state <= DONE;
end
CPLD2/BUS_Con.v
+16 -4
View File
@@ -76,18 +76,31 @@ module BUS_Con (
localparam DONE = 2'b11;
always @(posedge i_sys_clk) begin
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
recv_reg <= 32'd0;
bit_cnt <= 6'd0;
data_ready <= 1'b0;
err_flag <= 1'b0;
end
else begin
else begin
// Clear data_ready when FSM has consumed the command
if (state == CMD_SENT) begin
data_ready <= 1'b0;
end
if (cs_active) begin
if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data};
if (bit_cnt == 6'd31) begin
if (bit_cnt == 6'd7) begin
// 8th bit received: check if read (MSB=0) or write (MSB=1)
if (recv_reg[0] == 1'b0) begin
// Read command: set data_ready after 8 bits
data_ready <= 1'b1;
end
end
else if (bit_cnt == 6'd31) begin
// 32nd bit received: write command complete
data_ready <= 1'b1;
end
bit_cnt <= bit_cnt + 1'b1;
@@ -189,7 +202,6 @@ module BUS_Con (
CMD_SENT: begin
cmd_valid_out <= 1'b0;
data_ready <= 1'b0; // Clear data_ready when FSM consumes it
state <= DONE;
end
CPLD3/BUS_Con.v
+16 -4
View File
@@ -76,18 +76,31 @@ module BUS_Con (
localparam DONE = 2'b11;
always @(posedge i_sys_clk) begin
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
recv_reg <= 32'd0;
bit_cnt <= 6'd0;
data_ready <= 1'b0;
err_flag <= 1'b0;
end
else begin
else begin
// Clear data_ready when FSM has consumed the command
if (state == CMD_SENT) begin
data_ready <= 1'b0;
end
if (cs_active) begin
if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data};
if (bit_cnt == 6'd31) begin
if (bit_cnt == 6'd7) begin
// 8th bit received: check if read (MSB=0) or write (MSB=1)
if (recv_reg[0] == 1'b0) begin
// Read command: set data_ready after 8 bits
data_ready <= 1'b1;
end
end
else if (bit_cnt == 6'd31) begin
// 32nd bit received: write command complete
data_ready <= 1'b1;
end
bit_cnt <= bit_cnt + 1'b1;
@@ -189,7 +202,6 @@ module BUS_Con (
CMD_SENT: begin
cmd_valid_out <= 1'b0;
data_ready <= 1'b0; // Clear data_ready when FSM consumes it
state <= DONE;
end