diff --git a/CPLD1/BUS_Con.v b/CPLD1/BUS_Con.v
index 94fc671..26ad9d3 100644
--- a/CPLD1/BUS_Con.v
+++ b/CPLD1/BUS_Con.v
@@ -76,18 +76,31 @@ module BUS_Con (
     localparam DONE      = 2'b11;
     
 
-    always @(posedge i_sys_clk) begin
+   always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
             recv_reg      <= 32'd0;
             bit_cnt       <= 6'd0;
             data_ready    <= 1'b0;
             err_flag      <= 1'b0;
         end 
-       else begin
+        else begin
+            // Clear data_ready when FSM has consumed the command
+            if (state == CMD_SENT) begin
+                data_ready <= 1'b0;
+            end
+
             if (cs_active) begin
                 if (sclk_rise) begin
                     recv_reg <= {recv_reg[30:0], mosi_data}; 
-                    if (bit_cnt == 6'd31) begin
+                    if (bit_cnt == 6'd7) begin
+                        // 8th bit received: check if read (MSB=0) or write (MSB=1)
+                        if (recv_reg[0] == 1'b0) begin
+                            // Read command: set data_ready after 8 bits
+                            data_ready <= 1'b1;
+                        end
+                    end
+                    else if (bit_cnt == 6'd31) begin
+                        // 32nd bit received: write command complete
                         data_ready <= 1'b1;
                     end
                     bit_cnt  <= bit_cnt + 1'b1;
@@ -108,8 +121,8 @@ module BUS_Con (
             if (state == DONE) begin
                 recv_reg <= 'd0;
             end
-        end
-    end
+        end
+    end
 
     // --- 3. MISO (Transmit) Logic ---
     // Protocol: We shift out 32 bits. 
@@ -187,7 +200,6 @@ module BUS_Con (
 
                 CMD_SENT: begin
                     cmd_valid_out <= 1'b0;
-                    data_ready    <= 1'b0;  // Clear data_ready when FSM consumes it
                     state         <= DONE;
                 end
 
diff --git a/CPLD2/BUS_Con.v b/CPLD2/BUS_Con.v
index 5b5c63b..b836e16 100644
--- a/CPLD2/BUS_Con.v
+++ b/CPLD2/BUS_Con.v
@@ -76,18 +76,31 @@ module BUS_Con (
     localparam DONE      = 2'b11;
     
 
-    always @(posedge i_sys_clk) begin
+   always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
             recv_reg      <= 32'd0;
             bit_cnt       <= 6'd0;
             data_ready    <= 1'b0;
             err_flag      <= 1'b0;
         end 
-       else begin
+        else begin
+            // Clear data_ready when FSM has consumed the command
+            if (state == CMD_SENT) begin
+                data_ready <= 1'b0;
+            end
+
             if (cs_active) begin
                 if (sclk_rise) begin
                     recv_reg <= {recv_reg[30:0], mosi_data}; 
-                    if (bit_cnt == 6'd31) begin
+                    if (bit_cnt == 6'd7) begin
+                        // 8th bit received: check if read (MSB=0) or write (MSB=1)
+                        if (recv_reg[0] == 1'b0) begin
+                            // Read command: set data_ready after 8 bits
+                            data_ready <= 1'b1;
+                        end
+                    end
+                    else if (bit_cnt == 6'd31) begin
+                        // 32nd bit received: write command complete
                         data_ready <= 1'b1;
                     end
                     bit_cnt  <= bit_cnt + 1'b1;
@@ -108,8 +121,8 @@ module BUS_Con (
             if (state == DONE) begin
                 recv_reg <= 'd0;
             end
-        end
-    end
+        end
+    end
 
     // --- 3. MISO (Transmit) Logic ---
     // Protocol: We shift out 32 bits. 
@@ -189,7 +202,6 @@ module BUS_Con (
 
                 CMD_SENT: begin
                     cmd_valid_out <= 1'b0;
-                    data_ready    <= 1'b0;  // Clear data_ready when FSM consumes it
                     state         <= DONE;
                 end
 
diff --git a/CPLD3/BUS_Con.v b/CPLD3/BUS_Con.v
index 5b5c63b..b836e16 100644
--- a/CPLD3/BUS_Con.v
+++ b/CPLD3/BUS_Con.v
@@ -76,18 +76,31 @@ module BUS_Con (
     localparam DONE      = 2'b11;
     
 
-    always @(posedge i_sys_clk) begin
+   always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
             recv_reg      <= 32'd0;
             bit_cnt       <= 6'd0;
             data_ready    <= 1'b0;
             err_flag      <= 1'b0;
         end 
-       else begin
+        else begin
+            // Clear data_ready when FSM has consumed the command
+            if (state == CMD_SENT) begin
+                data_ready <= 1'b0;
+            end
+
             if (cs_active) begin
                 if (sclk_rise) begin
                     recv_reg <= {recv_reg[30:0], mosi_data}; 
-                    if (bit_cnt == 6'd31) begin
+                    if (bit_cnt == 6'd7) begin
+                        // 8th bit received: check if read (MSB=0) or write (MSB=1)
+                        if (recv_reg[0] == 1'b0) begin
+                            // Read command: set data_ready after 8 bits
+                            data_ready <= 1'b1;
+                        end
+                    end
+                    else if (bit_cnt == 6'd31) begin
+                        // 32nd bit received: write command complete
                         data_ready <= 1'b1;
                     end
                     bit_cnt  <= bit_cnt + 1'b1;
@@ -108,8 +121,8 @@ module BUS_Con (
             if (state == DONE) begin
                 recv_reg <= 'd0;
             end
-        end
-    end
+        end
+    end
 
     // --- 3. MISO (Transmit) Logic ---
     // Protocol: We shift out 32 bits. 
@@ -189,7 +202,6 @@ module BUS_Con (
 
                 CMD_SENT: begin
                     cmd_valid_out <= 1'b0;
-                    data_ready    <= 1'b0;  // Clear data_ready when FSM consumes it
                     state         <= DONE;
                 end