yuysh/NewInstrCalBoard_CPLD
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Fix bugs and Unify the PMU_OC logic

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yuysh
2026-06-09 11:41:21 +08:00
parent 092cad794c
commit e19adb09f9
5 changed files with 33 additions and 56 deletions
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CPLD1/CPLD_Con.v
+4 -4
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@@ -74,16 +74,16 @@ module CPLD_Con (
//Reg Parsing
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17] ; // RC_RL Shifter
CPLD1/RelayConTop.v
+6 -6
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@@ -169,12 +169,12 @@ module RelayConTop (
assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1;
assign o_RC_T27 = RC_Tx[5];
assign o_RC_T28 = RC_Tx[4];
assign o_RC_T29 = RC_Tx[3];
assign o_RC_T30 = RC_Tx[2];
assign o_RC_T31 = RC_Tx[1];
assign o_RC_T32 = RC_Tx[0];
assign o_RC_T27 = RC_Tx[0];
assign o_RC_T28 = RC_Tx[1];
assign o_RC_T29 = RC_Tx[2];
assign o_RC_T30 = RC_Tx[3];
assign o_RC_T31 = RC_Tx[4];
assign o_RC_T32 = RC_Tx[5];
assign o_RC_RLSel = RC_RLSel;
assign o_RC_VSel = RC_VSel;
CPLD2/CPLD_Con.v
+6 -6
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@@ -58,10 +58,10 @@ module CPLD_Con (
reg [15:0]delay_cnt;
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3;; // Channel Number div 8
wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8
wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8
wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8
//Channels
wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
@@ -1202,7 +1202,7 @@ module CPLD_Con (
'd68: begin
relay_l1 <= 8'b0000_0000;
if (delay_cnt == 'd500) begin
relay_l2 <= 16'b0000_0001_0000_0000;
relay_l2 <= 16'b0010_0000_0000_0000;
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= 32'b0000_0100_0000_0000_0000_0000_0000_0000;
@@ -1366,7 +1366,7 @@ module CPLD_Con (
'd200: begin
relay_l1 <= 8'b1000_0000;
if (delay_cnt == 'd500) begin
relay_l2 <= 16'b0000_0100_0000_0000;
relay_l2 <= 16'b1000_0000_0000_0000;
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= 32'b1000_0000_0000_0000_0000_0000_0000_0000;
CPLD2/RelayConTop.v
+4 -27
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@@ -124,8 +124,6 @@ BUS_Con BUS_Con_2(
.o_RC_F(RC_F),
.o_RC_S(RC_S),
.o_RC_T(RC_T),
.o_OC_x09(OC_x09),
.o_OC_x25(OC_x25),
.o_err(cpld_err_flag)
);
@@ -134,31 +132,10 @@ BUS_Con BUS_Con_2(
assign o_RC_S = RC_S;
assign o_RC_T = RC_T[25:0];
assign o_PMU_OC_1[8] = OC_x09[0];
assign o_PMU_OC_2[8] = OC_x09[1];
assign o_PMU_OC_3[8] = OC_x09[2];
assign o_PMU_OC_4[8] = OC_x09[3];
assign o_PMU_OC_1[24] = OC_x25[0];
assign o_PMU_OC_2[24] = OC_x25[1];
assign o_PMU_OC_3[24] = OC_x25[2];
assign o_PMU_OC_4[24] = OC_x25[3];
assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
assign o_PMU_OC_1 = PMU_OC_1 ;
assign o_PMU_OC_2 = PMU_OC_2 ;
assign o_PMU_OC_3 = PMU_OC_3 ;
assign o_PMU_OC_4 = PMU_OC_4 ;
assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag;
CPLD3/CPLD_Con.v
+5 -5
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@@ -117,19 +117,19 @@ module CPLD_Con (
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
PMU_RC <= 4'b0001;
PMU_RC <= 4'b1110;
end
4'b0010: begin
PMU_RC <= 4'b0010;
PMU_RC <= 4'b1101;
end
4'b0100: begin
PMU_RC <= 4'b0100;
PMU_RC <= 4'b1011;
end
4'b1000: begin
PMU_RC <= 4'b1000;
PMU_RC <= 4'b0111;
end
default:begin
PMU_RC <= 4'b0000;
PMU_RC <= 4'b1111;
end
endcase
end