diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v index 743b7f0..16985d1 100644 --- a/CPLD1/CPLD_Con.v +++ b/CPLD1/CPLD_Con.v @@ -74,18 +74,18 @@ module CPLD_Con ( //Reg Parsing //Shift Counter - wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8 - wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7]; // Channel Number div 64 - wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17]; // RC_RL Shifter - wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8 - wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7]; // Channel Number div 64 - wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17]; // RC_RL Shifter - wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8 - wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7]; // Channel Number div 64 - wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17]; // RC_RL Shifter - wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8 - wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7]; // Channel Number div 64 - wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17]; // RC_RL Shifter + wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3; // Channel Number div 8 + wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7] ; // Channel Number div 64 + wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17] ; // RC_RL Shifter + wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8 + wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7] ; // Channel Number div 64 + wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17] ; // RC_RL Shifter + wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8 + wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7] ; // Channel Number div 64 + wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17] ; // RC_RL Shifter + wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8 + wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7] ; // Channel Number div 64 + wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17] ; // RC_RL Shifter //Channels wire [8:0]Channel_1 = i_DC_Con1[9:1] ; diff --git a/CPLD1/RelayConTop.v b/CPLD1/RelayConTop.v index 2fe8504..2f70938 100644 --- a/CPLD1/RelayConTop.v +++ b/CPLD1/RelayConTop.v @@ -169,12 +169,12 @@ module RelayConTop ( assign o_DMM_EN = DMM_EN; assign o_IO_RC1 = IO_RC1; - assign o_RC_T27 = RC_Tx[5]; - assign o_RC_T28 = RC_Tx[4]; - assign o_RC_T29 = RC_Tx[3]; - assign o_RC_T30 = RC_Tx[2]; - assign o_RC_T31 = RC_Tx[1]; - assign o_RC_T32 = RC_Tx[0]; + assign o_RC_T27 = RC_Tx[0]; + assign o_RC_T28 = RC_Tx[1]; + assign o_RC_T29 = RC_Tx[2]; + assign o_RC_T30 = RC_Tx[3]; + assign o_RC_T31 = RC_Tx[4]; + assign o_RC_T32 = RC_Tx[5]; assign o_RC_RLSel = RC_RLSel; assign o_RC_VSel = RC_VSel; diff --git a/CPLD2/CPLD_Con.v b/CPLD2/CPLD_Con.v index 04f2e87..830a9ad 100644 --- a/CPLD2/CPLD_Con.v +++ b/CPLD2/CPLD_Con.v @@ -58,10 +58,10 @@ module CPLD_Con ( reg [15:0]delay_cnt; //Shift Counter - wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8 - wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8 - wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8 - wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8 + wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3;; // Channel Number div 8 + wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8 + wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8 + wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8 //Channels wire [8:0]Channel_1 = i_DC_Con1[9:1] ; @@ -1202,7 +1202,7 @@ module CPLD_Con ( 'd68: begin relay_l1 <= 8'b0000_0000; if (delay_cnt == 'd500) begin - relay_l2 <= 16'b0000_0001_0000_0000; + relay_l2 <= 16'b0010_0000_0000_0000; end else if (delay_cnt == 'd1000) begin relay_l3 <= 32'b0000_0100_0000_0000_0000_0000_0000_0000; @@ -1366,7 +1366,7 @@ module CPLD_Con ( 'd200: begin relay_l1 <= 8'b1000_0000; if (delay_cnt == 'd500) begin - relay_l2 <= 16'b0000_0100_0000_0000; + relay_l2 <= 16'b1000_0000_0000_0000; end else if (delay_cnt == 'd1000) begin relay_l3 <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; diff --git a/CPLD2/RelayConTop.v b/CPLD2/RelayConTop.v index 103f5e9..8255f3e 100644 --- a/CPLD2/RelayConTop.v +++ b/CPLD2/RelayConTop.v @@ -124,8 +124,6 @@ BUS_Con BUS_Con_2( .o_RC_F(RC_F), .o_RC_S(RC_S), .o_RC_T(RC_T), - .o_OC_x09(OC_x09), - .o_OC_x25(OC_x25), .o_err(cpld_err_flag) ); @@ -134,31 +132,10 @@ BUS_Con BUS_Con_2( assign o_RC_S = RC_S; assign o_RC_T = RC_T[25:0]; - assign o_PMU_OC_1[8] = OC_x09[0]; - assign o_PMU_OC_2[8] = OC_x09[1]; - assign o_PMU_OC_3[8] = OC_x09[2]; - assign o_PMU_OC_4[8] = OC_x09[3]; - - assign o_PMU_OC_1[24] = OC_x25[0]; - assign o_PMU_OC_2[24] = OC_x25[1]; - assign o_PMU_OC_3[24] = OC_x25[2]; - assign o_PMU_OC_4[24] = OC_x25[3]; - - assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0]; - assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8]; - assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25]; - - assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0]; - assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9]; - assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25]; - - assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0]; - assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9]; - assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25]; - - assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0]; - assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9]; - assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25]; + assign o_PMU_OC_1 = PMU_OC_1 ; + assign o_PMU_OC_2 = PMU_OC_2 ; + assign o_PMU_OC_3 = PMU_OC_3 ; + assign o_PMU_OC_4 = PMU_OC_4 ; assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag; diff --git a/CPLD3/CPLD_Con.v b/CPLD3/CPLD_Con.v index 726a787..e226dc0 100644 --- a/CPLD3/CPLD_Con.v +++ b/CPLD3/CPLD_Con.v @@ -117,19 +117,19 @@ module CPLD_Con ( else if (dc_t == 1'b1) begin case (dc_slot_flag) 4'b0001: begin - PMU_RC <= 4'b0001; + PMU_RC <= 4'b1110; end 4'b0010: begin - PMU_RC <= 4'b0010; + PMU_RC <= 4'b1101; end 4'b0100: begin - PMU_RC <= 4'b0100; + PMU_RC <= 4'b1011; end 4'b1000: begin - PMU_RC <= 4'b1000; + PMU_RC <= 4'b0111; end default:begin - PMU_RC <= 4'b0000; + PMU_RC <= 4'b1111; end endcase end