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Fix bugs and Unify the PMU_OC logic

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yuysh
2026-06-09 11:41:21 +08:00
parent 092cad794c
commit e19adb09f9
5 changed files with 33 additions and 56 deletions
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CPLD2/CPLD_Con.v
+6 -6
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@@ -58,10 +58,10 @@ module CPLD_Con (
reg [15:0]delay_cnt;
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3;; // Channel Number div 8
wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8
wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8
wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8
//Channels
wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
@@ -1202,7 +1202,7 @@ module CPLD_Con (
'd68: begin
relay_l1 <= 8'b0000_0000;
if (delay_cnt == 'd500) begin
relay_l2 <= 16'b0000_0001_0000_0000;
relay_l2 <= 16'b0010_0000_0000_0000;
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= 32'b0000_0100_0000_0000_0000_0000_0000_0000;
@@ -1366,7 +1366,7 @@ module CPLD_Con (
'd200: begin
relay_l1 <= 8'b1000_0000;
if (delay_cnt == 'd500) begin
relay_l2 <= 16'b0000_0100_0000_0000;
relay_l2 <= 16'b1000_0000_0000_0000;
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= 32'b1000_0000_0000_0000_0000_0000_0000_0000;