yuysh/NewInstrCalBoard_CPLD
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Fix bugs and Unify the PMU_OC logic

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yuysh
2026-06-09 11:41:21 +08:00
parent 092cad794c
commit e19adb09f9
5 changed files with 33 additions and 56 deletions
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CPLD1/CPLD_Con.v
+12 -12
View File
@@ -74,18 +74,18 @@ module CPLD_Con (
//Reg Parsing
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17]; // RC_RL Shifter
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17]; // RC_RL Shifter
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17]; // RC_RL Shifter
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17]; // RC_RL Shifter
wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17] ; // RC_RL Shifter
//Channels
wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
CPLD1/RelayConTop.v
+6 -6
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@@ -169,12 +169,12 @@ module RelayConTop (
assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1;
assign o_RC_T27 = RC_Tx[5];
assign o_RC_T28 = RC_Tx[4];
assign o_RC_T29 = RC_Tx[3];
assign o_RC_T30 = RC_Tx[2];
assign o_RC_T31 = RC_Tx[1];
assign o_RC_T32 = RC_Tx[0];
assign o_RC_T27 = RC_Tx[0];
assign o_RC_T28 = RC_Tx[1];
assign o_RC_T29 = RC_Tx[2];
assign o_RC_T30 = RC_Tx[3];
assign o_RC_T31 = RC_Tx[4];
assign o_RC_T32 = RC_Tx[5];
assign o_RC_RLSel = RC_RLSel;
assign o_RC_VSel = RC_VSel;