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Change RC_RLSel logic

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yuysh
2026-06-01 16:19:58 +08:00
parent e60d56dd26
commit 8f65c6908d
1 changed files with 6 additions and 6 deletions
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CPLD1/CPLD_Con.v
+6 -6
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@@ -122,7 +122,7 @@ module CPLD_Con (
DMM_en <= 'd0; DMM_en <= 'd0;
RC_VISel <='d0; RC_VISel <='d0;
RC_RLSel <='d0; RC_RLSel <='hfffff;
PMU_OC_1 <= 'd0 ; PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ; PMU_OC_2 <= 'd0 ;
@@ -268,7 +268,7 @@ module CPLD_Con (
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con1[21:17] - 1); RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con1[21:17] - 1);
if (i_DC_Con1[23] == 1'b0) begin //Select PMU if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1); PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1); DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
@@ -290,7 +290,7 @@ module CPLD_Con (
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con2[21:17] - 1); RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con2[21:17] - 1);
if (i_DC_Con2[23] == 1'b0) begin //Select PMU if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2); PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2); DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
@@ -312,7 +312,7 @@ module CPLD_Con (
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con3[21:17] - 1); RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con3[21:17] - 1);
if (i_DC_Con3[23] == 1'b0) begin //Select PMU if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3); PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3); DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
@@ -334,7 +334,7 @@ module CPLD_Con (
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1); RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con4[21:17] - 1);
if (i_DC_Con4[23] == 1'b0) begin //Select PMU if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4); PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4); DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
@@ -346,7 +346,7 @@ module CPLD_Con (
end end
default:begin // You Should NOT be HERE default:begin // You Should NOT be HERE
RC_VISel <='d0; RC_VISel <='d0;
RC_RLSel <='d0; RC_RLSel <='hfffff;
PMU_OC_1 <= 'd0 ; PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ; PMU_OC_2 <= 'd0 ;