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Feat: CPLD3: Add AD5522 Reset

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yuysh
2026-06-16 16:20:53 +08:00
parent 37228e2bac
commit 8554c0aac3
6 changed files with 103 additions and 32 deletions
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CPLD1/NewExtIns_CPLD1.ldf
+1 -1
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@@ -2,7 +2,7 @@
<BaliProject version="3.2" title="NewExtIns_CPLD1" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1"> <BaliProject version="3.2" title="NewExtIns_CPLD1" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/> <Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1"> <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop" top="RelayConTop"/> <Options top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog"> <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/> <Options top_module="RelayConTop"/>
</Source> </Source>
CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf
+1 -1
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@@ -1,5 +1,5 @@
# #
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R. # Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
# #
# Period Constraints # Period Constraints
CPLD3/AD5522_Con.v
+20
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@@ -0,0 +1,20 @@
module AD5522_Con (
input i_sys_clk,
input i_rst_n,
output o_AD5522_Reset
);
reg AD5522_Reset;
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
AD5522_Reset <= 'd0;
end else begin
AD5522_Reset <= 'd1;
end
end
assign o_AD5522_Reset = AD5522_Reset;
endmodule
CPLD3/NewExtIns_CPLD3.lpf
+18 -9
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@@ -1,4 +1,4 @@
rvl_alias "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK RESETPATHS ; BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ; BLOCK ASYNCPATHS ;
@@ -8,10 +8,10 @@ LOCATE COMP "i_sclk" SITE "AA10" ;
LOCATE COMP "i_cs" SITE "AB11" ; LOCATE COMP "i_cs" SITE "AB11" ;
LOCATE COMP "i_mosi" SITE "AB12" ; LOCATE COMP "i_mosi" SITE "AB12" ;
LOCATE COMP "o_miso" SITE "AA14" ; LOCATE COMP "o_miso" SITE "AA14" ;
IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
@@ -22,8 +22,17 @@ LOCATE COMP "o_PMU_RC[0]" SITE "V2" ;
LOCATE COMP "o_PMU_RC[1]" SITE "N18" ; LOCATE COMP "o_PMU_RC[1]" SITE "N18" ;
LOCATE COMP "o_PMU_RC[2]" SITE "P19" ; LOCATE COMP "o_PMU_RC[2]" SITE "P19" ;
LOCATE COMP "o_PMU_RC[3]" SITE "P18" ; LOCATE COMP "o_PMU_RC[3]" SITE "P18" ;
IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ;
BLOCK JTAGPATHS ; BLOCK JTAGPATHS ;
LOCATE COMP "o_PMU1_AD5522_Reset" SITE "H17" ;
LOCATE COMP "o_PMU2_AD5522_Reset" SITE "L20" ;
LOCATE COMP "o_PMU3_AD5522_Reset" SITE "C21" ;
LOCATE COMP "o_PMU4_AD5522_Reset" SITE "R21" ;
IOBUF PORT "o_PMU1_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU2_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU3_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU4_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_con_done" IO_TYPE=LVCMOS25 ;
CPLD3/RelayConTop.v
+42
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@@ -12,6 +12,11 @@ module RelayConTop (
output [3:0]o_PMU_RC, output [3:0]o_PMU_RC,
output o_PMU1_AD5522_Reset,
output o_PMU2_AD5522_Reset,
output o_PMU3_AD5522_Reset,
output o_PMU4_AD5522_Reset,
output o_wready, output o_wready,
output o_err, output o_err,
output o_con_done output o_con_done
@@ -42,6 +47,11 @@ module RelayConTop (
wire [23:0]DC_Con3 ; wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ; wire [23:0]DC_Con4 ;
//PMU AD5522
wire [3:0]PMU_AD5522_Reset ;
//DPS AD5522
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
@@ -105,9 +115,41 @@ module RelayConTop (
.o_err(cpld_err_flag) .o_err(cpld_err_flag)
); );
AD5522_Con PMU1_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[0])
);
AD5522_Con PMU2_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[1])
);
AD5522_Con PMU3_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[2])
);
AD5522_Con PMU4_AD5522(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.o_AD5522_Reset(PMU_AD5522_Reset[3])
);
assign o_con_done = con_done; assign o_con_done = con_done;
assign o_PMU_RC = PMU_RC; assign o_PMU_RC = PMU_RC;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag; assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
assign o_PMU1_AD5522_Reset = PMU_AD5522_Reset[0];
assign o_PMU2_AD5522_Reset = PMU_AD5522_Reset[1];
assign o_PMU3_AD5522_Reset = PMU_AD5522_Reset[2];
assign o_PMU4_AD5522_Reset = PMU_AD5522_Reset[3];
endmodule endmodule
CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf
+1 -1
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@@ -1,5 +1,5 @@
# #
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R. # Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
# #
# Period Constraints # Period Constraints