From 8554c0aac3568df0858651230fcdd6a92898879d Mon Sep 17 00:00:00 2001 From: YuYang Shen Date: Tue, 16 Jun 2026 16:20:53 +0800 Subject: [PATCH] Feat: CPLD3: Add AD5522 Reset --- CPLD1/NewExtIns_CPLD1.ldf | 2 +- .../impl1/NewExtIns_CPLD1_impl1_synplify.lpf | 2 +- CPLD3/AD5522_Con.v | 20 ++++++ CPLD3/NewExtIns_CPLD3.lpf | 67 +++++++++++-------- CPLD3/RelayConTop.v | 42 ++++++++++++ .../impl1/NewExtIns_CPLD3_impl1_synplify.lpf | 2 +- 6 files changed, 103 insertions(+), 32 deletions(-) create mode 100644 CPLD3/AD5522_Con.v diff --git a/CPLD1/NewExtIns_CPLD1.ldf b/CPLD1/NewExtIns_CPLD1.ldf index f5d69fb..ab693ea 100644 --- a/CPLD1/NewExtIns_CPLD1.ldf +++ b/CPLD1/NewExtIns_CPLD1.ldf @@ -2,7 +2,7 @@ - + diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf index cb8f15d..23af319 100644 --- a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf @@ -1,5 +1,5 @@ # -# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R. +# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. # # Period Constraints diff --git a/CPLD3/AD5522_Con.v b/CPLD3/AD5522_Con.v new file mode 100644 index 0000000..5c8399e --- /dev/null +++ b/CPLD3/AD5522_Con.v @@ -0,0 +1,20 @@ +module AD5522_Con ( + input i_sys_clk, + input i_rst_n, + + output o_AD5522_Reset +); + + reg AD5522_Reset; + + always @(posedge i_sys_clk) begin + if (!i_rst_n) begin + AD5522_Reset <= 'd0; + end else begin + AD5522_Reset <= 'd1; + end + end + + assign o_AD5522_Reset = AD5522_Reset; + +endmodule \ No newline at end of file diff --git a/CPLD3/NewExtIns_CPLD3.lpf b/CPLD3/NewExtIns_CPLD3.lpf index 67d4e79..6b2e9bd 100644 --- a/CPLD3/NewExtIns_CPLD3.lpf +++ b/CPLD3/NewExtIns_CPLD3.lpf @@ -1,29 +1,38 @@ -rvl_alias "i_sys_clk" "i_sys_clk"; -RVL_ALIAS "i_sys_clk" "i_sys_clk"; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -LOCATE COMP "i_sys_clk" SITE "B9" ; -LOCATE COMP "i_rst_n" SITE "Y14" ; -LOCATE COMP "i_sclk" SITE "AA10" ; -LOCATE COMP "i_cs" SITE "AB11" ; -LOCATE COMP "i_mosi" SITE "AB12" ; -LOCATE COMP "o_miso" SITE "AA14" ; -IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ; -IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ; -IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; -IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; -IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; -IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; -LOCATE COMP "o_err" SITE "AB16" ; -LOCATE COMP "o_PMU_RC[0]" SITE "V2" ; -LOCATE COMP "o_PMU_RC[1]" SITE "N18" ; -LOCATE COMP "o_PMU_RC[2]" SITE "P19" ; -LOCATE COMP "o_PMU_RC[3]" SITE "P18" ; -IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 ; -BLOCK JTAGPATHS ; +RVL_ALIAS "i_sys_clk" "i_sys_clk"; +RVL_ALIAS "i_sys_clk" "i_sys_clk"; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "i_sys_clk" SITE "B9" ; +LOCATE COMP "i_rst_n" SITE "Y14" ; +LOCATE COMP "i_sclk" SITE "AA10" ; +LOCATE COMP "i_cs" SITE "AB11" ; +LOCATE COMP "i_mosi" SITE "AB12" ; +LOCATE COMP "o_miso" SITE "AA14" ; +IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; +IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; +IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; +LOCATE COMP "o_err" SITE "AB16" ; +LOCATE COMP "o_PMU_RC[0]" SITE "V2" ; +LOCATE COMP "o_PMU_RC[1]" SITE "N18" ; +LOCATE COMP "o_PMU_RC[2]" SITE "P19" ; +LOCATE COMP "o_PMU_RC[3]" SITE "P18" ; +IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +BLOCK JTAGPATHS ; +LOCATE COMP "o_PMU1_AD5522_Reset" SITE "H17" ; +LOCATE COMP "o_PMU2_AD5522_Reset" SITE "L20" ; +LOCATE COMP "o_PMU3_AD5522_Reset" SITE "C21" ; +LOCATE COMP "o_PMU4_AD5522_Reset" SITE "R21" ; +IOBUF PORT "o_PMU1_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_PMU2_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_PMU3_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_PMU4_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_con_done" IO_TYPE=LVCMOS25 ; diff --git a/CPLD3/RelayConTop.v b/CPLD3/RelayConTop.v index 324bf1b..6d694dc 100644 --- a/CPLD3/RelayConTop.v +++ b/CPLD3/RelayConTop.v @@ -11,6 +11,11 @@ module RelayConTop ( input i_wvalid, output [3:0]o_PMU_RC, + + output o_PMU1_AD5522_Reset, + output o_PMU2_AD5522_Reset, + output o_PMU3_AD5522_Reset, + output o_PMU4_AD5522_Reset, output o_wready, output o_err, @@ -42,6 +47,11 @@ module RelayConTop ( wire [23:0]DC_Con3 ; wire [23:0]DC_Con4 ; + //PMU AD5522 + wire [3:0]PMU_AD5522_Reset ; + + //DPS AD5522 + wire con_rvalid; wire con_done; @@ -105,9 +115,41 @@ module RelayConTop ( .o_err(cpld_err_flag) ); + AD5522_Con PMU1_AD5522( + .i_sys_clk(i_sys_clk), + .i_rst_n(i_rst_n), + .o_AD5522_Reset(PMU_AD5522_Reset[0]) + ); + + AD5522_Con PMU2_AD5522( + .i_sys_clk(i_sys_clk), + .i_rst_n(i_rst_n), + .o_AD5522_Reset(PMU_AD5522_Reset[1]) + ); + + AD5522_Con PMU3_AD5522( + .i_sys_clk(i_sys_clk), + .i_rst_n(i_rst_n), + .o_AD5522_Reset(PMU_AD5522_Reset[2]) + ); + + AD5522_Con PMU4_AD5522( + .i_sys_clk(i_sys_clk), + .i_rst_n(i_rst_n), + .o_AD5522_Reset(PMU_AD5522_Reset[3]) + ); + assign o_con_done = con_done; assign o_PMU_RC = PMU_RC; assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag; + + assign o_PMU1_AD5522_Reset = PMU_AD5522_Reset[0]; + + assign o_PMU2_AD5522_Reset = PMU_AD5522_Reset[1]; + + assign o_PMU3_AD5522_Reset = PMU_AD5522_Reset[2]; + + assign o_PMU4_AD5522_Reset = PMU_AD5522_Reset[3]; endmodule diff --git a/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf b/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf index cb8f15d..23af319 100644 --- a/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf +++ b/CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf @@ -1,5 +1,5 @@ # -# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R. +# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. # # Period Constraints