Feat: CPLD3: Add AD5522 Reset

This commit is contained in:
2026-06-16 16:20:53 +08:00
parent 37228e2bac
commit 8554c0aac3
6 changed files with 103 additions and 32 deletions
+1 -1
View File
@@ -2,7 +2,7 @@
<BaliProject version="3.2" title="NewExtIns_CPLD1" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop" top="RelayConTop"/>
<Options top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/>
</Source>
@@ -1,5 +1,5 @@
#
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
#
# Period Constraints