yuysh/NewInstrCalBoard_CPLD
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 2 Wiki Activity

Update gitignore

Browse Source
This commit is contained in:
Jeremy Shen
2026-05-27 17:40:07 +08:00
parent e3d13b3a43
commit 81e230066e
6 changed files with 42 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.gitignore
+1 -1
View File
@@ -9,13 +9,13 @@
# ---------- Build output ----------
impl1/
*_tcr.dir/
tb_RelayConTop
# ---------- Auto-generated junk ----------
# Lattice intermediate / absolute-path files
*.lst
*.naf
*.tcl
*.log
# QuestaSim / VCS simulation junk
*.ado
CPLD1/tb_RelayConTop/tb_RelayConTop.sort
+3
View File
@@ -0,0 +1,3 @@
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v
CPLD1/tb_RelayConTop/tb_RelayConTop.spf
+11
View File
@@ -0,0 +1,11 @@
<BaliSimProject version="1.3" path="." stage="1" language="1" name="tb_RelayConTop" simType="QuestaSim">
<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.vo" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
<Source worklib="work" path="RelayConTop_tf.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf" type="VERILOG" langstandard="" include="none"/>
<Sdf path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="/DUT" language="" name="tb_RelayConTop"/>
</BaliSimProject>
CPLD2/tb_RelayConTop/tb_RelayConTop.sort
+5
View File
@@ -0,0 +1,5 @@
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/CPLD_Con.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/Reg_file.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/BUS_Con.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/RelayConTop.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/tb_RelayConTop.sv
CPLD2/tb_RelayConTop/tb_RelayConTop.spf
+11
View File
@@ -0,0 +1,11 @@
<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_RelayConTop" simType="ModelSim">
<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="" include="none"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="" language="" name="tb_RelayConTop"/>
</BaliSimProject>
CPLD3/tb_RelayConTop/tb_RelayConTop.spf
+11
View File
@@ -0,0 +1,11 @@
<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_RelayConTop" simType="QuestaSim">
<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="" include="none"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="" language="" name="tb_RelayConTop"/>
</BaliSimProject>