diff --git a/.gitignore b/.gitignore
index 7456746..e071b10 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,13 +9,13 @@
 # ---------- Build output ----------
 impl1/
 *_tcr.dir/
-tb_RelayConTop
 
 # ---------- Auto-generated junk ----------
 # Lattice intermediate / absolute-path files
 *.lst
 *.naf
 *.tcl
+*.log
 
 # QuestaSim / VCS simulation junk
 *.ado
diff --git a/CPLD1/tb_RelayConTop/tb_RelayConTop.sort b/CPLD1/tb_RelayConTop/tb_RelayConTop.sort
new file mode 100644
index 0000000..878947f
--- /dev/null
+++ b/CPLD1/tb_RelayConTop/tb_RelayConTop.sort
@@ -0,0 +1,3 @@
+
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv
+/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v
diff --git a/CPLD1/tb_RelayConTop/tb_RelayConTop.spf b/CPLD1/tb_RelayConTop/tb_RelayConTop.spf
new file mode 100644
index 0000000..3bf77d2
--- /dev/null
+++ b/CPLD1/tb_RelayConTop/tb_RelayConTop.spf
@@ -0,0 +1,11 @@
+<BaliSimProject version="1.3" path="." stage="1" language="1" name="tb_RelayConTop" simType="QuestaSim">
+    <Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.vo" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
+    <Source worklib="work" path="RelayConTop_tf.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
+    <Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf" type="VERILOG" langstandard="" include="none"/>
+    <Sdf path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf"/>
+    <SimLib value="pmi_work ovi_machxo2"/>
+    <GlbInc value=""/>
+    <Macro value=""/>
+    <TopModule instance="/DUT" language="" name="tb_RelayConTop"/>
+</BaliSimProject>
diff --git a/CPLD2/tb_RelayConTop/tb_RelayConTop.sort b/CPLD2/tb_RelayConTop/tb_RelayConTop.sort
new file mode 100644
index 0000000..3d5d0e2
--- /dev/null
+++ b/CPLD2/tb_RelayConTop/tb_RelayConTop.sort
@@ -0,0 +1,5 @@
+D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/CPLD_Con.v
+D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/Reg_file.v
+D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/BUS_Con.v
+D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/RelayConTop.v
+D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/tb_RelayConTop.sv
diff --git a/CPLD2/tb_RelayConTop/tb_RelayConTop.spf b/CPLD2/tb_RelayConTop/tb_RelayConTop.spf
new file mode 100644
index 0000000..444331d
--- /dev/null
+++ b/CPLD2/tb_RelayConTop/tb_RelayConTop.spf
@@ -0,0 +1,11 @@
+<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_RelayConTop" simType="ModelSim">
+    <Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="" include="none"/>
+    <SimLib value="pmi_work ovi_machxo2"/>
+    <GlbInc value=""/>
+    <Macro value=""/>
+    <TopModule instance="" language="" name="tb_RelayConTop"/>
+</BaliSimProject>
diff --git a/CPLD3/tb_RelayConTop/tb_RelayConTop.spf b/CPLD3/tb_RelayConTop/tb_RelayConTop.spf
new file mode 100644
index 0000000..26e0796
--- /dev/null
+++ b/CPLD3/tb_RelayConTop/tb_RelayConTop.spf
@@ -0,0 +1,11 @@
+<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_RelayConTop" simType="QuestaSim">
+    <Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="" include="none"/>
+    <Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="" include="none"/>
+    <SimLib value="pmi_work ovi_machxo2"/>
+    <GlbInc value=""/>
+    <Macro value=""/>
+    <TopModule instance="" language="" name="tb_RelayConTop"/>
+</BaliSimProject>