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Update gitignore

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This commit is contained in:
Jeremy Shen
2026-05-27 17:40:07 +08:00
parent e3d13b3a43
commit 81e230066e
6 changed files with 42 additions and 1 deletions
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.gitignore
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@@ -9,13 +9,13 @@
# ---------- Build output ---------- # ---------- Build output ----------
impl1/ impl1/
*_tcr.dir/ *_tcr.dir/
tb_RelayConTop
# ---------- Auto-generated junk ---------- # ---------- Auto-generated junk ----------
# Lattice intermediate / absolute-path files # Lattice intermediate / absolute-path files
*.lst *.lst
*.naf *.naf
*.tcl *.tcl
*.log
# QuestaSim / VCS simulation junk # QuestaSim / VCS simulation junk
*.ado *.ado
CPLD1/tb_RelayConTop/tb_RelayConTop.sort
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/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v
CPLD1/tb_RelayConTop/tb_RelayConTop.spf
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<BaliSimProject version="1.3" path="." stage="1" language="1" name="tb_RelayConTop" simType="QuestaSim">
<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.vo" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
<Source worklib="work" path="RelayConTop_tf.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf" type="VERILOG" langstandard="" include="none"/>
<Sdf path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="/DUT" language="" name="tb_RelayConTop"/>
</BaliSimProject>
CPLD2/tb_RelayConTop/tb_RelayConTop.sort
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D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/CPLD_Con.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/Reg_file.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/BUS_Con.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/RelayConTop.v
D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/tb_RelayConTop.sv
CPLD2/tb_RelayConTop/tb_RelayConTop.spf
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<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_RelayConTop" simType="ModelSim">
<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="" include="none"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="" language="" name="tb_RelayConTop"/>
</BaliSimProject>
CPLD3/tb_RelayConTop/tb_RelayConTop.spf
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<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_RelayConTop" simType="QuestaSim">
<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="" include="none"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="" language="" name="tb_RelayConTop"/>
</BaliSimProject>