yuysh/NewInstrCalBoard_CPLD
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Update gitignore

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This commit is contained in:
Jeremy Shen
2026-05-27 17:40:07 +08:00
parent e3d13b3a43
commit 81e230066e
6 changed files with 42 additions and 1 deletions
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CPLD1/tb_RelayConTop/tb_RelayConTop.sort
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/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv
/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v
CPLD1/tb_RelayConTop/tb_RelayConTop.spf
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<BaliSimProject version="1.3" path="." stage="1" language="1" name="tb_RelayConTop" simType="QuestaSim">
<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.vo" type="VERILOG" langstandard="" include="none"/>
<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="System Verilog" include="none"/>
<Source worklib="work" path="RelayConTop_tf.v" type="VERILOG" langstandard="Verilog 2001" include="none"/>
<Source worklib="" path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf" type="VERILOG" langstandard="" include="none"/>
<Sdf path="impl1/NewExtIns_CPLD1_impl1_mapvo.sdf"/>
<SimLib value="pmi_work ovi_machxo2"/>
<GlbInc value=""/>
<Macro value=""/>
<TopModule instance="/DUT" language="" name="tb_RelayConTop"/>
</BaliSimProject>