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Fix RC_RLSel Shifting logic(2/?)

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yuysh
2026-06-02 18:33:16 +08:00
parent 9f47d03477
commit 607b43837d
1 changed files with 16 additions and 4 deletions
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CPLD1/CPLD_Con.v
+16 -4
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@@ -72,12 +72,16 @@ module CPLD_Con (
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17]; // RC_RL Shifter
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17]; // RC_RL Shifter
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17]; // RC_RL Shifter
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17]; // RC_RL Shifter
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
@@ -268,7 +272,9 @@ module CPLD_Con (
err_flag <= 1'b1;
end
else begin
RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con1[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con1[21:17] - 1)));
RC_RLSel <= (RC_RLShifter1 >= 1 && RC_RLShifter1 <= 18)
? ~(18'b1 << (RC_RLShifter1 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
@@ -290,7 +296,9 @@ module CPLD_Con (
err_flag <= 1'b1;
end
else begin
RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con2[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con2[21:17] - 1)));
RC_RLSel <= (RC_RLShifter2 >= 1 && RC_RLShifter2 <= 18)
? ~(18'b1 << (RC_RLShifter2 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
@@ -312,7 +320,9 @@ module CPLD_Con (
err_flag <= 1'b1;
end
else begin
RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con3[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con3[21:17] - 1)));
RC_RLSel <= (RC_RLShifter3 >= 1 && RC_RLShifter3 <= 18)
? ~(18'b1 << (RC_RLShifter3 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
@@ -334,7 +344,9 @@ module CPLD_Con (
err_flag <= 1'b1;
end
else begin
RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con4[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con4[21:17] - 1)));
RC_RLSel <= (RC_RLShifter4 >= 1 && RC_RLShifter4 <= 18)
? ~(18'b1 << (RC_RLShifter4 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);