Fix MISO Logic

2026-06-01 12:37:02 +08:00
parent 54a64ec222
commit 5b949c6b63
6 changed files with 48 additions and 39 deletions
@@ -8,7 +8,7 @@ module RelayConTop (
 	output o_miso,
 	output o_rvalid,
 	input i_rready,
-	input i_wvaild,
+	input i_wvalid,

 	output [3:0]o_PMU_RC,

@@ -42,7 +42,7 @@ module RelayConTop (
 	wire [23:0]DC_Con3 ;
 	wire [23:0]DC_Con4 ;

-	wire con_rvaild;
+	wire con_rvalid;
 	wire con_done;

 	BUS_Con Bus_Con_3(