diff --git a/CPLD1/BUS_Con.v b/CPLD1/BUS_Con.v index c28774e..94fc671 100644 --- a/CPLD1/BUS_Con.v +++ b/CPLD1/BUS_Con.v @@ -83,12 +83,13 @@ module BUS_Con ( data_ready <= 1'b0; err_flag <= 1'b0; end - else begin - data_ready <= 1'b0; - + else begin if (cs_active) begin if (sclk_rise) begin recv_reg <= {recv_reg[30:0], mosi_data}; + if (bit_cnt == 6'd31) begin + data_ready <= 1'b1; + end bit_cnt <= bit_cnt + 1'b1; end else if (cs_rise) begin @@ -107,7 +108,7 @@ module BUS_Con ( if (state == DONE) begin recv_reg <= 'd0; end - end + end end // --- 3. MISO (Transmit) Logic --- @@ -134,14 +135,15 @@ module BUS_Con ( miso_shift <= 32'd0; end else begin if (!cs_active) begin - // Pre-load the shifter while CS is High - // This ensures Bit 31 is ready BEFORE the first clock edge - miso_shift <= tx_buffer; - end else begin + // Reset shifter while CS is High + miso_shift <= 32'd0; + end else if (sclk_fall) begin // Shift on Falling Edge (Master samples on Rising) - if (sclk_fall) begin - miso_shift <= {miso_shift[30:0], 1'b0}; - end + miso_shift <= {miso_shift[30:0], 1'b0}; + end + // Load register data when read completes (takes priority over shift) + if (i_rvalid) begin + miso_shift <= {8'h00, i_rdata}; end end end @@ -185,6 +187,7 @@ module BUS_Con ( CMD_SENT: begin cmd_valid_out <= 1'b0; + data_ready <= 1'b0; // Clear data_ready when FSM consumes it state <= DONE; end diff --git a/CPLD2/BUS_Con.v b/CPLD2/BUS_Con.v index 82c450f..5b5c63b 100644 --- a/CPLD2/BUS_Con.v +++ b/CPLD2/BUS_Con.v @@ -83,12 +83,13 @@ module BUS_Con ( data_ready <= 1'b0; err_flag <= 1'b0; end - else begin - data_ready <= 1'b0; - + else begin if (cs_active) begin if (sclk_rise) begin recv_reg <= {recv_reg[30:0], mosi_data}; + if (bit_cnt == 6'd31) begin + data_ready <= 1'b1; + end bit_cnt <= bit_cnt + 1'b1; end else if (cs_rise) begin @@ -107,7 +108,7 @@ module BUS_Con ( if (state == DONE) begin recv_reg <= 'd0; end - end + end end // --- 3. MISO (Transmit) Logic --- @@ -134,14 +135,15 @@ module BUS_Con ( miso_shift <= 32'd0; end else begin if (!cs_active) begin - // Pre-load the shifter while CS is High - // This ensures Bit 31 is ready BEFORE the first clock edge - miso_shift <= tx_buffer; - end else begin + // Reset shifter while CS is High + miso_shift <= 32'd0; + end else if (sclk_fall) begin // Shift on Falling Edge (Master samples on Rising) - if (sclk_fall) begin - miso_shift <= {miso_shift[30:0], 1'b0}; - end + miso_shift <= {miso_shift[30:0], 1'b0}; + end + // Load register data when read completes (takes priority over shift) + if (i_rvalid) begin + miso_shift <= {8'h00, i_rdata}; end end end @@ -187,6 +189,7 @@ module BUS_Con ( CMD_SENT: begin cmd_valid_out <= 1'b0; + data_ready <= 1'b0; // Clear data_ready when FSM consumes it state <= DONE; end diff --git a/CPLD3/BUS_Con.v b/CPLD3/BUS_Con.v index cc61c73..5b5c63b 100644 --- a/CPLD3/BUS_Con.v +++ b/CPLD3/BUS_Con.v @@ -83,12 +83,13 @@ module BUS_Con ( data_ready <= 1'b0; err_flag <= 1'b0; end - else begin - data_ready <= 1'b0; - + else begin if (cs_active) begin if (sclk_rise) begin recv_reg <= {recv_reg[30:0], mosi_data}; + if (bit_cnt == 6'd31) begin + data_ready <= 1'b1; + end bit_cnt <= bit_cnt + 1'b1; end else if (cs_rise) begin @@ -107,7 +108,7 @@ module BUS_Con ( if (state == DONE) begin recv_reg <= 'd0; end - end + end end // --- 3. MISO (Transmit) Logic --- @@ -134,14 +135,15 @@ module BUS_Con ( miso_shift <= 32'd0; end else begin if (!cs_active) begin - // Pre-load the shifter while CS is High - // This ensures Bit 31 is ready BEFORE the first clock edge - miso_shift <= tx_buffer; - end else begin + // Reset shifter while CS is High + miso_shift <= 32'd0; + end else if (sclk_fall) begin // Shift on Falling Edge (Master samples on Rising) - if (sclk_fall) begin - miso_shift <= {miso_shift[30:0], 1'b0}; - end + miso_shift <= {miso_shift[30:0], 1'b0}; + end + // Load register data when read completes (takes priority over shift) + if (i_rvalid) begin + miso_shift <= {8'h00, i_rdata}; end end end @@ -187,6 +189,7 @@ module BUS_Con ( CMD_SENT: begin cmd_valid_out <= 1'b0; + data_ready <= 1'b0; // Clear data_ready when FSM consumes it state <= DONE; end @@ -210,6 +213,6 @@ module BUS_Con ( assign o_wready = (state == IDLE); // Pass through unused signal or hook it up if needed - assign o_rvalid = 1'b0; + assign o_rvalid = i_rvalid; endmodule \ No newline at end of file diff --git a/CPLD3/NewExtIns_CPLD3.lpf b/CPLD3/NewExtIns_CPLD3.lpf index ef512d7..417ce08 100644 --- a/CPLD3/NewExtIns_CPLD3.lpf +++ b/CPLD3/NewExtIns_CPLD3.lpf @@ -1,4 +1,4 @@ -rvl_alias "i_sys_clk" "i_sys_clk"; +rvl_alias "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; @@ -13,7 +13,7 @@ IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; -IOBUF PORT "o_rvaild" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; diff --git a/CPLD3/Reg_file.v b/CPLD3/Reg_file.v index 8f00652..3dc0fc8 100644 --- a/CPLD3/Reg_file.v +++ b/CPLD3/Reg_file.v @@ -33,7 +33,7 @@ module Reg_file ( // --- Parameters --- localparam REG_COUNT = 16; localparam [23:0] - IDENT = 24'h800000 | 12'b0001_0000_0000, //CPLD3==1,version=1.0.0 + IDENT = 24'h800000 | 12'b0001_1000_0000, //CPLD3==1,version=1.1.0 STATE_INIT = 24'h800000; // State Machine Definition diff --git a/CPLD3/RelayConTop.v b/CPLD3/RelayConTop.v index 9c7aeb6..324bf1b 100644 --- a/CPLD3/RelayConTop.v +++ b/CPLD3/RelayConTop.v @@ -8,7 +8,7 @@ module RelayConTop ( output o_miso, output o_rvalid, input i_rready, - input i_wvaild, + input i_wvalid, output [3:0]o_PMU_RC, @@ -42,7 +42,7 @@ module RelayConTop ( wire [23:0]DC_Con3 ; wire [23:0]DC_Con4 ; - wire con_rvaild; + wire con_rvalid; wire con_done; BUS_Con Bus_Con_3(