Fix MISO Logic

CPLD2/BUS_Con.v

@@ -83,12 +83,13 @@ module BUS_Con (
             data_ready    <= 1'b0;
             err_flag      <= 1'b0;
         end 
-		else begin
-            data_ready <= 1'b0; 
-
+       else begin
             if (cs_active) begin
                 if (sclk_rise) begin
                     recv_reg <= {recv_reg[30:0], mosi_data}; 
+                    if (bit_cnt == 6'd31) begin
+                        data_ready <= 1'b1;
+                    end
                     bit_cnt  <= bit_cnt + 1'b1;
                 end
 				else if (cs_rise) begin
@@ -107,7 +108,7 @@ module BUS_Con (
             if (state == DONE) begin
                 recv_reg <= 'd0;
             end
-        end
+        end
     end
 
     // --- 3. MISO (Transmit) Logic ---
@@ -134,14 +135,15 @@ module BUS_Con (
             miso_shift <= 32'd0;
         end else begin
             if (!cs_active) begin
-                // Pre-load the shifter while CS is High
-                // This ensures Bit 31 is ready BEFORE the first clock edge
-                miso_shift <= tx_buffer;
-            end else begin
+                // Reset shifter while CS is High
+                miso_shift <= 32'd0;
+            end else if (sclk_fall) begin
                 // Shift on Falling Edge (Master samples on Rising)
-                if (sclk_fall) begin
-                    miso_shift <= {miso_shift[30:0], 1'b0};
-                end
+                miso_shift <= {miso_shift[30:0], 1'b0};
+            end
+            // Load register data when read completes (takes priority over shift)
+            if (i_rvalid) begin
+                miso_shift <= {8'h00, i_rdata};
             end
         end
     end
@@ -187,6 +189,7 @@ module BUS_Con (
 
                 CMD_SENT: begin
                     cmd_valid_out <= 1'b0;
+                    data_ready    <= 1'b0;  // Clear data_ready when FSM consumes it
                     state         <= DONE;
                 end