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Modify simulation files

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yuysh
2026-05-29 16:32:58 +08:00
parent 611945be04
commit 3e722a7f15
24 changed files with 17150 additions and 20488 deletions
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CPLD3/impl1/impl1.xcf
+4 -4
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@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
<FileTime>01/19/26 18:24:04</FileTime>
<JedecChecksum>0x4480</JedecChecksum>
<File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
<FileTime>05/29/26 16:05:22</FileTime>
<JedecChecksum>0xA758</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions>
</ispXCF>