yuysh/NewInstrCalBoard_CPLD
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Modify simulation files

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yuysh
2026-05-29 16:32:58 +08:00
parent 611945be04
commit 3e722a7f15
24 changed files with 17150 additions and 20488 deletions
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CPLD3/debug.rvl
+5 -4
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@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26">
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532996" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="695927056" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -12,9 +12,9 @@
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="Bus_Con_3/i_cs"/>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="Bus_Con_3/i_mosi"/>
<Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
@@ -126,7 +126,8 @@
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
</Trigger>
</Dataset>