Modify simulation files

This commit is contained in:
2026-05-29 16:32:58 +08:00
parent 611945be04
commit 3e722a7f15
24 changed files with 17150 additions and 20488 deletions
+107 -57
View File
@@ -27,75 +27,125 @@
<WinUI CoreIndex="0">
<TraceSigTreeData>
<TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="i_cs" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="i_mosi" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="i_sclk" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag" NodeType="1" PortIndex="4">
<TraceSignal IsHidden="false" Name="Bus_Con_3/i_cs" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="Bus_Con_3/i_sclk" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="Bus_Con_3/i_mosi" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="Bus_Con_3/err_flag" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/err_flag" NodeType="0" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/err_flag" NodeType="0" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_con_exec" NodeType="0" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1" NodeType="1" PortIndex="8">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:0" NodeType="2" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:1" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:2" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:3" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC" NodeType="1" PortIndex="8">
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:0" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:1" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:2" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:3" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:4" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:5" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:6" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:7" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:8" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:9" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:10" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:11" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:12" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:13" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:14" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:15" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:16" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:17" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:18" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:19" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:20" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:21" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:22" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:23" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2" NodeType="1" PortIndex="32">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:0" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:1" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:2" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:3" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out" NodeType="1" PortIndex="12">
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:0" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:1" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:2" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:3" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:4" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:5" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:6" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:7" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:8" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:9" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:10" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:11" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:12" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:13" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:14" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:15" NodeType="2" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:16" NodeType="2" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:17" NodeType="2" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:18" NodeType="2" PortIndex="50"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:19" NodeType="2" PortIndex="51"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:20" NodeType="2" PortIndex="52"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:21" NodeType="2" PortIndex="53"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:22" NodeType="2" PortIndex="54"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:23" NodeType="2" PortIndex="55"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3" NodeType="1" PortIndex="56">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:0" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:1" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:2" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:3" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:4" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:5" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:6" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out" NodeType="1" PortIndex="19">
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:0" NodeType="2" PortIndex="56"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:1" NodeType="2" PortIndex="57"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:2" NodeType="2" PortIndex="58"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:3" NodeType="2" PortIndex="59"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:4" NodeType="2" PortIndex="60"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:5" NodeType="2" PortIndex="61"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:6" NodeType="2" PortIndex="62"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:7" NodeType="2" PortIndex="63"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:8" NodeType="2" PortIndex="64"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:9" NodeType="2" PortIndex="65"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:10" NodeType="2" PortIndex="66"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:11" NodeType="2" PortIndex="67"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:12" NodeType="2" PortIndex="68"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:13" NodeType="2" PortIndex="69"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:14" NodeType="2" PortIndex="70"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:15" NodeType="2" PortIndex="71"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:16" NodeType="2" PortIndex="72"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:17" NodeType="2" PortIndex="73"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:18" NodeType="2" PortIndex="74"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:19" NodeType="2" PortIndex="75"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:20" NodeType="2" PortIndex="76"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:21" NodeType="2" PortIndex="77"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:22" NodeType="2" PortIndex="78"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:23" NodeType="2" PortIndex="79"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4" NodeType="1" PortIndex="80">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:0" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:1" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:2" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:3" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:4" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:5" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:6" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:7" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:8" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:9" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:10" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:11" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:12" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:13" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:14" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:15" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:16" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:17" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:18" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:19" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:20" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:21" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:22" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:23" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state" NodeType="1" PortIndex="43">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:0" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:1" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:2" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:3" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/i_con_done" NodeType="0" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/busy_flag" NodeType="0" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/exec_bit" NodeType="0" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:0" NodeType="2" PortIndex="80"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:1" NodeType="2" PortIndex="81"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:2" NodeType="2" PortIndex="82"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:3" NodeType="2" PortIndex="83"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:4" NodeType="2" PortIndex="84"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:5" NodeType="2" PortIndex="85"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:6" NodeType="2" PortIndex="86"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:7" NodeType="2" PortIndex="87"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:8" NodeType="2" PortIndex="88"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:9" NodeType="2" PortIndex="89"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:10" NodeType="2" PortIndex="90"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:11" NodeType="2" PortIndex="91"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:12" NodeType="2" PortIndex="92"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:13" NodeType="2" PortIndex="93"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:14" NodeType="2" PortIndex="94"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:15" NodeType="2" PortIndex="95"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:16" NodeType="2" PortIndex="96"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:17" NodeType="2" PortIndex="97"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:18" NodeType="2" PortIndex="98"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:19" NodeType="2" PortIndex="99"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:20" NodeType="2" PortIndex="100"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:21" NodeType="2" PortIndex="101"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:22" NodeType="2" PortIndex="102"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:23" NodeType="2" PortIndex="103"/>
</TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/>
File diff suppressed because one or more lines are too long
+2051 -2051
View File
File diff suppressed because it is too large Load Diff
+5 -4
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26">
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695532996" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="695927056" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -12,9 +12,9 @@
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="Bus_Con_3/i_cs"/>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="Bus_Con_3/i_mosi"/>
<Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
@@ -126,7 +126,8 @@
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="con_exec,"/>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
</Trigger>
</Dataset>
+129 -128
View File
@@ -1,129 +1,130 @@
<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/debug.rvl" Date="2026-05-26">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="Bus_Con_3/i_sclk"/>
<Sig Name="i_rst_n"/>
<Sig Name="Bus_Con_3/i_cs"/>
<Sig Name="Bus_Con_3/i_mosi"/>
<Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con1:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="6" Name="TU1" ID="1" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
</Trigger>
</Dataset>
</Core>
<Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvs" Date="2026-05-29">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="i_rst_n"/>
<Sig Name="Bus_Con_3/i_cs"/>
<Sig Name="Bus_Con_3/i_sclk"/>
<Sig Name="Bus_Con_3/i_mosi"/>
<Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con1:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="7" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
</Trigger>
</Dataset>
</Core>
</Project>
Binary file not shown.
File diff suppressed because it is too large Load Diff
@@ -1,5 +1,5 @@
#
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
#
# Period Constraints
+4 -4
View File
@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
<FileTime>01/19/26 18:24:04</FileTime>
<JedecChecksum>0x4480</JedecChecksum>
<File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
<FileTime>05/29/26 16:05:22</FileTime>
<JedecChecksum>0xA758</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions>
</ispXCF>