Modify simulation files
This commit is contained in:
+107
-39
@@ -1,7 +1,7 @@
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<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26">
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<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29">
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<IP Version="1_6_042617"/>
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<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
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<Core InsertDataset="0" Insert="1" Reveal_sig="695532641" Name="RelayConTop_LA0" ID="0">
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<Core InsertDataset="0" Insert="1" Reveal_sig="695926902" Name="RelayConTop_LA0" ID="0">
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<Setting>
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<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
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<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
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@@ -16,46 +16,114 @@
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<Sig Type="SIG" Name="BUS_Con_2/i_cs"/>
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<Sig Type="SIG" Name="BUS_Con_2/i_sclk"/>
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<Sig Type="SIG" Name="BUS_Con_2/i_mosi"/>
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<Sig Type="SIG" Name="BUS_Con_2/i_reg_busy"/>
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<Sig Type="SIG" Name="CPLD_Reg_2/o_exec"/>
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<Bus Name="RC_T">
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<Sig Type="SIG" Name="RC_T:0"/>
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<Sig Type="SIG" Name="RC_T:1"/>
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<Sig Type="SIG" Name="RC_T:2"/>
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<Sig Type="SIG" Name="RC_T:3"/>
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<Sig Type="SIG" Name="RC_T:4"/>
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<Sig Type="SIG" Name="RC_T:5"/>
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<Sig Type="SIG" Name="RC_T:6"/>
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<Sig Type="SIG" Name="RC_T:7"/>
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<Sig Type="SIG" Name="RC_T:8"/>
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<Sig Type="SIG" Name="RC_T:9"/>
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<Sig Type="SIG" Name="RC_T:10"/>
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<Sig Type="SIG" Name="RC_T:11"/>
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<Sig Type="SIG" Name="RC_T:12"/>
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<Sig Type="SIG" Name="RC_T:13"/>
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<Sig Type="SIG" Name="RC_T:14"/>
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<Sig Type="SIG" Name="RC_T:15"/>
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<Sig Type="SIG" Name="RC_T:16"/>
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<Sig Type="SIG" Name="RC_T:17"/>
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<Sig Type="SIG" Name="RC_T:18"/>
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<Sig Type="SIG" Name="RC_T:19"/>
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<Sig Type="SIG" Name="RC_T:20"/>
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<Sig Type="SIG" Name="RC_T:21"/>
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<Sig Type="SIG" Name="RC_T:22"/>
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<Sig Type="SIG" Name="RC_T:23"/>
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<Sig Type="SIG" Name="RC_T:24"/>
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<Sig Type="SIG" Name="RC_T:25"/>
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<Sig Type="SIG" Name="RC_T:26"/>
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<Sig Type="SIG" Name="RC_T:27"/>
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<Sig Type="SIG" Name="RC_T:28"/>
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<Sig Type="SIG" Name="RC_T:29"/>
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<Sig Type="SIG" Name="RC_T:30"/>
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<Sig Type="SIG" Name="RC_T:31"/>
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</Bus>
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<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
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<Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
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<Bus Name="DC_Con1">
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<Sig Type="SIG" Name="DC_Con1:0"/>
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<Sig Type="SIG" Name="DC_Con1:1"/>
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<Sig Type="SIG" Name="DC_Con1:2"/>
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<Sig Type="SIG" Name="DC_Con1:3"/>
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<Sig Type="SIG" Name="DC_Con1:4"/>
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<Sig Type="SIG" Name="DC_Con1:5"/>
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<Sig Type="SIG" Name="DC_Con1:6"/>
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<Sig Type="SIG" Name="DC_Con1:7"/>
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<Sig Type="SIG" Name="DC_Con1:8"/>
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<Sig Type="SIG" Name="DC_Con1:9"/>
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<Sig Type="SIG" Name="DC_Con1:10"/>
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<Sig Type="SIG" Name="DC_Con1:11"/>
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<Sig Type="SIG" Name="DC_Con1:12"/>
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<Sig Type="SIG" Name="DC_Con1:13"/>
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<Sig Type="SIG" Name="DC_Con1:14"/>
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<Sig Type="SIG" Name="DC_Con1:15"/>
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<Sig Type="SIG" Name="DC_Con1:16"/>
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<Sig Type="SIG" Name="DC_Con1:17"/>
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<Sig Type="SIG" Name="DC_Con1:18"/>
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<Sig Type="SIG" Name="DC_Con1:19"/>
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<Sig Type="SIG" Name="DC_Con1:20"/>
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<Sig Type="SIG" Name="DC_Con1:21"/>
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<Sig Type="SIG" Name="DC_Con1:22"/>
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<Sig Type="SIG" Name="DC_Con1:23"/>
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</Bus>
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<Bus Name="DC_Con2">
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<Sig Type="SIG" Name="DC_Con2:0"/>
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<Sig Type="SIG" Name="DC_Con2:1"/>
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<Sig Type="SIG" Name="DC_Con2:2"/>
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<Sig Type="SIG" Name="DC_Con2:3"/>
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<Sig Type="SIG" Name="DC_Con2:4"/>
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<Sig Type="SIG" Name="DC_Con2:5"/>
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<Sig Type="SIG" Name="DC_Con2:6"/>
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<Sig Type="SIG" Name="DC_Con2:7"/>
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<Sig Type="SIG" Name="DC_Con2:8"/>
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<Sig Type="SIG" Name="DC_Con2:9"/>
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<Sig Type="SIG" Name="DC_Con2:10"/>
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<Sig Type="SIG" Name="DC_Con2:11"/>
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<Sig Type="SIG" Name="DC_Con2:12"/>
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<Sig Type="SIG" Name="DC_Con2:13"/>
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<Sig Type="SIG" Name="DC_Con2:14"/>
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<Sig Type="SIG" Name="DC_Con2:15"/>
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<Sig Type="SIG" Name="DC_Con2:16"/>
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<Sig Type="SIG" Name="DC_Con2:17"/>
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<Sig Type="SIG" Name="DC_Con2:18"/>
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<Sig Type="SIG" Name="DC_Con2:19"/>
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<Sig Type="SIG" Name="DC_Con2:20"/>
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<Sig Type="SIG" Name="DC_Con2:21"/>
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<Sig Type="SIG" Name="DC_Con2:22"/>
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<Sig Type="SIG" Name="DC_Con2:23"/>
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</Bus>
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<Bus Name="DC_Con3">
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<Sig Type="SIG" Name="DC_Con3:0"/>
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<Sig Type="SIG" Name="DC_Con3:1"/>
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<Sig Type="SIG" Name="DC_Con3:2"/>
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<Sig Type="SIG" Name="DC_Con3:3"/>
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<Sig Type="SIG" Name="DC_Con3:4"/>
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<Sig Type="SIG" Name="DC_Con3:5"/>
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<Sig Type="SIG" Name="DC_Con3:6"/>
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<Sig Type="SIG" Name="DC_Con3:7"/>
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<Sig Type="SIG" Name="DC_Con3:8"/>
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<Sig Type="SIG" Name="DC_Con3:9"/>
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<Sig Type="SIG" Name="DC_Con3:10"/>
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<Sig Type="SIG" Name="DC_Con3:11"/>
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<Sig Type="SIG" Name="DC_Con3:12"/>
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<Sig Type="SIG" Name="DC_Con3:13"/>
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<Sig Type="SIG" Name="DC_Con3:14"/>
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<Sig Type="SIG" Name="DC_Con3:15"/>
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<Sig Type="SIG" Name="DC_Con3:16"/>
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<Sig Type="SIG" Name="DC_Con3:17"/>
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<Sig Type="SIG" Name="DC_Con3:18"/>
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<Sig Type="SIG" Name="DC_Con3:19"/>
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<Sig Type="SIG" Name="DC_Con3:20"/>
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<Sig Type="SIG" Name="DC_Con3:21"/>
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<Sig Type="SIG" Name="DC_Con3:22"/>
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<Sig Type="SIG" Name="DC_Con3:23"/>
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</Bus>
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<Bus Name="DC_Con4">
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<Sig Type="SIG" Name="DC_Con4:0"/>
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<Sig Type="SIG" Name="DC_Con4:1"/>
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<Sig Type="SIG" Name="DC_Con4:2"/>
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<Sig Type="SIG" Name="DC_Con4:3"/>
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<Sig Type="SIG" Name="DC_Con4:4"/>
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<Sig Type="SIG" Name="DC_Con4:5"/>
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<Sig Type="SIG" Name="DC_Con4:6"/>
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<Sig Type="SIG" Name="DC_Con4:7"/>
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<Sig Type="SIG" Name="DC_Con4:8"/>
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<Sig Type="SIG" Name="DC_Con4:9"/>
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<Sig Type="SIG" Name="DC_Con4:10"/>
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<Sig Type="SIG" Name="DC_Con4:11"/>
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<Sig Type="SIG" Name="DC_Con4:12"/>
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<Sig Type="SIG" Name="DC_Con4:13"/>
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<Sig Type="SIG" Name="DC_Con4:14"/>
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<Sig Type="SIG" Name="DC_Con4:15"/>
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<Sig Type="SIG" Name="DC_Con4:16"/>
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<Sig Type="SIG" Name="DC_Con4:17"/>
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<Sig Type="SIG" Name="DC_Con4:18"/>
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<Sig Type="SIG" Name="DC_Con4:19"/>
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<Sig Type="SIG" Name="DC_Con4:20"/>
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<Sig Type="SIG" Name="DC_Con4:21"/>
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<Sig Type="SIG" Name="DC_Con4:22"/>
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<Sig Type="SIG" Name="DC_Con4:23"/>
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</Bus>
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</Trace>
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<Trigger>
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<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
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