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Unify the OC_Con logic

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yuysh
2026-06-05 16:49:20 +08:00
parent 607b43837d
commit 36e6eb5768
2 changed files with 83 additions and 86 deletions
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CPLD1/RelayConTop.v
+11 -24
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@@ -79,6 +79,9 @@ module RelayConTop (
//DMM I Select
wire RC_ISel;
//Force/Sense Control
wire [1:0]RC_LOFS ;
wire con_rvalid;
wire con_done;
@@ -139,8 +142,6 @@ module RelayConTop (
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.o_con_done(con_done),
.o_OC_x01(OC_x01),
.o_OC_x17(OC_x17),
.o_RC_Tx(RC_Tx),
.o_DMM_EN(DMM_EN),
.o_PMU_OC_1(PMU_OC_1),
@@ -149,35 +150,21 @@ module RelayConTop (
.o_PMU_OC_4(PMU_OC_4),
.o_RC_VSel(RC_VSel),
.o_RC_ISel(RC_ISel),
.o_RC_LOFS(RC_LOFS),
.o_RC_RLSel(RC_RLSel),
.o_IO_RC1(IO_RC1),
.o_err(cpld_err_flag)
);
assign o_con_done = con_done;
//assign o_OC_x01 = OC_x01;
assign o_PMU_OC_1[0] = OC_x01[0];
assign o_PMU_OC_2[0] = OC_x01[1];
assign o_PMU_OC_3[0] = OC_x01[2];
assign o_PMU_OC_4[0] = OC_x01[3];
//assign o_OC_x17 = OC_x17;
assign o_PMU_OC_1[16] = OC_x17[0];
assign o_PMU_OC_2[16] = OC_x17[1];
assign o_PMU_OC_3[16] = OC_x17[2];
assign o_PMU_OC_4[16] = OC_x17[3];
assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
assign o_PMU_OC_1 = PMU_OC_1;
assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
assign o_PMU_OC_2 = PMU_OC_2;
assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4;
assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1;
@@ -193,8 +180,8 @@ module RelayConTop (
assign o_RC_VSel = RC_VSel;
assign o_RC_ISel = RC_ISel;
assign o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10; //if Measure V then close RC_LOF[0]
assign o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10;
assign o_RC_LOF = RC_LOFS;
assign o_RC_LOS = RC_LOFS;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;