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Unify the OC_Con logic

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yuysh
2026-06-05 16:49:20 +08:00
parent 607b43837d
commit 36e6eb5768
2 changed files with 83 additions and 86 deletions
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CPLD1/CPLD_Con.v
+72 -62
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@@ -16,8 +16,6 @@ module CPLD_Con (
input [23:0]i_DC_Con4,
//Output RELAYs
output [3:0]o_OC_x01,
output [3:0]o_OC_x17,
output [18:0]o_DMM_EN,
output o_IO_RC1,
output [5:0]o_RC_Tx,
@@ -31,6 +29,9 @@ module CPLD_Con (
output o_RC_VSel,
output o_RC_ISel,
// Force/Sense Control
output [1:0]o_RC_LOFS,
// Output RLoad Sel
output [17:0]o_RC_RLSel,
@@ -47,7 +48,9 @@ module CPLD_Con (
reg[5:0]RC_Tx;
reg io_RC;
reg RC_VISel;
reg RC_VSel;
reg RC_ISel;
reg [1:0]RC_LOFS;
reg [17:0]RC_RLSel ;
reg [31:0]PMU_OC_1 ;
reg [31:0]PMU_OC_2 ;
@@ -82,6 +85,8 @@ module CPLD_Con (
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7]; // Channel Number div 64
wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17]; // RC_RL Shifter
wire [3:0]DC_OC1 = {PMU_OC_4[0],PMU_OC_3[0],PMU_OC_2[0],PMU_OC_1[0]} ;
wire [3:0]DC_OC17 = {PMU_OC_4[16],PMU_OC_3[16],PMU_OC_2[16],PMU_OC_1[16]} ;
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
@@ -120,12 +125,11 @@ module CPLD_Con (
freq_slot_flag <= 'd0;
dc_slot_flag <= 'd0;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
DMM_en <= 'd0;
RC_VISel <='d0;
RC_VSel <= 'd1; //Vpk HIGH Disable, LOW Enable
RC_ISel <= 'd1; //Apk HIGH Disable, LOW Enable
RC_LOFS <= 'hf; //HIGH Disable, LOW Enable
RC_RLSel <='hfffff;
PMU_OC_1 <= 'd0 ;
@@ -165,95 +169,81 @@ module CPLD_Con (
case (freq_slot_flag)
4'b0001: begin
if (i_freq_relay1[9:1] < 9) begin
OC_x01 <= 4'b0001;
OC_x17 <= 'd0;
PMU_OC_1 <= 'd1;
DMM_en <= 19'b000_0000_0000_0000_0001;
end
else if (i_freq_relay1[9:1] < 73) begin
DMM_en <= 19'b000_0000_0000_0000_0010;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
PMU_OC_1 <= 'd0;
end
else if (i_freq_relay1[9:1] < 137) begin
OC_x17 <= 4'b0001;
OC_x01 <= 'd0;
PMU_OC_1 <= 1'b1 << 16;
DMM_en <= 19'b000_0000_0000_0000_0100;
end
else begin
DMM_en <= 19'b000_0000_0000_0000_1000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
PMU_OC_1 <= 'd0;
end
end
4'b0010: begin
if (i_freq_relay2[9:1] < 9) begin
OC_x01 <= 4'b0010;
OC_x17 <= 'd0;
PMU_OC_2 <= 'd1;
DMM_en <= 19'b000_0000_0000_0001_0000;
end
else if (i_freq_relay2[9:1] < 73) begin
DMM_en <= 19'b000_0000_0000_0010_0000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
PMU_OC_2 <= 'd0;
end
else if (i_freq_relay2[9:1] < 137) begin
OC_x17 <= 4'b0010;
OC_x01 <= 'd0;
PMU_OC_2 <= 1'b1 << 16;
DMM_en <= 19'b000_0000_0000_0100_0000;
end
else begin
OC_x01 <= 'd0;
OC_x17 <= 'd0;
PMU_OC_2 <= 'd0;
DMM_en <= 19'b000_0000_0000_1000_0000;
end
end
4'b0100: begin
if (i_freq_relay3[9:1] < 9) begin
OC_x01 <= 'b0100;
OC_x17 <= 'd0;
PMU_OC_3 <= 'd1;
DMM_en <= 19'b000_0000_0001_0000_0000;
end
else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
OC_x01 <= 4'b0000;
OC_x17 <= 'd0;
PMU_OC_3 <= 'd0;
DMM_en <= 19'b000_0000_0010_0000_0000;
end
else if (i_freq_relay3[9:1] < 137) begin
DMM_en <= 19'b000_0000_0100_0000_0000;
OC_x01 <= 'd0;
OC_x17 <= 'b0100;
PMU_OC_3 <= 1'b1 << 16;
end
else if (i_freq_relay3[9:1] < 201) begin
OC_x17 <= 4'd0;
OC_x01 <= 'd0;
PMU_OC_3 <= 'd0;
DMM_en <= 19'b000_0000_1000_0000_0000;
end
end
4'b1000: begin
if (i_freq_relay4[9:1] < 9) begin
OC_x01 <= 4'b1000;
OC_x17 <= 'd0;
PMU_OC_4 <= 'd1;
DMM_en <= 19'b000_0001_0000_0000_0000;
end
else if (i_freq_relay4[9:1] < 72) begin
DMM_en <= 19'b000_0010_0000_0000_0000;
OC_x01 <= 'd0;
OC_x17 <= 'd0;
PMU_OC_4 <= 'd0;
end
else if (i_freq_relay4[9:1] < 137) begin
OC_x17 <= 4'b1000;
OC_x01 <= 'd0;
PMU_OC_4 <= 1'b1 << 16;
DMM_en <= 19'b000_0100_0000_0000_0000;
end
else begin
OC_x01 <= 'd0;
OC_x17 <= 'd0;
PMU_OC_4 <= 'd0;
DMM_en <= 19'b000_1000_0000_0000_0000;
end
end
default: begin // You Should NOT be HERE
OC_x01 <= 4'b0000;
OC_x17 <= 4'b0000;
PMU_OC_1 <= 'd0;
PMU_OC_2 <= 'd0;
PMU_OC_3 <= 'd0;
PMU_OC_4 <= 'd0;
DMM_en <= 'd0;
end
endcase
@@ -261,11 +251,16 @@ module CPLD_Con (
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
//Here Set Mode and F/S
if (i_DC_Con1[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end
else begin
RC_VISel <= 1'b0; //Select Voltage
RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end
//Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
@@ -274,7 +269,7 @@ module CPLD_Con (
else begin
RC_RLSel <= (RC_RLShifter1 >= 1 && RC_RLShifter1 <= 18)
? ~(18'b1 << (RC_RLShifter1 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
: 18'h3FFFF; //Set RLoad
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
@@ -286,10 +281,14 @@ module CPLD_Con (
end
4'b0010: begin
if (i_DC_Con2[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end
else begin
RC_VISel <= 1'b0; //Select Voltage
RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end
//Sanity Check
if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
@@ -298,7 +297,7 @@ module CPLD_Con (
else begin
RC_RLSel <= (RC_RLShifter2 >= 1 && RC_RLShifter2 <= 18)
? ~(18'b1 << (RC_RLShifter2 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
: 18'h3FFFF; // 否则�1（即不置 0�
if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
@@ -310,10 +309,14 @@ module CPLD_Con (
end
4'b0100:begin
if (i_DC_Con3[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end
else begin
RC_VISel <= 1'b0; //Select Voltage
RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end
//Sanity Check
if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
@@ -322,7 +325,7 @@ module CPLD_Con (
else begin
RC_RLSel <= (RC_RLShifter3 >= 1 && RC_RLShifter3 <= 18)
? ~(18'b1 << (RC_RLShifter3 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
: 18'h3FFFF; // 否则�1（即不置 0�
if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
@@ -334,10 +337,14 @@ module CPLD_Con (
end
4'b1000:begin
if (i_DC_Con4[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
RC_VSel <= 1'b1; //Select Current
RC_ISel <= 1'b0;
RC_LOFS <= 2'b01;
end
else begin
RC_VISel <= 1'b0; //Select Voltage
RC_VSel <= 1'b0; //Select Voltage
RC_ISel <= 1'b1;
RC_LOFS <= 2'b10;
end
//Sanity Check
if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
@@ -346,7 +353,7 @@ module CPLD_Con (
else begin
RC_RLSel <= (RC_RLShifter4 >= 1 && RC_RLShifter4 <= 18)
? ~(18'b1 << (RC_RLShifter4 - 1))
: 18'h3FFFF; // 否则全 1（即不置 0）
: 18'h3FFFF; // 否则�1（即不置 0�
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
@@ -357,8 +364,10 @@ module CPLD_Con (
end
end
default:begin // You Should NOT be HERE
RC_VISel <='d0;
RC_RLSel <='hfffff;
RC_VSel <= 'd1;
RC_ISel <= 'd1;
RC_RLSel <= 'hf;
RC_LOFS <= 'hf;
PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
@@ -377,15 +386,16 @@ module CPLD_Con (
end
assign o_con_done = done_flag;
assign o_DMM_EN = DMM_en;
assign o_OC_x01 = OC_x01;
assign o_OC_x17 = OC_x17;
assign o_IO_RC1 = io_RC;
assign o_err = err_flag;
assign o_RC_Tx = RC_Tx;
assign o_RC_ISel = (RC_VISel==1'b1)?1:0;
assign o_RC_VSel = (RC_VISel==1'b1)?0:1;
assign o_DMM_EN = DMM_en;
assign o_IO_RC1 = io_RC;
assign o_RC_Tx = RC_Tx;
assign o_RC_VSel = RC_VSel;
assign o_RC_ISel = RC_ISel;
assign o_RC_LOFS = RC_LOFS;
assign o_RC_RLSel = RC_RLSel;