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Jeremy Shen
2026-05-27 17:25:48 +08:00
parent fe2e5a3fdc
commit 2c6716e5eb
46 changed files with 15406 additions and 0 deletions
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CPLD2/NewExtIns_CPLD2.ldf
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop" top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/>
</Source>
<Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="Reg_file.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="NewExtIns_CPLD2.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="debug.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
<Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
</BaliProject>