Init Repo
This commit is contained in:
Jeremy Shen
Vendored
+3
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{
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"iis.configDir": ""
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}
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+215
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module BUS_Con (
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input i_sys_clk,
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input i_rst_n,
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// SPI Interface
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input i_sclk,
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input i_mosi,
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input i_cs,
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output o_miso, // <-- MISO Logic added here
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// Local Interface
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output o_rvalid, // (Typo in original: o_rvalid)
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input i_rvalid, // Valid signal from Backend (Data is ready)
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input i_wvalid,
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output o_wready,
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input i_reg_busy,
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input [23:0] i_rdata, // Data from Backend to send to Master
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output o_wr,
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output o_cmd_valid,
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output [23:0] o_data,
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output [6:0] o_addr,
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output o_err
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);
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// --- 1. Synchronization ---
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reg [1:0] cs_sync;
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reg [1:0] sclk_sync;
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reg [1:0] mosi_sync;
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wire cs_active;
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wire cs_rise;
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wire sclk_rise; // For Sampling MOSI
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wire sclk_fall; // For Shifting MISO
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wire mosi_data;
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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cs_sync <= 2'b11;
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sclk_sync <= 2'b00;
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mosi_sync <= 2'b00;
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end else begin
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cs_sync <= {cs_sync[0], i_cs};
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sclk_sync <= {sclk_sync[0], i_sclk};
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mosi_sync <= {mosi_sync[0], i_mosi};
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end
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end
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assign cs_active = ~cs_sync[1];
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assign cs_rise = (!cs_sync[1] && cs_sync[0]);
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// SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
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assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]);
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assign sclk_fall = (sclk_sync[1] && !sclk_sync[0]); // Logic for MISO
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assign mosi_data = mosi_sync[1];
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// --- 2. MOSI (Receive) Logic ---
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reg [31:0] recv_reg;
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reg [5:0] bit_cnt;
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reg data_ready;
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reg err_flag;
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reg [1:0] state;
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//
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reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
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reg [31:0] miso_shift; // The actual shifter
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// Output Registers
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reg [6:0] addr_out;
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reg [23:0] data_out;
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reg wr_out;
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reg cmd_valid_out;
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//
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localparam IDLE = 2'b00;
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localparam CMD_SENT = 2'b01;
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localparam WAIT_BUSY = 2'b10;
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localparam DONE = 2'b11;
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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recv_reg <= 32'd0;
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bit_cnt <= 6'd0;
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data_ready <= 1'b0;
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err_flag <= 1'b0;
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end
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else begin
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data_ready <= 1'b0;
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if (cs_active) begin
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if (sclk_rise) begin
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recv_reg <= {recv_reg[30:0], mosi_data};
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bit_cnt <= bit_cnt + 1'b1;
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end
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else if (cs_rise) begin
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if (bit_cnt == 6'd32) begin
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data_ready <= 1'b1;
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err_flag <= 1'b0;
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bit_cnt <= 6'd0;
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end
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else if (bit_cnt != 0) begin
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err_flag <= 1'b1;
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bit_cnt <= 6'd0;
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recv_reg <= 'd0;
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end
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end
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end
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if (state == DONE) begin
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recv_reg <= 'd0;
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end
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end
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end
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// --- 3. MISO (Transmit) Logic ---
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// Protocol: We shift out 32 bits.
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// Format: [8 bit Status/Padding] + [24 bit i_rdata]
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// Capture data from backend when valid
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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tx_buffer <= 32'd0;
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end else begin
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// If backend provides valid read data, store it.
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// We pad the top 8 bits with Zeros (or you can put status flags here)
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if (i_rvalid) begin
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tx_buffer <= {8'h00, i_rdata};
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end
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end
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end
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// Shift data out
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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miso_shift <= 32'd0;
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end else begin
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if (!cs_active) begin
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// Pre-load the shifter while CS is High
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// This ensures Bit 31 is ready BEFORE the first clock edge
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miso_shift <= tx_buffer;
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end else begin
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// Shift on Falling Edge (Master samples on Rising)
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if (sclk_fall) begin
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miso_shift <= {miso_shift[30:0], 1'b0};
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end
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end
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end
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end
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// Tri-state MISO when CS is high (optional, usually good practice)
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// If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
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assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
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// --- 4. Register Control FSM ---
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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state <= IDLE;
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cmd_valid_out <= 1'b0;
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addr_out <= 7'd0;
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data_out <= 24'd0;
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wr_out <= 1'b0;
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end else begin
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case (state)
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IDLE: begin
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if (data_ready) begin
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addr_out <= recv_reg[30:24];
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data_out <= recv_reg[23:0];
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wr_out <= recv_reg[31];
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if (!i_reg_busy) begin
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cmd_valid_out <= 1'b1;
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state <= CMD_SENT;
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end else begin
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state <= WAIT_BUSY;
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end
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end
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end
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WAIT_BUSY: begin
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if (!i_reg_busy) begin
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cmd_valid_out <= 1'b1;
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state <= CMD_SENT;
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end
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end
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CMD_SENT: begin
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cmd_valid_out <= 1'b0;
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state <= DONE;
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end
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DONE: begin
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if (!i_reg_busy) begin
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state <= IDLE;
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addr_out <= 'd0;
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data_out <= 'd0;
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wr_out <= 'd0;
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end
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end
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endcase
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end
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end
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assign o_addr = addr_out;
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assign o_data = data_out;
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assign o_wr = wr_out;
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assign o_cmd_valid = cmd_valid_out;
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assign o_err = err_flag;
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assign o_wready = (state == IDLE);
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// Pass through unused signal or hook it up if needed
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assign o_rvalid = i_rvalid;
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endmodule
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@@ -0,0 +1,329 @@
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module CPLD_Con (
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input i_sys_clk,
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input i_rst_n,
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input i_con_exec,
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// Freq Relay Control
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input [23:0]i_freq_relay1,
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input [23:0]i_freq_relay2,
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input [23:0]i_freq_relay3,
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input [23:0]i_freq_relay4,
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// DC related Control
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input [23:0]i_DC_Con1,
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input [23:0]i_DC_Con2,
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input [23:0]i_DC_Con3,
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input [23:0]i_DC_Con4,
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//Output RELAYs
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output [7:0]o_RC_F, //Ref: Schematic
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output [15:0]o_RC_S,
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output [31:0]o_RC_T,
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output [3:0] o_OC_x09,
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output [3:0] o_OC_x25,
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output [31:0]o_PMU_OC_1 ,
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output [31:0]o_PMU_OC_2 ,
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output [31:0]o_PMU_OC_3 ,
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output [31:0]o_PMU_OC_4,
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//Output FLAGs
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output o_err,
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output o_con_done
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);
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//Output Relay Reg
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reg [3:0] OC_x09;
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reg [3:0] OC_x25;
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//Condition Tester
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reg [15:0]en_t ;
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reg freq_t;
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reg dc_t;
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//Relay Reg
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reg [7:0]relay_l1;
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reg [15:0]relay_l2 ;
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reg [31:0]relay_l3 ;
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reg [31:0]PMU_OC_1 ;
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reg [31:0]PMU_OC_2 ;
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reg [31:0]PMU_OC_3 ;
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reg [31:0]PMU_OC_4 ;
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//Flags
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reg exec_done_flag;
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reg exec_flag;
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reg [3:0]freq_slot_flag;
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reg [3:0]dc_slot_flag ;
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reg err_flag;
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//Counter
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reg [15:0]delay_cnt;
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wire [8:0] freq_relay1 = i_freq_relay1[9:1];
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wire [8:0] freq_relay2 = i_freq_relay2[9:1];
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wire [8:0] freq_relay3 = i_freq_relay3[9:1];
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wire [8:0] freq_relay4 = i_freq_relay4[9:1];
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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delay_cnt <= 'd0;
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end
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else begin
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if (exec_flag == 1'b1) begin
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delay_cnt <= delay_cnt + 1'd1;
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end
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else begin
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delay_cnt <= 'd0;
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end
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end
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end
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//Function Identify
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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en_t <= 'd0;
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freq_t <= 'd0;
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dc_t <= 'd0;
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end
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else begin
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en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
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freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
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dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
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end
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end
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// Main Controller Function
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always @(posedge i_sys_clk) begin
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if (i_rst_n == 1'b0) begin
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relay_l1 <= 'd0;
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relay_l2 <= 'd0;
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relay_l3 <= 'd0;
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exec_flag <= 1'b0;
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exec_done_flag <= 1'b1;
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freq_slot_flag <= 'd0;
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PMU_OC_1 <= 'd0;
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PMU_OC_2 <= 'd0;
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PMU_OC_3 <= 'd0;
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PMU_OC_4 <= 'd0;
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dc_slot_flag<='d0;
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err_flag <= 'd0;
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end
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else begin
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if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
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//To DO: More Sanity Check?
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if (en_t > 'd1) begin //Only ONE Enable bit should be set!
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err_flag <= 1'b1;
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end
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else begin
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exec_done_flag <= 'd0;
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exec_flag <= 1'b1;
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freq_slot_flag[0] <= i_freq_relay1[0];
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freq_slot_flag[1] <= i_freq_relay2[0];
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freq_slot_flag[2] <= i_freq_relay3[0];
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freq_slot_flag[3] <= i_freq_relay4[0];
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dc_slot_flag[0] <= i_DC_Con1[0];
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dc_slot_flag[1] <= i_DC_Con2[0];
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dc_slot_flag[2] <= i_DC_Con3[0];
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dc_slot_flag[3] <= i_DC_Con4[0];
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end
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end
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else if (exec_flag == 1'b1) begin
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//Output Relay
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if (freq_t == 1'b1) begin
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case (freq_slot_flag)
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4'b0001: begin
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relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]};
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if (delay_cnt == 'd500) begin
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relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]};
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end
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else if (delay_cnt == 'd1000) begin
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relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]};
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end
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else if (delay_cnt == 'd1080) begin
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exec_flag <= 'd0;
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exec_done_flag <= 1'b1;
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end
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if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin
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OC_x09 <= 4'b0001;
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end
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else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin
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OC_x25 <= 4'b0001;
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end
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else begin
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OC_x09 <= 'd0;
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OC_x25 <= 'd0;
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end
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end
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4'b0010: begin
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relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0};
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if (delay_cnt == 'd500) begin
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relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0};
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end
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else if (delay_cnt == 'd1000) begin
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relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0};
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end
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else if (delay_cnt == 'd1080) begin
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exec_flag <= 'd0;
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exec_done_flag <= 1'b1;
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end
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if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin
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OC_x09 <= 4'b0010;
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end
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else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin
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OC_x25 <= 4'b0010;
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end
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else begin
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OC_x09 <= 'd0;
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OC_x25 <= 'd0;
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end
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end
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4'b0100: begin
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relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0};
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if (delay_cnt == 'd500) begin
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relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0};
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end
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else if (delay_cnt == 'd1000) begin
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relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0};
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end
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else if (delay_cnt == 'd1080) begin
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exec_flag <= 'd0;
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exec_done_flag <= 1'b1;
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end
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if ((freq_relay3 > 64) &(freq_relay3 <73)) begin
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OC_x09 <= 4'b0100;
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end
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else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin
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OC_x25 <= 4'b0100;
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end
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else begin
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OC_x09 <= 'd0;
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OC_x25 <= 'd0;
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end
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end
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4'b1000: begin
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relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0};
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if (delay_cnt == 'd500) begin
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relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0};
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end
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else if (delay_cnt == 'd1000) begin
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relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0};
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end
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else if (delay_cnt == 'd1080) begin
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exec_flag <= 'd0;
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exec_done_flag <= 1'b1;
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end
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if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin
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OC_x09 <= 4'b1000;
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end
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else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin
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OC_x25 <= 4'b1000;
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end
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else begin
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OC_x09 <= 'd0;
|
||||
OC_x25 <= 'd0;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
OC_x09 <= 4'b0000;
|
||||
OC_x25 <= 4'b0000;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else if (dc_t == 1'b1) begin
|
||||
case (dc_slot_flag)
|
||||
4'b0001: begin
|
||||
//Sanity Check
|
||||
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
|
||||
err_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
|
||||
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
|
||||
end
|
||||
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
|
||||
|
||||
end
|
||||
end
|
||||
exec_flag <= 'd0;
|
||||
exec_done_flag <= 1'b1;
|
||||
end
|
||||
4'b0010: begin
|
||||
//Sanity Check
|
||||
if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
|
||||
err_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (i_DC_Con2[23] == 1'b0) begin //Select PMU
|
||||
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
|
||||
end
|
||||
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
|
||||
|
||||
end
|
||||
end
|
||||
exec_flag <= 'd0;
|
||||
exec_done_flag <= 1'b1;
|
||||
end
|
||||
4'b0100:begin
|
||||
//Sanity Check
|
||||
if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
|
||||
err_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (i_DC_Con3[23] == 1'b0) begin //Select PMU
|
||||
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
|
||||
end
|
||||
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
|
||||
|
||||
end
|
||||
end
|
||||
exec_flag <= 'd0;
|
||||
exec_done_flag <= 1'b1;
|
||||
end
|
||||
4'b1000:begin
|
||||
//Sanity Check
|
||||
if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
|
||||
err_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
|
||||
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
|
||||
end
|
||||
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
|
||||
|
||||
end
|
||||
end
|
||||
exec_flag <= 'd0;
|
||||
exec_done_flag <= 1'b1;
|
||||
end
|
||||
default:begin // You Should NOT be HERE
|
||||
PMU_OC_1 <= 'd0 ;
|
||||
PMU_OC_2 <= 'd0 ;
|
||||
PMU_OC_3 <= 'd0 ;
|
||||
PMU_OC_4 <= 'd0 ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign o_RC_F = relay_l1;
|
||||
assign o_RC_S = relay_l2;
|
||||
assign o_RC_T = relay_l3;
|
||||
assign o_con_done = exec_done_flag;
|
||||
assign o_OC_x09 = OC_x09;
|
||||
assign o_OC_x25 = OC_x25;
|
||||
|
||||
assign o_PMU_OC_1 = PMU_OC_1;
|
||||
assign o_PMU_OC_2 = PMU_OC_2;
|
||||
assign o_PMU_OC_3 = PMU_OC_3;
|
||||
assign o_PMU_OC_4 = PMU_OC_4;
|
||||
|
||||
assign o_err = err_flag;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,206 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ReportTrimmedUserNets" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
@@ -0,0 +1 @@
|
||||
VERSION=20110520
|
||||
@@ -0,0 +1,38 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="RelayConTop" top="RelayConTop"/>
|
||||
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RelayConTop"/>
|
||||
</Source>
|
||||
<Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="Reg_file.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
|
||||
<Options VerilogStandard="System Verilog"/>
|
||||
</Source>
|
||||
<Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="NewExtIns_CPLD2.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="debug.rvl" type="Reveal" type_short="Reveal">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
|
||||
</BaliProject>
|
||||
@@ -0,0 +1,324 @@
|
||||
rvl_alias "i_sys_clk" "i_sys_clk";
|
||||
RVL_ALIAS "i_sys_clk" "i_sys_clk";
|
||||
RVL_ALIAS "i_sys_clk" "i_sys_clk";
|
||||
RVL_ALIAS "i_sys_clk" "i_sys_clk";
|
||||
RVL_ALIAS "i_sys_clk" "i_sys_clk";
|
||||
RVL_ALIAS "i_sys_clk" "i_sys_clk";
|
||||
RVL_ALIAS "i_sys_clk" "i_sys_clk";
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
LOCATE COMP "i_sys_clk" SITE "B9" ;
|
||||
LOCATE COMP "i_rst_n" SITE "Y14" ;
|
||||
LOCATE COMP "i_sclk" SITE "AA16" ;
|
||||
LOCATE COMP "i_cs" SITE "Y15" ;
|
||||
LOCATE COMP "i_mosi" SITE "AB12" ;
|
||||
//LOCATE COMP "o_RC_T[26]" SITE "U13" ;
|
||||
//LOCATE COMP "o_RC_T[27]" SITE "U12" ;
|
||||
//LOCATE COMP "o_RC_T[28]" SITE "T12" ;
|
||||
//LOCATE COMP "o_RC_T[29]" SITE "T11" ;
|
||||
//LOCATE COMP "o_RC_T[30]" SITE "U11" ;
|
||||
//LOCATE COMP "o_RC_T[31]" SITE "V11" ;
|
||||
IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
|
||||
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_RC_F[0]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_F[1]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
|
||||
IOBUF PORT "o_RC_F[2]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_F[3]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_F[4]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_F[5]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_F[6]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_F[7]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[0]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[1]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[2]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[3]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[4]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[5]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[6]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[7]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[8]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[9]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[10]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[11]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[12]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[13]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[14]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_S[15]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[0]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[1]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[2]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[3]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[4]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[5]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[6]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[7]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[8]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[9]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[10]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[11]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[12]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[13]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[14]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[15]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[16]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[17]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[18]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[19]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[20]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[21]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[22]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[23]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[24]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_RC_T[25]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
|
||||
BLOCK JTAGPATHS ;
|
||||
LOCATE COMP "o_RC_F[0]" SITE "U13" ;
|
||||
LOCATE COMP "o_RC_F[1]" SITE "U12" ;
|
||||
LOCATE COMP "o_RC_F[2]" SITE "T12" ;
|
||||
LOCATE COMP "o_RC_F[3]" SITE "T11" ;
|
||||
LOCATE COMP "o_RC_F[4]" SITE "U11" ;
|
||||
LOCATE COMP "o_RC_F[5]" SITE "V11" ;
|
||||
LOCATE COMP "o_RC_F[6]" SITE "W11" ;
|
||||
LOCATE COMP "o_RC_F[7]" SITE "U10" ;
|
||||
LOCATE COMP "o_RC_S[0]" SITE "T10" ;
|
||||
LOCATE COMP "o_RC_S[1]" SITE "W9" ;
|
||||
LOCATE COMP "o_RC_S[2]" SITE "AB2" ;
|
||||
LOCATE COMP "o_RC_S[3]" SITE "Y3" ;
|
||||
LOCATE COMP "o_RC_S[4]" SITE "AA3" ;
|
||||
LOCATE COMP "o_RC_S[5]" SITE "AB3" ;
|
||||
LOCATE COMP "o_RC_S[6]" SITE "Y4" ;
|
||||
LOCATE COMP "o_RC_S[7]" SITE "AA4" ;
|
||||
LOCATE COMP "o_RC_S[8]" SITE "Y5" ;
|
||||
LOCATE COMP "o_RC_S[9]" SITE "W6" ;
|
||||
LOCATE COMP "o_RC_S[10]" SITE "AB5" ;
|
||||
LOCATE COMP "o_RC_S[11]" SITE "AB6" ;
|
||||
LOCATE COMP "o_RC_S[12]" SITE "Y6" ;
|
||||
LOCATE COMP "o_RC_S[13]" SITE "Y7" ;
|
||||
LOCATE COMP "o_RC_S[14]" SITE "AB7" ;
|
||||
LOCATE COMP "o_RC_S[15]" SITE "AA7" ;
|
||||
LOCATE COMP "o_RC_T[0]" SITE "AA8" ;
|
||||
LOCATE COMP "o_RC_T[1]" SITE "Y10" ;
|
||||
LOCATE COMP "o_RC_T[2]" SITE "AB10" ;
|
||||
LOCATE COMP "o_RC_T[3]" SITE "AA10" ;
|
||||
LOCATE COMP "o_RC_T[4]" SITE "AA11" ;
|
||||
LOCATE COMP "o_RC_T[5]" SITE "AB11" ;
|
||||
LOCATE COMP "o_RC_T[6]" SITE "AA12" ;
|
||||
LOCATE COMP "o_RC_T[7]" SITE "AB13" ;
|
||||
LOCATE COMP "o_RC_T[8]" SITE "V8" ;
|
||||
LOCATE COMP "o_RC_T[9]" SITE "V12" ;
|
||||
LOCATE COMP "o_RC_T[10]" SITE "W12" ;
|
||||
LOCATE COMP "o_RC_T[11]" SITE "Y12" ;
|
||||
LOCATE COMP "o_RC_T[12]" SITE "V13" ;
|
||||
LOCATE COMP "o_RC_T[13]" SITE "V14" ;
|
||||
LOCATE COMP "o_RC_T[14]" SITE "V16" ;
|
||||
LOCATE COMP "o_RC_T[15]" SITE "AB17" ;
|
||||
LOCATE COMP "o_RC_T[16]" SITE "Y18" ;
|
||||
LOCATE COMP "o_RC_T[17]" SITE "AA19" ;
|
||||
LOCATE COMP "o_RC_T[18]" SITE "AB20" ;
|
||||
LOCATE COMP "o_RC_T[19]" SITE "W19" ;
|
||||
LOCATE COMP "o_RC_T[20]" SITE "W17" ;
|
||||
LOCATE COMP "o_RC_T[21]" SITE "Y17" ;
|
||||
LOCATE COMP "o_RC_T[22]" SITE "T15" ;
|
||||
LOCATE COMP "o_RC_T[23]" SITE "U15" ;
|
||||
LOCATE COMP "o_RC_T[24]" SITE "T13" ;
|
||||
LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
|
||||
LOCATE COMP "o_err" SITE "AB16" ;
|
||||
IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 ;
|
||||
IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 ;
|
||||
LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
|
||||
LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
|
||||
LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
|
||||
LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
|
||||
LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
|
||||
LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
|
||||
LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
|
||||
LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
|
||||
LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
|
||||
LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
|
||||
LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
|
||||
LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
|
||||
LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
|
||||
LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
|
||||
LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
|
||||
LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
|
||||
LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
|
||||
LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
|
||||
LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
|
||||
LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
|
||||
LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
|
||||
LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
|
||||
LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
|
||||
LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
|
||||
LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
|
||||
LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
|
||||
LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
|
||||
LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
|
||||
LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
|
||||
LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
|
||||
LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
|
||||
LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
|
||||
LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
|
||||
LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
|
||||
LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
|
||||
LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
|
||||
LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
|
||||
LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
|
||||
LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
|
||||
LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
|
||||
LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
|
||||
LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
|
||||
LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
|
||||
LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
|
||||
LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
|
||||
LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
|
||||
LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
|
||||
LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
|
||||
LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
|
||||
LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
|
||||
LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
|
||||
LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
|
||||
USE PRIMARY NET "i_sys_clk_c" ;
|
||||
IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 ;
|
||||
@@ -0,0 +1,178 @@
|
||||
module Reg_file (
|
||||
input i_sys_clk,
|
||||
input i_rst_n,
|
||||
|
||||
// Bus Interface
|
||||
input i_wr_req,
|
||||
input i_wr,
|
||||
input [6:0] i_addr,
|
||||
input [23:0] i_wdata,
|
||||
|
||||
output [23:0] o_rdata,
|
||||
output o_rvalid,
|
||||
output o_busy,
|
||||
output o_err,
|
||||
|
||||
// Controller Interface
|
||||
input i_con_done, // 1=IDLE/DONE, 0=BUSY
|
||||
output o_exec,
|
||||
|
||||
// Direct Register Outputs
|
||||
output [23:0] o_freq1,
|
||||
output [23:0] o_freq2,
|
||||
output [23:0] o_freq3,
|
||||
output [23:0] o_freq4,
|
||||
|
||||
//DC Regs
|
||||
output [23:0] o_DC1,
|
||||
output [23:0] o_DC2,
|
||||
output [23:0] o_DC3,
|
||||
output [23:0] o_DC4
|
||||
);
|
||||
|
||||
// --- Parameters ---
|
||||
localparam REG_COUNT = 16;
|
||||
localparam [23:0]
|
||||
IDENT = 24'h400000 | 12'b0001_0001_0000, //CPLD2==1,version=1.1.0
|
||||
STATE_INIT = 24'h800000;
|
||||
|
||||
// State Machine Definition
|
||||
localparam IDLE = 4'd0;
|
||||
localparam BUSY = 4'd1;
|
||||
localparam EXEC_ACK = 4'd2; // Wait for controller to go BUSY (Done=0)
|
||||
localparam EXEC_WAIT = 4'd3; // Wait for controller to go DONE (Done=1)
|
||||
|
||||
// --- Internal Signals ---
|
||||
reg [3:0] state;
|
||||
reg [23:0] regtable [0:REG_COUNT - 1];
|
||||
reg [23:0] rdata_reg;
|
||||
|
||||
reg busy_flag;
|
||||
reg err_flag;
|
||||
reg rvalid_flag;
|
||||
|
||||
integer i;
|
||||
|
||||
// Mapping Control Bits
|
||||
wire exec_bit = regtable[1][0];
|
||||
|
||||
always @(posedge i_sys_clk or negedge i_rst_n) begin
|
||||
if (!i_rst_n) begin
|
||||
for (i = 0; i < REG_COUNT; i = i + 1) begin
|
||||
regtable[i] <= 24'h0;
|
||||
end
|
||||
regtable[0] <= IDENT;
|
||||
regtable[1] <= STATE_INIT;
|
||||
|
||||
rvalid_flag <= 1'b0;
|
||||
busy_flag <= 1'b0;
|
||||
err_flag <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
else begin
|
||||
case (state)
|
||||
IDLE: begin
|
||||
rvalid_flag <= 1'b0;
|
||||
err_flag <= 1'b0;
|
||||
|
||||
// Priority Check: Did we crash/reset while EXEC bit was still 1?
|
||||
if (exec_bit == 1'b1) begin
|
||||
state <= EXEC_ACK;
|
||||
busy_flag <= 1'b1;
|
||||
end
|
||||
else if (i_wr_req == 1'b1) begin
|
||||
busy_flag <= 1'b1;
|
||||
state <= BUSY;
|
||||
|
||||
// Addr Sanity Check
|
||||
if ((i_wr && (i_addr == 'd0 || i_addr >= REG_COUNT)) ||
|
||||
(!i_wr && (i_addr >= REG_COUNT)))
|
||||
begin
|
||||
err_flag <= 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
busy_flag <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
BUSY: begin
|
||||
if (err_flag) begin
|
||||
state <= IDLE;
|
||||
end
|
||||
else begin
|
||||
if (i_wr == 1'b1) begin // --- WRITE ---
|
||||
if (exec_bit == 1'b1) begin
|
||||
// Cannot write if Controller is already running
|
||||
err_flag <= 1'b1;
|
||||
state <= IDLE;
|
||||
end
|
||||
else begin
|
||||
regtable[i_addr] <= i_wdata;
|
||||
|
||||
// Check if this write is a "Start Command"
|
||||
if (i_addr == 7'd1 && i_wdata[0] == 1'b1) begin
|
||||
// Go to Handshake Start
|
||||
state <= EXEC_ACK;
|
||||
end else begin
|
||||
state <= IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin // --- READ ---
|
||||
rdata_reg <= regtable[i_addr];
|
||||
rvalid_flag <= 1'b1;
|
||||
state <= IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// --- EXEC PHASE 1: ACK ---
|
||||
// Wait for Controller to register the command and pull 'done' LOW (Busy)
|
||||
EXEC_ACK: begin
|
||||
busy_flag <= 1'b1;
|
||||
if (i_con_done == 1'b0) begin
|
||||
state <= EXEC_WAIT;
|
||||
end
|
||||
// Optional: Timeout counter here to prevent hanging if Controller is dead
|
||||
end
|
||||
|
||||
// --- EXEC PHASE 2: WAIT ---
|
||||
// Now wait for Controller to finish and pull 'done' HIGH (Idle/Ready)
|
||||
EXEC_WAIT: begin
|
||||
busy_flag <= 1'b1;
|
||||
if (i_con_done == 1'b1) begin
|
||||
// 1. Clear the Exec bit (Auto-Clear)
|
||||
// 2. Set the Ready bit (Bit 23) if you wish
|
||||
regtable[1] <= {1'b1, regtable[1][22:1], 1'b0};
|
||||
|
||||
busy_flag <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
default: state <= IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign o_rvalid = rvalid_flag;
|
||||
assign o_rdata = rdata_reg;
|
||||
assign o_busy = busy_flag;
|
||||
assign o_err = err_flag;
|
||||
|
||||
// Output the control bit to the controller
|
||||
// This stays HIGH during both EXEC_ACK and EXEC_WAIT
|
||||
assign o_exec = exec_bit;
|
||||
|
||||
assign o_freq1 = regtable[2];
|
||||
assign o_freq2 = regtable[3];
|
||||
assign o_freq3 = regtable[4];
|
||||
assign o_freq4 = regtable[5];
|
||||
|
||||
assign o_DC1 = regtable[6];
|
||||
assign o_DC2 = regtable[7];
|
||||
assign o_DC3 = regtable[8];
|
||||
assign o_DC4 = regtable[9];
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,167 @@
|
||||
module RelayConTop (
|
||||
input i_sys_clk,
|
||||
input i_rst_n,
|
||||
|
||||
input i_sclk,
|
||||
input i_mosi,
|
||||
input i_cs,
|
||||
output o_miso,
|
||||
output o_rvalid,
|
||||
input i_rready,
|
||||
input i_wvalid,
|
||||
output o_wready,
|
||||
output o_err,
|
||||
output [7:0]o_RC_F, //Ref: Schematic
|
||||
output [15:0]o_RC_S,
|
||||
output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1)
|
||||
//output [3:0] o_OC_x09,
|
||||
//output [3:0] o_OC_x25,
|
||||
output [31:0]o_PMU_OC_1 ,
|
||||
output [31:0]o_PMU_OC_2 ,
|
||||
output [31:0]o_PMU_OC_3 ,
|
||||
output [31:0]o_PMU_OC_4
|
||||
);
|
||||
|
||||
wire [7:0] RC_F;
|
||||
wire [15:0] RC_S;
|
||||
wire [31:0] RC_T;
|
||||
wire [3:0]OC_x09 ;
|
||||
wire [3:0]OC_x25 ;
|
||||
|
||||
wire [23:0]r_data ;
|
||||
wire [23:0]w_data ;
|
||||
wire [6:0]reg_addr ;
|
||||
|
||||
wire cmd_valid;
|
||||
wire reg_busy;
|
||||
wire wr_flag; //1=write,0=read
|
||||
wire bus_err_flag;
|
||||
wire reg_err_flag;
|
||||
wire cpld_err_flag;
|
||||
|
||||
wire con_exec;
|
||||
wire [23:0]freq1_relay ;
|
||||
wire [23:0]freq2_relay ;
|
||||
wire [23:0]freq3_relay ;
|
||||
wire [23:0]freq4_relay ;
|
||||
|
||||
//DC Control Reg output
|
||||
wire [23:0]DC_Con1 ;
|
||||
wire [23:0]DC_Con2 ;
|
||||
wire [23:0]DC_Con3 ;
|
||||
wire [23:0]DC_Con4 ;
|
||||
|
||||
//PMU OC Control
|
||||
wire [31:0]PMU_OC_1 ;
|
||||
wire [31:0]PMU_OC_2 ;
|
||||
wire [31:0]PMU_OC_3 ;
|
||||
wire [31:0]PMU_OC_4 ;
|
||||
|
||||
wire con_rvalid;
|
||||
|
||||
wire con_done;
|
||||
|
||||
BUS_Con BUS_Con_2(
|
||||
.i_sys_clk(i_sys_clk),
|
||||
.i_rst_n(i_rst_n),
|
||||
.i_sclk(i_sclk),
|
||||
.i_mosi(i_mosi),
|
||||
.i_cs(i_cs),
|
||||
.i_rvalid(con_rvalid),
|
||||
.i_wvalid(i_wvalid),
|
||||
.i_reg_busy(reg_busy),
|
||||
.i_rdata(r_data),
|
||||
.o_cmd_valid(cmd_valid),
|
||||
.o_wr(wr_flag),
|
||||
.o_miso(o_miso),
|
||||
.o_rvalid(o_rvalid),
|
||||
.o_wready(o_wready),
|
||||
.o_data(w_data),
|
||||
.o_addr(reg_addr),
|
||||
.o_err(bus_err_flag)
|
||||
);
|
||||
|
||||
Reg_file CPLD_Reg_2(
|
||||
.i_sys_clk(i_sys_clk),
|
||||
.i_rst_n(i_rst_n),
|
||||
.i_wr_req(cmd_valid),
|
||||
.i_wr(wr_flag),
|
||||
.i_addr(reg_addr),
|
||||
.i_wdata(w_data),
|
||||
.i_con_done(con_done), //Controller Exec Done
|
||||
.o_freq1(freq1_relay), //Freq_Slot1
|
||||
.o_freq2(freq2_relay), //Freq_Slot2
|
||||
.o_freq3(freq3_relay), //Freq_Slot3
|
||||
.o_freq4(freq4_relay), //Freq_Slot4
|
||||
.o_DC1(DC_Con1),
|
||||
.o_DC2(DC_Con2),
|
||||
.o_DC3(DC_Con3),
|
||||
.o_DC4(DC_Con4),
|
||||
.o_rvalid(con_rvalid),
|
||||
.o_rdata(r_data),
|
||||
.o_exec(con_exec), //Exec cmd
|
||||
.o_busy(reg_busy),
|
||||
.o_err(reg_err_flag)
|
||||
);
|
||||
|
||||
CPLD_Con CPLD_Con_2(
|
||||
.i_sys_clk(i_sys_clk),
|
||||
.i_rst_n(i_rst_n),
|
||||
.i_con_exec(con_exec),
|
||||
.i_freq_relay1(freq1_relay),
|
||||
.i_freq_relay2(freq2_relay),
|
||||
.i_freq_relay3(freq3_relay),
|
||||
.i_freq_relay4(freq4_relay),
|
||||
.i_DC_Con1(DC_Con1),
|
||||
.i_DC_Con2(DC_Con2),
|
||||
.i_DC_Con3(DC_Con3),
|
||||
.i_DC_Con4(DC_Con4),
|
||||
.o_PMU_OC_1(PMU_OC_1),
|
||||
.o_PMU_OC_2(PMU_OC_2),
|
||||
.o_PMU_OC_3(PMU_OC_3),
|
||||
.o_PMU_OC_4(PMU_OC_4),
|
||||
.o_con_done(con_done),
|
||||
.o_RC_F(RC_F),
|
||||
.o_RC_S(RC_S),
|
||||
.o_RC_T(RC_T),
|
||||
.o_OC_x09(OC_x09),
|
||||
.o_OC_x25(OC_x25),
|
||||
.o_err(cpld_err_flag)
|
||||
);
|
||||
|
||||
|
||||
assign o_RC_F = RC_F;
|
||||
assign o_RC_S = RC_S;
|
||||
assign o_RC_T = RC_T[25:0];
|
||||
|
||||
assign o_PMU_OC_1[8] = OC_x09[0];
|
||||
assign o_PMU_OC_2[8] = OC_x09[1];
|
||||
assign o_PMU_OC_3[8] = OC_x09[2];
|
||||
assign o_PMU_OC_4[8] = OC_x09[3];
|
||||
|
||||
assign o_PMU_OC_1[24] = OC_x25[0];
|
||||
assign o_PMU_OC_2[24] = OC_x25[1];
|
||||
assign o_PMU_OC_3[24] = OC_x25[2];
|
||||
assign o_PMU_OC_4[24] = OC_x25[3];
|
||||
|
||||
assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
|
||||
assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
|
||||
assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
|
||||
|
||||
assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
|
||||
assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
|
||||
assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
|
||||
|
||||
assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
|
||||
assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
|
||||
assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
|
||||
|
||||
assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
|
||||
assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
|
||||
assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
|
||||
|
||||
|
||||
assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,68 @@
|
||||
<Project ModBy="Inserter" SigType="0" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26">
|
||||
<IP Version="1_6_042617"/>
|
||||
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
|
||||
<Core InsertDataset="0" Insert="1" Reveal_sig="695532641" Name="RelayConTop_LA0" ID="0">
|
||||
<Setting>
|
||||
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
|
||||
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
|
||||
<Capture Mode="0" MinSamplesPerTrig="8"/>
|
||||
<Event CntEnable="0" MaxEventCnt="8"/>
|
||||
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
|
||||
<DistRAM Disable="0"/>
|
||||
</Setting>
|
||||
<Dataset Name="Base">
|
||||
<Trace>
|
||||
<Sig Type="SIG" Name="i_rst_n"/>
|
||||
<Sig Type="SIG" Name="BUS_Con_2/i_cs"/>
|
||||
<Sig Type="SIG" Name="BUS_Con_2/i_sclk"/>
|
||||
<Sig Type="SIG" Name="BUS_Con_2/i_mosi"/>
|
||||
<Sig Type="SIG" Name="BUS_Con_2/i_reg_busy"/>
|
||||
<Sig Type="SIG" Name="CPLD_Reg_2/o_exec"/>
|
||||
<Bus Name="RC_T">
|
||||
<Sig Type="SIG" Name="RC_T:0"/>
|
||||
<Sig Type="SIG" Name="RC_T:1"/>
|
||||
<Sig Type="SIG" Name="RC_T:2"/>
|
||||
<Sig Type="SIG" Name="RC_T:3"/>
|
||||
<Sig Type="SIG" Name="RC_T:4"/>
|
||||
<Sig Type="SIG" Name="RC_T:5"/>
|
||||
<Sig Type="SIG" Name="RC_T:6"/>
|
||||
<Sig Type="SIG" Name="RC_T:7"/>
|
||||
<Sig Type="SIG" Name="RC_T:8"/>
|
||||
<Sig Type="SIG" Name="RC_T:9"/>
|
||||
<Sig Type="SIG" Name="RC_T:10"/>
|
||||
<Sig Type="SIG" Name="RC_T:11"/>
|
||||
<Sig Type="SIG" Name="RC_T:12"/>
|
||||
<Sig Type="SIG" Name="RC_T:13"/>
|
||||
<Sig Type="SIG" Name="RC_T:14"/>
|
||||
<Sig Type="SIG" Name="RC_T:15"/>
|
||||
<Sig Type="SIG" Name="RC_T:16"/>
|
||||
<Sig Type="SIG" Name="RC_T:17"/>
|
||||
<Sig Type="SIG" Name="RC_T:18"/>
|
||||
<Sig Type="SIG" Name="RC_T:19"/>
|
||||
<Sig Type="SIG" Name="RC_T:20"/>
|
||||
<Sig Type="SIG" Name="RC_T:21"/>
|
||||
<Sig Type="SIG" Name="RC_T:22"/>
|
||||
<Sig Type="SIG" Name="RC_T:23"/>
|
||||
<Sig Type="SIG" Name="RC_T:24"/>
|
||||
<Sig Type="SIG" Name="RC_T:25"/>
|
||||
<Sig Type="SIG" Name="RC_T:26"/>
|
||||
<Sig Type="SIG" Name="RC_T:27"/>
|
||||
<Sig Type="SIG" Name="RC_T:28"/>
|
||||
<Sig Type="SIG" Name="RC_T:29"/>
|
||||
<Sig Type="SIG" Name="RC_T:30"/>
|
||||
<Sig Type="SIG" Name="RC_T:31"/>
|
||||
</Bus>
|
||||
<Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
|
||||
<Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
|
||||
<Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
|
||||
<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
|
||||
</Trace>
|
||||
<Trigger>
|
||||
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/>
|
||||
<TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/>
|
||||
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
|
||||
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
|
||||
</Trigger>
|
||||
</Dataset>
|
||||
</Core>
|
||||
</Project>
|
||||
@@ -0,0 +1,964 @@
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Testbench: CPLD2 - RelayConTop
|
||||
// Project: NewCalBoard DIG
|
||||
// Tool: Lattice Diamond Verilog-2001 simulator
|
||||
// Purpose: Verify SPI interface, register file, and relay control logic
|
||||
// for CPLD2 (RC_F/RC_S/RC_T relay control + OC channels + PMU_OC).
|
||||
//
|
||||
// CPLD2-specific:
|
||||
// - Outputs: RC_F[7:0], RC_S[15:0], RC_T[25:0], OC_x09[3:0], OC_x25[3:0]
|
||||
// - PMU_OC_1-4[31:0] (from OC_x09/OC_x25 mapping)
|
||||
// - CPLD_Con handles freq relays only (DC slots are stubs)
|
||||
// - Signal names: i_wvaild (typo), i_rvaild (typo)
|
||||
//
|
||||
// Architecture (3 sub-modules):
|
||||
// RelayConTop
|
||||
// - BUS_Con - SPI Mode 0 master interface (32-bit transactions)
|
||||
// - Reg_file - 16-register file + execution FSM
|
||||
// - CPLD_Con - Freq relay control logic (no DC handling)
|
||||
//
|
||||
// SPI Protocol:
|
||||
// Frame: [WR:1][Addr:7][Data:24] (MSB first, CPOL=0 CPHA=0)
|
||||
// Read response: [8'h00][24-bit rdata]
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
`define SYS_CLK_PERIOD 20 // 50 MHz system clock
|
||||
`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock (200x slower than sys clk)
|
||||
|
||||
module tb_RelayConTop;
|
||||
|
||||
//==========================================================================
|
||||
// Signal declarations - mirrors CPLD2 RelayConTop pinout
|
||||
//==========================================================================
|
||||
|
||||
// Clock & reset
|
||||
reg i_sys_clk;
|
||||
reg i_rst_n;
|
||||
|
||||
// SPI interface (Zynq PS drives these)
|
||||
reg i_sclk;
|
||||
reg i_mosi;
|
||||
reg i_cs;
|
||||
|
||||
// Flow control (CPLD2 uses typo names: i_wvaild, i_rvaild)
|
||||
reg i_rready;
|
||||
reg i_wvaild;
|
||||
|
||||
// Status outputs (monitored by testbench)
|
||||
// Note: CPLD2 does NOT expose o_con_done as a top-level output
|
||||
wire o_miso;
|
||||
wire o_rvalid;
|
||||
wire o_wready;
|
||||
wire o_err;
|
||||
|
||||
// Relay control outputs (CPLD2 specific)
|
||||
wire [7:0] o_RC_F; // RC_F relays (2 bits used per slot)
|
||||
wire [15:0] o_RC_S; // RC_S relays (4 bits used per slot)
|
||||
wire [25:0] o_RC_T; // RC_T relays (8 bits used per slot, only 26 bits)
|
||||
|
||||
// OC channel selectors
|
||||
wire [3:0] o_OC_x09; // OC channel selector (range 65-72)
|
||||
wire [3:0] o_OC_x25; // OC channel selector (range 193-200)
|
||||
|
||||
// PMU output channels (4 x 32-bit, mapped from OC_x09/OC_x25)
|
||||
wire [31:0] o_PMU_OC_1;
|
||||
wire [31:0] o_PMU_OC_2;
|
||||
wire [31:0] o_PMU_OC_3;
|
||||
wire [31:0] o_PMU_OC_4;
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// DUT instantiation - CPLD2 specific pin names
|
||||
// Note: CPLD2 does NOT expose o_con_done as a top-level output
|
||||
//==========================================================================
|
||||
RelayConTop DUT (
|
||||
.i_sys_clk (i_sys_clk),
|
||||
.i_rst_n (i_rst_n),
|
||||
.i_sclk (i_sclk),
|
||||
.i_mosi (i_mosi),
|
||||
.i_cs (i_cs),
|
||||
.o_miso (o_miso),
|
||||
.o_rvalid (o_rvalid),
|
||||
.i_rready (i_rready),
|
||||
.i_wvaild (i_wvaild), // CPLD2 typo: wvaild
|
||||
.o_wready (o_wready),
|
||||
.o_err (o_err),
|
||||
.o_RC_F (o_RC_F),
|
||||
.o_RC_S (o_RC_S),
|
||||
.o_RC_T (o_RC_T),
|
||||
.o_PMU_OC_1 (o_PMU_OC_1),
|
||||
.o_PMU_OC_2 (o_PMU_OC_2),
|
||||
.o_PMU_OC_3 (o_PMU_OC_3),
|
||||
.o_PMU_OC_4 (o_PMU_OC_4)
|
||||
);
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Clock generation
|
||||
//==========================================================================
|
||||
|
||||
// System clock: 50 MHz (period = 20 ns)
|
||||
initial begin
|
||||
i_sys_clk = 0;
|
||||
forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
|
||||
end
|
||||
|
||||
// SPI clock: 1 MHz (period = 400 ns)
|
||||
initial begin
|
||||
i_sclk = 0;
|
||||
forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
|
||||
end
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test statistics
|
||||
//==========================================================================
|
||||
integer test_pass;
|
||||
integer test_fail;
|
||||
integer test_num;
|
||||
|
||||
initial begin
|
||||
test_pass = 0;
|
||||
test_fail = 0;
|
||||
test_num = 0;
|
||||
end
|
||||
|
||||
// Helper: log a pass
|
||||
task tb_pass;
|
||||
input string msg;
|
||||
begin
|
||||
test_pass = test_pass + 1;
|
||||
$display("[PASS] Test %0d: %s", test_num, msg);
|
||||
end
|
||||
endtask
|
||||
|
||||
// Helper: log a fail with optional detail
|
||||
task tb_fail;
|
||||
input string msg;
|
||||
input string detail;
|
||||
begin
|
||||
test_fail = test_fail + 1;
|
||||
$display("[FAIL] Test %0d: %s >> %s", test_num, msg, detail);
|
||||
end
|
||||
endtask
|
||||
|
||||
// Helper: assert a condition
|
||||
task tb_assert;
|
||||
input condition;
|
||||
input string msg;
|
||||
input string detail;
|
||||
begin
|
||||
test_num = test_num + 1;
|
||||
if (condition) begin
|
||||
tb_pass(msg);
|
||||
end else begin
|
||||
tb_fail(msg, detail);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// SPI helper tasks
|
||||
//
|
||||
// SPI Mode 0 timing:
|
||||
// - CPOL = 0: SCLK idle LOW
|
||||
// - CPHA = 0: data sampled on RISING edge, shifted on FALLING edge
|
||||
// - MSB first, 32 bits per transaction
|
||||
//
|
||||
// Frame layout: [bit31: WR] [bit30:24: Addr(7b)] [bit23:0: Data(24b)]
|
||||
// Read response: [8'h00][24-bit rdata] shifted out on falling SCLK edges
|
||||
//
|
||||
// MISO is tri-stated (high-Z) when CS is HIGH.
|
||||
//==========================================================================
|
||||
|
||||
// --- spi_send: Drive a 32-bit word out through MOSI ---
|
||||
task spi_send;
|
||||
input [31:0] data;
|
||||
integer i;
|
||||
begin
|
||||
@(negedge i_sclk);
|
||||
i_cs = 1'b0;
|
||||
@(negedge i_sclk);
|
||||
|
||||
for (i = 31; i >= 0; i = i - 1) begin
|
||||
i_mosi = data[i];
|
||||
@(posedge i_sclk);
|
||||
end
|
||||
|
||||
@(negedge i_sclk);
|
||||
i_cs = 1'b1;
|
||||
i_mosi = 1'b0;
|
||||
@(negedge i_sclk);
|
||||
end
|
||||
endtask
|
||||
|
||||
// --- spi_read: Send command, capture 32-bit response on MISO ---
|
||||
task spi_read;
|
||||
input [31:0] cmd;
|
||||
output [31:0] rdata;
|
||||
integer i;
|
||||
begin
|
||||
@(negedge i_sclk);
|
||||
i_cs = 1'b0;
|
||||
@(negedge i_sclk);
|
||||
|
||||
rdata = 32'b0;
|
||||
for (i = 31; i >= 0; i = i - 1) begin
|
||||
i_mosi = cmd[i];
|
||||
@(posedge i_sclk);
|
||||
@(negedge i_sclk);
|
||||
#1;
|
||||
rdata[i] = o_miso;
|
||||
end
|
||||
|
||||
@(negedge i_sclk);
|
||||
i_cs = 1'b1;
|
||||
i_mosi = 1'b0;
|
||||
@(negedge i_sclk);
|
||||
end
|
||||
endtask
|
||||
|
||||
// --- spi_write: Send a write command (no response capture needed) ---
|
||||
task spi_write;
|
||||
input [31:0] data;
|
||||
begin
|
||||
spi_send(data);
|
||||
end
|
||||
endtask
|
||||
|
||||
// --- wait_con_done: Poll o_wready for HIGH (CPLD2 doesn't expose con_done)
|
||||
// When execution completes, the SPI interface becomes ready again (o_wready=1)
|
||||
task wait_con_done;
|
||||
input [15:0] max_cycles;
|
||||
output [1:0] result;
|
||||
integer i;
|
||||
begin
|
||||
result = 2'b0;
|
||||
|
||||
// Wait for o_wready to go HIGH (SPI interface ready after execution)
|
||||
for (i = 0; i < max_cycles; i = i + 1) begin
|
||||
#(`SYS_CLK_PERIOD);
|
||||
if (o_wready) begin
|
||||
result = 2'b1;
|
||||
return;
|
||||
end
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
// --- wait_wready: Poll o_wready until HIGH ---
|
||||
task wait_wready;
|
||||
input [15:0] max_cycles;
|
||||
output [1:0] result;
|
||||
integer i;
|
||||
begin
|
||||
result = 2'b0;
|
||||
for (i = 0; i < max_cycles; i = i + 1) begin
|
||||
#(`SYS_CLK_PERIOD);
|
||||
if (o_wready) begin
|
||||
result = 2'b1;
|
||||
return;
|
||||
end
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Convenience: build SPI frame fields
|
||||
//==========================================================================
|
||||
function [31:0] mk_write;
|
||||
input [6:0] addr;
|
||||
input [23:0] data;
|
||||
begin
|
||||
mk_write = {1'b1, addr, data};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [31:0] mk_read;
|
||||
input [6:0] addr;
|
||||
begin
|
||||
mk_read = {1'b0, addr, 24'b0};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Main test sequence
|
||||
//==========================================================================
|
||||
initial begin
|
||||
// Initialize all signals to safe defaults
|
||||
i_rst_n = 1'b0;
|
||||
i_cs = 1'b1;
|
||||
i_mosi = 1'b0;
|
||||
i_rready = 1'b0;
|
||||
i_wvaild = 1'b0;
|
||||
|
||||
// Hold reset for 4 system clock cycles (80 ns)
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
|
||||
// Allow CPLD internal state machines to settle
|
||||
#(`SYS_CLK_PERIOD * 10);
|
||||
|
||||
$display("");
|
||||
$display("=============================================================");
|
||||
$display(" CPLD2 RelayConTop - Comprehensive Testbench");
|
||||
$display(" System clock: %d MHz | SPI clock: %d MHz",
|
||||
1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
|
||||
$display(" Outputs: RC_F[7:0], RC_S[15:0], RC_T[25:0], OC_x09/25, PMU_OC[4x32]");
|
||||
$display("=============================================================");
|
||||
$display("");
|
||||
|
||||
test_reset_behavior();
|
||||
test_register_rw();
|
||||
test_exec_protocol();
|
||||
test_freq_slots();
|
||||
test_rc_relay_outputs();
|
||||
test_dc_stub_behavior();
|
||||
test_error_conditions();
|
||||
test_edge_cases();
|
||||
|
||||
print_summary();
|
||||
|
||||
#(`SYS_CLK_PERIOD * 20);
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 1: Reset behavior & IDENT register (ADDR 0)
|
||||
//==========================================================================
|
||||
task test_reset_behavior;
|
||||
reg [31:0] r_ident;
|
||||
begin
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 1: Reset behavior & IDENT register");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
tb_assert(o_wready === 1'b1,
|
||||
"o_wready is HIGH after reset (SPI ready, controller idle)", "");
|
||||
|
||||
tb_assert(o_err === 1'b0,
|
||||
"o_err is LOW after reset", "");
|
||||
|
||||
tb_assert(o_wready === 1'b1,
|
||||
"o_wready is HIGH after reset (SPI ready)", "");
|
||||
|
||||
// IDENT register: CPLD2=bit22, version=1.1.0 = 24'h400010
|
||||
spi_read(mk_read(7'd0), r_ident);
|
||||
r_ident = r_ident[23:0];
|
||||
tb_assert(r_ident === 24'h400010,
|
||||
"IDENT register returns 24'h400010 (CPLD2, v1.1.0)", "");
|
||||
|
||||
// All relay outputs should be zero after reset
|
||||
tb_assert(o_RC_F === 8'b0,
|
||||
"o_RC_F is all zeros after reset", "");
|
||||
|
||||
tb_assert(o_RC_S === 16'b0,
|
||||
"o_RC_S is all zeros after reset", "");
|
||||
|
||||
tb_assert(o_RC_T[25:0] === 26'b0,
|
||||
"o_RC_T[25:0] is all zeros after reset", "");
|
||||
|
||||
tb_assert(o_OC_x09 === 4'b0,
|
||||
"o_OC_x09 is all zeros after reset", "");
|
||||
|
||||
tb_assert(o_OC_x25 === 4'b0,
|
||||
"o_OC_x25 is all zeros after reset", "");
|
||||
|
||||
tb_assert(o_PMU_OC_1 === 32'b0 && o_PMU_OC_2 === 32'b0 &&
|
||||
o_PMU_OC_3 === 32'b0 && o_PMU_OC_4 === 32'b0,
|
||||
"All PMU_OC outputs are zero after reset", "");
|
||||
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 2: Register read/write (ADDR 0-9)
|
||||
//==========================================================================
|
||||
task test_register_rw;
|
||||
reg [31:0] rdata;
|
||||
begin
|
||||
$display("");
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 2: Register read/write (ADDR 0-9)");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
spi_write(mk_write(7'd2, 24'h000005));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd2), rdata);
|
||||
tb_assert(rdata === 24'h000005,
|
||||
"Freq_Slot1 (ADDR 2) write/read back", "");
|
||||
|
||||
spi_write(mk_write(7'd3, 24'h003001));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd3), rdata);
|
||||
tb_assert(rdata === 24'h003001,
|
||||
"Freq_Slot2 (ADDR 3) write/read back", "");
|
||||
|
||||
spi_write(mk_write(7'd4, 24'h001040));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd4), rdata);
|
||||
tb_assert(rdata === 24'h001040,
|
||||
"Freq_Slot3 (ADDR 4) write/read back", "");
|
||||
|
||||
spi_write(mk_write(7'd5, 24'h000802));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd5), rdata);
|
||||
tb_assert(rdata === 24'h000802,
|
||||
"Freq_Slot4 (ADDR 5) write/read back", "");
|
||||
|
||||
spi_write(mk_write(7'd6, 24'h002003));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd6), rdata);
|
||||
tb_assert(rdata === 24'h002003,
|
||||
"DC_Slot1 (ADDR 6) write/read back", "");
|
||||
|
||||
spi_write(mk_write(7'd7, 24'h004005));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd7), rdata);
|
||||
tb_assert(rdata === 24'h004005,
|
||||
"DC_Slot2 (ADDR 7) write/read back", "");
|
||||
|
||||
spi_write(mk_write(7'd8, 24'h006007));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd8), rdata);
|
||||
tb_assert(rdata === 24'h006007,
|
||||
"DC_Slot3 (ADDR 8) write/read back", "");
|
||||
|
||||
spi_write(mk_write(7'd9, 24'h008009));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd9), rdata);
|
||||
tb_assert(rdata === 24'h008009,
|
||||
"DC_Slot4 (ADDR 9) write/read back", "");
|
||||
|
||||
spi_read(mk_read(7'd1), rdata);
|
||||
tb_assert(rdata === 24'h800000,
|
||||
"STATE register (ADDR 1) default (RDY=1)", "");
|
||||
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 3: Execution protocol
|
||||
//==========================================================================
|
||||
task test_exec_protocol;
|
||||
reg [1:0] done_result;
|
||||
begin
|
||||
$display("");
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 3: Execution protocol");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
// Configure and trigger execution with Freq_Slot1
|
||||
spi_write(mk_write(7'd2, 24'h000005));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001)); // EXEC=1
|
||||
@(negedge i_sclk);
|
||||
|
||||
wait_con_done(500, done_result);
|
||||
tb_assert(done_result === 1'b1,
|
||||
"con_done goes HIGH after execution completes", "");
|
||||
|
||||
tb_assert(o_err === 1'b0,
|
||||
"No error flag set after successful execution", "");
|
||||
|
||||
wait_wready(100, done_result);
|
||||
tb_assert(done_result === 1'b1,
|
||||
"o_wready is HIGH after execution (SPI ready)", "");
|
||||
|
||||
// Execute with DC_Slot1 (should complete but produce no output)
|
||||
spi_write(mk_write(7'd6, 24'h002003));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_result);
|
||||
tb_assert(done_result === 1'b1,
|
||||
"DC slot execution completes (stub behavior)", "");
|
||||
tb_assert(o_err === 1'b0,
|
||||
"No error after DC slot execution (stub)", "");
|
||||
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 4: Frequency slot decoding (all 4 slots)
|
||||
//
|
||||
// Freq_Slot N bit layout:
|
||||
// Bit 23:10: Per Relay_Control (14 bits)
|
||||
// Bit 9:1: Channel_Number (9 bits)
|
||||
// Bit 0: Slot_EN (1=Enable)
|
||||
//
|
||||
// Channel ranges:
|
||||
// 1-8: OC_x09 = slot_bit, PMU_OC[0] bit 0
|
||||
// 9-72: (no OC_x09/OC_x25), PMU_OC[0] from channel
|
||||
// 73-136: OC_x25 = slot_bit, PMU_OC[0] bit 16+
|
||||
// 137-200: (no OC_x09/OC_x25), PMU_OC[0] bit 24+
|
||||
//==========================================================================
|
||||
task test_freq_slots;
|
||||
reg [1:0] done_r;
|
||||
begin
|
||||
$display("");
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 4: Frequency slot decoding (all 4 slots)");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
// Slot1 Ch5 (range 1-8): OC_x09 = 4'b0001
|
||||
// = (1<<23) | (0<<22) | (5<<1) | 1 = 24'h08000B (sets RC_F[1:0]=01)
|
||||
$display(" Slot1 Ch5 (range 1-8): OC_x09=0001");
|
||||
spi_write(mk_write(7'd2, 24'h08000B));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot1 Ch5 exec done", "timeout");
|
||||
tb_assert(o_OC_x09[0] === 1'b1, "Slot1 Ch5: OC_x09[0]=1", "OC_x09[0] mismatch");
|
||||
tb_assert(o_OC_x25 === 4'b0, "Slot1 Ch5: OC_x25=0", "OC_x25 mismatch");
|
||||
tb_assert(o_RC_F[1:0] == 2'b01, "Slot1 Ch5: RC_F[1:0] has relay bits", "RC_F mismatch");
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// Slot1 Ch50 (range 9-72): no OC_x09/OC_x25
|
||||
// = (0<<10) | (50<<1) | 1 = 24'h000065
|
||||
$display(" Slot1 Ch50 (range 9-72): OC_x09=0, OC_x25=0");
|
||||
spi_write(mk_write(7'd2, 24'h000065));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot1 Ch50 exec done", "timeout");
|
||||
tb_assert(o_OC_x09 === 4'b0, "Slot1 Ch50: OC_x09=0", "OC_x09 mismatch");
|
||||
tb_assert(o_OC_x25 === 4'b0, "Slot1 Ch50: OC_x25=0", "OC_x25 mismatch");
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// Slot1 Ch100 (range 73-136): OC_x25 = 4'b0001
|
||||
// = (0<<10) | (100<<1) | 1 = 24'h0000C9
|
||||
$display(" Slot1 Ch100 (range 73-136): OC_x25=0001");
|
||||
spi_write(mk_write(7'd2, 24'h0000C9));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot1 Ch100 exec done", "timeout");
|
||||
tb_assert(o_OC_x09 === 4'b0, "Slot1 Ch100: OC_x09=0", "OC_x09 mismatch");
|
||||
tb_assert(o_OC_x25[0] === 1'b1, "Slot1 Ch100: OC_x25[0]=1", "OC_x25[0] mismatch");
|
||||
tb_assert(o_RC_T[15:8] != 8'b0, "Slot1 Ch100: RC_T has relay bits", "RC_T mismatch");
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// Slot1 Ch150 (range 137-200): no OC_x09/OC_x25
|
||||
// = (0<<10) | (150<<1) | 1 = 24'h00012D
|
||||
$display(" Slot1 Ch150 (range 137-200): OC_x09=0, OC_x25=0");
|
||||
spi_write(mk_write(7'd2, 24'h00012D));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot1 Ch150 exec done", "timeout");
|
||||
tb_assert(o_OC_x09 === 4'b0, "Slot1 Ch150: OC_x09=0", "OC_x09 mismatch");
|
||||
tb_assert(o_OC_x25 === 4'b0, "Slot1 Ch150: OC_x25=0", "OC_x25 mismatch");
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// Slot2 Ch5 (range 1-8): OC_x09 = 4'b0010
|
||||
// = (1<<23) | (0<<22) | (5<<1) | 1 = 24'h08000B (sets RC_F[3:2]=01)
|
||||
$display(" Slot2 Ch5 (range 1-8): OC_x09=0010");
|
||||
spi_write(mk_write(7'd3, 24'h08000B));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot2 Ch5 exec done", "timeout");
|
||||
tb_assert(o_OC_x09[1] === 1'b1, "Slot2 Ch5: OC_x09[1]=1", "OC_x09[1] mismatch");
|
||||
tb_assert(o_RC_F[5:4] == 2'b01, "Slot2 Ch5: RC_F[5:4] has relay bits", "RC_F mismatch");
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// Slot3 Ch100 (range 73-136): OC_x25 = 4'b0100
|
||||
// = (0xAA<<10) | (100<<1) | 1 = 24'h02A8C9 (sets RC_T bits)
|
||||
$display(" Slot3 Ch100 (range 73-136): OC_x25=0100");
|
||||
spi_write(mk_write(7'd4, 24'h02A8C9));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot3 Ch100 exec done", "timeout");
|
||||
tb_assert(o_OC_x25[2] === 1'b1, "Slot3 Ch100: OC_x25[2]=1", "OC_x25[2] mismatch");
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// Slot4 Ch50 (range 9-72): no OC_x09/OC_x25
|
||||
// = (0<<10) | (50<<1) | 1 = 24'h000065
|
||||
$display(" Slot4 Ch50 (range 9-72): OC_x09=0, OC_x25=0");
|
||||
spi_write(mk_write(7'd5, 24'h000065));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot4 Ch50 exec done", "timeout");
|
||||
tb_assert(o_OC_x09 === 4'b0, "Slot4 Ch50: OC_x09=0", "OC_x09 mismatch");
|
||||
tb_assert(o_OC_x25 === 4'b0, "Slot4 Ch50: OC_x25=0", "OC_x25 mismatch");
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 5: RC relay output patterns (RC_F, RC_S, RC_T)
|
||||
//
|
||||
// CPLD2 CPLD_Con relay mapping (frequency mode):
|
||||
// Slot1: RC_F[1:0], RC_S[3:0], RC_T[7:0]
|
||||
// Slot2: RC_F[5:4], RC_S[11:8], RC_T[23:16]
|
||||
// Slot3: RC_F[7:6], RC_S[15:12], RC_T[15:8] (bit-reordered)
|
||||
// Slot4: RC_F[1:0], RC_S[3:0], RC_T[7:0]
|
||||
//
|
||||
// Timing: relay_l1 at t=0, relay_l2 at t=500, relay_l3 at t=1000
|
||||
// exec_done at t=1080
|
||||
//==========================================================================
|
||||
task test_rc_relay_outputs;
|
||||
reg [1:0] done_r;
|
||||
begin
|
||||
$display("");
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 5: RC relay output patterns (RC_F/RC_S/RC_T)");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
// 5a. Slot4 Ch5: Verify RC_F, RC_S, RC_T relay bit extraction
|
||||
// Freq_Slot4 with RC_F[1:0]={1,0}, RC_S[3:0]={1,0,1,0}, Ch=5
|
||||
// = (1<<23) | (0xA<<18) | (5<<1) | 1 = 24'hA8000B
|
||||
$display(" Slot4: RC_F/RC_S/RC_T relay extraction");
|
||||
spi_write(mk_write(7'd5, 24'hA8000B));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot4 relay exec done", "timeout");
|
||||
|
||||
// RC_F[1:0] should have relay bits from freq4[23:22]
|
||||
tb_assert(o_RC_F[1:0] != 2'b00,
|
||||
"Slot4: RC_F[1:0] has relay bits from freq4[23:22]",
|
||||
$sformatf("RC_F[1:0]=%b", o_RC_F[1:0]));
|
||||
|
||||
// RC_S[3:0] should have relay bits from freq4[21:18]
|
||||
tb_assert(o_RC_S[3:0] != 4'b0000,
|
||||
"Slot4: RC_S[3:0] has relay bits from freq4[21:18]",
|
||||
$sformatf("RC_S[3:0]=%b", o_RC_S[3:0]));
|
||||
|
||||
// RC_T[7:0] should have relay bits from freq4[17:10]
|
||||
tb_assert(o_RC_T[7:0] != 8'b00000000,
|
||||
"Slot4: RC_T[7:0] has relay bits from freq4[17:10]",
|
||||
$sformatf("RC_T[7:0]=%b", o_RC_T[7:0]));
|
||||
|
||||
// 5b. Slot4 with specific relay pattern: bits 23=1, 22=0, 21=1, 20=0, 19=1, 18=0, Ch=5
|
||||
// = (1<<23) | (0<<22) | (1<<21) | (0<<20) | (1<<19) | (0<<18) | (5<<1) | 1
|
||||
// = 24'hA8000B
|
||||
$display(" Slot4: RC_F/RC_S/RC_T specific relay pattern");
|
||||
spi_write(mk_write(7'd5, 24'hA8000B));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Slot4 pattern exec done", "timeout");
|
||||
|
||||
// Verify RC_F[1:0] = {freq4[22], freq4[23]} = {0, 1} = 2'b01
|
||||
tb_assert(o_RC_F[1:0] === 2'b01,
|
||||
"Slot4: RC_F[1:0] = {freq4[22], freq4[23]} = 01",
|
||||
$sformatf("RC_F[1:0]=%b", o_RC_F[1:0]));
|
||||
|
||||
// Verify RC_S[3:0] = {freq4[21], freq4[20], freq4[19], freq4[18]} = {1, 0, 1, 0} = 4'b1010
|
||||
tb_assert(o_RC_S[3:0] === 4'b1010,
|
||||
"Slot4: RC_S[3:0] = freq4[21:18] = 1010",
|
||||
$sformatf("RC_S[3:0]=%b", o_RC_S[3:0]));
|
||||
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 6: DC stub behavior
|
||||
//
|
||||
// CPLD2 CPLD_Con has DC slot cases but they are stubs:
|
||||
// - No relay output changes
|
||||
// - No PMU_OC output changes
|
||||
// - Just sets exec_flag=0, exec_done_flag=1
|
||||
//
|
||||
// The top module maps OC_x09/OC_x25 to PMU_OC via:
|
||||
// PMU_OC_N[8] = OC_x09[N-1]
|
||||
// PMU_OC_N[24] = OC_x25[N-1]
|
||||
// PMU_OC_N[7:0] = PMU_OC_internal[7:0] (always zero for DC stubs)
|
||||
// PMU_OC_N[23:9] = PMU_OC_internal[23:8] (always zero for DC stubs)
|
||||
// PMU_OC_N[31:25] = PMU_OC_internal[31:25] (always zero for DC stubs)
|
||||
//==========================================================================
|
||||
task test_dc_stub_behavior;
|
||||
reg [1:0] done_r;
|
||||
begin
|
||||
$display("");
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 6: DC stub behavior (no output changes)");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
// 6a. DC_Slot1: Should complete but produce no relay/PMU output
|
||||
$display(" DC1: Stub behavior - no relay or PMU output");
|
||||
spi_write(mk_write(7'd6, 24'h002003));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "DC1 exec done (stub)", "timeout");
|
||||
|
||||
// RC outputs should remain at their previous state or be zero
|
||||
// (DC stub doesn't change relay outputs)
|
||||
tb_assert(o_err === 1'b0,
|
||||
"DC1 stub: no error flag", "");
|
||||
|
||||
// 6b. DC_Slot2: Same stub behavior
|
||||
$display(" DC2: Stub behavior - no relay or PMU output");
|
||||
spi_write(mk_write(7'd7, 24'h004005));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "DC2 exec done (stub)", "timeout");
|
||||
tb_assert(o_err === 1'b0,
|
||||
"DC2 stub: no error flag", "");
|
||||
|
||||
// 6c. DC_Slot3: Same stub behavior
|
||||
$display(" DC3: Stub behavior - no relay or PMU output");
|
||||
spi_write(mk_write(7'd8, 24'h006007));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "DC3 exec done (stub)", "timeout");
|
||||
tb_assert(o_err === 1'b0,
|
||||
"DC3 stub: no error flag", "");
|
||||
|
||||
// 6d. DC_Slot4: Same stub behavior
|
||||
$display(" DC4: Stub behavior - no relay or PMU output");
|
||||
spi_write(mk_write(7'd9, 24'h008009));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "DC4 exec done (stub)", "timeout");
|
||||
tb_assert(o_err === 1'b0,
|
||||
"DC4 stub: no error flag", "");
|
||||
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 7: Error conditions
|
||||
//==========================================================================
|
||||
task test_error_conditions;
|
||||
reg [1:0] done_r;
|
||||
reg [31:0] rdata;
|
||||
begin
|
||||
$display("");
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 7: Error conditions");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
// 7a. Short SPI transaction (16 bits)
|
||||
$display(" Error 7a: Short SPI transaction (16 bits)");
|
||||
i_cs = 1'b0;
|
||||
@(negedge i_sclk);
|
||||
@(negedge i_sclk);
|
||||
for (integer bi = 0; bi < 16; bi = bi + 1) begin
|
||||
i_mosi = 1'b0;
|
||||
@(posedge i_sclk);
|
||||
@(negedge i_sclk);
|
||||
end
|
||||
i_cs = 1'b1;
|
||||
@(negedge i_sclk);
|
||||
#(`SYS_CLK_PERIOD * 5);
|
||||
tb_assert(o_err === 1'b1,
|
||||
"o_err HIGH after short SPI transaction", "");
|
||||
i_rst_n = 1'b0;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
|
||||
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// 7b. Write to IDENT register (ADDR 0, read-only)
|
||||
$display(" Error 7b: Write to IDENT register (ADDR 0)");
|
||||
spi_write(mk_write(7'd0, 24'hDEADBEE >> 8));
|
||||
@(negedge i_sclk);
|
||||
tb_assert(o_err === 1'b1,
|
||||
"o_err HIGH after write to IDENT register", "");
|
||||
i_rst_n = 1'b0;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
|
||||
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// 7c. Read out-of-bounds address (ADDR 16)
|
||||
$display(" Error 7c: Read out-of-bounds address (ADDR 16)");
|
||||
spi_read(mk_read(7'd16), rdata);
|
||||
@(negedge i_sclk);
|
||||
#(`SYS_CLK_PERIOD * 5);
|
||||
tb_assert(o_err === 1'b1,
|
||||
"o_err HIGH after reading ADDR 16", "");
|
||||
i_rst_n = 1'b0;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
|
||||
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// 7d. Multiple slot enable bits (en_t > 1)
|
||||
$display(" Error 7d: Multiple slot enable bits");
|
||||
spi_write(mk_write(7'd2, 24'h000005));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd3, 24'h000006));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001));
|
||||
@(negedge i_sclk);
|
||||
wait_con_done(500, done_r);
|
||||
tb_assert(done_r === 1'b1, "Execution completes (even with error)", "");
|
||||
tb_assert(o_err === 1'b1,
|
||||
"o_err HIGH with multiple slot enables", "");
|
||||
i_rst_n = 1'b0;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
|
||||
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// 7e. Write to out-of-bounds address (ADDR 31)
|
||||
$display(" Error 7e: Write to out-of-bounds address (ADDR 31)");
|
||||
spi_write(mk_write(7'd31, 24'h123456));
|
||||
@(negedge i_sclk);
|
||||
#(`SYS_CLK_PERIOD * 5);
|
||||
tb_assert(o_err === 1'b1,
|
||||
"o_err HIGH after writing ADDR 31", "");
|
||||
i_rst_n = 1'b0;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
|
||||
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Test Group 8: Edge cases
|
||||
//==========================================================================
|
||||
task test_edge_cases;
|
||||
reg [31:0] rdata;
|
||||
begin
|
||||
$display("");
|
||||
$display("-------------------------------------------------------------");
|
||||
$display(" Group 8: Edge cases");
|
||||
$display("-------------------------------------------------------------");
|
||||
|
||||
// 8a. Brief CS pulse (too short for 32-bit)
|
||||
$display(" Edge 8a: Brief CS pulse");
|
||||
i_cs = 1'b0;
|
||||
@(negedge i_sclk);
|
||||
@(negedge i_sclk);
|
||||
i_cs = 1'b1;
|
||||
@(negedge i_sclk);
|
||||
#(`SYS_CLK_PERIOD * 5);
|
||||
tb_assert(o_err === 1'b1,
|
||||
"o_err detected brief CS pulse", "");
|
||||
i_rst_n = 1'b0;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
|
||||
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// 8b. Rapid successive SPI writes
|
||||
$display(" Edge 8b: Rapid successive SPI writes");
|
||||
spi_write(mk_write(7'd2, 24'h000001));
|
||||
spi_write(mk_write(7'd3, 24'h000002));
|
||||
spi_write(mk_write(7'd4, 24'h000003));
|
||||
spi_write(mk_write(7'd5, 24'h000004));
|
||||
@(negedge i_sclk);
|
||||
spi_read(mk_read(7'd2), rdata);
|
||||
tb_assert(rdata === 24'h000001, "Rapid write: ADDR 2 correct", "ADDR 2 mismatch");
|
||||
spi_read(mk_read(7'd3), rdata);
|
||||
tb_assert(rdata === 24'h000002, "Rapid write: ADDR 3 correct", "ADDR 3 mismatch");
|
||||
spi_read(mk_read(7'd4), rdata);
|
||||
tb_assert(rdata === 24'h000003, "Rapid write: ADDR 4 correct", "ADDR 4 mismatch");
|
||||
spi_read(mk_read(7'd5), rdata);
|
||||
tb_assert(rdata === 24'h000004, "Rapid write: ADDR 5 correct", "ADDR 5 mismatch");
|
||||
|
||||
#(`SPI_CLK_PERIOD);
|
||||
|
||||
// 8c. Write to reserved registers (ADDR 10-15) - no error
|
||||
$display(" Edge 8c: Write to reserved registers");
|
||||
spi_write(mk_write(7'd10, 24'hABCDEF));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd15, 24'h123456));
|
||||
@(negedge i_sclk);
|
||||
tb_assert(o_err === 1'b0, "No error writing to reserved ADDR 10 and 15",
|
||||
"Unexpected error");
|
||||
|
||||
// 8d. Write STATE with EXEC=1 while already executing (should error)
|
||||
$display(" Edge 8d: Write STATE while already executing");
|
||||
spi_write(mk_write(7'd2, 24'h000005));
|
||||
@(negedge i_sclk);
|
||||
spi_write(mk_write(7'd1, 24'h000001)); // EXEC=1
|
||||
@(negedge i_sclk);
|
||||
// Try to write another register while EXEC is still active
|
||||
spi_write(mk_write(7'd3, 24'h000006));
|
||||
@(negedge i_sclk);
|
||||
#(`SYS_CLK_PERIOD * 5);
|
||||
tb_assert(o_err === 1'b1,
|
||||
"o_err HIGH when writing during execution", "");
|
||||
i_rst_n = 1'b0;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
i_rst_n = 1'b1;
|
||||
#(`SYS_CLK_PERIOD * 4);
|
||||
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
|
||||
|
||||
#(`SPI_CLK_PERIOD * 2);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//==========================================================================
|
||||
// Summary
|
||||
//==========================================================================
|
||||
task print_summary;
|
||||
begin
|
||||
$display("");
|
||||
$display("=============================================================");
|
||||
$display(" Test Summary");
|
||||
$display("=============================================================");
|
||||
$display(" Total tests: %0d", test_pass + test_fail);
|
||||
$display(" Passed: %0d", test_pass);
|
||||
$display(" Failed: %0d", test_fail);
|
||||
$display("=============================================================");
|
||||
if (test_fail == 0) begin
|
||||
$display(" *** ALL TESTS PASSED ***");
|
||||
end else begin
|
||||
$display(" *** SOME TESTS FAILED - CHECK DESIGN ***");
|
||||
end
|
||||
$display("=============================================================");
|
||||
$display("");
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,79 @@
|
||||
<!DOCTYPE ispTLA>
|
||||
<ispTLA>
|
||||
<CreationDate>??? 1?? 13 14:14:20 2026</CreationDate>
|
||||
<XCFFileName/>
|
||||
<CableSetting>
|
||||
<IsTRSTConnected val="false"/>
|
||||
<TRSTSetting val="0"/>
|
||||
<IsBSCANConnected val="false"/>
|
||||
<BSCANSetting val="0"/>
|
||||
<CableType val="USB"/>
|
||||
<PortAddress val="0"/>
|
||||
<PortSetting val="0"/>
|
||||
<TCKDelay val="1"/>
|
||||
</CableSetting>
|
||||
<DeviceCount>1</DeviceCount>
|
||||
<Device>
|
||||
<DeviceIndex>0</DeviceIndex>
|
||||
<DeviceName>1. LCMXO2-7000HC</DeviceName>
|
||||
<DeviceID>0x012BD043</DeviceID>
|
||||
<HasIspTRACY>true</HasIspTRACY>
|
||||
<HasJTAG2WB>false</HasJTAG2WB>
|
||||
<SERDES/>
|
||||
<IRBypassLen>8</IRBypassLen>
|
||||
<RVLFileName>debug.rvl</RVLFileName>
|
||||
<RVSFileName>debug.rvs</RVSFileName>
|
||||
<LACoreCount>1</LACoreCount>
|
||||
<WinUI CoreIndex="0">
|
||||
<TraceSigTreeData>
|
||||
<TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
|
||||
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_cs" NodeType="0" PortIndex="1"/>
|
||||
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_sclk" NodeType="0" PortIndex="2"/>
|
||||
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_mosi" NodeType="0" PortIndex="3"/>
|
||||
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_reg_busy" NodeType="0" PortIndex="4"/>
|
||||
<TraceSignal IsHidden="false" Name="CPLD_Reg_2/o_exec" NodeType="0" PortIndex="5"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T" NodeType="1" PortIndex="6">
|
||||
<BusRadix Radix="0"/>
|
||||
<IsExpanded Expand="false"/>
|
||||
</TraceSignal>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:0" NodeType="2" PortIndex="6"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:1" NodeType="2" PortIndex="7"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:2" NodeType="2" PortIndex="8"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:3" NodeType="2" PortIndex="9"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:4" NodeType="2" PortIndex="10"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:5" NodeType="2" PortIndex="11"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:6" NodeType="2" PortIndex="12"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:7" NodeType="2" PortIndex="13"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:8" NodeType="2" PortIndex="14"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:9" NodeType="2" PortIndex="15"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:10" NodeType="2" PortIndex="16"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:11" NodeType="2" PortIndex="17"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:12" NodeType="2" PortIndex="18"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:13" NodeType="2" PortIndex="19"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:14" NodeType="2" PortIndex="20"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:15" NodeType="2" PortIndex="21"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:16" NodeType="2" PortIndex="22"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:17" NodeType="2" PortIndex="23"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:18" NodeType="2" PortIndex="24"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:19" NodeType="2" PortIndex="25"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:20" NodeType="2" PortIndex="26"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:21" NodeType="2" PortIndex="27"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:22" NodeType="2" PortIndex="28"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:23" NodeType="2" PortIndex="29"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:24" NodeType="2" PortIndex="30"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:25" NodeType="2" PortIndex="31"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:26" NodeType="2" PortIndex="32"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:27" NodeType="2" PortIndex="33"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:28" NodeType="2" PortIndex="34"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:29" NodeType="2" PortIndex="35"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:30" NodeType="2" PortIndex="36"/>
|
||||
<TraceSignal IsHidden="false" Name="RC_T:31" NodeType="2" PortIndex="37"/>
|
||||
</TraceSigTreeData>
|
||||
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
|
||||
<CoreRun Run="true"/>
|
||||
<CoreWndUIData>
|
||||
<ClockFrequency Unit="ns" Frequency="-1.0"/>
|
||||
</CoreWndUIData>
|
||||
</WinUI>
|
||||
</Device>
|
||||
</ispTLA>
|
||||
+2469
File diff suppressed because one or more lines are too long
Reference in New Issue
Block a user