Init Repo
This commit is contained in:
Jeremy Shen
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#
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# vlib work
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# vlog -sv tb_RelayConTop.sv RelayConTop.v BUS_Con.v Reg_file.v CPLD_Con.v
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# vsim tb_RelayConTop
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# run -all
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# quit
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#
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# Questa Lattice OEM Edition-64 vlog 2024.2 Compiler 2024.05 May 20 2024
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# Start time: 18:32:29 on May 25,2026
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# vlog -sv tb_RelayConTop.sv RelayConTop.v BUS_Con.v Reg_file.v CPLD_Con.v
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# -- Compiling module tb_RelayConTop
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# ** Warning: tb_RelayConTop.sv(765): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
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# -- Compiling module RelayConTop
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# -- Compiling module BUS_Con
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# -- Compiling module Reg_file
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# -- Compiling module CPLD_Con
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# ** Warning: CPLD_Con.v(215): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
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#
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# Top level modules:
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# tb_RelayConTop
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# End time: 18:32:29 on May 25,2026, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 2
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# vsim tb_RelayConTop
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# Start time: 18:32:29 on May 25,2026
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# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
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# // Questa Lattice OEM Edition-64
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# // Version 2024.2 linux_x86_64 May 20 2024
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# //
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# // Unpublished work. Copyright 2024 Siemens
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# //
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# // This material contains trade secrets or otherwise confidential information
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# // owned by Siemens Industry Software Inc. or its affiliates (collectively,
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# // "SISW"), or its licensors. Access to and use of this information is strictly
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# // limited as set forth in the Customer's applicable agreements with SISW.
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# //
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# // This material may not be copied, distributed, or otherwise disclosed outside
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# // of the Customer's facilities without the express written permission of SISW,
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# // and may not be used in any way not expressly authorized by SISW.
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# //
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# Loading sv_std.std
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# Loading work.tb_RelayConTop(fast)
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#
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# =============================================================
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# CPLD1 RelayConTop - Comprehensive Testbench
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# System clock: 50 MHz | SPI clock: 2 MHz
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# =============================================================
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#
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# -------------------------------------------------------------
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# Group 1: Reset behavior & IDENT register
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# -------------------------------------------------------------
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# [PASS] Test 1: controller idle)
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# [PASS] Test 2: LOW after reset
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# [PASS] Test 3: eset (SPI ready)
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# [FAIL] Test 4: (CPLD1, v1.1.0) >>
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# [PASS] Test 5:
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# eros after reset
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# [PASS] Test 6:
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# eros after reset
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# [PASS] Test 7: zero after reset
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#
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# -------------------------------------------------------------
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# Group 2: Register read/write (ADDR 0-9)
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# -------------------------------------------------------------
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# [FAIL] Test 8: write/read back >>
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# [FAIL] Test 9: write/read back >>
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# [FAIL] Test 10: write/read back >>
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# [FAIL] Test 11: write/read back >>
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# [FAIL] Test 12: back (PMU mode) >>
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# [FAIL] Test 13: write/read back >>
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# [FAIL] Test 14: write/read back >>
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# [FAIL] Test 15: write/read back >>
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# [FAIL] Test 16: default (RDY=1) >>
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#
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# -------------------------------------------------------------
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# Group 3: Execution protocol
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# -------------------------------------------------------------
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# [PASS] Test 17: cution completes
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# [FAIL] Test 18: essful execution >>
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# [PASS] Test 19: tion (SPI ready)
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# [PASS] Test 20: tes successfully
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# [FAIL] Test 21: C slot execution >>
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#
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# -------------------------------------------------------------
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# Group 4: Frequency slot decoding (all 4 slots)
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# -------------------------------------------------------------
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# Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1
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# [PASS] Test 22: t1 Ch5 exec done
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# [FAIL] Test 23: ot1: RC_T27 idle >> RC_T27 mismatch
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# [FAIL] Test 24: 5: PMU_OC_1[0]=1 >> OC_1[0] mismatch
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# [FAIL] Test 25: Ch5: DMM_EN[0]=1 >>
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# M_EN[0] mismatch
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# [PASS] Test 26: 5: PMU_OC_2[0]=0
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# Slot1 Ch50 (range 9-72): DMM_EN[1]=1
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# [PASS] Test 27: 1 Ch50 exec done
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# [FAIL] Test 28: h50: DMM_EN[1]=1 >>
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# M_EN[1] mismatch
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# [PASS] Test 29: 0: PMU_OC_1[0]=0
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# Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1
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# [PASS] Test 30: Ch100 exec done
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# [FAIL] Test 31: : PMU_OC_1[16]=1 >> C_1[16] mismatch
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# [FAIL] Test 32: 100: DMM_EN[2]=1 >>
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# M_EN[2] mismatch
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# Slot1 Ch150 (range 137-200): DMM_EN[3]=1
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# [PASS] Test 33: Ch150 exec done
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# [FAIL] Test 34: 150: DMM_EN[3]=1 >>
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# M_EN[3] mismatch
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# Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1
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# [PASS] Test 35: t2 Ch5 exec done
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# [FAIL] Test 36: 5: PMU_OC_2[0]=1 >> OC_2[0] mismatch
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# [FAIL] Test 37: Ch5: DMM_EN[4]=1 >>
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# M_EN[4] mismatch
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# Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1
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# [PASS] Test 38: Ch100 exec done
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# [FAIL] Test 39: : PMU_OC_3[16]=1 >> C_3[16] mismatch
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# [FAIL] Test 40: 00: DMM_EN[10]=1 >>
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# _EN[10] mismatch
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# Slot4 Ch50 (range 9-72): DMM_EN[5]=1
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# [PASS] Test 41: 4 Ch50 exec done
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# [FAIL] Test 42: h50: DMM_EN[5]=1 >>
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# M_EN[5] mismatch
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#
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# -------------------------------------------------------------
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# Group 5: DC slot PMU mode (DPS is stubbed, not tested)
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# -------------------------------------------------------------
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# DC1: V mode, Rload=3, Ch=3, PMU
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# [PASS] Test 43: V-mode exec done
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# [PASS] Test 44: _VSel=1 (V mode)
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# [PASS] Test 45: _ISel=0 (V mode)
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# [FAIL] Test 46: 8'b100 (Rload=3) >> C_RLSel mismatch
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# [FAIL] Test 47: OC_1[0]=1 (Ch=3) >> OC_1[0] mismatch
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# DC1: I mode, Rload=1, Ch=11, PMU
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# [PASS] Test 48: I-mode exec done
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# [FAIL] Test 49: _VSel=0 (I mode) >> RC_VSel mismatch
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# [FAIL] Test 50: _ISel=1 (I mode) >> RC_ISel mismatch
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# [FAIL] Test 51: l[0]=1 (Rload=1) >> C_RLSel mismatch
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# [FAIL] Test 52: C_1[1]=1 (Ch=11) >> OC_1[1] mismatch
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# DC2: V mode, Rload=5, Ch=19, PMU
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# [PASS] Test 53: V-mode exec done
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# [PASS] Test 54: _VSel=1 (V mode)
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# [FAIL] Test 55: C_2[2]=1 (Ch=19) >> OC_2[2] mismatch
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# DC3: V mode, Rload=10, Ch=27, PMU
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# [PASS] Test 56: V-mode exec done
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# [FAIL] Test 57: C_3[3]=1 (Ch=27) >> OC_3[3] mismatch
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# DC4: V mode, Rload=18, Ch=35, PMU
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# [PASS] Test 58: V-mode exec done
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# [FAIL] Test 59: 17]=1 (Rload=18) >> C_RLSel mismatch
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# [FAIL] Test 60: C_4[4]=1 (Ch=35) >> OC_4[4] mismatch
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# [PASS] Test 61: 1 when RC_VSel=1
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#
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# -------------------------------------------------------------
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# Group 6: RC_Tx relay output (slot 4)
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# -------------------------------------------------------------
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# Slot4: RC_Tx = 6'b101010
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# [PASS] Test 62: RC_Tx exec done
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# [FAIL] Test 63: T27=1 (RC_Tx[5]) >> RC_T27 mismatch
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# [FAIL] Test 64: T28=0 (RC_Tx[4]) >> RC_T28 mismatch
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# [FAIL] Test 65: T29=1 (RC_Tx[3]) >> RC_T29 mismatch
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# [FAIL] Test 66: T30=0 (RC_Tx[2]) >> RC_T30 mismatch
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# [FAIL] Test 67: T31=1 (RC_Tx[1]) >> RC_T31 mismatch
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# [FAIL] Test 68: T32=0 (RC_Tx[0]) >> RC_T32 mismatch
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#
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# -------------------------------------------------------------
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# Group 7: Error conditions
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# -------------------------------------------------------------
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# Error 7a: Short SPI transaction (16 bits)
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# [PASS] Test 69: SPI transaction
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# [PASS] Test 70: ared after reset
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# Error 7b: Write to IDENT register (ADDR 0)
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# [PASS] Test 71: o IDENT register
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# [PASS] Test 72: ared after reset
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# Error 7c: Read out-of-bounds address (ADDR 16)
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# [PASS] Test 73: reading ADDR 16
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# [PASS] Test 74: ared after reset
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# Error 7d: Multiple slot enable bits
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# [PASS] Test 75: even with error)
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# [PASS] Test 76: ple slot enables
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# [PASS] Test 77: ared after reset
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# Error 7e: Write to out-of-bounds address (ADDR 31)
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# [PASS] Test 78: writing ADDR 31
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# [PASS] Test 79: ared after reset
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#
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# -------------------------------------------------------------
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# Group 8: Edge cases
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# -------------------------------------------------------------
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# Edge 8a: Brief CS pulse
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# [PASS] Test 80: d brief CS pulse
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# [PASS] Test 81: ared after reset
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# Edge 8b: Rapid successive SPI writes
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# [FAIL] Test 82: : ADDR 2 correct >> ADDR 2 mismatch
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# [FAIL] Test 83: : ADDR 3 correct >> ADDR 3 mismatch
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# [FAIL] Test 84: : ADDR 4 correct >> ADDR 4 mismatch
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# [FAIL] Test 85: : ADDR 5 correct >> ADDR 5 mismatch
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# Edge 8c: Write to reserved registers
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# [FAIL] Test 86: d ADDR 10 and 15 >> Unexpected error
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#
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# =============================================================
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# Test Summary
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# =============================================================
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# Total tests: 86
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# Passed: 41
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# Failed: 45
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# =============================================================
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# *** SOME TESTS FAILED - CHECK DESIGN ***
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# =============================================================
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#
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# ** Note: $finish : tb_RelayConTop.sv(349)
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# Time: 1101600 ns Iteration: 0 Instance: /tb_RelayConTop
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# End time: 18:32:29 on May 25,2026, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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