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This commit is contained in:
Jeremy Shen
2026-05-28 09:30:38 +08:00
parent 81e230066e
commit 0d6272e7c9
97 changed files with 180289 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
CPLD2/impl1/NewExtIns_CPLD2_impl1.areasrr
+162
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@@ -0,0 +1,162 @@
----------------------------------------------------------------------
Report for cell RelayConTop.verilog
Register bits: 1275 of 6864 (19%)
PIC Latch: 0
I/O cells: 187
Cell usage:
cell count Res Usage(%)
CCU2D 59 100.0
FD1P3AX 427 100.0
FD1P3AY 3 100.0
FD1P3BX 33 100.0
FD1P3DX 347 100.0
FD1P3IX 175 100.0
FD1P3JX 1 100.0
FD1S3AX 20 100.0
FD1S3AY 1 100.0
FD1S3BX 4 100.0
FD1S3DX 87 100.0
FD1S3IX 33 100.0
FD1S3JX 1 100.0
GSR 1 100.0
IB 5 100.0
IFS1P3IX 2 100.0
IFS1P3JX 1 100.0
INV 18 100.0
L6MUX21 74 100.0
OB 181 100.0
OBZ 1 100.0
OFS1P3DX 4 100.0
OFS1P3IX 136 100.0
ORCALUT4 1290 100.0
PFUMX 104 100.0
PUR 1 100.0
VHI 15 100.0
VLO 15 100.0
jtagconn16 1 100.0
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
BUS_Con_uniq_1 1 100.0
CPLD_Con_uniq_1 1 100.0
Reg_file_uniq_1 1 100.0
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
reveal_coretop 1 100.0
TOTAL 3049
----------------------------------------------------------------------
Report for cell CPLD_Con_uniq_1.netlist
Instance path: CPLD_Con_2
Cell usage:
cell count Res Usage(%)
CCU2D 9 15.3
FD1P3IX 44 25.1
FD1P3JX 1 100.0
FD1S3AX 14 70.0
FD1S3IX 23 69.7
INV 1 5.6
ORCALUT4 339 26.3
VHI 1 6.7
VLO 1 6.7
TOTAL 433
----------------------------------------------------------------------
Report for cell Reg_file_uniq_1.netlist
Instance path: CPLD_Reg_2
Cell usage:
cell count Res Usage(%)
FD1P3AX 409 95.8
FD1P3AY 3 100.0
FD1S3AX 4 20.0
FD1S3AY 1 100.0
L6MUX21 72 97.3
ORCALUT4 250 19.4
PFUMX 97 93.3
VHI 1 6.7
VLO 1 6.7
TOTAL 838
----------------------------------------------------------------------
Report for cell BUS_Con_uniq_1.netlist
Instance path: BUS_Con_2
Cell usage:
cell count Res Usage(%)
FD1P3IX 131 74.9
FD1S3AX 2 10.0
FD1S3IX 10 30.3
FD1S3JX 1 100.0
ORCALUT4 96 7.4
VHI 1 6.7
VLO 1 6.7
TOTAL 242
----------------------------------------------------------------------
Report for cell reveal_coretop.verilog
Instance path: RelayConTop_reveal_coretop_instance
Cell usage:
cell count Res Usage(%)
CCU2D 50 84.7
FD1P3AX 18 4.2
FD1P3BX 33 100.0
FD1P3DX 347 100.0
FD1S3BX 4 100.0
FD1S3DX 87 100.0
INV 16 88.9
L6MUX21 2 2.7
ORCALUT4 605 46.9
PFUMX 7 6.7
VHI 11 73.3
VLO 11 73.3
jtagconn16 1 100.0
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
TOTAL 1197
----------------------------------------------------------------------
Report for cell relaycontop_la0.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0
Cell usage:
cell count Res Usage(%)
CCU2D 50 84.7
FD1P3AX 18 4.2
FD1P3BX 33 100.0
FD1P3DX 347 100.0
FD1S3BX 4 100.0
FD1S3DX 87 100.0
INV 16 88.9
L6MUX21 2 2.7
ORCALUT4 605 46.9
PFUMX 7 6.7
VHI 10 66.7
VLO 10 66.7
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0_trig 1 100.0
TOTAL 1193
----------------------------------------------------------------------
Report for cell relaycontop_la0_trig.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u
Cell usage:
cell count Res Usage(%)
CCU2D 18 30.5
FD1P3AX 16 3.7
FD1P3BX 1 3.0
FD1P3DX 61 17.6
FD1S3BX 4 100.0
FD1S3DX 32 36.8
INV 9 50.0
L6MUX21 2 2.7
ORCALUT4 193 15.0
PFUMX 7 6.7
VHI 7 46.7
VLO 7 46.7
pmi_distributed_dpram_4s_2s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 2 100.0
TOTAL 359
CPLD2/impl1/NewExtIns_CPLD2_impl1.bit
BIN
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Binary file not shown.
CPLD2/impl1/NewExtIns_CPLD2_impl1.hub
+1
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@@ -0,0 +1 @@
HUBID_00 REVEAL_0
CPLD2/impl1/NewExtIns_CPLD2_impl1.jed
+11472
View File
File diff suppressed because it is too large Load Diff
CPLD2/impl1/NewExtIns_CPLD2_impl1.p2t.tmp0
+9
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@@ -0,0 +1,9 @@
-w
-l 5
-i 6
-n 1
-t 1
-s 1
-c 0
-e 0
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
CPLD2/impl1/NewExtIns_CPLD2_impl1.pt
+10
View File
@@ -0,0 +1,10 @@
-v
10
-gt
-sethld
-sp 4
-sphld m
CPLD2/impl1/NewExtIns_CPLD2_impl1_map.cam
+258
View File
@@ -0,0 +1,258 @@
[ START MERGED ]
i_rst_n_c_i i_rst_n_c
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/tt_wr_en
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jshift_d2.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn
xo2chub/cdn.CN jtaghub16_jtck
xo2chub/jrstn_i jtaghub16_jrstn
[ END MERGED ]
[ START CLIPPED ]
xo2chub/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te_0[2]
CPLD_Con_2/GND
xo2chub/VCC
xo2chub/bit_count_cry_0_COUT[3]
xo2chub/rom_rd_addr_cry_0_S0[0]
xo2chub/N_2
xo2chub/rom_rd_addr_s_0_S1[7]
xo2chub/rom_rd_addr_s_0_COUT[7]
xo2chub/jtdo2_int_prm_16_0_0_S1
xo2chub/jtdo2_int_prm_16_0_0_S0
xo2chub/N_3
xo2chub/er2_tdo[14]
xo2chub/er2_tdo[15]
xo2chub/jtdo2_int_prm_15_0_0_S1
xo2chub/jtdo2_int_prm_15_0_0_S0
xo2chub/er2_tdo[12]
xo2chub/er2_tdo[13]
xo2chub/jtdo2_int_prm_13_0_0_S1
xo2chub/jtdo2_int_prm_13_0_0_S0
xo2chub/er2_tdo[10]
xo2chub/er2_tdo[11]
xo2chub/jtdo2_int_prm_11_0_0_S1
xo2chub/jtdo2_int_prm_11_0_0_S0
xo2chub/er2_tdo[8]
xo2chub/er2_tdo[9]
xo2chub/jtdo2_int_prm_9_0_0_S1
xo2chub/jtdo2_int_prm_9_0_0_S0
xo2chub/er2_tdo[6]
xo2chub/er2_tdo[7]
xo2chub/jtdo2_int_prm_7_0_0_S1
xo2chub/jtdo2_int_prm_7_0_0_S0
xo2chub/er2_tdo[4]
xo2chub/er2_tdo[5]
xo2chub/jtdo2_int_prm_5_0_0_S1
xo2chub/jtdo2_int_prm_5_0_0_S0
xo2chub/er2_tdo[2]
xo2chub/er2_tdo[3]
xo2chub/jtdo2_int_prm_3_0_0_S1
xo2chub/jtdo2_int_prm_3_0_0_S0
xo2chub/er2_tdo[1]
xo2chub/jtdo2_int_prm_1_0_0_S0
xo2chub/jtdo2_int_prm_1_0_0_COUT
xo2chub/ip_enable[15]
xo2chub/genblk7.un1_jtagf_u_1
xo2chub/genblk7.un1_jtagf_u
xo2chub/tdoa
xo2chub/tdia
xo2chub/tmsa
xo2chub/tcka
xo2chub/cdn
xo2chub/bit_count_cry_0_S0[0]
xo2chub/N_1
GND
VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_S1[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_COUT[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_S1[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_COUT[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu_0[3]
CPLD_Con_2/un1_delay_cnt_1_s_15_0_S1
CPLD_Con_2/un1_delay_cnt_1_s_15_0_COUT
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S1
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S0
CPLD_Con_2/N_10
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:49:45 2026
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "i_sys_clk" SITE "B9" ;
LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
LOCATE COMP "o_RC_T[24]" SITE "T13" ;
LOCATE COMP "o_RC_T[23]" SITE "U15" ;
LOCATE COMP "o_RC_T[22]" SITE "T15" ;
LOCATE COMP "o_RC_T[21]" SITE "Y17" ;
LOCATE COMP "o_RC_T[20]" SITE "W17" ;
LOCATE COMP "o_RC_T[19]" SITE "W19" ;
LOCATE COMP "o_RC_T[18]" SITE "AB20" ;
LOCATE COMP "o_RC_T[17]" SITE "AA19" ;
LOCATE COMP "o_RC_T[16]" SITE "Y18" ;
LOCATE COMP "o_RC_T[15]" SITE "AB17" ;
LOCATE COMP "o_RC_T[14]" SITE "V16" ;
LOCATE COMP "o_RC_T[13]" SITE "V14" ;
LOCATE COMP "o_RC_T[12]" SITE "V13" ;
LOCATE COMP "o_RC_T[11]" SITE "Y12" ;
LOCATE COMP "o_RC_T[10]" SITE "W12" ;
LOCATE COMP "o_RC_T[9]" SITE "V12" ;
LOCATE COMP "o_RC_T[8]" SITE "V8" ;
LOCATE COMP "o_RC_T[7]" SITE "AB13" ;
LOCATE COMP "o_RC_T[6]" SITE "AA12" ;
LOCATE COMP "o_RC_T[5]" SITE "AB11" ;
LOCATE COMP "o_RC_T[4]" SITE "AA11" ;
LOCATE COMP "o_RC_T[3]" SITE "AA10" ;
LOCATE COMP "o_RC_T[2]" SITE "AB10" ;
LOCATE COMP "o_RC_T[1]" SITE "Y10" ;
LOCATE COMP "o_RC_T[0]" SITE "AA8" ;
LOCATE COMP "o_RC_S[15]" SITE "AA7" ;
LOCATE COMP "o_RC_S[14]" SITE "AB7" ;
LOCATE COMP "o_RC_S[13]" SITE "Y7" ;
LOCATE COMP "o_RC_S[12]" SITE "Y6" ;
LOCATE COMP "o_RC_S[11]" SITE "AB6" ;
LOCATE COMP "o_RC_S[10]" SITE "AB5" ;
LOCATE COMP "o_RC_S[9]" SITE "W6" ;
LOCATE COMP "o_RC_S[8]" SITE "Y5" ;
LOCATE COMP "o_RC_S[7]" SITE "AA4" ;
LOCATE COMP "o_RC_S[6]" SITE "Y4" ;
LOCATE COMP "o_RC_S[5]" SITE "AB3" ;
LOCATE COMP "o_RC_S[4]" SITE "AA3" ;
LOCATE COMP "o_RC_S[3]" SITE "Y3" ;
LOCATE COMP "o_RC_S[2]" SITE "AB2" ;
LOCATE COMP "o_RC_S[1]" SITE "W9" ;
LOCATE COMP "o_RC_S[0]" SITE "T10" ;
LOCATE COMP "o_RC_F[7]" SITE "U10" ;
LOCATE COMP "o_RC_F[6]" SITE "W11" ;
LOCATE COMP "o_RC_F[5]" SITE "V11" ;
LOCATE COMP "o_RC_F[4]" SITE "U11" ;
LOCATE COMP "o_RC_F[3]" SITE "T11" ;
LOCATE COMP "o_RC_F[2]" SITE "T12" ;
LOCATE COMP "o_RC_F[1]" SITE "U12" ;
LOCATE COMP "o_RC_F[0]" SITE "U13" ;
LOCATE COMP "o_err" SITE "AB16" ;
LOCATE COMP "i_cs" SITE "Y15" ;
LOCATE COMP "i_mosi" SITE "AB12" ;
LOCATE COMP "i_sclk" SITE "AA16" ;
LOCATE COMP "i_rst_n" SITE "Y14" ;
USE PRIMARY NET "i_sys_clk_c" ;
SCHEMATIC END ;
[ END DESIGN PREFS ]
CPLD2/impl1/NewExtIns_CPLD2_impl1_map.hrr
+209
View File
@@ -0,0 +1,209 @@
---------------------------------------------------
Report for cell RelayConTop
Instance path: RelayConTop
Cell usage:
cell count Res Usage(%)
SLIC 760.00 100.0
IOLGC 142.00 100.0
LUT4 1344.00 100.0
DISTRAM 6.00 100.0
IOREG 142 100.0
IOBUF 187 100.0
PFUREG 1190 100.0
RIPPLE 76 100.0
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
xo2chub 1 3.2
reveal_coretop 1 42.6
Reg_file_uniq_1 1 28.8
CPLD_Con_uniq_1 1 17.3
BUS_Con_uniq_1 1 8.1
---------------------------------------------------
Report for cell CPLD_Con_uniq_1
Instance path: RelayConTop/CPLD_Con_2
Cell usage:
cell count Res Usage(%)
SLIC 131.50 17.3
LUT4 340.00 25.3
PFUREG 82 6.9
RIPPLE 9 11.8
---------------------------------------------------
Report for cell Reg_file_uniq_1
Instance path: RelayConTop/CPLD_Reg_2
Cell usage:
cell count Res Usage(%)
SLIC 218.58 28.8
LUT4 250.00 18.6
PFUREG 417 35.0
---------------------------------------------------
Report for cell BUS_Con_uniq_1
Instance path: RelayConTop/BUS_Con_2
Cell usage:
cell count Res Usage(%)
SLIC 61.75 8.1
LUT4 96.00 7.1
PFUREG 144 12.1
---------------------------------------------------
Report for cell reveal_coretop
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance
Cell usage:
cell count Res Usage(%)
SLIC 323.42 42.6
LUT4 645.00 48.0
DISTRAM 4.00 66.7
PFUREG 495 41.6
RIPPLE 50 65.8
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
relaycontop_la0 1 42.6
---------------------------------------------------
Report for cell relaycontop_la0
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0
Cell usage:
cell count Res Usage(%)
SLIC 323.42 42.6
LUT4 645.00 48.0
DISTRAM 4.00 66.7
PFUREG 495 41.6
RIPPLE 50 65.8
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
rvl_tm_Z3 1 15.6
rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s 1 14.4
relaycontop_la0_trig 1 12.5
---------------------------------------------------
Report for cell relaycontop_la0_trig
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u
Cell usage:
cell count Res Usage(%)
SLIC 95.13 12.5
LUT4 189.00 14.1
DISTRAM 4.00 66.7
PFUREG 118 9.9
RIPPLE 18 23.7
SUB MODULES
cell count SLC Usage(%)
rvl_tu_1s_0s_0s_0s_1s_2 1 0.8
rvl_tu_1s_0s_0s_0s_1s_1 1 0.8
rvl_tcnt_2s_3s_1_0s 1 1.3
rvl_te_Z1_0 1 4.0
rvl_te_Z1_1 1 4.8
rvl_decode_2s_2s 1 0.4
---------------------------------------------------
Report for cell rvl_decode_2s_2s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u
Cell usage:
cell count Res Usage(%)
SLIC 3.10 0.4
LUT4 12.50 0.9
---------------------------------------------------
Report for cell rvl_tu_1s_0s_0s_0s_1s_2
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0
Cell usage:
cell count Res Usage(%)
SLIC 6.08 0.8
LUT4 11.00 0.8
PFUREG 8 0.7
---------------------------------------------------
Report for cell rvl_tu_1s_0s_0s_0s_1s_1
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1
Cell usage:
cell count Res Usage(%)
SLIC 6.18 0.8
LUT4 12.00 0.9
PFUREG 8 0.7
---------------------------------------------------
Report for cell rvl_te_Z1_1
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0
Cell usage:
cell count Res Usage(%)
SLIC 36.20 4.8
LUT4 69.50 5.2
DISTRAM 2.00 33.3
PFUREG 53 4.5
RIPPLE 9 11.8
SUB MODULES
cell count SLC Usage(%)
pmi_distributed_dpramXbnoner224pb08036b 1 0.3
---------------------------------------------------
Report for cell pmi_distributed_dpramXbnoner224pb08036b
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram
Cell usage:
cell count Res Usage(%)
SLIC 2.25 0.3
LUT4 1.00 0.1
DISTRAM 2.00 33.3
PFUREG 2 0.2
---------------------------------------------------
Report for cell rvl_te_Z1_0
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1
Cell usage:
cell count Res Usage(%)
SLIC 30.33 4.0
LUT4 53.00 3.9
DISTRAM 2.00 33.3
PFUREG 36 3.0
RIPPLE 9 11.8
SUB MODULES
cell count SLC Usage(%)
pmi_distributed_dpramXbnoner224pb08036b_0 1 0.3
---------------------------------------------------
Report for cell pmi_distributed_dpramXbnoner224pb08036b_0
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram
Cell usage:
cell count Res Usage(%)
SLIC 2.25 0.3
LUT4 1.00 0.1
DISTRAM 2.00 33.3
PFUREG 2 0.2
---------------------------------------------------
Report for cell rvl_tcnt_2s_3s_1_0s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0
Cell usage:
cell count Res Usage(%)
SLIC 9.73 1.3
LUT4 22.00 1.6
PFUREG 13 1.1
---------------------------------------------------
Report for cell rvl_jtag_int_42s_2s_0s_0s_6s_42s_42s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u
Cell usage:
cell count Res Usage(%)
SLIC 109.27 14.4
LUT4 249.50 18.6
PFUREG 168 14.1
RIPPLE 8 10.5
---------------------------------------------------
Report for cell rvl_tm_Z3
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u
Cell usage:
cell count Res Usage(%)
SLIC 118.57 15.6
LUT4 205.00 15.3
PFUREG 209 17.6
RIPPLE 24 31.6
EBR 10 100.0
SUB MODULES
cell count SLC Usage(%)
pmi_ram_dpXbnonesadr4211204842112048p1395c895 1 1.4
---------------------------------------------------
Report for cell pmi_ram_dpXbnonesadr4211204842112048p1395c895
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem
Cell usage:
cell count Res Usage(%)
SLIC 11.00 1.4
LUT4 42.00 3.1
PFUREG 2 0.2
EBR 10 100.0
---------------------------------------------------
Report for cell xo2chub
Instance path: RelayConTop/xo2chub
Cell usage:
cell count Res Usage(%)
SLIC 24.25 3.2
LUT4 12.00 0.9
PFUREG 51 4.3
RIPPLE 17 22.4
CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify.lpf
+26
View File
@@ -0,0 +1,26 @@
#
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
#
# Period Constraints
#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz;
#FREQUENCY PORT "i_sys_clk" 200.0 MHz;
# Output Constraints
# Input Constraints
# Point-to-point Delay Constraints
# Block Path Constraints
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
BLOCK ASYNCPATHS;
# End of generated Logical Preferences.
CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp2.lpf
View File
CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp4.lpf
View File
CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify_tmp8.lpf
View File
CPLD2/impl1/_cmd._cml
+1
View File
@@ -0,0 +1 @@
-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/NewExtIns_CPLD2_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/impl1/synwork/layer0.srs -jobname linker
CPLD2/impl1/impl1.xcf
+52
View File
@@ -0,0 +1,52 @@
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.12">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>MachXO2</Family>
<Name>LCMXO2-7000HC</Name>
<IDCode>0x012bd043</IDCode>
<Package>All</Package>
<PON>LCMXO2-7000HC</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File>
<FileTime>01/20/26 16:01:30</FileTime>
<JedecChecksum>0x566E</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>664</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>SVF Processor</SVFProcessor>
<Usercode>0x00000000</Usercode>
<AccessMode>FLASH</AccessMode>
</Option>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
<TCKDelay>1</TCKDelay>
</ProjectOptions>
<CableOptions>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID>
</CableOptions>
</ispXCF>
CPLD2/impl1/pmi_distributed_dpramXbnoner224pb08036b.edn
+233
View File
@@ -0,0 +1,233 @@
(edif pmi_distributed_dpramXbnoner224pb08036b
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 26 15 49 44)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner224pb08036b
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(1:0)") 2)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(1:0)") 2)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-3)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner224pb08036b__PMI__4__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef RAD2 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef WAD2 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr1
(joined
(portRef (member RdAddress 0))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 1))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 0))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 1))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner224pb08036b
(cellRef pmi_distributed_dpramXbnoner224pb08036b
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner224pb08036b_0.edn
+233
View File
@@ -0,0 +1,233 @@
(edif pmi_distributed_dpramXbnoner224pb08036b_0
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 26 15 49 45)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner224pb08036b_0
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(1:0)") 2)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(1:0)") 2)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-3)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner224pb08036b_0__PMI__4__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef RAD2 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef WAD2 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr1
(joined
(portRef (member RdAddress 0))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 1))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 0))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 1))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner224pb08036b_0
(cellRef pmi_distributed_dpramXbnoner224pb08036b_0
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2.edn
+239
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@@ -0,0 +1,239 @@
(edif pmi_distributed_dpramXbnoner238pb0819f2
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 15 18 6 2)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner238pb0819f2
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(2:0)") 3)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(2:0)") 3)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-7)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner238pb0819f2__PMI__8__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr2
(joined
(portRef (member RdAddress 0))
(portRef RAD2 (instanceRef mem_0_0))))
(net raddr1
(joined
(portRef (member RdAddress 1))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 2))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr2
(joined
(portRef (member WrAddress 0))
(portRef WAD2 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 1))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 2))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner238pb0819f2
(cellRef pmi_distributed_dpramXbnoner238pb0819f2
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2_0.edn
+239
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@@ -0,0 +1,239 @@
(edif pmi_distributed_dpramXbnoner238pb0819f2_0
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 15 18 6 2)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_0 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner238pb0819f2_0
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(2:0)") 3)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(2:0)") 3)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-7)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner238pb0819f2_0__PMI__8__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr2
(joined
(portRef (member RdAddress 0))
(portRef RAD2 (instanceRef mem_0_0))))
(net raddr1
(joined
(portRef (member RdAddress 1))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 2))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr2
(joined
(portRef (member WrAddress 0))
(portRef WAD2 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 1))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 2))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner238pb0819f2_0
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_0
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_distributed_dpramXbnoner238pb0819f2_1.edn
+239
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@@ -0,0 +1,239 @@
(edif pmi_distributed_dpramXbnoner238pb0819f2_1
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2026 5 15 18 6 2)
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_1 -pmi ")
(library ORCLIB
(edifLevel 0)
(technology
(numberDefinition))
(cell FD1P3DX
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port D
(direction INPUT))
(port SP
(direction INPUT))
(port CK
(direction INPUT))
(port CD
(direction INPUT))
(port Q
(direction OUTPUT)))))
(cell ROM16X1A
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port AD3
(direction INPUT))
(port AD2
(direction INPUT))
(port AD1
(direction INPUT))
(port AD0
(direction INPUT))
(port DO0
(direction OUTPUT)))))
(cell DPR16X4C
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port DI0
(direction INPUT))
(port DI1
(direction INPUT))
(port DI2
(direction INPUT))
(port DI3
(direction INPUT))
(port WCK
(direction INPUT))
(port WRE
(direction INPUT))
(port RAD0
(direction INPUT))
(port RAD1
(direction INPUT))
(port RAD2
(direction INPUT))
(port RAD3
(direction INPUT))
(port WAD0
(direction INPUT))
(port WAD1
(direction INPUT))
(port WAD2
(direction INPUT))
(port WAD3
(direction INPUT))
(port DO0
(direction OUTPUT))
(port DO1
(direction OUTPUT))
(port DO2
(direction OUTPUT))
(port DO3
(direction OUTPUT)))))
(cell VHI
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port Z
(direction OUTPUT)))))
(cell pmi_distributed_dpramXbnoner238pb0819f2_1
(cellType GENERIC)
(view view1
(viewType NETLIST)
(interface
(port (array (rename WrAddress "WrAddress(2:0)") 3)
(direction INPUT))
(port (array (rename Data "Data(1:0)") 2)
(direction INPUT))
(port WrClock
(direction INPUT))
(port WE
(direction INPUT))
(port WrClockEn
(direction INPUT))
(port (array (rename RdAddress "RdAddress(2:0)") 3)
(direction INPUT))
(port RdClock
(direction INPUT))
(port RdClockEn
(direction INPUT))
(port Reset
(direction INPUT))
(port (array (rename Q "Q(1:0)") 2)
(direction OUTPUT)))
(property NGD_DRC_MASK (integer 1))
(contents
(instance LUT4_0
(viewRef view1
(cellRef ROM16X1A))
(property initval
(string "0x8000")))
(instance FF_1
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance FF_0
(viewRef view1
(cellRef FD1P3DX))
(property GSR
(string "ENABLED")))
(instance scuba_vhi_inst
(viewRef view1
(cellRef VHI)))
(instance mem_0_0
(viewRef view1
(cellRef DPR16X4C))
(property MEM_INIT_FILE
(string "(0-7)(0-1)"))
(property MEM_LPC_FILE
(string "pmi_distributed_dpramXbnoner238pb0819f2_1__PMI__8__2__2B"))
(property COMP
(string "mem_0_0"))
(property initval
(string "0x0000000000000000")))
(net dataout1_ffin
(joined
(portRef DO1 (instanceRef mem_0_0))
(portRef D (instanceRef FF_1))))
(net dataout0_ffin
(joined
(portRef DO0 (instanceRef mem_0_0))
(portRef D (instanceRef FF_0))))
(net dec0_wre3
(joined
(portRef WRE (instanceRef mem_0_0))
(portRef DO0 (instanceRef LUT4_0))))
(net scuba_vhi
(joined
(portRef Z (instanceRef scuba_vhi_inst))
(portRef AD0 (instanceRef LUT4_0))
(portRef AD1 (instanceRef LUT4_0))
(portRef RAD3 (instanceRef mem_0_0))
(portRef WAD3 (instanceRef mem_0_0))
(portRef DI3 (instanceRef mem_0_0))
(portRef DI2 (instanceRef mem_0_0))))
(net dataout1
(joined
(portRef (member Q 0))
(portRef Q (instanceRef FF_1))))
(net dataout0
(joined
(portRef (member Q 1))
(portRef Q (instanceRef FF_0))))
(net reset
(joined
(portRef Reset)
(portRef CD (instanceRef FF_1))
(portRef CD (instanceRef FF_0))))
(net rden
(joined
(portRef RdClockEn)
(portRef SP (instanceRef FF_1))
(portRef SP (instanceRef FF_0))))
(net rdclk
(joined
(portRef RdClock)
(portRef CK (instanceRef FF_1))
(portRef CK (instanceRef FF_0))))
(net raddr2
(joined
(portRef (member RdAddress 0))
(portRef RAD2 (instanceRef mem_0_0))))
(net raddr1
(joined
(portRef (member RdAddress 1))
(portRef RAD1 (instanceRef mem_0_0))))
(net raddr0
(joined
(portRef (member RdAddress 2))
(portRef RAD0 (instanceRef mem_0_0))))
(net cken
(joined
(portRef WrClockEn)
(portRef AD2 (instanceRef LUT4_0))))
(net wren
(joined
(portRef WE)
(portRef AD3 (instanceRef LUT4_0))))
(net clk
(joined
(portRef WrClock)
(portRef WCK (instanceRef mem_0_0))))
(net datain1
(joined
(portRef (member Data 0))
(portRef DI1 (instanceRef mem_0_0))))
(net datain0
(joined
(portRef (member Data 1))
(portRef DI0 (instanceRef mem_0_0))))
(net waddr2
(joined
(portRef (member WrAddress 0))
(portRef WAD2 (instanceRef mem_0_0))))
(net waddr1
(joined
(portRef (member WrAddress 1))
(portRef WAD1 (instanceRef mem_0_0))))
(net waddr0
(joined
(portRef (member WrAddress 2))
(portRef WAD0 (instanceRef mem_0_0))))))))
(design pmi_distributed_dpramXbnoner238pb0819f2_1
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_1
(libraryRef ORCLIB)))
)
CPLD2/impl1/pmi_ram_dpXbnonesadr100112048100112048p13b98964.edn
+4451
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CPLD2/impl1/pmi_ram_dpXbnonesadr101112048101112048p13b9937e.edn
+4470
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CPLD2/impl1/pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b.edn
+4527
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CPLD2/impl1/pmi_ram_dpXbnonesadr105101024105101024p13b96f61.edn
+2136
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CPLD2/impl1/pmi_ram_dpXbnonesadr3411204834112048p1395d432.edn
+1741
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CPLD2/impl1/pmi_ram_dpXbnonesadr3811204838112048p1395f327.edn
+1491
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CPLD2/impl1/pmi_ram_dpXbnonesadr4011204840112048p1395baf7.edn
+1505
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CPLD2/impl1/pmi_ram_dpXbnonesadr4211204842112048p1395c895.edn
+2075
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CPLD2/impl1/pmi_ram_dpXbnonesadr4411204844112048p1395dab9.edn
+2113
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CPLD2/impl1/pmi_ram_dpXbnonesadr4511204845112048p1395e474.edn
+2132
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CPLD2/impl1/pmi_ram_dpXbnonesadr4611204846112048p1395ed3e.edn
+1729
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CPLD2/impl1/pmi_ram_dpXbnonesadr6711204867112048p139603f9.edn
+3096
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CPLD2/impl1/pmi_ram_dpXbnonesadr6811204868112048p13960e6d.edn
+3115
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CPLD2/impl1/pmi_ram_dpXbnonesadr7011204870112048p1395d212.edn
+3153
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CPLD2/impl1/pmi_ram_dpXbnonesadr7311204873112048p1395eb70.edn
+3392
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CPLD2/impl1/pmi_ram_dpXbnonesadr7511204875112048p1395fbe3.edn
+3430
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CPLD2/impl1/pmi_ram_dpXbnonesadr7611204876112048p139603f9.edn
+3449
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CPLD2/impl1/pmi_ram_dpXbnonesadr7711204877112048p13960d59.edn
+3468
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CPLD2/impl1/pmi_ram_dpXbnonesadr8111204881112048p1395e235.edn
+3544
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CPLD2/impl1/pmi_ram_dpXbnonesadr8211204882112048p1395ebf0.edn
+3745
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CPLD2/impl1/pmi_ram_dpXbnonesadr8611204886112048p13960e6d.edn
+3821
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CPLD2/impl1/pmi_ram_dpXbnonesadr8711204887112048p139613de.edn
+3840
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CPLD2/impl1/pmi_ram_dpXbnonesadr8811204888112048p13961f15.edn
+3859
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CPLD2/impl1/pmi_ram_dpXbnonesadr9011204890112048p1395e512.edn
+3897
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CPLD2/impl1/pmi_ram_dpXbnonesadr9211204892112048p1395f582.edn
+4117
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