424 lines
17 KiB
Markdown
424 lines
17 KiB
Markdown
# CPLD Firmware Architecture Reference
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> **Project:** NewCalBoard DIG
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> **Toolchain:** Lattice Diamond (CPLD1/2/3), Xilinx Vivado 2023.2 (NewExtInst_Debug)
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> **Note:** This firmware is NOT fully complete — several features are stubbed out or incomplete.
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---
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## 1. System Overview
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The system uses a **Zynq SoC (ARM + FPGA)** architecture with **3 external Lattice CPLDs** communicating via SPI:
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```
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┌─────────────────────────────────────────────────────────────────┐
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│ Zynq SoC (ARM + FPGA) │
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│ ┌──────────┐ AXI ┌──────────────┐ SPI ┌─────────┐ │
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│ │ ARM │◄────────►│NewExtInst_TOP│◄────────►│ CPLDs │ │
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│ │ (Linux) │ GP0 │ (Vivado BD) │ SPI_Con │ (3x) │ │
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│ └──────────┘ └──────────────┘ └─────────┘ │
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│ ▲ │ │
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│ │ ▼ │
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│ │ ┌─────────────────┐ │
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│ │ │ clk_wiz (PLL) │ → 100MHz CPLD clk │
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│ │ │ proc_sys_reset │ │
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│ │ └─────────────────┘ │
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│ │ │ │
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│ │ ▼ │
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│ │ ┌─────────────────┐ │
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│ │ │ ps7_axi_periph │ (1→3 split) │
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│ │ └─────────────────┘ │
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└─────────────────────────────────────────────────────────────────┘
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```
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### Key Components
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| Component | Tool | Purpose |
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|-----------|------|---------|
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| `NewExtInst_TOP` | Vivado 2023.2 | Top-level block design (Zynq PS + AXI peripherals) |
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| `CPLD1/2/3` | Lattice Diamond | CPLD firmware (Verilog) |
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| `Release/*.jed` | — | Programming files for CPLDs |
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---
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## 2. CPLD Architecture (CPLD1/2/3)
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Each CPLD has the same **3-module internal structure**:
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```
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RelayConTop (Top)
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├── BUS_Con — SPI master interface (Mode 0)
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├── Reg_file — Register file + FSM
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└── CPLD_Con — Relay control logic
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```
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### 2.1 Module: BUS_Con (SPI Interface)
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**Purpose:** Implements a SPI Mode 0 (CPOL=0, CPHA=0) master interface.
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**SPI Protocol:**
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- CS active LOW
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- MOSI sampled on rising edge of SCLK
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- MISO shifted on falling edge of SCLK
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- 32-bit transaction: `[Bit31: WR] [Bit30:24: Addr(7bit)] [Bit23:0: Data(24bit)]`
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**FSM States:**
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```
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IDLE → CMD_SENT → DONE → IDLE
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↑ ↓
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WAIT_BUSY (waits for reg_busy to clear)
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```
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**Key Signals:**
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| Signal | Direction | Description |
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|--------|-----------|-------------|
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| `i_sclk` | input | SPI clock |
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| `i_mosi` | input | SPI data in |
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| `i_cs` | input | Chip select (active LOW) |
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| `o_miso` | output | SPI data out (tri-state) |
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| `o_cmd_valid` | output | Command valid pulse |
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| `o_addr[6:0]` | output | Register address |
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| `o_data[23:0]` | output | Write data |
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| `o_wr` | output | 1=write, 0=read |
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| `o_wready` | output | Ready to accept new command |
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| `o_err` | output | Bit count error flag |
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**Important Notes:**
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- `o_rvalid` is hardcoded to `1'b0` (not implemented)
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- Typo in original: `o_rvaild` vs `o_rvalid` in LPF
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- MISO is tri-stated when CS is HIGH: `assign o_miso = cs_active ? miso_shift[31] : 1'bz;`
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### 2.2 Module: Reg_file (Register File)
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**Purpose:** 16-register file (0-15) with read/write FSM.
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**Register Map:**
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| Addr | Name | R/W | Description |
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|------|------|-----|-------------|
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| 0 | IDENT | R/W | Identity: CPLD3=0, CPLD2=0, CPLD1=1, Major=1, Minor=0, Rev=0 |
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| 1 | STATE | R/W | State/Execution control. Bit 0 = EXEC trigger, Bit 23 = RDY, Bits 22:1 = Reserved |
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| 2 | Freq_Slot1 | R/W | Frequency slot 1 relay control |
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| 3 | Freq_Slot2 | R/W | Frequency slot 2 relay control |
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| 4 | Freq_Slot3 | R/W | Frequency slot 3 relay control |
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| 5 | Freq_Slot4 | R/W | Frequency slot 4 relay control |
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| 6 | DC_Slot1 | R/W | DC slot 1 control |
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| 7 | DC_Slot2 | W | DC slot 2 control (write-only per Excel) |
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| 8 | DC_Slot3 | W | DC slot 3 control (write-only per Excel) |
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| 9 | DC_Slot4 | W | DC slot 4 control (write-only per Excel) |
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| 10-15 | — | — | Reserved/Unused |
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**Register Bit Layout (24 bits):**
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**Freq_Slot N (Addr 2-5):**
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```
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Bit 23:10: Per Relay_Control (1=Switch, 0=Not Switch) — 14 bits, one per relay
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Bit 9:1: Channel_Number (1-256) — 9 bits
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Bit 0: Slot_EN (1=Enable)
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```
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**RC_Tx Mapping (Slot 4 only, part of Per Relay_Control bits 17:12):**
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| RC_Tx Bit | Output Pin |
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|-----------|-----------|
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| [5] | o_RC_T27 |
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| [4] | o_RC_T28 |
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| [3] | o_RC_T29 |
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| [2] | o_RC_T30 |
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| [1] | o_RC_T31 |
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| [0] | o_RC_T32 |
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**Source:** `i_freq_relay4[17:12]` → `RC_Tx[5:0]` (part of Per Relay_Control field)
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**Relay Control Bits per Slot (from Excel Freq_CPLD sheet):**
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| Slot | RC_F | RC_S | RC_T |
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|------|------|------|------|
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| 1 | RC_F1, RC_F2 | RC_S1-RC_S4 | RC_T1-RC_T8 |
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| 2 | RC_F3, RC_F4 | RC_S5-RC_S8 | RC_T9-RC_T16 |
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| 3 | RC_F5, RC_F6 | RC_S9-RC_S12 | RC_T17-RC_T24 |
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| 4 | RC_F7, RC_F8 | RC_S13-RC_S16 | RC_T25-RC_T32 |
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**DC_Slot N (Addr 6-9):**
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```
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Bit 23: PMU(0)/DPS(1) — PMU or DPS mode select
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Bit 22: V(0)/I(1) — Voltage or Current select
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Bit 21:17: Rload_Sel (0-31) — Resistor selection (5-bit, 0-31 range)
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Bit 16:10: Reserved (7 bits)
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Bit 9:1: Channel_Number (1-256) — 9 bits
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Bit 0: Slot_EN (1=Enable)
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```
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**FSM States:**
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```
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IDLE → BUSY → EXEC_ACK → EXEC_WAIT → IDLE
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↑
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(crash recovery: if exec_bit==1 at reset)
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```
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**Execution Protocol:**
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1. Write `STATE` register with bit 0 = 1
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2. Register FSM enters EXEC_ACK, waits for `con_done` to go LOW (controller busy)
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3. Enters EXEC_WAIT, waits for `con_done` to go HIGH (controller done)
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4. Auto-clears exec bit, sets ready bit
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5. **Cannot write if controller is already running** (exec_bit==1 → error)
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### 2.3 Module: CPLD_Con (Control Logic)
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**Purpose:** Decodes register values and generates relay control outputs.
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**Key Logic:**
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- **Sanity check:** Only ONE enable bit should be active (`en_t > 1` → error)
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- **Freq mode:** Routes channel numbers to OC_x01/OC_x17/DMM_EN based on channel range
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- **DC mode:** Selects resistor, PMU/DPS, V/I mode
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**Freq Slot Decoding (per slot, from CPLD_Con.v code):**
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| Channel Range | OC_x01 | OC_x17 | DMM_EN |
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|--------------|--------|--------|--------|
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| 1-8 | Set | 0 | DMM1 |
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| 9-72 | 0 | 0 | DMM2/DMM3/DMM4 |
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| 73-136 | 0 | Set | DMM3/DMM4 |
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| 137-200 | 0 | 0 | DMM4 |
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**Note:** Code uses `< 9`, `< 72`, `< 137`, `< 201` for ranges. Excel Freq_CPLD sheet shows actual channel groupings are more complex (e.g., "1-4&65-68||5-8&69-72").
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**ARM_CPLD Pin Assignments (from Excel ARM_CPLD sheet):**
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| Signal | CPLD1 Pin | CPLD2 Pin | CPLD3 Pin | Notes |
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|--------|-----------|-----------|-----------|-------|
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| SCLK | AA16 | AA10 | AA16 | **LPF discrepancy**: CPLD1 LPF says AA10 |
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| CS | AB11 | Y15 | AB11 | |
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| MOSI | AB12 | AB12 | AB12 | Shared across all CPLDs |
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| MISO | AA14 | AA14 | AA14 | Shared across all CPLDs |
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| RST_N | Y14 | Y14 | Y14 | |
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| ERR | AB16 | AB16 | AB16 | |
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| WVAILD | AA15 | AA15 | AA15 | |
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| RREADY | AB15 | AA10 | AB15 | CPLD2: AA10 same as SCLK? |
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| WREADY | Y15 | Y15 | Y15 | |
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| CLK | AA10 | AA16 | AA10 | CPLD1/3: AA10, CPLD2: AA16 |
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| RVAILD | AA16 | AB15 | AA16 | CPLD2: AB15 same as RREADY? |
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**⚠ Critical Note:** CPLD1 and CPLD3 share identical SPI pins (SCLK=AA16, CS=AB11, MOSI=AB12, MISO=AA14). This requires external multiplexing or the LPF is incorrect. The LPF file may need review.
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**DC Slot Decoding (per slot):**
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- Bit 22: V(0)/I(1) select → `RC_VSel` / `RC_ISel`
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- Bit 21:17: Resistor selection → `RC_RLSel` (18-bit one-hot)
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- Bit 23: PMU(0)/DPS(1) — **DPS path is STUBBED OUT** (empty branch)
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**Output Signals:**
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| Signal | Width | Description |
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|--------|-------|-------------|
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| `o_OC_x01` | 4:0 | OC relay selector (CPLD1: 4-bit, CPLD2: 4-bit) |
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| `o_OC_x17` | 4:0 | OC relay selector (CPLD1: 4-bit, CPLD2: 4-bit) |
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| `o_RC_F[7:0]` | 8 | RC_F relays (CPLD2 only) |
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| `o_RC_S[15:0]` | 16 | RC_S relays (CPLD2 only) |
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| `o_RC_T[5:0]` | 6 | RC_T relays (CPLD1: 6 bits T27-T32, CPLD2: 26 bits) |
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| `o_RC_T27-T32` | 6 | RC_T relays (CPLD1 only, expanded from 5 bits) |
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| `o_RC_RLSel[17:0]` | 18 | Resistor load select (CPLD1 only) |
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| `o_RC_VSel` | 1 | Voltage select (CPLD1 only) |
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| `o_RC_ISel` | 1 | Current select (CPLD1 only) |
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| `o_RC_LOF[1:0]` | 2 | DMM_N port relay LOF (CPLD1 only) |
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| `o_RC_LOS[1:0]` | 2 | DMM_N port relay LOS (CPLD1 only) |
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| `o_PMU_OC_[1-4][31:0]` | 32 | PMU output channel (CPLD1 only) |
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| `o_PMU_RC[3:0]` | 4 | PMU relay control (CPLD3 only) |
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| `o_DMM_EN[18:0]` | 19 | DMM enable signals (CPLD1 only) |
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| `o_IO_RC1` | 1 | IO relay control (CPLD1 only) |
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| `o_con_done` | 1 | Execution done flag |
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| `o_err` | 1 | Error flag |
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---
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## 3. CPLD Differences
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### CPLD1 (Most Complete)
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- **Role:** Main relay control + PMU output + DMM enable
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- **Outputs:** Full set including PMU_OC, DMM_EN, RC_RLSel, RC_V/I Sel, RC_LOF/LOS, IO_RC1
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- **RC_Tx:** Expanded from 5 bits to 6 bits (T27-T32), source `[17:12]`
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- **RC_LOF/LOS:** 2-bit outputs for DMM_N port relays — `o_RC_LOF = (RC_VSel==1)? 2'b01 : 2'b10`
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- **SPI Pins:** SCLK=AA16, CS=AB11, MOSI=AB12, MISO=AA14 (per ARM_CPLD sheet)
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- **Clock:** B9, Reset: Y14
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- **Note:** LPF file has SCLK=AA10 (discrepancy with ARM_CPLD sheet which says AA16)
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### CPLD2 (Partial)
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- **Role:** RC_F/RC_S/RC_T relay control + OC channels
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- **Outputs:** RC_F[7:0], RC_S[15:0], RC_T[25:0], OC_[1-4][31:0]
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- **Missing:** No DC control, no DMM_EN, no RC_RLSel
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- **SPI Pins:** SCLK=AA10, CS=Y15, MOSI=AB12, MISO=AA14 (per ARM_CPLD sheet)
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- **Note:** `i_wvaild` typo (should be `i_wvalid`)
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- **Note:** No `CPLD_Con` DC handling — only Freq relay logic
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### CPLD3 (Minimal)
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- **Role:** PMU relay control only
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- **Outputs:** PMU_RC[3:0] only
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- **SPI Pins:** SCLK=AA16, CS=AB11, MOSI=AB12, MISO=AA14 (per ARM_CPLD sheet)
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- **Note:** No DC control, no Freq relay logic
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- **Note:** `i_rvalid` typo (should be `i_rvalid` — consistent with CPLD1)
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---
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## 4. System Interconnect (Vivado Block Design)
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### NewExtInst_TOP Architecture
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```
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Zynq PS (M_AXI_GP0)
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│
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▼
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ps7_0_axi_periph (1→3 split)
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├── M00 → SPI_Con_0 → CPLD1
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├── M01 → SPI_Con_1 → CPLD2
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└── M02 → SPI_Con_2 → CPLD3
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```
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### Clock Tree
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```
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Zynq FCLK_CLK0 → clk_wiz_0 → clk_out1 (100MHz) → CPLD SPI_Con IP
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↓
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rst_clk_wiz_0_100M → peripheral reset
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```
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### SPI_Con IP (Custom AXI Peripheral)
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- 3 instances (one per CPLD)
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- AXI4-Lite slave interface
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- 7-bit address space (matches CPLD register count)
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- Maps AXI writes to CPLD SPI commands
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---
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## 5. Known Issues & Incomplete Features
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### Critical Incomplete Features
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1. **DPS Path Not Implemented** — `CPLD_Con.v` lines 266-268, 288-290, 310-312, 332-334: DPS selection branch is empty (all 4 DC slots). When `i_DC_Con[N][23] == 1'b1`, no output is driven.
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2. **CPLD_Con Slot 4 Bug** — `CPLD_Con.v` line 328: `i_DC_Con1[23]` should be `i_DC_Con4[23]` for slot 4 PMU/DPS selection
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3. **CPLD2 Missing DC Control** — No `i_DC_Con` inputs, no DC handling in `CPLD_Con`
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4. **CPLD3 Minimal** — Only PMU_RC output, no relay logic
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5. **o_rvalid Hardcoded** — `BUS_Con.v` line 211: `assign o_rvalid = 1'b0;` (but commented out in CPLD1 top module)
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6. **IDENT Constant Bug** — `Reg_file.v` line 38: uses `||` (logical OR) instead of `|` (bitwise OR): `24'h200000 || 12'b0001_0000_0000` evaluates to `1'b1`, not the intended bit pattern
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### Typos Found
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| File | Typo | Should Be |
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|------|------|-----------|
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| `BUS_Con.v:92` | `o_cmd_vaild` | `o_cmd_valid` |
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| `CPLD1/RelayConTop.v:105` | `cmd_vaild` | `cmd_valid` |
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| `CPLD2/RelayConTop.v:11` | `i_wvaild` | `i_wvalid` |
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| `CPLD2/RelayConTop.v:56` | `i_rvaild` | `i_rvalid` |
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| `CPLD3/RelayConTop.v:25` | `cmd_vaild` | `cmd_valid` |
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| `LPF files` | `o_rvaild` | `o_rvalid` |
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### Design Concerns
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1. **No timeout on execution FSM** — If controller hangs, FSM can hang forever (line 139 in Reg_file.v: "Optional: Timeout counter here")
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2. **No concurrent execution** — Only one slot can execute at a time (`en_t > 1` → error)
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3. **Channel range validation incomplete** — DC slot checks 1-18 for resistor but 1-256 for channel
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4. **CPLD1/3 share same SPI pins** — Need external multiplexing or different pin assignment (see ARM_CPLD sheet)
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5. **LPF vs ARM_CPLD sheet discrepancy** — CPLD1 SCLK: LPF=AA10, ARM_CPLD=AA16. LPF may be outdated.
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6. **CPLD_Con channel range mismatch** — Code uses `< 9, < 72, < 137, < 201` but Excel Freq_CPLD shows complex groupings like "1-4&65-68||5-8&69-72"
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---
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## 6. File Inventory
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### Source Files (Verilog)
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| File | Location | Lines | Purpose |
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|------|----------|-------|---------|
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| `RelayConTop.v` | CPLD1/ | 194 | Top module (CPLD1) |
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| `RelayConTop.v` | CPLD2/ | 118 | Top module (CPLD2) |
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| `RelayConTop.v` | CPLD3/ | 98 | Top module (CPLD3) |
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| `BUS_Con.v` | CPLD1/ | 213 | SPI interface (shared) |
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| `BUS_Con.v` | CPLD2/ | — | Same as CPLD1 |
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| `BUS_Con.v` | CPLD3/ | — | Same as CPLD1 |
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| `Reg_file.v` | CPLD1/ | 179 | Register file (shared) |
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| `Reg_file.v` | CPLD2/ | — | Same as CPLD1 |
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| `Reg_file.v` | CPLD3/ | — | Same as CPLD1 |
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| `CPLD_Con.v` | CPLD1/ | 376 | Control logic (CPLD1 only) |
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| `RelayConTop_tf.v` | CPLD1/ | 93 | Test fixture template |
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### Constraints (LPF)
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| File | Location | Lines | Purpose |
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|------|----------|-------|---------|
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| `NewExtIns_CPLD1.lpf` | CPLD1/ | 283 | Pin assignments (CPLD1) |
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| `NewExtIns_CPLD2.lpf` | CPLD2/ | 322 | Pin assignments (CPLD2) |
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| `NewExtIns_CPLD3.lpf` | CPLD3/ | 29 | Pin assignments (CPLD3) |
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### Programming Files
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| File | Size | Date |
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|------|------|------|
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| `Release/NewExtIns_CPLD1.jed` | 1.4 MB | Jan 19 |
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| `Release/NewExtIns_CPLD2.jed` | 1.4 MB | Jan 19 |
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| `Release/NewExtIns_CPLD3.jed` | 1.4 MB | Jan 19 |
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### Vivado Block Design
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| File | Location | Purpose |
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|------|----------|---------|
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| `NewExtInst_TOP.v` | NewExtInst_Debug/.../sim/ | Top-level netlist |
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| `SPI_Con_v1_0.v` | .../ipshared/8878/hdl/ | Custom SPI AXI IP |
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| `processing_system7_v5_5.v` | .../ipshared/8fd3/ | Zynq PS IP |
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---
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## 7. Register Protocol Summary
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### Write Sequence (ARM → CPLD)
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1. ARM writes to AXI address via `M_AXI_GP0`
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2. `SPI_Con` IP converts to SPI transaction
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3. `BUS_Con` receives 32-bit SPI frame
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4. `Reg_file` stores data in register table
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5. If bit 0 of STATE register set → triggers execution
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### Read Sequence (CPLD → ARM)
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1. ARM reads AXI address
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2. `SPI_Con` initiates SPI transaction
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3. `BUS_Con` shifts out 32-bit response: `[8'h00][24-bit rdata]`
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4. **Note:** `o_rvalid` is hardcoded to 0 — read acknowledgment not implemented
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### Execution Sequence
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1. ARM writes `STATE` register with bit 0 = 1
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2. `Reg_file` FSM → EXEC_ACK (waits for `con_done` LOW)
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3. `CPLD_Con` decodes register values, drives outputs
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4. `CPLD_Con` sets `con_done` HIGH when complete
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5. `Reg_file` FSM → EXEC_WAIT (waits for `con_done` HIGH)
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6. Auto-clears exec bit, returns to IDLE
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---
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## 8. Key Bit Fields Reference
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### IDENT Register (Addr 0)
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```
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23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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CPLD3 CPLD2 CPLD1 Reserved Major Version Minor Version Reversion
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```
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- CPLD3, CPLD2, CPLD1: Board identity flags (CPLD1=1 means the CPLD communicating to IDENTIFY itself as CPLD1)
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- Major Version: 1
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- Minor Version: 0
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- Reversion: 0
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### Freq_Slot Register (Addr 2-5)
|
|
```
|
|
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Per Relay_Control (1=Switch, 0=Not Switch) Channel_Number Slot_EN
|
|
```
|
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- Bits 23:10: Per Relay_Control (14 bits, one per relay per slot)
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- Bits 9:1: Channel_Number (9 bits)
|
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- Bit 0: Slot_EN (1=Enable)
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|
|
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### DC_Slot Register (Addr 6-9)
|
|
```
|
|
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
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DPS V/I Rload_Sel (0-31) Reserved Channel_Number Slot_EN
|
|
```
|
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- Bit 23: DPS (0=PMU, 1=DPS)
|
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- Bit 22: V/I (0=Voltage, 1=Current)
|
|
- Bits 21:17: Rload_Sel (0-31, 5-bit resistor selection)
|
|
- Bits 16:10: Reserved (7 bits)
|
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- Bits 9:1: Channel_Number (9 bits)
|
|
- Bit 0: Slot_EN (1=Enable)
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|
|
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### STATE Register (Addr 1)
|
|
```
|
|
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
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RDY Reserved EXEC
|
|
```
|
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- Bit 23: RDY (ready flag)
|
|
- Bits 22:1: Reserved (22 bits)
|
|
- Bit 0: EXEC (1=start execution)
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|
|
|
---
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|
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*Document generated from source code analysis. Last updated: May 2026*
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