Revert to default

2026-05-18 13:54:11 +08:00
parent 44b40ab9e1
commit c5df01f33d
50 changed files with 4436 additions and 89 deletions
@@ -0,0 +1,91 @@
+module CPLD_Con (
+    input i_sys_clk,
+    input i_rst_n,
+    input i_con_exec,
+    input [23:0]i_freq_relay1,
+    input [23:0]i_freq_relay2,
+    input [23:0]i_freq_relay3,
+    input [23:0]i_freq_relay4,
+    output o_con_done,
+    output [3:0]o_PMU_RC,
+    output o_err
+);
+
+    //Relay Reg
+    reg [3:0] PMU_RC;
+
+    //Flags
+    reg exec_flag;
+    reg err_flag;
+    reg [3:0]slot_exec_flag;
+    reg done_flag;
+
+    //Counter
+    reg [15:0]delay_cnt;
+
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            delay_cnt <= 'd0;
+        end
+        else begin
+            if (exec_flag == 1'b1) begin
+                delay_cnt <= delay_cnt + 1'd1;
+            end
+            else begin
+                delay_cnt <= 'd0;
+            end
+        end
+    end
+
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            exec_flag <= 1'b0;
+            err_flag <= 1'b0;
+            slot_exec_flag <= 'd0;
+            done_flag <= 'd1;
+            PMU_RC <= 4'b1111;
+        end
+        else begin
+            if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
+                exec_flag <= 1'b1;
+                done_flag <= 1'b0;
+                //To DO: More Sanity Check?
+                if ( (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) > 2'd1 ) begin
+                    err_flag <= 1'b1;
+                end
+                else begin
+                    slot_exec_flag[0] <= i_freq_relay1[0];
+                    slot_exec_flag[1] <= i_freq_relay2[0];
+                    slot_exec_flag[2] <= i_freq_relay3[0];
+                    slot_exec_flag[3] <= i_freq_relay4[0];
+                end
+            end
+            else if (exec_flag == 1'b1) begin
+                case (slot_exec_flag)
+                    4'b0001: begin
+                        PMU_RC <= 4'b1111;
+                    end
+                    4'b0010: begin
+                        PMU_RC <= 4'b1100;
+                    end
+                    4'b0100: begin
+                        PMU_RC <= 4'b1010;
+                    end
+                    4'b1000: begin
+                        PMU_RC <= 4'b0110;
+                    end
+                endcase
+                done_flag <= 1'b1;
+            end
+        end
+        if (done_flag == 1) begin
+            exec_flag <= 1'b0; 
+        end
+    end 
+
+    assign o_con_done = done_flag;
+    assign o_PMU_RC = PMU_RC;
+    assign o_err = err_flag;
+
+
+endmodule