CPLD3 implementation
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-1
@@ -21,7 +21,13 @@ module Reg_file (
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output [23:0] o_freq1,
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output [23:0] o_freq2,
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output [23:0] o_freq3,
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output [23:0] o_freq4
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output [23:0] o_freq4,
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//DC Regs
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output [23:0] o_DC1,
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output [23:0] o_DC2,
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output [23:0] o_DC3,
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output [23:0] o_DC4
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);
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// --- Parameters ---
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@@ -162,4 +168,9 @@ module Reg_file (
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assign o_freq3 = regtable[4];
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assign o_freq4 = regtable[5];
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assign o_DC1 = regtable[6];
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assign o_DC2 = regtable[7];
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assign o_DC3 = regtable[8];
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assign o_DC4 = regtable[9];
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endmodule
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