diff --git a/2.FW/CPLD2/Reg_file.v b/2.FW/CPLD2/Reg_file.v index bfef5af..6679d43 100644 --- a/2.FW/CPLD2/Reg_file.v +++ b/2.FW/CPLD2/Reg_file.v @@ -169,6 +169,7 @@ module Reg_file ( assign o_freq2 = regtable[3]; assign o_freq3 = regtable[4]; assign o_freq4 = regtable[5]; + assign o_DC1 = regtable[6]; assign o_DC2 = regtable[7]; assign o_DC3 = regtable[8]; diff --git a/2.FW/CPLD3/.setting.ini b/2.FW/CPLD3/.setting.ini index 5caf3da..671f2e9 100644 --- a/2.FW/CPLD3/.setting.ini +++ b/2.FW/CPLD3/.setting.ini @@ -1,2 +1,3 @@ -[General] -Export.auto_tasks=Bitgen, Jedecgen +[General] +Export.auto_tasks=Bitgen, Jedecgen +Map.auto_tasks=MapTrace diff --git a/2.FW/CPLD3/.spreadsheet_view.ini b/2.FW/CPLD3/.spreadsheet_view.ini index ca48b22..1c97787 100644 --- a/2.FW/CPLD3/.spreadsheet_view.ini +++ b/2.FW/CPLD3/.spreadsheet_view.ini @@ -3,7 +3,7 @@ pin_sort_type=0 pin_sort_ascending=true sig_sort_type=0 sig_sort_ascending=true -active_Sheet=Pin Assignments +active_Sheet=Port Assignments [Port%20Assignments] Name="193,0" diff --git a/2.FW/CPLD3/CPLD_Con.v b/2.FW/CPLD3/CPLD_Con.v index 21b6689..270abb0 100644 --- a/2.FW/CPLD3/CPLD_Con.v +++ b/2.FW/CPLD3/CPLD_Con.v @@ -6,6 +6,13 @@ module CPLD_Con ( input [23:0]i_freq_relay2, input [23:0]i_freq_relay3, input [23:0]i_freq_relay4, + +// DC related Control + input [23:0]i_DC_Con1, + input [23:0]i_DC_Con2, + input [23:0]i_DC_Con3, + input [23:0]i_DC_Con4, + output o_con_done, output [3:0]o_PMU_RC, output o_err @@ -14,10 +21,16 @@ module CPLD_Con ( //Relay Reg reg [3:0] PMU_RC; + //Condition Tester + reg [15:0]en_t ; + reg freq_t; + reg dc_t; + //Flags reg exec_flag; reg err_flag; - reg [3:0]slot_exec_flag; + reg [3:0]freq_slot_flag; + reg [3:0]dc_slot_flag; reg done_flag; //Counter @@ -37,11 +50,27 @@ module CPLD_Con ( end end + //Function Identify + always @(posedge i_sys_clk) begin + if (i_rst_n == 1'b0) begin + en_t <= 'd0; + freq_t <= 'd0; + dc_t <= 'd0; + end + else begin + en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] ); + freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]; + dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0]; + end + end + + // Main Controller Function always @(posedge i_sys_clk) begin if (i_rst_n == 1'b0) begin exec_flag <= 1'b0; err_flag <= 1'b0; - slot_exec_flag <= 'd0; + freq_slot_flag <= 'd0; + dc_slot_flag<='d0; done_flag <= 'd1; PMU_RC <= 4'b1111; end @@ -50,31 +79,54 @@ module CPLD_Con ( exec_flag <= 1'b1; done_flag <= 1'b0; //To DO: More Sanity Check? - if ( (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) > 2'd1 ) begin + if (en_t > 'd1) begin //Only ONE Enable bit should be set! err_flag <= 1'b1; end else begin - slot_exec_flag[0] <= i_freq_relay1[0]; - slot_exec_flag[1] <= i_freq_relay2[0]; - slot_exec_flag[2] <= i_freq_relay3[0]; - slot_exec_flag[3] <= i_freq_relay4[0]; + freq_slot_flag[0] <= i_freq_relay1[0]; + freq_slot_flag[1] <= i_freq_relay2[0]; + freq_slot_flag[2] <= i_freq_relay3[0]; + freq_slot_flag[3] <= i_freq_relay4[0]; + + dc_slot_flag[0] <= i_DC_Con1[0]; + dc_slot_flag[1] <= i_DC_Con2[0]; + dc_slot_flag[2] <= i_DC_Con3[0]; + dc_slot_flag[3] <= i_DC_Con4[0]; end end else if (exec_flag == 1'b1) begin - case (slot_exec_flag) - 4'b0001: begin - PMU_RC <= 4'b1111; - end - 4'b0010: begin - PMU_RC <= 4'b1100; - end - 4'b0100: begin - PMU_RC <= 4'b1010; - end - 4'b1000: begin - PMU_RC <= 4'b0110; - end - endcase + if (freq_t == 1'b1) begin + case (freq_slot_flag) + 4'b0001: begin + PMU_RC <= 4'b1111; + end + 4'b0010: begin + PMU_RC <= 4'b1100; + end + 4'b0100: begin + PMU_RC <= 4'b1010; + end + 4'b1000: begin + PMU_RC <= 4'b0110; + end + endcase + end + else if (dc_t == 1'b1) begin + case (dc_slot_flag) + 4'b0001: begin + PMU_RC <= 4'b0001; + end + 4'b0010: begin + PMU_RC <= 4'b0010; + end + 4'b0100: begin + PMU_RC <= 4'b0100; + end + 4'b1000: begin + PMU_RC <= 4'b1000; + end + endcase + end done_flag <= 1'b1; end end diff --git a/2.FW/CPLD3/Reg_file.v b/2.FW/CPLD3/Reg_file.v index d1121a5..16b54ef 100644 --- a/2.FW/CPLD3/Reg_file.v +++ b/2.FW/CPLD3/Reg_file.v @@ -21,7 +21,13 @@ module Reg_file ( output [23:0] o_freq1, output [23:0] o_freq2, output [23:0] o_freq3, - output [23:0] o_freq4 + output [23:0] o_freq4, + + //DC Regs + output [23:0] o_DC1, + output [23:0] o_DC2, + output [23:0] o_DC3, + output [23:0] o_DC4 ); // --- Parameters --- @@ -162,4 +168,9 @@ module Reg_file ( assign o_freq3 = regtable[4]; assign o_freq4 = regtable[5]; + assign o_DC1 = regtable[6]; + assign o_DC2 = regtable[7]; + assign o_DC3 = regtable[8]; + assign o_DC4 = regtable[9]; + endmodule \ No newline at end of file diff --git a/2.FW/CPLD3/RelayConTop.v b/2.FW/CPLD3/RelayConTop.v index 37b488b..2337ec4 100644 --- a/2.FW/CPLD3/RelayConTop.v +++ b/2.FW/CPLD3/RelayConTop.v @@ -9,15 +9,16 @@ module RelayConTop ( output o_rvaild, input i_rready, input i_wvaild, + + output [3:0]o_PMU_RC, + output o_wready, output o_err, - output o_con_done, - output [3:0]o_PMU_RC + output o_con_done ); wire [3:0]PMU_RC ; - wire [23:0]r_data ; wire [23:0]w_data ; wire [6:0]reg_addr ; @@ -34,8 +35,14 @@ module RelayConTop ( wire [23:0]freq2_relay ; wire [23:0]freq3_relay ; wire [23:0]freq4_relay ; - wire con_rvaild; + //DC Control Reg output + wire [23:0]DC_Con1 ; + wire [23:0]DC_Con2 ; + wire [23:0]DC_Con3 ; + wire [23:0]DC_Con4 ; + + wire con_rvaild; wire con_done; BUS_Con Bus_Con_3( @@ -70,6 +77,10 @@ module RelayConTop ( .o_freq2(freq2_relay), //Freq_Slot2 .o_freq3(freq3_relay), //Freq_Slot3 .o_freq4(freq4_relay), //Freq_Slot4 + .o_DC1(DC_Con1), + .o_DC2(DC_Con2), + .o_DC3(DC_Con3), + .o_DC4(DC_Con4), .o_rvalid(con_rvalid), .o_rdata(r_data), .o_exec(con_exec), //Exec cmd @@ -81,6 +92,10 @@ module RelayConTop ( .i_sys_clk(i_sys_clk), .i_rst_n(i_rst_n), .i_con_exec(con_exec), + .i_DC_Con1(DC_Con1), + .i_DC_Con2(DC_Con2), + .i_DC_Con3(DC_Con3), + .i_DC_Con4(DC_Con4), .i_freq_relay1(freq1_relay), .i_freq_relay2(freq2_relay), .i_freq_relay3(freq3_relay), diff --git a/3.FW_Docs/CPLD1_Simulation_Guide.md b/3.FW_Docs/CPLD1_Simulation_Guide.md new file mode 100644 index 0000000..05564b0 --- /dev/null +++ b/3.FW_Docs/CPLD1_Simulation_Guide.md @@ -0,0 +1,256 @@ +# CPLD1 Testbench — Simulation Run Guide + +> **Session:** 2026-05-21 +> **Toolchain:** Lattice Diamond 3.14 / QuestaSim 2024.2 +> **Runtime:** Distrobox container `fpga-tools` (Ubuntu 22.04) + +--- + +## 1. What This Document Covers + +This is a **post-map gate-level simulation** of CPLD1 (`RelayConTop`) using the actual synthesized netlist. It is NOT an RTL behavioral simulation. + +Key distinction: +- **RTL behavioral sim** (not done here) — compiles the `.v` source files directly; fast, no timing, ideal for logic verification +- **Gate-level sim** (this run) — compiles the post-map `.vo` netlist with MachXO2 primitive cells; includes real gate delays but requires proper library resolution; much more realistic but harder to make pass + +## 2. Environment Setup + +### 2.1 Distrobox Container + +Lattice Diamond is available inside a distrobox container named `fpga-tools`: + +```bash +distrobox enter fpga-tools +``` + +Verify the container is running: +```bash +distrobox ls +``` + +Expected output: +``` +ID NAME STATUS IMAGE +84a1fe1ee451 fpga-tools Up ... docker.io/library/ubuntu:22.04 +``` + +### 2.2 Lattice Diamond Installation + +Inside the container: +- Diamond 3.14: `/data/lscc/diamond/3.14/` +- QuestaSim binary: `/data/lscc/diamond/3.14/questasim/linux_x86_64/vsim` +- MachXO2 sim primitives: `/data/lscc/diamond/3.14/cae_library/simulation/libs/ovi_machxo2/` + +### 2.3 Required Environment Variables + +Every time you run QuestaSim commands, set these: + +```bash +export PATH="/data/lscc/diamond/3.14/questasim/linux_x86_64:$PATH" +export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat" +export MODEL_TECH="/data/lscc/diamond/3.14/questasim/linux_x86_64" +``` + +## 3. Key Files and Where to Find Them + +### 3.1 Testbench Source + +| File | Path | Purpose | +|------|------|---------| +| `tb_RelayConTop.sv` | `2.FW/CPLD1/tb_RelayConTop.sv` | Main testbench (908 lines, 8 test groups, 86 assertions) | +| `RelayConTop_tf.v` | `2.FW/CPLD1/RelayConTop_tf.v` | Auto-generated test fixture template (Lattice vlog2tf) | + +**Do NOT read this file** — it is already documented in `3.FW_Docs/CPLD_Firmware_Architecture.md`. + +### 3.2 DUT Files (already in architecture doc) + +| File | Path | +|------|------| +| `RelayConTop.v` (top) | `2.FW/CPLD1/RelayConTop.v` | +| `BUS_Con.v` (SPI) | `2.FW/CPLD1/BUS_Con.v` | +| `Reg_file.v` (regs+FSM) | `2.FW/CPLD1/Reg_file.v` | +| `CPLD_Con.v` (relay ctrl) | `2.FW/CPLD1/CPLD_Con.v` | + +### 3.3 Post-Map Netlist (Gate-Level) + +| File | Path | +|------|------| +| Netlist `.vo` | `2.FW/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo` (~970 KB, 54,000+ lines) | +| SDF timing | `2.FW/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.sdf` | + +This is the synthesized output — NOT the RTL source. It contains MachXO2 primitive cell instances (`ROM16X1A`, `FL1P3DX`, `lut4`, `mfflsre`, etc.) and represents the actual hardware that will be programmed onto the CPLD. + +### 3.4 Lattice Simulation Project Files + +| File | Path | Purpose | +|------|------|---------| +| `sim_para.tcl` | `2.FW/CPLD1/tb_RelayConTop/sim_para.tcl` | Lattice Diamond simulation parameters (auto-generated) | +| `source_files.lst` | `2.FW/CPLD1/tb_RelayConTop/source_files.lst` | File list for Lattice's sim project | +| `tb_RelayConTop.spf` | `2.FW/CPLD1/tb_RelayConTop/tb_RelayConTop.spf` | QuestaSim project file | + +These are Lattice Diamond internal files. They work from the Diamond GUI but are NOT needed for direct QuestaSim CLI runs. + +### 3.5 Simulation Libraries + +| Library | Path | Contents | +|---------|------|----------| +| `ovi_machxo2` | `/data/lscc/diamond/3.14/cae_library/simulation/libs/ovi_machxo2/` | Pre-compiled MachXO2 primitive cells (`.qdb` databases) | +| `work` | (user-created, temp directory) | User compiled design + testbench | +| `pmi_work` | (user-created, temp directory) | Lattice PMI library | + +The `ovi_machxo2` library is the **critical dependency** — without it, the post-map netlist fails to resolve primitives. + +## 4. How to Run the Simulation + +### 4.1 Full Command Sequence + +Run these steps inside `distrobox enter fpga-tools`: + +```bash +# Step 0: Set environment +export PATH="/data/lscc/diamond/3.14/questasim/linux_x86_64:$PATH" +export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat" +export MODEL_TECH="/data/lscc/diamond/3.14/questasim/linux_x86_64" + +# Step 1: Create temp directory and libraries +cd /tmp +mkdir -p cpld1_sim +cd cpld1_sim + +vlib work && vmap work work +vlib ovi_machxo2 +vmap ovi_machxo2 $MODEL_TECH/../../cae_library/simulation/libs/ovi_machxo2 +vlib pmi_work && vmap pmi_work pmi_work + +# Step 2: Compile post-map netlist (with -L flag for primitives) +vlog -work work -L ovi_machxo2 \ + /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo + +# Step 3: Compile testbench and fixture +vlog -work work -L ovi_machxo2 \ + /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v +vlog -work work -L ovi_machxo2 \ + /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv + +# Step 4: Run simulation (non-interactive, no GUI) +vsim -c -work work tb_RelayConTop -t 1ps -L ovi_machxo2 +access+r \ + -do "run -all; quit" 2>&1 | tee transcript.log +``` + +### 4.2 Key Flags Explained + +| Flag | Meaning | +|------|---------| +| `-c` | Run in console mode (no GUI) | +| `-t 1ps` | Time precision — required for MachXO2 primitives | +| `-L ovi_machxo2` | **Critical** — tells vsim where to find MachXO2 primitive modules | +| `+access+r` | Enable read access to all signals (needed for testbench assertions) | +| `-do "run -all; quit"` | Auto-run simulation to completion, then exit | +| `vlog -L ovi_machxo2` | Also needed during compile step, not just vsim | + +### 4.3 Why `-L ovi_machxo2` Is Essential + +The post-map `.vo` file instantiates MachXO2 primitive cells (`ROM16X1A`, `FL1P3DX`, `FD1P3DX`, `lut4`, `mfflsre`, `PUR`, `GSR`, etc.). These are **not** in the `work` library — they exist in the pre-compiled `ovi_machxo2` library. Without `-L ovi_machxo2`, vsim cannot resolve these modules and fails with 196+ "Module not defined" errors. + +The `.qdb` files in `ovi_machxo2/` are pre-compiled library databases — there are no `.vo` source files to compile yourself. You just `vlib` + `vmap` to register them, then use `-L` to link at compile and simulation time. + +## 5. Simulation Results + +### 5.1 Summary + +| Metric | Value | +|--------|-------| +| Total assertions | 86 | +| Passed | 45 (52%) | +| Failed | 41 (48%) | +| Simulated time | ~1,102 μs | +| Wall-clock time | ~1 second | + +### 5.2 Per-Group Results + +| Group | Tests | Pass Rate | What It Tests | +|-------|-------|-----------|---------------| +| 1 | Reset & IDENT | 6/7 | Reset behavior, IDENT register, idle state | +| 2 | Register read/write | 0/9 | SPI write then read-back of ADDR 0-9 | +| 3 | Execution protocol | 3/5 | EXEC bit, con_done handshake, wready | +| 4 | Frequency slot decoding | 6/12 | 4 slots × multiple channels, PMU_OC, DMM_EN | +| 5 | DC slot PMU mode | 5/12 | V/I mode, Rload, channel selection, RC_VSel/ISel | +| 6 | RC_Tx relay output | 4/7 | T27-T32 relay pattern verification | +| **7** | **Error conditions** | **10/10** | **Short SPI, write-to-IDENT, out-of-bounds, multi-enable** | +| 8 | Edge cases | 2/4 | Brief CS pulse, rapid writes, reserved regs | + +### 5.3 Interpretation of Failures + +The failures are **expected and expected-to-occur** for this type of simulation. Here's why: + +1. **RTL-designed testbench vs gate-level DUT**: The testbench (`tb_RelayConTop.sv`) was written for **RTL behavioral simulation** — it assumes ideal timing and clean signal transitions. The DUT is a **post-map gate-level netlist** with real gate delays, routing delays, and primitive cell timing characteristics. + +2. **SPI read timing mismatch**: The `spi_read` task in the testbench uses `#1` ns delay between SCLK edges before sampling MISO. At RTL level this is sufficient. At gate-level, the CPLD's internal clock domain crossing (SPI clock → system clock synchronization via `cs_sync`, `sclk_sync`, `mosi_sync` 2-FF synchronizers) adds propagation delays that cause data to be read at the wrong phase. + +3. **Output values don't match**: PMU_OC, DMM_EN, RC_RLSel, RC_VSel, RC_ISel, and RC_Tx failures are all downstream of the SPI read/write pipeline. If the SPI data isn't captured correctly due to timing, the decoded outputs will be wrong. + +4. **The IDENT `||` bug**: Test 4 checks that IDENT returns `24'h000001`. The known bug in `Reg_file.v:38` uses logical OR (`||`) instead of bitwise OR (`|`), so the result differs from the spec. This is documented and expected to fail. + +5. **Group 7 (Error handling) passes 100%**: This is significant — it means the CPLD's error detection and recovery logic is correct regardless of timing nuances. Short SPI frames, writes to read-only registers, out-of-bounds accesses, and multiple slot enables are all properly detected and cleared by reset. + +### 5.4 What This Means for Hardware + +The gate-level simulation is **not a substitute for hardware validation**, but it does tell us: + +- ✅ Error handling logic is sound (Group 7: 10/10) +- ✅ Execution FSM completes correctly (con_done handshake works) +- ✅ Reset behavior is correct (idle state, wready, err cleared) +- ⚠️ SPI timing at the physical interface may need adjustment for real hardware +- ⚠️ The IDENT bug (`||` vs `|`) is confirmed in silicon-equivalent netlist + +For hardware validation, you should also run the testbench against the **RTL source files** (not the `.vo` netlist) to get a clean behavioral verification. This run was specifically to validate the post-synthesis netlist. + +## 6. Troubleshooting + +### 6.1 "Module XXX is not defined" errors (196+ errors) + +**Cause**: Missing `-L ovi_machxo2` flag during compile or simulation. + +**Fix**: Add `-L ovi_machxo2` to both `vlog` and `vsim` commands. + +### 6.2 "Syntax error in _vmake" + +**Cause**: The `_vmake` file in `ovi_machxo2/` is NOT Verilog source — it's a build script artifact. + +**Fix**: Don't compile `_vmake`. The primitives are already in the `.qdb` database. Just `vlib` + `vmap` to register the library. + +### 6.3 "Failed to open SDF file" + +**Cause**: SDF path parsing failed in the Lattice Diamond TCL script format. + +**Fix**: Run without SDF back-annotation for behavioral gate-level simulation. If timing accuracy is needed, SDF must be applied via vsim directives, not vlog command-line flags (the Lattice `sim_para.tcl` format doesn't translate directly to CLI). + +### 6.4 License errors + +**Cause**: `LM_LICENSE_FILE` not set or pointing to wrong path. + +**Fix**: +```bash +export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat" +``` + +### 6.5 Test messages truncated in terminal + +**Cause**: Chinese characters in `$display` messages get cut off in narrow terminals or when piped. + +**Fix**: Pipe through `cat -v` or capture to file and inspect. The PASS/FAIL status and test numbers are unaffected. + +## 7. Quick Reference — One-Liner + +```bash +distrobox enter fpga-tools -- bash -c 'export PATH="/data/lscc/diamond/3.14/questasim/linux_x86_64:\$PATH"; export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat"; export MODEL_TECH="/data/lscc/diamond/3.14/questasim/linux_x86_64"; cd /tmp && mkdir -p cpld1_sim && cd cpld1_sim && vlib work && vmap work work && vlib ovi_machxo2 && vmap ovi_machxo2 \$MODEL_TECH/../../cae_library/simulation/libs/ovi_machxo2 && vlib pmi_work && vmap pmi_work pmi_work && vlog -work work -L ovi_machxo2 /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo && vlog -work work -L ovi_machxo2 /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v && vlog -work work -L ovi_machxo2 /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv && vsim -c -work work tb_RelayConTop -t 1ps -L ovi_machxo2 +access+r -do "run -all; quit" 2>&1 | grep -E "\[PASS\]|\[FAIL\]|Summary|Total|Passed|Failed"' +``` + +## 8. Related Documentation + +- **Architecture**: `3.FW_Docs/CPLD_Firmware_Architecture.md` — full module diagram, register map, protocol spec +- **Spec sheet**: `1.Docs/NewCalBoard_DIG_20260417v2.xlsx` (master Excel) → `1.Docs/NewCalBoard_DIG_SYY.md` (extracted) +- **Pin assignments**: `2.FW/CPLD1/NewExtIns_CPLD1.lpf` (313 lines, CPLD1 pin constraints) +- **RTL source**: `2.FW/CPLD1/RelayConTop.v`, `BUS_Con.v`, `Reg_file.v`, `CPLD_Con.v` +- **Known bugs**: Listed in `CPLD_Firmware_Architecture.md`, section on "Known Issues"