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CPLD3 implementation

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This commit is contained in:
Jeremy Shen
2026-05-22 16:59:29 +08:00
parent 7f43729caf
commit 99ef0f0e6e
7 changed files with 365 additions and 29 deletions
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2.FW/CPLD3/.setting.ini
+3 -2
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@@ -1,2 +1,3 @@
[General]
Export.auto_tasks=Bitgen, Jedecgen
[General]
Export.auto_tasks=Bitgen, Jedecgen
Map.auto_tasks=MapTrace
2.FW/CPLD3/.spreadsheet_view.ini
+1 -1
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@@ -3,7 +3,7 @@ pin_sort_type=0
pin_sort_ascending=true
sig_sort_type=0
sig_sort_ascending=true
active_Sheet=Pin Assignments
active_Sheet=Port Assignments
[Port%20Assignments]
Name="193,0"
2.FW/CPLD3/CPLD_Con.v
+73 -21
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@@ -6,6 +6,13 @@ module CPLD_Con (
input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
output o_con_done,
output [3:0]o_PMU_RC,
output o_err
@@ -14,10 +21,16 @@ module CPLD_Con (
//Relay Reg
reg [3:0] PMU_RC;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Flags
reg exec_flag;
reg err_flag;
reg [3:0]slot_exec_flag;
reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag;
reg done_flag;
//Counter
@@ -37,11 +50,27 @@ module CPLD_Con (
end
end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
exec_flag <= 1'b0;
err_flag <= 1'b0;
slot_exec_flag <= 'd0;
freq_slot_flag <= 'd0;
dc_slot_flag<='d0;
done_flag <= 'd1;
PMU_RC <= 4'b1111;
end
@@ -50,31 +79,54 @@ module CPLD_Con (
exec_flag <= 1'b1;
done_flag <= 1'b0;
//To DO: More Sanity Check?
if ( (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) > 2'd1 ) begin
if (en_t > 'd1) begin //Only ONE Enable bit should be set!
err_flag <= 1'b1;
end
else begin
slot_exec_flag[0] <= i_freq_relay1[0];
slot_exec_flag[1] <= i_freq_relay2[0];
slot_exec_flag[2] <= i_freq_relay3[0];
slot_exec_flag[3] <= i_freq_relay4[0];
freq_slot_flag[0] <= i_freq_relay1[0];
freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end
end
else if (exec_flag == 1'b1) begin
case (slot_exec_flag)
4'b0001: begin
PMU_RC <= 4'b1111;
end
4'b0010: begin
PMU_RC <= 4'b1100;
end
4'b0100: begin
PMU_RC <= 4'b1010;
end
4'b1000: begin
PMU_RC <= 4'b0110;
end
endcase
if (freq_t == 1'b1) begin
case (freq_slot_flag)
4'b0001: begin
PMU_RC <= 4'b1111;
end
4'b0010: begin
PMU_RC <= 4'b1100;
end
4'b0100: begin
PMU_RC <= 4'b1010;
end
4'b1000: begin
PMU_RC <= 4'b0110;
end
endcase
end
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
PMU_RC <= 4'b0001;
end
4'b0010: begin
PMU_RC <= 4'b0010;
end
4'b0100: begin
PMU_RC <= 4'b0100;
end
4'b1000: begin
PMU_RC <= 4'b1000;
end
endcase
end
done_flag <= 1'b1;
end
end
2.FW/CPLD3/Reg_file.v
+12 -1
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@@ -21,7 +21,13 @@ module Reg_file (
output [23:0] o_freq1,
output [23:0] o_freq2,
output [23:0] o_freq3,
output [23:0] o_freq4
output [23:0] o_freq4,
//DC Regs
output [23:0] o_DC1,
output [23:0] o_DC2,
output [23:0] o_DC3,
output [23:0] o_DC4
);
// --- Parameters ---
@@ -162,4 +168,9 @@ module Reg_file (
assign o_freq3 = regtable[4];
assign o_freq4 = regtable[5];
assign o_DC1 = regtable[6];
assign o_DC2 = regtable[7];
assign o_DC3 = regtable[8];
assign o_DC4 = regtable[9];
endmodule
2.FW/CPLD3/RelayConTop.v
+19 -4
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@@ -9,15 +9,16 @@ module RelayConTop (
output o_rvaild,
input i_rready,
input i_wvaild,
output [3:0]o_PMU_RC,
output o_wready,
output o_err,
output o_con_done,
output [3:0]o_PMU_RC
output o_con_done
);
wire [3:0]PMU_RC ;
wire [23:0]r_data ;
wire [23:0]w_data ;
wire [6:0]reg_addr ;
@@ -34,8 +35,14 @@ module RelayConTop (
wire [23:0]freq2_relay ;
wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ;
wire con_rvaild;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
wire con_rvaild;
wire con_done;
BUS_Con Bus_Con_3(
@@ -70,6 +77,10 @@ module RelayConTop (
.o_freq2(freq2_relay), //Freq_Slot2
.o_freq3(freq3_relay), //Freq_Slot3
.o_freq4(freq4_relay), //Freq_Slot4
.o_DC1(DC_Con1),
.o_DC2(DC_Con2),
.o_DC3(DC_Con3),
.o_DC4(DC_Con4),
.o_rvalid(con_rvalid),
.o_rdata(r_data),
.o_exec(con_exec), //Exec cmd
@@ -81,6 +92,10 @@ module RelayConTop (
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_con_exec(con_exec),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.i_freq_relay1(freq1_relay),
.i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay),