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Bug fix & CPLD2 PMU implementation

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This commit is contained in:
Jeremy Shen
2026-05-21 17:15:14 +08:00
parent 13611d20a0
commit 7f43729caf
9 changed files with 1373 additions and 585 deletions
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2.FW/CPLD1/CPLD_Con.v
+1 -1
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@@ -20,7 +20,7 @@ module CPLD_Con (
output [3:0]o_OC_x17, output [3:0]o_OC_x17,
output [18:0]o_DMM_EN, output [18:0]o_DMM_EN,
output o_IO_RC1, output o_IO_RC1,
output [4:0]o_RC_Tx, output [5:0]o_RC_Tx,
output [31:0]o_PMU_OC_1 , output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 , output [31:0]o_PMU_OC_2 ,
2.FW/CPLD1/tb_RelayConTop.sv
+847 -249
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File diff suppressed because it is too large Load Diff
2.FW/CPLD1/tb_RelayConTop/source_files.lst
+2 -5
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@@ -1,5 +1,2 @@
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/CPLD_Freq_Con.v=work," "/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv=work,System Verilog"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/Reg_file.v=work," "/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v=work,Verilog 2001"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/BUS_Con.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/RelayConTop.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/tb_RelayConTop.sv=work,"
2.FW/CPLD2/.spreadsheet_view.ini
+3 -3
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@@ -3,10 +3,10 @@ pin_sort_type=0
pin_sort_ascending=true pin_sort_ascending=true
sig_sort_type=0 sig_sort_type=0
sig_sort_ascending=true sig_sort_ascending=true
active_Sheet=Global Preferences active_Sheet=Port Assignments
[Port%20Assignments] [Port%20Assignments]
Name="176,0" Name="216,0"
Group%20By="118,1" Group%20By="118,1"
Pin="71,2" Pin="71,2"
BANK="91,3" BANK="91,3"
@@ -65,7 +65,7 @@ Prioritize="100,ELLIPSIS"
[Timing%20Preferences] [Timing%20Preferences]
Preference%20Name="146,ELLIPSIS" Preference%20Name="146,ELLIPSIS"
Preference%20Value="143,ELLIPSIS" Preference%20Value="143,ELLIPSIS"
Preference%20Unit="1122,ELLIPSIS" Preference%20Unit="133,ELLIPSIS"
[Group] [Group]
Group%20Type\Name="153,ELLIPSIS" Group%20Type\Name="153,ELLIPSIS"
2.FW/CPLD2/CPLD_Con.v
+228 -95
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@@ -2,32 +2,61 @@ module CPLD_Con (
input i_sys_clk, input i_sys_clk,
input i_rst_n, input i_rst_n,
input i_con_exec, input i_con_exec,
// Freq Relay Control
input [23:0]i_freq_relay1, input [23:0]i_freq_relay1,
input [23:0]i_freq_relay2, input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3, input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4, input [23:0]i_freq_relay4,
output o_con_done,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
//Output RELAYs
output [7:0]o_RC_F, //Ref: Schematic output [7:0]o_RC_F, //Ref: Schematic
output [15:0]o_RC_S, output [15:0]o_RC_S,
output [31:0]o_RC_T, output [31:0]o_RC_T,
output [3:0] o_OC_x09, output [3:0] o_OC_x09,
output [3:0] o_OC_x25 output [3:0] o_OC_x25,
output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4,
//Output FLAGs
output o_err,
output o_con_done
); );
//Output Relay Reg //Output Relay Reg
reg [3:0] OC_x09; reg [3:0] OC_x09;
reg [3:0] OC_x25; reg [3:0] OC_x25;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Relay Reg //Relay Reg
reg [7:0]relay_l1; reg [7:0]relay_l1;
reg [15:0]relay_l2 ; reg [15:0]relay_l2 ;
reg [31:0]relay_l3 ; reg [31:0]relay_l3 ;
reg [31:0]PMU_OC_1 ;
reg [31:0]PMU_OC_2 ;
reg [31:0]PMU_OC_3 ;
reg [31:0]PMU_OC_4 ;
//Flags //Flags
reg exec_done_flag; reg exec_done_flag;
reg exec_flag; reg exec_flag;
reg [3:0]slot_exec_flag; reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag ;
reg err_flag; reg err_flag;
//Counter //Counter
@@ -52,6 +81,21 @@ module CPLD_Con (
end end
end end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin if (i_rst_n == 1'b0) begin
relay_l1 <= 'd0; relay_l1 <= 'd0;
@@ -59,125 +103,207 @@ module CPLD_Con (
relay_l3 <= 'd0; relay_l3 <= 'd0;
exec_flag <= 1'b0; exec_flag <= 1'b0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
slot_exec_flag <= 'd0; freq_slot_flag <= 'd0;
dc_slot_flag<='d0;
err_flag <= 'd0; err_flag <= 'd0;
end end
else begin else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
exec_done_flag <= 'd0;
exec_flag <= 1'b1;
//To DO: More Sanity Check? //To DO: More Sanity Check?
// Add the bits together. Verilog handles the width expansion automatically for the comparison. if (en_t > 'd1) begin //Only ONE Enable bit should be set!
if ( (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) > 2'd1 ) begin
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
slot_exec_flag[0] <= i_freq_relay1[0]; exec_done_flag <= 'd0;
slot_exec_flag[1] <= i_freq_relay2[0]; exec_flag <= 1'b1;
slot_exec_flag[2] <= i_freq_relay3[0];
slot_exec_flag[3] <= i_freq_relay4[0]; freq_slot_flag[0] <= i_freq_relay1[0];
freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end end
end end
else if (exec_flag == 1'b1) begin else if (exec_flag == 1'b1) begin
//Output Relay //Output Relay
case (slot_exec_flag) if (freq_t == 1'b1) begin
4'b0001: begin case (freq_slot_flag)
relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]}; 4'b0001: begin
if (delay_cnt == 'd500) begin relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]};
relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]}; if (delay_cnt == 'd500) begin
relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin
OC_x09 <= 4'b0001;
end
else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin
OC_x25 <= 4'b0001;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end end
else if (delay_cnt == 'd1000) begin 4'b0010: begin
relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]}; relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0};
if (delay_cnt == 'd500) begin
relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin
OC_x09 <= 4'b0010;
end
else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin
OC_x25 <= 4'b0010;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end end
else if (delay_cnt == 'd1080) begin 4'b0100: begin
relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0};
if (delay_cnt == 'd500) begin
relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay3 > 64) &(freq_relay3 <73)) begin
OC_x09 <= 4'b0100;
end
else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin
OC_x25 <= 4'b0100;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end
4'b1000: begin
relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0};
if (delay_cnt == 'd500) begin
relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0;
exec_done_flag <= 1'b1;
end
if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin
OC_x09 <= 4'b1000;
end
else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin
OC_x25 <= 4'b1000;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end
default: begin
OC_x09 <= 4'b0000;
OC_x25 <= 4'b0000;
end
endcase
end
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
//Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
end
end
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin 4'b0010: begin
OC_x09 <= 4'b0001; //Sanity Check
end if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin err_flag <= 1'b1;
OC_x25 <= 4'b0001; end
end else begin
else begin if (i_DC_Con2[23] == 1'b0) begin //Select PMU
OC_x09 <= 'd0; PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
OC_x25 <= 'd0; end
end else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
end
4'b0010: begin end
relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0}; end
if (delay_cnt == 'd500) begin
relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin 4'b0100:begin
OC_x09 <= 4'b0010; //Sanity Check
end if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin err_flag <= 1'b1;
OC_x25 <= 4'b0010; end
end else begin
else begin if (i_DC_Con3[23] == 1'b0) begin //Select PMU
OC_x09 <= 'd0; PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
OC_x25 <= 'd0; end
end else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
end
4'b0100: begin end
relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0}; end
if (delay_cnt == 'd500) begin
relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay3 > 64) &(freq_relay3 <73)) begin 4'b1000:begin
OC_x09 <= 4'b0100; //Sanity Check
end if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin err_flag <= 1'b1;
OC_x25 <= 4'b0100; end
end else begin
else begin if (i_DC_Con4[23] == 1'b0) begin //Select PMU
OC_x09 <= 'd0; PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
OC_x25 <= 'd0; end
end else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
end
4'b1000: begin end
relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0}; end
if (delay_cnt == 'd500) begin
relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0};
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0};
end
else if (delay_cnt == 'd1080) begin
exec_flag <= 'd0; exec_flag <= 'd0;
exec_done_flag <= 1'b1; exec_done_flag <= 1'b1;
end end
if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin default:begin // You Should NOT be HERE
OC_x09 <= 4'b1000; PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
end end
else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin endcase
OC_x25 <= 4'b1000; end
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
end
end
default: begin
OC_x09 <= 4'b0000;
OC_x25 <= 4'b0000;
end
endcase
end end
end end
end end
@@ -189,4 +315,11 @@ module CPLD_Con (
assign o_OC_x09 = OC_x09; assign o_OC_x09 = OC_x09;
assign o_OC_x25 = OC_x25; assign o_OC_x25 = OC_x25;
assign o_PMU_OC_1 = PMU_OC_1;
assign o_PMU_OC_2 = PMU_OC_2;
assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4;
assign o_err = err_flag;
endmodule endmodule
2.FW/CPLD2/NewExtIns_CPLD2.ldf
+1 -1
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@@ -2,7 +2,7 @@
<BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1"> <BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/> <Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1"> <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop"/> <Options def_top="CPLD_Con" top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog"> <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/> <Options top_module="RelayConTop"/>
</Source> </Source>
2.FW/CPLD2/NewExtIns_CPLD2.lpf
+194 -193
View File
@@ -1,4 +1,4 @@
rvl_alias "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk";
@@ -127,196 +127,197 @@ LOCATE COMP "o_RC_T[23]" SITE "U15" ;
LOCATE COMP "o_RC_T[24]" SITE "T13" ; LOCATE COMP "o_RC_T[24]" SITE "T13" ;
LOCATE COMP "o_RC_T[25]" SITE "AA13" ; LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
LOCATE COMP "o_err" SITE "AB16" ; LOCATE COMP "o_err" SITE "AB16" ;
IOBUF PORT "o_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_OC_1[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_2[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_3[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_OC_4[8]" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_OC_1[8]" SITE "D14" ; LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
LOCATE COMP "o_OC_1[9]" SITE "G13" ; LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
LOCATE COMP "o_OC_1[10]" SITE "C13" ; LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
LOCATE COMP "o_OC_1[11]" SITE "F13" ; LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
LOCATE COMP "o_OC_1[12]" SITE "C17" ; LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
LOCATE COMP "o_OC_1[13]" SITE "F17" ; LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
LOCATE COMP "o_OC_1[14]" SITE "D17" ; LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
LOCATE COMP "o_OC_1[15]" SITE "E17" ; LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
LOCATE COMP "o_OC_1[24]" SITE "N5" ; LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
LOCATE COMP "o_OC_1[25]" SITE "D15" ; LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
LOCATE COMP "o_OC_1[26]" SITE "P3" ; LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
LOCATE COMP "o_OC_1[27]" SITE "M4" ; LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
LOCATE COMP "o_OC_1[28]" SITE "R6" ; LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
LOCATE COMP "o_OC_1[29]" SITE "T5" ; LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
LOCATE COMP "o_OC_1[30]" SITE "P6" ; LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
LOCATE COMP "o_OC_1[31]" SITE "U4" ; LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
LOCATE COMP "o_OC_2[8]" SITE "C1" ; LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
LOCATE COMP "o_OC_2[9]" SITE "C2" ; LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
LOCATE COMP "o_OC_2[10]" SITE "C3" ; LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
LOCATE COMP "o_OC_2[11]" SITE "B1" ; LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
LOCATE COMP "o_OC_2[12]" SITE "H5" ; LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
LOCATE COMP "o_OC_2[13]" SITE "H6" ; LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
LOCATE COMP "o_OC_2[14]" SITE "H2" ; LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
LOCATE COMP "o_OC_2[15]" SITE "H3" ; LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
LOCATE COMP "o_OC_2[24]" SITE "T7" ; LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
LOCATE COMP "o_OC_2[25]" SITE "U5" ; LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
LOCATE COMP "o_OC_2[26]" SITE "W5" ; LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
LOCATE COMP "o_OC_2[27]" SITE "T6" ; LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
LOCATE COMP "o_OC_2[28]" SITE "E8" ; LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
LOCATE COMP "o_OC_2[29]" SITE "E9" ; LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
LOCATE COMP "o_OC_2[30]" SITE "E10" ; LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
LOCATE COMP "o_OC_2[31]" SITE "D11" ; LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
LOCATE COMP "o_OC_3[8]" SITE "A11" ; LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
LOCATE COMP "o_OC_3[9]" SITE "A12" ; LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
LOCATE COMP "o_OC_3[10]" SITE "B12" ; LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
LOCATE COMP "o_OC_3[11]" SITE "A13" ; LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
LOCATE COMP "o_OC_3[12]" SITE "B19" ; LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
LOCATE COMP "o_OC_3[13]" SITE "C18" ; LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
LOCATE COMP "o_OC_3[14]" SITE "A17" ; LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
LOCATE COMP "o_OC_3[15]" SITE "B16" ; LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
LOCATE COMP "o_OC_3[24]" SITE "B13" ; LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
LOCATE COMP "o_OC_3[25]" SITE "B14" ; LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
LOCATE COMP "o_OC_3[26]" SITE "B15" ; LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
LOCATE COMP "o_OC_3[27]" SITE "C15" ; LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
LOCATE COMP "o_OC_3[28]" SITE "G21" ; LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
LOCATE COMP "o_OC_3[29]" SITE "E22" ; LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
LOCATE COMP "o_OC_3[30]" SITE "E20" ; LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
LOCATE COMP "o_OC_3[31]" SITE "D21" ; LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
LOCATE COMP "o_OC_4[8]" SITE "G1" ; LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
LOCATE COMP "o_OC_4[9]" SITE "G2" ; LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
LOCATE COMP "o_OC_4[10]" SITE "G3" ; LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
LOCATE COMP "o_OC_4[11]" SITE "F1" ; LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
LOCATE COMP "o_OC_4[12]" SITE "C4" ; LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
LOCATE COMP "o_OC_4[13]" SITE "C5" ; LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
LOCATE COMP "o_OC_4[14]" SITE "G11" ; LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
LOCATE COMP "o_OC_4[15]" SITE "E11" ; LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
LOCATE COMP "o_OC_4[24]" SITE "E1" ; LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
LOCATE COMP "o_OC_4[25]" SITE "D1" ; LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
LOCATE COMP "o_OC_4[26]" SITE "E2" ; LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
LOCATE COMP "o_OC_4[27]" SITE "D3" ; LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
LOCATE COMP "o_OC_4[28]" SITE "C11" ; LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
LOCATE COMP "o_OC_4[29]" SITE "A2" ; LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
LOCATE COMP "o_OC_4[30]" SITE "B3" ; LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
LOCATE COMP "o_OC_4[31]" SITE "A3" ; LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
USE PRIMARY NET "i_sys_clk_c" ; USE PRIMARY NET "i_sys_clk_c" ;
IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 ;
2.FW/CPLD2/Reg_file.v
+12 -2
View File
@@ -21,13 +21,19 @@ module Reg_file (
output [23:0] o_freq1, output [23:0] o_freq1,
output [23:0] o_freq2, output [23:0] o_freq2,
output [23:0] o_freq3, output [23:0] o_freq3,
output [23:0] o_freq4 output [23:0] o_freq4,
//DC Regs
output [23:0] o_DC1,
output [23:0] o_DC2,
output [23:0] o_DC3,
output [23:0] o_DC4
); );
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h400000 | 12'b0001_0000_0000, //CPLD2==1,version=1.0.0 IDENT = 24'h400000 | 12'b0001_0001_0000, //CPLD2==1,version=1.1.0
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
@@ -163,5 +169,9 @@ module Reg_file (
assign o_freq2 = regtable[3]; assign o_freq2 = regtable[3];
assign o_freq3 = regtable[4]; assign o_freq3 = regtable[4];
assign o_freq4 = regtable[5]; assign o_freq4 = regtable[5];
assign o_DC1 = regtable[6];
assign o_DC2 = regtable[7];
assign o_DC3 = regtable[8];
assign o_DC4 = regtable[9];
endmodule endmodule
2.FW/CPLD2/RelayConTop.v
+58 -9
View File
@@ -16,10 +16,10 @@ module RelayConTop (
output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1) output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1)
//output [3:0] o_OC_x09, //output [3:0] o_OC_x09,
//output [3:0] o_OC_x25, //output [3:0] o_OC_x25,
output [31:0]o_OC_1, output [31:0]o_PMU_OC_1 ,
output [31:0]o_OC_2, output [31:0]o_PMU_OC_2 ,
output [31:0]o_OC_3, output [31:0]o_PMU_OC_3 ,
output [31:0]o_OC_4 output [31:0]o_PMU_OC_4
); );
wire [7:0] RC_F; wire [7:0] RC_F;
@@ -37,12 +37,26 @@ module RelayConTop (
wire wr_flag; //1=write,0=read wire wr_flag; //1=write,0=read
wire bus_err_flag; wire bus_err_flag;
wire reg_err_flag; wire reg_err_flag;
wire cpld_err_flag;
wire con_exec; wire con_exec;
wire [23:0]freq1_relay ; wire [23:0]freq1_relay ;
wire [23:0]freq2_relay ; wire [23:0]freq2_relay ;
wire [23:0]freq3_relay ; wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ; wire [23:0]freq4_relay ;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
//PMU OC Control
wire [31:0]PMU_OC_1 ;
wire [31:0]PMU_OC_2 ;
wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ;
wire con_rvalid; wire con_rvalid;
wire con_done; wire con_done;
@@ -79,6 +93,10 @@ module RelayConTop (
.o_freq2(freq2_relay), //Freq_Slot2 .o_freq2(freq2_relay), //Freq_Slot2
.o_freq3(freq3_relay), //Freq_Slot3 .o_freq3(freq3_relay), //Freq_Slot3
.o_freq4(freq4_relay), //Freq_Slot4 .o_freq4(freq4_relay), //Freq_Slot4
.o_DC1(DC_Con1),
.o_DC2(DC_Con2),
.o_DC3(DC_Con3),
.o_DC4(DC_Con4),
.o_rvalid(con_rvalid), .o_rvalid(con_rvalid),
.o_rdata(r_data), .o_rdata(r_data),
.o_exec(con_exec), //Exec cmd .o_exec(con_exec), //Exec cmd
@@ -94,12 +112,21 @@ module RelayConTop (
.i_freq_relay2(freq2_relay), .i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay), .i_freq_relay3(freq3_relay),
.i_freq_relay4(freq4_relay), .i_freq_relay4(freq4_relay),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.o_PMU_OC_1(PMU_OC_1),
.o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4),
.o_con_done(con_done), .o_con_done(con_done),
.o_RC_F(RC_F), .o_RC_F(RC_F),
.o_RC_S(RC_S), .o_RC_S(RC_S),
.o_RC_T(RC_T), .o_RC_T(RC_T),
.o_OC_x09(OC_x09), .o_OC_x09(OC_x09),
.o_OC_x25(OC_x25) .o_OC_x25(OC_x25),
.o_err(cpld_err_flag)
); );
@@ -107,10 +134,32 @@ module RelayConTop (
assign o_RC_S = RC_S; assign o_RC_S = RC_S;
assign o_RC_T = RC_T[25:0]; assign o_RC_T = RC_T[25:0];
//assign o_OC_1[8] = OC_x09[0]; assign o_PMU_OC_1[8] = OC_x09[0];
//assign o_OC_2[8] = OC_x09[1]; assign o_PMU_OC_2[8] = OC_x09[1];
//assign o_OC_3[8] = OC_x09[2]; assign o_PMU_OC_3[8] = OC_x09[2];
//assign o_OC_4[8] = OC_x09[3]; assign o_PMU_OC_4[8] = OC_x09[3];
assign o_PMU_OC_1[24] = OC_x25[0];
assign o_PMU_OC_2[24] = OC_x25[1];
assign o_PMU_OC_3[24] = OC_x25[2];
assign o_PMU_OC_4[24] = OC_x25[3];
assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
assign o_err = bus_err_flag || reg_err_flag; assign o_err = bus_err_flag || reg_err_flag;