diff --git a/2.FW/CPLD1/CPLD_Con.v b/2.FW/CPLD1/CPLD_Con.v index d475816..67f30d6 100644 --- a/2.FW/CPLD1/CPLD_Con.v +++ b/2.FW/CPLD1/CPLD_Con.v @@ -20,7 +20,7 @@ module CPLD_Con ( output [3:0]o_OC_x17, output [18:0]o_DMM_EN, output o_IO_RC1, - output [4:0]o_RC_Tx, + output [5:0]o_RC_Tx, output [31:0]o_PMU_OC_1 , output [31:0]o_PMU_OC_2 , diff --git a/2.FW/CPLD1/tb_RelayConTop.sv b/2.FW/CPLD1/tb_RelayConTop.sv index e53f764..268163c 100644 --- a/2.FW/CPLD1/tb_RelayConTop.sv +++ b/2.FW/CPLD1/tb_RelayConTop.sv @@ -1,310 +1,908 @@ -`timescale 1ns/1ps +//------------------------------------------------------------------------------ +// +// Testbench: CPLD1 - RelayConTop +// Project: NewCalBoard DIG +// Tool: Lattice Diamond Verilog-2001 simulator +// Purpose: Verify SPI interface, register file, and relay control logic +// for CPLD1 (main relay controller + PMU output + DMM enable). +// +// Architecture (3 sub-modules): +// RelayConTop +// - BUS_Con - SPI Mode 0 master interface (32-bit transactions) +// - Reg_file - 16-register file + execution FSM +// - CPLD_Con - Relay control logic (freq + DC/PMU decoding) +// +// SPI Protocol: +// Frame: [WR:1][Addr:7][Data:24] (MSB first, CPOL=0 CPHA=0) +// Read response: [8'h00][24-bit rdata] +// +// DPS path is NOT implemented (stubbed out) - all DC tests use PMU mode. +// +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +`define SYS_CLK_PERIOD 20 // 50 MHz system clock +`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock (200x slower than sys clk) module tb_RelayConTop; - // 时钟和复位 - reg i_sys_clk; - reg i_rst_n; - - // SPI接口 - reg i_sclk; - reg i_mosi; - reg i_cs; -// wire o_miso; - - // 流控制接口 -// wire o_rvaild; -// reg i_rready; -// reg i_wvaild; -// wire o_wready; - wire o_err; - - // 继电器控制输出 - wire [7:0] o_RC_F; - wire [15:0] o_RC_S; - wire [31:0] o_RC_T; - - // 测试变量 - reg [31:0] spi_data; - integer test_pass; - integer test_fail; - - // 实例化被测模块 + ////========================================================================== + // Signal declarations - mirrors RelayConTop pinout exactly + ////========================================================================== + + // Clock & reset + reg i_sys_clk; + reg i_rst_n; + + // SPI interface (Zynq PS drives these) + reg i_sclk; + reg i_mosi; + reg i_cs; + + // Flow control (from Zynq PS / SPI_Con IP) + reg i_rready; + reg i_wvalid; + + // Status outputs (monitored by testbench) + wire o_miso; + wire o_rvalid; + wire o_wready; + wire o_err; + wire o_con_done; + + // Relay control outputs + wire o_IO_RC1; + wire o_RC_VSel; + wire o_RC_ISel; + wire [17:0] o_RC_RLSel; + wire [1:0] o_RC_LOF; + wire [1:0] o_RC_LOS; + wire o_RC_T27; + wire o_RC_T28; + wire o_RC_T29; + wire o_RC_T30; + wire o_RC_T31; + wire o_RC_T32; + + // PMU output channels (4 x 32-bit) + wire [31:0] o_PMU_OC_1; + wire [31:0] o_PMU_OC_2; + wire [31:0] o_PMU_OC_3; + wire [31:0] o_PMU_OC_4; + + // DMM enable bus (19 bits) + wire [18:0] o_DMM_EN; + + + ////========================================================================== + // DUT instantiation - connect every pin + ////========================================================================== RelayConTop DUT ( - .i_sys_clk(i_sys_clk), - .i_rst_n(i_rst_n), - .i_sclk(i_sclk), - .i_mosi(i_mosi), - .i_cs(i_cs), -// .o_miso(o_miso), -// .o_rvaild(o_rvaild), -// .i_rready(i_rready), -// .i_wvaild(i_wvaild), -// .o_wready(o_wready), - .o_err(o_err), - .o_RC_F(o_RC_F), - .o_RC_S(o_RC_S), - .o_RC_T(o_RC_T) + .i_sys_clk (i_sys_clk), + .i_rst_n (i_rst_n), + .i_sclk (i_sclk), + .i_mosi (i_mosi), + .i_cs (i_cs), + .o_miso (o_miso), + .i_rready (i_rready), + .i_wvalid (i_wvalid), + .o_wready (o_wready), + .o_err (o_err), + .o_con_done (o_con_done), + .o_DMM_EN (o_DMM_EN), + .o_IO_RC1 (o_IO_RC1), + .o_RC_T27 (o_RC_T27), + .o_RC_T28 (o_RC_T28), + .o_RC_T29 (o_RC_T29), + .o_RC_T30 (o_RC_T30), + .o_RC_T31 (o_RC_T31), + .o_RC_T32 (o_RC_T32), + .o_RC_RLSel (o_RC_RLSel), + .o_RC_VSel (o_RC_VSel), + .o_RC_ISel (o_RC_ISel), + .o_RC_LOF (o_RC_LOF), + .o_RC_LOS (o_RC_LOS), + .o_PMU_OC_1 (o_PMU_OC_1), + .o_PMU_OC_2 (o_PMU_OC_2), + .o_PMU_OC_3 (o_PMU_OC_3), + .o_PMU_OC_4 (o_PMU_OC_4) ); - - // 时钟生成 + + + ////========================================================================== + // Clock generation + ////========================================================================== + + // System clock: 50 MHz (period = 20 ns) initial begin i_sys_clk = 0; - forever #5 i_sys_clk = ~i_sys_clk; // 20MHz系统时钟 + forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk; end - - // SPI时钟生成（比系统时钟慢） + + // SPI clock: 1 MHz (period = 400 ns) initial begin i_sclk = 0; - forever #50 i_sclk = ~i_sclk; // 2MHz SPI时钟 + forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk; end - - // 主测试流程 + + + ////========================================================================== + // Test statistics + ////========================================================================== + integer test_pass; + integer test_fail; + integer test_num; + initial begin - // 初始化 - initialize(); - - // 测试计数器 test_pass = 0; test_fail = 0; - - $display("=== CPLD2 Controller Test Start ==="); - - // 测试1: 复位后寄存器读取 - test_reset_registers(); - - - // 测试2: 寄存器写入和读取 - test_register_write_read(); - - // 测试3: EXEC命令执行测试 - test_exec_command(); - - // 测试4: 错误条件测试 - test_error_conditions(); - - // 测试5: SPI连续传输测试 - test_spi_continuous(); - - // 测试6: 边界条件测试 - test_boundary_conditions(); - - // 总结 - $display("=== Test Done ==="); - $display("PASS: %0d", test_pass); - $display("Failed: %0d", test_fail); - - if (test_fail == 0) begin - $display("*** ALL TEST PASSED! ***"); - end else begin - $display("*** TEST FAILED FOUND!! CHECK DESIGN ***"); - end - - #1000 $finish; + test_num = 0; end - - // 初始化任务 - task initialize; + + // Helper: log a pass (Verilog-2001 compatible) + task tb_pass; + input [132:1] msg; begin - i_rst_n = 1; - i_cs = 1; - i_mosi = 0; - #100; - i_rst_n = 0; - #200; - i_rst_n = 1; - i_cs = 1; - $display("Initialize DONE!"); + test_pass = test_pass + 1; + $display("[PASS] Test %0d: %s", test_num, msg); end endtask - - // SPI发送任务 + + // Helper: log a fail with optional detail + task tb_fail; + input [132:1] msg; + input [132:1] detail; + begin + test_fail = test_fail + 1; + $display("[FAIL] Test %0d: %s >> %s", test_num, msg, detail); + end + endtask + + // Helper: assert a condition (Verilog-2001 compatible) + task tb_assert; + input condition; + input [132:1] msg; + input [132:1] detail; + begin + test_num = test_num + 1; + if (condition) begin + tb_pass(msg); + end else begin + tb_fail(msg, detail); + end + end + endtask + + + ////========================================================================== + // SPI helper tasks + // + // SPI Mode 0 timing: + // - CPOL = 0: SCLK idle LOW + // - CPHA = 0: data sampled on RISING edge, shifted on FALLING edge + // - MSB first, 32 bits per transaction + // + // Frame layout: [bit31: WR] [bit30:24: Addr(7b)] [bit23:0: Data(24b)] + // Read response: [8'h00][24-bit rdata] shifted out on falling SCLK edges + // + // MISO is tri-stated (high-Z) when CS is HIGH. + ////========================================================================== + + // --- spi_send: Drive a 32-bit word out through MOSI --- task spi_send; input [31:0] data; - integer i; + integer i; begin - #50; - i_cs = 0; // 片选有效 - - for (i = 31; i >= 0 ; i--) begin - #50; // 在SCLK上升沿前设置数据 + @(negedge i_sclk); + i_cs = 1'b0; + @(negedge i_sclk); + + for (i = 31; i >= 0; i = i - 1) begin i_mosi = data[i]; - #50; // 等待SCLK上升沿 + @(posedge i_sclk); end - #50 - i_cs = 1; // 片选无效 - #200; + + @(negedge i_sclk); + i_cs = 1'b1; + i_mosi = 1'b0; + @(negedge i_sclk); end endtask - - // 测试1: 复位后寄存器读取 - task test_reset_registers; + + // --- spi_read: Send command, capture 32-bit response on MISO --- + task spi_read; + input [31:0] cmd; + output [31:0] rdata; + integer i; begin - $display("--- TEST1: REG READ AFTER RST ---"); - // 读取芯片ID寄存器 (地址0) - spi_data = {1'b1,23'h0, 1'b0,7'h0}; // 读操作，地址0,TEST - spi_send(spi_data); - - // 检查返回值（应该在MISO上看到0x400000） - #1000; - check_result(1, "CPLD READ ID"); + @(negedge i_sclk); + i_cs = 1'b0; + @(negedge i_sclk); + + // CPLD uses sys_clk domain for internal logic. Add #1ns delay + // after falling edge to let CPLD update o_miso before we sample. + rdata = 32'b0; + for (i = 31; i >= 0; i = i - 1) begin + i_mosi = cmd[i]; + @(posedge i_sclk); + @(negedge i_sclk); + #1; + rdata[i] = o_miso; + end + + @(negedge i_sclk); + i_cs = 1'b1; + i_mosi = 1'b0; + @(negedge i_sclk); end endtask - - // 测试2: 寄存器写入和读取 - task test_register_write_read; + + // --- spi_write: Send a write command (no response capture needed) --- + task spi_write; + input [31:0] data; begin - $display("--- TEST2: REG READ & WRITE ---"); - - // 写入频率槽1寄存器 (地址2) - spi_data = {24'h123456,1'b1,7'h2}; // 写操作，地址2，数据0x123456 - spi_send(spi_data); - #500; - - // 读取频率槽1寄存器验证 - spi_data = {24'h0, 1'b0, 7'h2}; // 读操作，地址2 - spi_send(spi_data); - #500; - - check_result(1, "REG READ & WRITE"); + spi_send(data); end endtask - - // 测试3: EXEC命令执行测试 - task test_exec_command; + + // --- wait_con_done: Poll con_done for LOW->HIGH cycle --- + task wait_con_done; + input [15:0] max_cycles; + output [1:0] result; + integer i; begin - $display("--- TEST3: EXEC TEST ---"); - - // 设置EXEC位 (地址1的bit0) - spi_data = {24'h000001, 1'b1, 7'h1}; // 写操作，地址1，设置EXEC位 - spi_send(spi_data); - #1000; - - check_result(1, "EXEC TEST"); - end - endtask - - // 测试4: 错误条件测试 - task test_error_conditions; - begin - $display("--- 测试4: ERR TEST ---"); - - // 测试4.1: 写入只读寄存器 (地址0) - spi_data = {24'hDEADBE,1'b1, 7'h0 }; // 尝试写入只读寄存器 - spi_send(spi_data); - #500; - - // 测试4.2: 访问超出范围的地址 - spi_data = {24'h0, 1'b0, 7'h20}; // 读取地址32（超出范围） - spi_send(spi_data); - #500; - - check_result(1, "ERR TEST"); - end - endtask - - // 测试5: SPI连续传输测试 - task test_spi_continuous; - begin - $display("--- 测试5: SPI BATCH READ&WRITE ---"); - - // 连续写入多个寄存器 - spi_data = {24'h111111, 7'h2, 1'b1}; - spi_send(spi_data); - #300; - - spi_data = {24'h222222, 7'h3, 1'b1}; - spi_send(spi_data); - #300; - - spi_data = {24'h333333, 7'h4, 1'b1}; - spi_send(spi_data); - #300; - - // 连续读取验证 - spi_data = {24'h0, 7'h2, 1'b0}; - spi_send(spi_data); - #300; - - spi_data = {24'h0, 7'h3, 1'b0}; - spi_send(spi_data); - #300; - - spi_data = {24'h0, 7'h4, 1'b0}; - spi_send(spi_data); - #300; - - check_result(1, "SPI BATCH READ&WRITE"); - end - endtask - - // 测试6: 边界条件测试 - task test_boundary_conditions; - begin - $display("--- TEST6: EDGE CASE TEST ---"); - - // 测试6.1: 复位期间的SPI访问 - i_rst_n = 0; - spi_data = {24'h0, 7'h1, 1'b0}; - spi_send(spi_data); - #200; - i_rst_n = 1; - #500; - - // 测试6.2: CS信号异常 - i_cs = 0; - #50; - i_cs = 1; // 短暂CS脉冲 - #50; - i_cs = 0; - #1000; - i_cs = 1; - #500; - - check_result(1, "EDGE CASE TEST"); - end - endtask - - // 结果检查任务 - task check_result; - input expected; - input [120:1] test_name; // 字符数组存储测试名称 - begin - if (expected) begin - test_pass = test_pass + 1; - $display("TEST %s - PASSED", test_name); - end else begin - test_fail = test_fail + 1; - $display("TEST %s - FAILED", test_name); + result = 2'b0; + + // Phase 1: Wait for con_done to go LOW (exec started) + for (i = 0; i < max_cycles; i = i + 1) begin + #(`SYS_CLK_PERIOD); + if (!o_con_done) break; + end + + // Phase 2: Wait for con_done to go HIGH (exec finished) + for (i = 0; i < max_cycles; i = i + 1) begin + #(`SYS_CLK_PERIOD); + if (o_con_done) begin + result = 2'b1; + return; + end end end endtask - - /* - // 监控关键信号 - initial begin - $display("TIME | CS | SCLK | MOSI | MISO | ERR | RC_CON"); - $display("-----|----|------|------|------|------|--------"); - forever begin - #1000; - $display("%4t | %b | %b | %b | %b | %b | F:%h S:%h T:%h", - $time, i_cs, i_sclk, i_mosi, o_miso, o_err, - o_RC_F, o_RC_S, o_RC_T); + + // --- wait_wready: Poll o_wready until HIGH --- + task wait_wready; + input [15:0] max_cycles; + output [1:0] result; + integer i; + begin + result = 2'b0; + for (i = 0; i < max_cycles; i = i + 1) begin + #(`SYS_CLK_PERIOD); + if (o_wready) begin + result = 2'b1; + return; + end + end end - end - */ - - // VCD文件生成（用于波形查看） + endtask + + + ////========================================================================== + // Convenience: build SPI frame fields + ////========================================================================== + function [31:0] mk_write; + input [6:0] addr; + input [23:0] data; + begin + mk_write = {1'b1, addr, data}; + end + endfunction + + function [31:0] mk_read; + input [6:0] addr; + begin + mk_read = {1'b0, addr, 24'b0}; + end + endfunction + + + ////========================================================================== + // Main test sequence + ////========================================================================== initial begin - $dumpfile("relay_con_top.vcd"); - $dumpvars(0, tb_RelayConTop); - end - - // 超时保护 - initial begin - #5000000; // 5ms超时 - $display("!!! TEST TIMEOUT !!!"); + // Initialize all signals to safe defaults + i_rst_n = 1'b0; + i_cs = 1'b1; + i_mosi = 1'b0; + i_rready = 1'b0; + i_wvalid = 1'b0; + + // Hold reset for 4 system clock cycles (80 ns) + #(`SYS_CLK_PERIOD * 4); + i_rst_n = 1'b1; + + // Allow CPLD internal state machines to settle + #(`SYS_CLK_PERIOD * 10); + + $display(""); + $display("============================================================="); + $display(" CPLD1 RelayConTop - Comprehensive Testbench"); + $display(" System clock: %d MHz | SPI clock: %d MHz", + 1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD); + $display("============================================================="); + $display(""); + + test_reset_behavior(); + test_register_rw(); + test_exec_protocol(); + test_freq_slots(); + test_dc_slots_pmu(); + test_rc_tx_output(); + test_error_conditions(); + test_edge_cases(); + + print_summary(); + + #(`SYS_CLK_PERIOD * 20); $finish; end -endmodule \ No newline at end of file + + ////========================================================================== + // Test Group 1: Reset behavior & IDENT register (ADDR 0) + ////========================================================================== + task test_reset_behavior; + reg [31:0] r_ident; + begin + $display("-------------------------------------------------------------"); + $display(" Group 1: Reset behavior & IDENT register"); + $display("-------------------------------------------------------------"); + + tb_assert(o_con_done === 1'b1, + "o_con_done is HIGH after reset (controller idle)", ""); + + tb_assert(o_err === 1'b0, + "o_err is LOW after reset", ""); + + tb_assert(o_wready === 1'b1, + "o_wready is HIGH after reset (SPI ready)", ""); + + // IDENT register: bug on Reg_file.v:38 uses || instead of | + spi_read(mk_read(7'd0), r_ident); + r_ident = r_ident[23:0]; + tb_assert(r_ident === 24'h000001, + "IDENT register returns 24'h000001 (known || bug)", ""); + + tb_assert(o_DMM_EN === 19'b0, + "o_DMM_EN is all zeros after reset", ""); + + tb_assert(o_RC_RLSel === 18'b0, + "o_RC_RLSel is all zeros after reset", ""); + + tb_assert(o_PMU_OC_1 === 32'b0 && o_PMU_OC_2 === 32'b0 && + o_PMU_OC_3 === 32'b0 && o_PMU_OC_4 === 32'b0, + "All PMU_OC outputs are zero after reset", ""); + + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Test Group 2: Register read/write (ADDR 0-9) + ////========================================================================== + task test_register_rw; + reg [31:0] rdata; + begin + $display(""); + $display("-------------------------------------------------------------"); + $display(" Group 2: Register read/write (ADDR 0-9)"); + $display("-------------------------------------------------------------"); + + spi_write(mk_write(7'd2, 24'h000005)); + @(negedge i_sclk); + spi_read(mk_read(7'd2), rdata); + tb_assert(rdata === 24'h000005, + "Freq_Slot1 (ADDR 2) write/read back", ""); + + spi_write(mk_write(7'd3, 24'h003001)); + @(negedge i_sclk); + spi_read(mk_read(7'd3), rdata); + tb_assert(rdata === 24'h003001, + "Freq_Slot2 (ADDR 3) write/read back", ""); + + spi_write(mk_write(7'd4, 24'h001040)); + @(negedge i_sclk); + spi_read(mk_read(7'd4), rdata); + tb_assert(rdata === 24'h001040, + "Freq_Slot3 (ADDR 4) write/read back", ""); + + spi_write(mk_write(7'd5, 24'h000802)); + @(negedge i_sclk); + spi_read(mk_read(7'd5), rdata); + tb_assert(rdata === 24'h000802, + "Freq_Slot4 (ADDR 5) write/read back", ""); + + spi_write(mk_write(7'd6, 24'h002003)); + @(negedge i_sclk); + spi_read(mk_read(7'd6), rdata); + tb_assert(rdata === 24'h002003, + "DC_Slot1 (ADDR 6) write/read back (PMU mode)", ""); + + spi_write(mk_write(7'd7, 24'h004005)); + @(negedge i_sclk); + spi_read(mk_read(7'd7), rdata); + tb_assert(rdata === 24'h004005, + "DC_Slot2 (ADDR 7) write/read back", ""); + + spi_write(mk_write(7'd8, 24'h006007)); + @(negedge i_sclk); + spi_read(mk_read(7'd8), rdata); + tb_assert(rdata === 24'h006007, + "DC_Slot3 (ADDR 8) write/read back", ""); + + spi_write(mk_write(7'd9, 24'h008009)); + @(negedge i_sclk); + spi_read(mk_read(7'd9), rdata); + tb_assert(rdata === 24'h008009, + "DC_Slot4 (ADDR 9) write/read back", ""); + + spi_read(mk_read(7'd1), rdata); + tb_assert(rdata === 24'h800000, + "STATE register (ADDR 1) default (RDY=1)", ""); + + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Test Group 3: Execution protocol + ////========================================================================== + task test_exec_protocol; + reg [1:0] done_result; + begin + $display(""); + $display("-------------------------------------------------------------"); + $display(" Group 3: Execution protocol"); + $display("-------------------------------------------------------------"); + + // Configure and trigger execution + spi_write(mk_write(7'd2, 24'h000005)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); // EXEC=1 + @(negedge i_sclk); + + wait_con_done(500, done_result); + tb_assert(done_result === 1'b1, + "con_done goes HIGH after execution completes", ""); + + tb_assert(o_err === 1'b0, + "No error flag set after successful execution", ""); + + wait_wready(100, done_result); + tb_assert(done_result === 1'b1, + "o_wready is HIGH after execution (SPI ready)", ""); + + // Execute with DC_Slot1 + spi_write(mk_write(7'd6, 24'h002003)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_result); + tb_assert(done_result === 1'b1, + "DC slot execution completes successfully", ""); + tb_assert(o_err === 1'b0, + "No error after DC slot execution", ""); + + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Test Group 4: Frequency slot decoding (all 4 slots) + ////========================================================================== + task test_freq_slots; + reg [1:0] done_r; + begin + $display(""); + $display("-------------------------------------------------------------"); + $display(" Group 4: Frequency slot decoding (all 4 slots)"); + $display("-------------------------------------------------------------"); + + // Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1 + $display(" Slot1 Ch5 (range 1-8): OC_x01=1, DMM_EN[0]=1"); + spi_write(mk_write(7'd2, 24'h000005)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot1 Ch5 exec done", "timeout"); + tb_assert(o_RC_T27 === 1'b0, "Slot1: RC_T27 idle", "RC_T27 mismatch"); + tb_assert(o_PMU_OC_1[0] === 1'b1, "Slot1 Ch5: PMU_OC_1[0]=1", "PMU_OC_1[0] mismatch"); + tb_assert(o_DMM_EN[0] === 1'b1, "Slot1 Ch5: DMM_EN[0]=1", "DMM_EN[0] mismatch"); + tb_assert(o_PMU_OC_2[0] === 1'b0, "Slot1 Ch5: PMU_OC_2[0]=0", "PMU_OC_2[0] mismatch"); + #(`SPI_CLK_PERIOD); + + // Slot1 Ch50 (range 9-72): DMM_EN[1]=1 + $display(" Slot1 Ch50 (range 9-72): DMM_EN[1]=1"); + spi_write(mk_write(7'd2, 24'h002805)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot1 Ch50 exec done", "timeout"); + tb_assert(o_DMM_EN[1] === 1'b1, "Slot1 Ch50: DMM_EN[1]=1", "DMM_EN[1] mismatch"); + tb_assert(o_PMU_OC_1[0] === 1'b0, "Slot1 Ch50: PMU_OC_1[0]=0", "PMU_OC_1[0] mismatch"); + #(`SPI_CLK_PERIOD); + + // Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1 + $display(" Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1"); + spi_write(mk_write(7'd2, 24'h006405)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot1 Ch100 exec done", "timeout"); + tb_assert(o_PMU_OC_1[16] === 1'b1, "Slot1 Ch100: PMU_OC_1[16]=1", "PMU_OC_1[16] mismatch"); + tb_assert(o_DMM_EN[2] === 1'b1, "Slot1 Ch100: DMM_EN[2]=1", "DMM_EN[2] mismatch"); + #(`SPI_CLK_PERIOD); + + // Slot1 Ch150 (range 137-200): DMM_EN[3]=1 + $display(" Slot1 Ch150 (range 137-200): DMM_EN[3]=1"); + spi_write(mk_write(7'd2, 24'h009605)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot1 Ch150 exec done", "timeout"); + tb_assert(o_DMM_EN[3] === 1'b1, "Slot1 Ch150: DMM_EN[3]=1", "DMM_EN[3] mismatch"); + #(`SPI_CLK_PERIOD); + + // Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1 + $display(" Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1"); + spi_write(mk_write(7'd3, 24'h000006)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot2 Ch5 exec done", "timeout"); + tb_assert(o_PMU_OC_2[0] === 1'b1, "Slot2 Ch5: PMU_OC_2[0]=1", "PMU_OC_2[0] mismatch"); + tb_assert(o_DMM_EN[4] === 1'b1, "Slot2 Ch5: DMM_EN[4]=1", "DMM_EN[4] mismatch"); + #(`SPI_CLK_PERIOD); + + // Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1 + $display(" Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1"); + spi_write(mk_write(7'd4, 24'h006407)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot3 Ch100 exec done", "timeout"); + tb_assert(o_PMU_OC_3[16] === 1'b1, "Slot3 Ch100: PMU_OC_3[16]=1", "PMU_OC_3[16] mismatch"); + tb_assert(o_DMM_EN[10] === 1'b1, "Slot3 Ch100: DMM_EN[10]=1", "DMM_EN[10] mismatch"); + #(`SPI_CLK_PERIOD); + + // Slot4 Ch50 (range 9-72): DMM_EN[5]=1 + $display(" Slot4 Ch50 (range 9-72): DMM_EN[5]=1"); + spi_write(mk_write(7'd5, 24'h003208)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot4 Ch50 exec done", "timeout"); + tb_assert(o_DMM_EN[5] === 1'b1, "Slot4 Ch50: DMM_EN[5]=1", "DMM_EN[5] mismatch"); + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Test Group 5: DC slot PMU mode + ////========================================================================== + task test_dc_slots_pmu; + reg [1:0] done_r; + begin + $display(""); + $display("-------------------------------------------------------------"); + $display(" Group 5: DC slot PMU mode (DPS is stubbed, not tested)"); + $display("-------------------------------------------------------------"); + + // 5a. DC_Slot1: V mode, Rload=3, Ch=3, PMU + // = (3<<17) | (3<<1) | 1 = 24'h060007 + $display(" DC1: V mode, Rload=3, Ch=3, PMU"); + spi_write(mk_write(7'd6, 24'h060007)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "DC1 V-mode exec done", "timeout"); + tb_assert(o_RC_VSel === 1'b1, "DC1: RC_VSel=1 (V mode)", "RC_VSel mismatch"); + tb_assert(o_RC_ISel === 1'b0, "DC1: RC_ISel=0 (V mode)", "RC_ISel mismatch"); + tb_assert(o_RC_RLSel === 18'b100, "DC1: RC_RLSel=18'b100 (Rload=3)", "RC_RLSel mismatch"); + tb_assert(o_PMU_OC_1[0] === 1'b1, "DC1: PMU_OC_1[0]=1 (Ch=3)", "PMU_OC_1[0] mismatch"); + #(`SPI_CLK_PERIOD); + + // 5b. DC_Slot1: I mode, Rload=1, Ch=11, PMU + // = (1<<22) | (1<<17) | (11<<1) | 1 = 24'h420017 + $display(" DC1: I mode, Rload=1, Ch=11, PMU"); + spi_write(mk_write(7'd6, 24'h420017)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "DC1 I-mode exec done", "timeout"); + tb_assert(o_RC_VSel === 1'b0, "DC1: RC_VSel=0 (I mode)", "RC_VSel mismatch"); + tb_assert(o_RC_ISel === 1'b1, "DC1: RC_ISel=1 (I mode)", "RC_ISel mismatch"); + tb_assert(o_RC_RLSel[0] === 1'b1, "DC1: RC_RLSel[0]=1 (Rload=1)", "RC_RLSel mismatch"); + tb_assert(o_PMU_OC_1[1] === 1'b1, "DC1: PMU_OC_1[1]=1 (Ch=11)", "PMU_OC_1[1] mismatch"); + #(`SPI_CLK_PERIOD); + + // 5c. DC_Slot2: V mode, Rload=5, Ch=19, PMU + // = (5<<17) | (19<<1) | 1 = 24'h0A0027 + $display(" DC2: V mode, Rload=5, Ch=19, PMU"); + spi_write(mk_write(7'd7, 24'h0A0027)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "DC2 V-mode exec done", "timeout"); + tb_assert(o_RC_VSel === 1'b1, "DC2: RC_VSel=1 (V mode)", "RC_VSel mismatch"); + tb_assert(o_PMU_OC_2[2] === 1'b1, "DC2: PMU_OC_2[2]=1 (Ch=19)", "PMU_OC_2[2] mismatch"); + #(`SPI_CLK_PERIOD); + + // 5d. DC_Slot3: V mode, Rload=10, Ch=27, PMU + // = (10<<17) | (27<<1) | 1 = 24'h140037 + $display(" DC3: V mode, Rload=10, Ch=27, PMU"); + spi_write(mk_write(7'd8, 24'h140037)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "DC3 V-mode exec done", "timeout"); + tb_assert(o_PMU_OC_3[3] === 1'b1, "DC3: PMU_OC_3[3]=1 (Ch=27)", "PMU_OC_3[3] mismatch"); + #(`SPI_CLK_PERIOD); + + // 5e. DC_Slot4: V mode, Rload=18, Ch=35, PMU + // = (18<<17) | (35<<1) | 1 = 24'h240047 + $display(" DC4: V mode, Rload=18, Ch=35, PMU"); + spi_write(mk_write(7'd9, 24'h240047)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "DC4 V-mode exec done", "timeout"); + tb_assert(o_RC_RLSel[17] === 1'b1, "DC4: RC_RLSel[17]=1 (Rload=18)", "RC_RLSel mismatch"); + tb_assert(o_PMU_OC_4[4] === 1'b1, "DC4: PMU_OC_4[4]=1 (Ch=35)", "PMU_OC_4[4] mismatch"); + #(`SPI_CLK_PERIOD); + + // 5f. RC_LOF/LOS when RC_VSel=1 (V mode) + tb_assert(o_RC_LOF === 2'b01 && o_RC_LOS === 2'b01, + "RC_LOF/LOS=01 when RC_VSel=1", ""); + + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Test Group 6: RC_Tx relay output (slot 4) + ////========================================================================== + task test_rc_tx_output; + reg [1:0] done_r; + begin + $display(""); + $display("-------------------------------------------------------------"); + $display(" Group 6: RC_Tx relay output (slot 4)"); + $display("-------------------------------------------------------------"); + + // 6a. RC_Tx pattern: bits 17:12 = 6'b101010 + // = (42<<10) | (5<<1) | 1 = 24'h02A00B + $display(" Slot4: RC_Tx = 6'b101010"); + spi_write(mk_write(7'd5, 24'h02A00B)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Slot4 RC_Tx exec done", "timeout"); + + tb_assert(o_RC_T27 === 1'b1, "RC_T27=1 (RC_Tx[5])", "RC_T27 mismatch"); + tb_assert(o_RC_T28 === 1'b0, "RC_T28=0 (RC_Tx[4])", "RC_T28 mismatch"); + tb_assert(o_RC_T29 === 1'b1, "RC_T29=1 (RC_Tx[3])", "RC_T29 mismatch"); + tb_assert(o_RC_T30 === 1'b0, "RC_T30=0 (RC_Tx[2])", "RC_T30 mismatch"); + tb_assert(o_RC_T31 === 1'b1, "RC_T31=1 (RC_Tx[1])", "RC_T31 mismatch"); + tb_assert(o_RC_T32 === 1'b0, "RC_T32=0 (RC_Tx[0])", "RC_T32 mismatch"); + + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Test Group 7: Error conditions + ////========================================================================== + task test_error_conditions; + reg [1:0] done_r; + reg [31:0] rdata; + begin + $display(""); + $display("-------------------------------------------------------------"); + $display(" Group 7: Error conditions"); + $display("-------------------------------------------------------------"); + + // 7a. Short SPI transaction (16 bits) + $display(" Error 7a: Short SPI transaction (16 bits)"); + i_cs = 1'b0; + @(negedge i_sclk); + @(negedge i_sclk); + for (integer bi = 0; bi < 16; bi = bi + 1) begin + i_mosi = 1'b0; + @(posedge i_sclk); + @(negedge i_sclk); + end + i_cs = 1'b1; + @(negedge i_sclk); + #(`SYS_CLK_PERIOD * 5); + tb_assert(o_err === 1'b1, + "o_err HIGH after short SPI transaction", ""); + i_rst_n = 1'b0; + #(`SYS_CLK_PERIOD * 4); + i_rst_n = 1'b1; + #(`SYS_CLK_PERIOD * 4); + tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared"); + + // 7b. Write to IDENT register (ADDR 0, read-only) + $display(" Error 7b: Write to IDENT register (ADDR 0)"); + spi_write(mk_write(7'd0, 24'hDEADBEE >> 8)); + @(negedge i_sclk); + tb_assert(o_err === 1'b1, + "o_err HIGH after write to IDENT register", ""); + i_rst_n = 1'b0; + #(`SYS_CLK_PERIOD * 4); + i_rst_n = 1'b1; + #(`SYS_CLK_PERIOD * 4); + tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared"); + + #(`SPI_CLK_PERIOD); + + // 7c. Read out-of-bounds address (ADDR 16) + $display(" Error 7c: Read out-of-bounds address (ADDR 16)"); + spi_read(mk_read(7'd16), rdata); + @(negedge i_sclk); + #(`SYS_CLK_PERIOD * 5); + tb_assert(o_err === 1'b1, + "o_err HIGH after reading ADDR 16", ""); + i_rst_n = 1'b0; + #(`SYS_CLK_PERIOD * 4); + i_rst_n = 1'b1; + #(`SYS_CLK_PERIOD * 4); + tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared"); + + #(`SPI_CLK_PERIOD); + + // 7d. Multiple slot enables (en_t > 1) + $display(" Error 7d: Multiple slot enable bits"); + spi_write(mk_write(7'd2, 24'h000005)); + @(negedge i_sclk); + spi_write(mk_write(7'd3, 24'h000006)); + @(negedge i_sclk); + spi_write(mk_write(7'd1, 24'h000001)); + @(negedge i_sclk); + wait_con_done(500, done_r); + tb_assert(done_r === 1'b1, "Execution completes (even with error)", ""); + tb_assert(o_err === 1'b1, + "o_err HIGH with multiple slot enables", ""); + i_rst_n = 1'b0; + #(`SYS_CLK_PERIOD * 4); + i_rst_n = 1'b1; + #(`SYS_CLK_PERIOD * 4); + tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared"); + + #(`SPI_CLK_PERIOD); + + // 7e. Write to out-of-bounds address (ADDR 31) + $display(" Error 7e: Write to out-of-bounds address (ADDR 31)"); + spi_write(mk_write(7'd31, 24'h123456)); + @(negedge i_sclk); + #(`SYS_CLK_PERIOD * 5); + tb_assert(o_err === 1'b1, + "o_err HIGH after writing ADDR 31", ""); + i_rst_n = 1'b0; + #(`SYS_CLK_PERIOD * 4); + i_rst_n = 1'b1; + #(`SYS_CLK_PERIOD * 4); + tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared"); + + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Test Group 8: Edge cases + ////========================================================================== + task test_edge_cases; + reg [31:0] rdata; + begin + $display(""); + $display("-------------------------------------------------------------"); + $display(" Group 8: Edge cases"); + $display("-------------------------------------------------------------"); + + // 8a. Brief CS pulse (too short for 32-bit) + $display(" Edge 8a: Brief CS pulse"); + i_cs = 1'b0; + @(negedge i_sclk); + @(negedge i_sclk); + i_cs = 1'b1; + @(negedge i_sclk); + #(`SYS_CLK_PERIOD * 5); + tb_assert(o_err === 1'b1, + "o_err detected brief CS pulse", ""); + i_rst_n = 1'b0; + #(`SYS_CLK_PERIOD * 4); + i_rst_n = 1'b1; + #(`SYS_CLK_PERIOD * 4); + tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared"); + + #(`SPI_CLK_PERIOD); + + // 8b. Rapid successive SPI writes + $display(" Edge 8b: Rapid successive SPI writes"); + spi_write(mk_write(7'd2, 24'h000001)); + spi_write(mk_write(7'd3, 24'h000002)); + spi_write(mk_write(7'd4, 24'h000003)); + spi_write(mk_write(7'd5, 24'h000004)); + @(negedge i_sclk); + spi_read(mk_read(7'd2), rdata); + tb_assert(rdata === 24'h000001, "Rapid write: ADDR 2 correct", "ADDR 2 mismatch"); + spi_read(mk_read(7'd3), rdata); + tb_assert(rdata === 24'h000002, "Rapid write: ADDR 3 correct", "ADDR 3 mismatch"); + spi_read(mk_read(7'd4), rdata); + tb_assert(rdata === 24'h000003, "Rapid write: ADDR 4 correct", "ADDR 4 mismatch"); + spi_read(mk_read(7'd5), rdata); + tb_assert(rdata === 24'h000004, "Rapid write: ADDR 5 correct", "ADDR 5 mismatch"); + + #(`SPI_CLK_PERIOD); + + // 8c. Write to reserved registers (ADDR 10-15) - no error + $display(" Edge 8c: Write to reserved registers"); + spi_write(mk_write(7'd10, 24'hABCDEF)); + @(negedge i_sclk); + spi_write(mk_write(7'd15, 24'h123456)); + @(negedge i_sclk); + tb_assert(o_err === 1'b0, "No error writing to reserved ADDR 10 and 15", + "Unexpected error"); + + #(`SPI_CLK_PERIOD * 2); + end + endtask + + + ////========================================================================== + // Summary + ////========================================================================== + task print_summary; + begin + $display(""); + $display("============================================================="); + $display(" Test Summary"); + $display("============================================================="); + $display(" Total tests: %0d", test_pass + test_fail); + $display(" Passed: %0d", test_pass); + $display(" Failed: %0d", test_fail); + $display("============================================================="); + if (test_fail == 0) begin + $display(" *** ALL TESTS PASSED ***"); + end else begin + $display(" *** SOME TESTS FAILED - CHECK DESIGN ***"); + end + $display("============================================================="); + $display(""); + end + endtask + +endmodule diff --git a/2.FW/CPLD1/tb_RelayConTop/source_files.lst b/2.FW/CPLD1/tb_RelayConTop/source_files.lst index 8390a54..34fa918 100644 --- a/2.FW/CPLD1/tb_RelayConTop/source_files.lst +++ b/2.FW/CPLD1/tb_RelayConTop/source_files.lst @@ -1,5 +1,2 @@ -"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/CPLD_Freq_Con.v=work," -"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/Reg_file.v=work," -"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/BUS_Con.v=work," -"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/RelayConTop.v=work," -"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/tb_RelayConTop.sv=work," +"/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv=work,System Verilog" +"/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v=work,Verilog 2001" diff --git a/2.FW/CPLD2/.spreadsheet_view.ini b/2.FW/CPLD2/.spreadsheet_view.ini index 276d124..1aad265 100644 --- a/2.FW/CPLD2/.spreadsheet_view.ini +++ b/2.FW/CPLD2/.spreadsheet_view.ini @@ -3,10 +3,10 @@ pin_sort_type=0 pin_sort_ascending=true sig_sort_type=0 sig_sort_ascending=true -active_Sheet=Global Preferences +active_Sheet=Port Assignments [Port%20Assignments] -Name="176,0" +Name="216,0" Group%20By="118,1" Pin="71,2" BANK="91,3" @@ -65,7 +65,7 @@ Prioritize="100,ELLIPSIS" [Timing%20Preferences] Preference%20Name="146,ELLIPSIS" Preference%20Value="143,ELLIPSIS" -Preference%20Unit="1122,ELLIPSIS" +Preference%20Unit="133,ELLIPSIS" [Group] Group%20Type\Name="153,ELLIPSIS" diff --git a/2.FW/CPLD2/CPLD_Con.v b/2.FW/CPLD2/CPLD_Con.v index 701bc69..ac34a8b 100644 --- a/2.FW/CPLD2/CPLD_Con.v +++ b/2.FW/CPLD2/CPLD_Con.v @@ -2,32 +2,61 @@ module CPLD_Con ( input i_sys_clk, input i_rst_n, input i_con_exec, + +// Freq Relay Control input [23:0]i_freq_relay1, input [23:0]i_freq_relay2, input [23:0]i_freq_relay3, input [23:0]i_freq_relay4, - output o_con_done, + +// DC related Control + input [23:0]i_DC_Con1, + input [23:0]i_DC_Con2, + input [23:0]i_DC_Con3, + input [23:0]i_DC_Con4, + +//Output RELAYs output [7:0]o_RC_F, //Ref: Schematic output [15:0]o_RC_S, output [31:0]o_RC_T, output [3:0] o_OC_x09, - output [3:0] o_OC_x25 + output [3:0] o_OC_x25, + + output [31:0]o_PMU_OC_1 , + output [31:0]o_PMU_OC_2 , + output [31:0]o_PMU_OC_3 , + output [31:0]o_PMU_OC_4, + +//Output FLAGs + output o_err, + output o_con_done ); //Output Relay Reg reg [3:0] OC_x09; reg [3:0] OC_x25; + //Condition Tester + reg [15:0]en_t ; + reg freq_t; + reg dc_t; + //Relay Reg reg [7:0]relay_l1; reg [15:0]relay_l2 ; reg [31:0]relay_l3 ; + reg [31:0]PMU_OC_1 ; + reg [31:0]PMU_OC_2 ; + reg [31:0]PMU_OC_3 ; + reg [31:0]PMU_OC_4 ; + //Flags reg exec_done_flag; reg exec_flag; - reg [3:0]slot_exec_flag; + reg [3:0]freq_slot_flag; + reg [3:0]dc_slot_flag ; reg err_flag; //Counter @@ -52,6 +81,21 @@ module CPLD_Con ( end end + //Function Identify + always @(posedge i_sys_clk) begin + if (i_rst_n == 1'b0) begin + en_t <= 'd0; + freq_t <= 'd0; + dc_t <= 'd0; + end + else begin + en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] ); + freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]; + dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0]; + end + end + +// Main Controller Function always @(posedge i_sys_clk) begin if (i_rst_n == 1'b0) begin relay_l1 <= 'd0; @@ -59,125 +103,207 @@ module CPLD_Con ( relay_l3 <= 'd0; exec_flag <= 1'b0; exec_done_flag <= 1'b1; - slot_exec_flag <= 'd0; + freq_slot_flag <= 'd0; + dc_slot_flag<='d0; err_flag <= 'd0; end else begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin - exec_done_flag <= 'd0; - exec_flag <= 1'b1; //To DO: More Sanity Check? - // Add the bits together. Verilog handles the width expansion automatically for the comparison. - if ( (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) > 2'd1 ) begin + if (en_t > 'd1) begin //Only ONE Enable bit should be set! err_flag <= 1'b1; end else begin - slot_exec_flag[0] <= i_freq_relay1[0]; - slot_exec_flag[1] <= i_freq_relay2[0]; - slot_exec_flag[2] <= i_freq_relay3[0]; - slot_exec_flag[3] <= i_freq_relay4[0]; + exec_done_flag <= 'd0; + exec_flag <= 1'b1; + + freq_slot_flag[0] <= i_freq_relay1[0]; + freq_slot_flag[1] <= i_freq_relay2[0]; + freq_slot_flag[2] <= i_freq_relay3[0]; + freq_slot_flag[3] <= i_freq_relay4[0]; + + dc_slot_flag[0] <= i_DC_Con1[0]; + dc_slot_flag[1] <= i_DC_Con2[0]; + dc_slot_flag[2] <= i_DC_Con3[0]; + dc_slot_flag[3] <= i_DC_Con4[0]; end end else if (exec_flag == 1'b1) begin //Output Relay - case (slot_exec_flag) - 4'b0001: begin - relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]}; - if (delay_cnt == 'd500) begin - relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]}; + if (freq_t == 1'b1) begin + case (freq_slot_flag) + 4'b0001: begin + relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]}; + if (delay_cnt == 'd500) begin + relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]}; + end + else if (delay_cnt == 'd1000) begin + relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]}; + end + else if (delay_cnt == 'd1080) begin + exec_flag <= 'd0; + exec_done_flag <= 1'b1; + end + if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin + OC_x09 <= 4'b0001; + end + else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin + OC_x25 <= 4'b0001; + end + else begin + OC_x09 <= 'd0; + OC_x25 <= 'd0; + end end - else if (delay_cnt == 'd1000) begin - relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]}; + 4'b0010: begin + relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0}; + if (delay_cnt == 'd500) begin + relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0}; + end + else if (delay_cnt == 'd1000) begin + relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0}; + end + else if (delay_cnt == 'd1080) begin + exec_flag <= 'd0; + exec_done_flag <= 1'b1; + end + if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin + OC_x09 <= 4'b0010; + end + else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin + OC_x25 <= 4'b0010; + end + else begin + OC_x09 <= 'd0; + OC_x25 <= 'd0; + end end - else if (delay_cnt == 'd1080) begin + 4'b0100: begin + relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0}; + if (delay_cnt == 'd500) begin + relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0}; + end + else if (delay_cnt == 'd1000) begin + relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0}; + end + else if (delay_cnt == 'd1080) begin + exec_flag <= 'd0; + exec_done_flag <= 1'b1; + end + if ((freq_relay3 > 64) &(freq_relay3 <73)) begin + OC_x09 <= 4'b0100; + end + else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin + OC_x25 <= 4'b0100; + end + else begin + OC_x09 <= 'd0; + OC_x25 <= 'd0; + end + end + 4'b1000: begin + relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0}; + if (delay_cnt == 'd500) begin + relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0}; + end + else if (delay_cnt == 'd1000) begin + relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0}; + end + else if (delay_cnt == 'd1080) begin + exec_flag <= 'd0; + exec_done_flag <= 1'b1; + end + if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin + OC_x09 <= 4'b1000; + end + else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin + OC_x25 <= 4'b1000; + end + else begin + OC_x09 <= 'd0; + OC_x25 <= 'd0; + end + end + default: begin + OC_x09 <= 4'b0000; + OC_x25 <= 4'b0000; + end + endcase + end + else if (dc_t == 1'b1) begin + case (dc_slot_flag) + 4'b0001: begin + //Sanity Check + if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin + err_flag <= 1'b1; + end + else begin + if (i_DC_Con1[23] == 1'b0) begin //Select PMU + PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8); + end + else if (i_DC_Con1[23] == 1'b1) begin //Select DPS + + end + end exec_flag <= 'd0; exec_done_flag <= 1'b1; end - if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin - OC_x09 <= 4'b0001; - end - else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin - OC_x25 <= 4'b0001; - end - else begin - OC_x09 <= 'd0; - OC_x25 <= 'd0; - end - end - 4'b0010: begin - relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0}; - if (delay_cnt == 'd500) begin - relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0}; - end - else if (delay_cnt == 'd1000) begin - relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0}; - end - else if (delay_cnt == 'd1080) begin + 4'b0010: begin + //Sanity Check + if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin + err_flag <= 1'b1; + end + else begin + if (i_DC_Con2[23] == 1'b0) begin //Select PMU + PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8); + end + else if (i_DC_Con2[23] == 1'b1) begin //Select DPS + + end + end exec_flag <= 'd0; exec_done_flag <= 1'b1; end - if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin - OC_x09 <= 4'b0010; - end - else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin - OC_x25 <= 4'b0010; - end - else begin - OC_x09 <= 'd0; - OC_x25 <= 'd0; - end - end - 4'b0100: begin - relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0}; - if (delay_cnt == 'd500) begin - relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0}; - end - else if (delay_cnt == 'd1000) begin - relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0}; - end - else if (delay_cnt == 'd1080) begin + 4'b0100:begin + //Sanity Check + if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin + err_flag <= 1'b1; + end + else begin + if (i_DC_Con3[23] == 1'b0) begin //Select PMU + PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8); + end + else if (i_DC_Con3[23] == 1'b1) begin //Select DPS + + end + end exec_flag <= 'd0; exec_done_flag <= 1'b1; end - if ((freq_relay3 > 64) &(freq_relay3 <73)) begin - OC_x09 <= 4'b0100; - end - else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin - OC_x25 <= 4'b0100; - end - else begin - OC_x09 <= 'd0; - OC_x25 <= 'd0; - end - end - 4'b1000: begin - relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0}; - if (delay_cnt == 'd500) begin - relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0}; - end - else if (delay_cnt == 'd1000) begin - relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0}; - end - else if (delay_cnt == 'd1080) begin + 4'b1000:begin + //Sanity Check + if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin + err_flag <= 1'b1; + end + else begin + if (i_DC_Con4[23] == 1'b0) begin //Select PMU + PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8); + end + else if (i_DC_Con4[23] == 1'b1) begin //Select DPS + + end + end exec_flag <= 'd0; exec_done_flag <= 1'b1; end - if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin - OC_x09 <= 4'b1000; + default:begin // You Should NOT be HERE + PMU_OC_1 <= 'd0 ; + PMU_OC_2 <= 'd0 ; + PMU_OC_3 <= 'd0 ; + PMU_OC_4 <= 'd0 ; end - else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin - OC_x25 <= 4'b1000; - end - else begin - OC_x09 <= 'd0; - OC_x25 <= 'd0; - end - end - default: begin - OC_x09 <= 4'b0000; - OC_x25 <= 4'b0000; - end - endcase + endcase + end end end end @@ -189,4 +315,11 @@ module CPLD_Con ( assign o_OC_x09 = OC_x09; assign o_OC_x25 = OC_x25; + assign o_PMU_OC_1 = PMU_OC_1; + assign o_PMU_OC_2 = PMU_OC_2; + assign o_PMU_OC_3 = PMU_OC_3; + assign o_PMU_OC_4 = PMU_OC_4; + + assign o_err = err_flag; + endmodule \ No newline at end of file diff --git a/2.FW/CPLD2/NewExtIns_CPLD2.ldf b/2.FW/CPLD2/NewExtIns_CPLD2.ldf index f192cb0..311daa7 100644 --- a/2.FW/CPLD2/NewExtIns_CPLD2.ldf +++ b/2.FW/CPLD2/NewExtIns_CPLD2.ldf @@ -2,7 +2,7 @@ - + diff --git a/2.FW/CPLD2/NewExtIns_CPLD2.lpf b/2.FW/CPLD2/NewExtIns_CPLD2.lpf index f6391ed..524b088 100644 --- a/2.FW/CPLD2/NewExtIns_CPLD2.lpf +++ b/2.FW/CPLD2/NewExtIns_CPLD2.lpf @@ -1,4 +1,4 @@ -rvl_alias "i_sys_clk" "i_sys_clk"; +RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; @@ -11,12 +11,12 @@ LOCATE COMP "i_rst_n" SITE "Y14" ; LOCATE COMP "i_sclk" SITE "AA16" ; LOCATE COMP "i_cs" SITE "Y15" ; LOCATE COMP "i_mosi" SITE "AB12" ; -//LOCATE COMP "o_RC_T[26]" SITE "U13" ; -//LOCATE COMP "o_RC_T[27]" SITE "U12" ; -//LOCATE COMP "o_RC_T[28]" SITE "T12" ; -//LOCATE COMP "o_RC_T[29]" SITE "T11" ; -//LOCATE COMP "o_RC_T[30]" SITE "U11" ; -//LOCATE COMP "o_RC_T[31]" SITE "V11" ; +//LOCATE COMP "o_RC_T[26]" SITE "U13" ; +//LOCATE COMP "o_RC_T[27]" SITE "U12" ; +//LOCATE COMP "o_RC_T[28]" SITE "T12" ; +//LOCATE COMP "o_RC_T[29]" SITE "T11" ; +//LOCATE COMP "o_RC_T[30]" SITE "U11" ; +//LOCATE COMP "o_RC_T[31]" SITE "V11" ; IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ; IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ; @@ -127,196 +127,197 @@ LOCATE COMP "o_RC_T[23]" SITE "U15" ; LOCATE COMP "o_RC_T[24]" SITE "T13" ; LOCATE COMP "o_RC_T[25]" SITE "AA13" ; LOCATE COMP "o_err" SITE "AB16" ; -IOBUF PORT "o_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_OC_1[8]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_OC_2[8]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_OC_3[8]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_OC_4[8]" IO_TYPE=LVCMOS33 ; -LOCATE COMP "o_OC_1[8]" SITE "D14" ; -LOCATE COMP "o_OC_1[9]" SITE "G13" ; -LOCATE COMP "o_OC_1[10]" SITE "C13" ; -LOCATE COMP "o_OC_1[11]" SITE "F13" ; -LOCATE COMP "o_OC_1[12]" SITE "C17" ; -LOCATE COMP "o_OC_1[13]" SITE "F17" ; -LOCATE COMP "o_OC_1[14]" SITE "D17" ; -LOCATE COMP "o_OC_1[15]" SITE "E17" ; -LOCATE COMP "o_OC_1[24]" SITE "N5" ; -LOCATE COMP "o_OC_1[25]" SITE "D15" ; -LOCATE COMP "o_OC_1[26]" SITE "P3" ; -LOCATE COMP "o_OC_1[27]" SITE "M4" ; -LOCATE COMP "o_OC_1[28]" SITE "R6" ; -LOCATE COMP "o_OC_1[29]" SITE "T5" ; -LOCATE COMP "o_OC_1[30]" SITE "P6" ; -LOCATE COMP "o_OC_1[31]" SITE "U4" ; -LOCATE COMP "o_OC_2[8]" SITE "C1" ; -LOCATE COMP "o_OC_2[9]" SITE "C2" ; -LOCATE COMP "o_OC_2[10]" SITE "C3" ; -LOCATE COMP "o_OC_2[11]" SITE "B1" ; -LOCATE COMP "o_OC_2[12]" SITE "H5" ; -LOCATE COMP "o_OC_2[13]" SITE "H6" ; -LOCATE COMP "o_OC_2[14]" SITE "H2" ; -LOCATE COMP "o_OC_2[15]" SITE "H3" ; -LOCATE COMP "o_OC_2[24]" SITE "T7" ; -LOCATE COMP "o_OC_2[25]" SITE "U5" ; -LOCATE COMP "o_OC_2[26]" SITE "W5" ; -LOCATE COMP "o_OC_2[27]" SITE "T6" ; -LOCATE COMP "o_OC_2[28]" SITE "E8" ; -LOCATE COMP "o_OC_2[29]" SITE "E9" ; -LOCATE COMP "o_OC_2[30]" SITE "E10" ; -LOCATE COMP "o_OC_2[31]" SITE "D11" ; -LOCATE COMP "o_OC_3[8]" SITE "A11" ; -LOCATE COMP "o_OC_3[9]" SITE "A12" ; -LOCATE COMP "o_OC_3[10]" SITE "B12" ; -LOCATE COMP "o_OC_3[11]" SITE "A13" ; -LOCATE COMP "o_OC_3[12]" SITE "B19" ; -LOCATE COMP "o_OC_3[13]" SITE "C18" ; -LOCATE COMP "o_OC_3[14]" SITE "A17" ; -LOCATE COMP "o_OC_3[15]" SITE "B16" ; -LOCATE COMP "o_OC_3[24]" SITE "B13" ; -LOCATE COMP "o_OC_3[25]" SITE "B14" ; -LOCATE COMP "o_OC_3[26]" SITE "B15" ; -LOCATE COMP "o_OC_3[27]" SITE "C15" ; -LOCATE COMP "o_OC_3[28]" SITE "G21" ; -LOCATE COMP "o_OC_3[29]" SITE "E22" ; -LOCATE COMP "o_OC_3[30]" SITE "E20" ; -LOCATE COMP "o_OC_3[31]" SITE "D21" ; -LOCATE COMP "o_OC_4[8]" SITE "G1" ; -LOCATE COMP "o_OC_4[9]" SITE "G2" ; -LOCATE COMP "o_OC_4[10]" SITE "G3" ; -LOCATE COMP "o_OC_4[11]" SITE "F1" ; -LOCATE COMP "o_OC_4[12]" SITE "C4" ; -LOCATE COMP "o_OC_4[13]" SITE "C5" ; -LOCATE COMP "o_OC_4[14]" SITE "G11" ; -LOCATE COMP "o_OC_4[15]" SITE "E11" ; -LOCATE COMP "o_OC_4[24]" SITE "E1" ; -LOCATE COMP "o_OC_4[25]" SITE "D1" ; -LOCATE COMP "o_OC_4[26]" SITE "E2" ; -LOCATE COMP "o_OC_4[27]" SITE "D3" ; -LOCATE COMP "o_OC_4[28]" SITE "C11" ; -LOCATE COMP "o_OC_4[29]" SITE "A2" ; -LOCATE COMP "o_OC_4[30]" SITE "B3" ; -LOCATE COMP "o_OC_4[31]" SITE "A3" ; +IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_2[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_3[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[16]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[17]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[18]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[19]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[20]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[21]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[22]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[23]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[24]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[25]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[26]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[27]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[28]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[29]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[30]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_4[31]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 ; +LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ; +LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ; +LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ; +LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ; +LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ; +LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ; +LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ; +LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ; +LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ; +LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ; +LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ; +LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ; +LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ; +LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ; +LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ; +LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ; +LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ; +LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ; +LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ; +LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ; +LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ; +LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ; +LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ; +LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ; +LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ; +LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ; +LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ; +LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ; +LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ; +LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ; +LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ; +LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ; +LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ; +LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ; +LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ; +LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ; +LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ; +LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ; +LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ; +LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ; +LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ; +LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ; +LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ; +LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ; +LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ; +LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ; +LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ; +LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ; +LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ; +LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ; +LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ; +LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ; +LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ; +LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ; +LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ; +LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ; +LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ; +LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ; +LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ; +LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ; +LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ; +LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ; +LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ; +LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ; USE PRIMARY NET "i_sys_clk_c" ; +IOBUF PORT "o_rvalid" IO_TYPE=LVCMOS33 ; diff --git a/2.FW/CPLD2/Reg_file.v b/2.FW/CPLD2/Reg_file.v index e26cb6a..bfef5af 100644 --- a/2.FW/CPLD2/Reg_file.v +++ b/2.FW/CPLD2/Reg_file.v @@ -21,13 +21,19 @@ module Reg_file ( output [23:0] o_freq1, output [23:0] o_freq2, output [23:0] o_freq3, - output [23:0] o_freq4 + output [23:0] o_freq4, + + //DC Regs + output [23:0] o_DC1, + output [23:0] o_DC2, + output [23:0] o_DC3, + output [23:0] o_DC4 ); // --- Parameters --- localparam REG_COUNT = 16; localparam [23:0] - IDENT = 24'h400000 | 12'b0001_0000_0000, //CPLD2==1,version=1.0.0 + IDENT = 24'h400000 | 12'b0001_0001_0000, //CPLD2==1,version=1.1.0 STATE_INIT = 24'h800000; // State Machine Definition @@ -163,5 +169,9 @@ module Reg_file ( assign o_freq2 = regtable[3]; assign o_freq3 = regtable[4]; assign o_freq4 = regtable[5]; + assign o_DC1 = regtable[6]; + assign o_DC2 = regtable[7]; + assign o_DC3 = regtable[8]; + assign o_DC4 = regtable[9]; endmodule \ No newline at end of file diff --git a/2.FW/CPLD2/RelayConTop.v b/2.FW/CPLD2/RelayConTop.v index a8f3b7c..51785b1 100644 --- a/2.FW/CPLD2/RelayConTop.v +++ b/2.FW/CPLD2/RelayConTop.v @@ -16,10 +16,10 @@ module RelayConTop ( output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1) //output [3:0] o_OC_x09, //output [3:0] o_OC_x25, - output [31:0]o_OC_1, - output [31:0]o_OC_2, - output [31:0]o_OC_3, - output [31:0]o_OC_4 + output [31:0]o_PMU_OC_1 , + output [31:0]o_PMU_OC_2 , + output [31:0]o_PMU_OC_3 , + output [31:0]o_PMU_OC_4 ); wire [7:0] RC_F; @@ -37,12 +37,26 @@ module RelayConTop ( wire wr_flag; //1=write,0=read wire bus_err_flag; wire reg_err_flag; + wire cpld_err_flag; wire con_exec; wire [23:0]freq1_relay ; wire [23:0]freq2_relay ; wire [23:0]freq3_relay ; wire [23:0]freq4_relay ; + + //DC Control Reg output + wire [23:0]DC_Con1 ; + wire [23:0]DC_Con2 ; + wire [23:0]DC_Con3 ; + wire [23:0]DC_Con4 ; + + //PMU OC Control + wire [31:0]PMU_OC_1 ; + wire [31:0]PMU_OC_2 ; + wire [31:0]PMU_OC_3 ; + wire [31:0]PMU_OC_4 ; + wire con_rvalid; wire con_done; @@ -79,6 +93,10 @@ module RelayConTop ( .o_freq2(freq2_relay), //Freq_Slot2 .o_freq3(freq3_relay), //Freq_Slot3 .o_freq4(freq4_relay), //Freq_Slot4 + .o_DC1(DC_Con1), + .o_DC2(DC_Con2), + .o_DC3(DC_Con3), + .o_DC4(DC_Con4), .o_rvalid(con_rvalid), .o_rdata(r_data), .o_exec(con_exec), //Exec cmd @@ -94,12 +112,21 @@ module RelayConTop ( .i_freq_relay2(freq2_relay), .i_freq_relay3(freq3_relay), .i_freq_relay4(freq4_relay), + .i_DC_Con1(DC_Con1), + .i_DC_Con2(DC_Con2), + .i_DC_Con3(DC_Con3), + .i_DC_Con4(DC_Con4), + .o_PMU_OC_1(PMU_OC_1), + .o_PMU_OC_2(PMU_OC_2), + .o_PMU_OC_3(PMU_OC_3), + .o_PMU_OC_4(PMU_OC_4), .o_con_done(con_done), .o_RC_F(RC_F), .o_RC_S(RC_S), .o_RC_T(RC_T), .o_OC_x09(OC_x09), - .o_OC_x25(OC_x25) + .o_OC_x25(OC_x25), + .o_err(cpld_err_flag) ); @@ -107,10 +134,32 @@ module RelayConTop ( assign o_RC_S = RC_S; assign o_RC_T = RC_T[25:0]; - //assign o_OC_1[8] = OC_x09[0]; - //assign o_OC_2[8] = OC_x09[1]; - //assign o_OC_3[8] = OC_x09[2]; - //assign o_OC_4[8] = OC_x09[3]; + assign o_PMU_OC_1[8] = OC_x09[0]; + assign o_PMU_OC_2[8] = OC_x09[1]; + assign o_PMU_OC_3[8] = OC_x09[2]; + assign o_PMU_OC_4[8] = OC_x09[3]; + + assign o_PMU_OC_1[24] = OC_x25[0]; + assign o_PMU_OC_2[24] = OC_x25[1]; + assign o_PMU_OC_3[24] = OC_x25[2]; + assign o_PMU_OC_4[24] = OC_x25[3]; + + assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0]; + assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8]; + assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25]; + + assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0]; + assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9]; + assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25]; + + assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0]; + assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9]; + assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25]; + + assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0]; + assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9]; + assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25]; + assign o_err = bus_err_flag || reg_err_flag;