Bug fix & CPLD2 PMU implementation
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@@ -16,10 +16,10 @@ module RelayConTop (
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output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1)
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//output [3:0] o_OC_x09,
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//output [3:0] o_OC_x25,
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output [31:0]o_OC_1,
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output [31:0]o_OC_2,
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output [31:0]o_OC_3,
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output [31:0]o_OC_4
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output [31:0]o_PMU_OC_1 ,
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output [31:0]o_PMU_OC_2 ,
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output [31:0]o_PMU_OC_3 ,
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output [31:0]o_PMU_OC_4
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);
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wire [7:0] RC_F;
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@@ -37,12 +37,26 @@ module RelayConTop (
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wire wr_flag; //1=write,0=read
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wire bus_err_flag;
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wire reg_err_flag;
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wire cpld_err_flag;
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wire con_exec;
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wire [23:0]freq1_relay ;
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wire [23:0]freq2_relay ;
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wire [23:0]freq3_relay ;
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wire [23:0]freq4_relay ;
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//DC Control Reg output
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wire [23:0]DC_Con1 ;
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wire [23:0]DC_Con2 ;
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wire [23:0]DC_Con3 ;
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wire [23:0]DC_Con4 ;
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//PMU OC Control
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wire [31:0]PMU_OC_1 ;
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wire [31:0]PMU_OC_2 ;
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wire [31:0]PMU_OC_3 ;
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wire [31:0]PMU_OC_4 ;
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wire con_rvalid;
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wire con_done;
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@@ -79,6 +93,10 @@ module RelayConTop (
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.o_freq2(freq2_relay), //Freq_Slot2
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.o_freq3(freq3_relay), //Freq_Slot3
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.o_freq4(freq4_relay), //Freq_Slot4
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.o_DC1(DC_Con1),
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.o_DC2(DC_Con2),
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.o_DC3(DC_Con3),
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.o_DC4(DC_Con4),
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.o_rvalid(con_rvalid),
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.o_rdata(r_data),
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.o_exec(con_exec), //Exec cmd
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@@ -94,12 +112,21 @@ module RelayConTop (
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.i_freq_relay2(freq2_relay),
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.i_freq_relay3(freq3_relay),
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.i_freq_relay4(freq4_relay),
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.i_DC_Con1(DC_Con1),
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.i_DC_Con2(DC_Con2),
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.i_DC_Con3(DC_Con3),
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.i_DC_Con4(DC_Con4),
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.o_PMU_OC_1(PMU_OC_1),
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.o_PMU_OC_2(PMU_OC_2),
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.o_PMU_OC_3(PMU_OC_3),
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.o_PMU_OC_4(PMU_OC_4),
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.o_con_done(con_done),
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.o_RC_F(RC_F),
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.o_RC_S(RC_S),
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.o_RC_T(RC_T),
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.o_OC_x09(OC_x09),
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.o_OC_x25(OC_x25)
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.o_OC_x25(OC_x25),
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.o_err(cpld_err_flag)
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);
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@@ -107,10 +134,32 @@ module RelayConTop (
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assign o_RC_S = RC_S;
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assign o_RC_T = RC_T[25:0];
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//assign o_OC_1[8] = OC_x09[0];
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//assign o_OC_2[8] = OC_x09[1];
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//assign o_OC_3[8] = OC_x09[2];
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//assign o_OC_4[8] = OC_x09[3];
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assign o_PMU_OC_1[8] = OC_x09[0];
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assign o_PMU_OC_2[8] = OC_x09[1];
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assign o_PMU_OC_3[8] = OC_x09[2];
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assign o_PMU_OC_4[8] = OC_x09[3];
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assign o_PMU_OC_1[24] = OC_x25[0];
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assign o_PMU_OC_2[24] = OC_x25[1];
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assign o_PMU_OC_3[24] = OC_x25[2];
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assign o_PMU_OC_4[24] = OC_x25[3];
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assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
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assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
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assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
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assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
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assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
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assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
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assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
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assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
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assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
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assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
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assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
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assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
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assign o_err = bus_err_flag || reg_err_flag;
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