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Bug fix & CPLD2 PMU implementation

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This commit is contained in:
Jeremy Shen
2026-05-21 17:15:14 +08:00
parent 13611d20a0
commit 7f43729caf
9 changed files with 1373 additions and 585 deletions
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2.FW/CPLD1/tb_RelayConTop/source_files.lst
+2 -5
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@@ -1,5 +1,2 @@
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/CPLD_Freq_Con.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/Reg_file.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/BUS_Con.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/RelayConTop.v=work,"
"D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD1/tb_RelayConTop.sv=work,"
"/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/tb_RelayConTop.sv=work,System Verilog"
"/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/RelayConTop_tf.v=work,Verilog 2001"