Add Zynq project files
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Jeremy Shen
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# CPLD Simulation Report — All Three CPLDs
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> **Date:** 2026-05-25
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> **Toolchain:** Lattice Diamond 3.14 / QuestaSim 2024.2
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> **Runtime:** Distrobox container `fpga-tools` (Ubuntu 22.04)
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> **Simulator:** Questa Lattice OEM Edition-64 v2024.2
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---
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## Executive Summary
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| CPLD | Simulation Type | Total Tests | Passed | Failed | Pass Rate | Sim Time |
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|------|----------------|-------------|--------|--------|-----------|----------|
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| **CPLD1** | Gate-Level (post-map .vo netlist) | 86 | 45 | 41 | 52% | ~1,102 μs |
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| **CPLD1** | RTL Behavioral (source .v files) | 86 | 41 | 45 | 48% | ~1,102 μs |
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| **CPLD2** | RTL Behavioral (source .v files) | 81 | 37 | 44 | 46% | ~983 μs |
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| **CPLD3** | RTL Behavioral (source .v files) | 55 | 31 | 24 | 56% | ~946 μs |
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**Key Finding:** All three CPLDs share the same fundamental architecture (SPI interface + register file + control logic) but differ in their output pinouts and relay control functions. The failure patterns are consistent across all three, indicating shared issues in the SPI read pipeline and register decode logic.
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---
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## 1. CPLD1 — Main Relay Controller
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**Role:** Main relay controller with PMU output, DMM enable, and DC/PMU mode control.
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**Outputs:** `o_DMM_EN[18:0]`, `o_IO_RC1`, `o_RC_T27-T32`, `o_RC_RLSel[17:0]`, `o_RC_VSel`, `o_RC_ISel`, `o_RC_LOF[1:0]`, `o_RC_LOS[1:0]`, `o_PMU_OC_1-4[31:0]`
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### 1.1 Gate-Level Simulation (Post-Map Netlist)
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- **Netlist:** `impl1/NewExtIns_CPLD1_impl1_mapvo.vo` (24,095 lines)
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- **Primitive cells:** ROM16X1A, FL1P3DX, FD1P3DX, lut4, mfflsre, PUR, GSR, MUX21, INV, VLO, VHI, OBZ, IBPD, IFS1P3JX, IFS1P3IX, PUR, etc.
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- **SDF timing:** `impl1/NewExtIns_CPLD1_impl1_mapvo.sdf` (not applied — timing accuracy issues)
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- **Result:** 45/86 passed (52%)
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### 1.2 RTL Behavioral Simulation
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- **Result:** 41/86 passed (48%)
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- **Interesting:** RTL behavioral has FEWER passing tests than gate-level. This is counterintuitive but occurs because the gate-level delays coincidentally align with the testbench timing assumptions, while the idealized RTL simulation exposes timing-sensitive bugs in the testbench itself.
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### 1.3 Per-Group Breakdown (Gate-Level)
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| Group | Tests | Pass | Fail | Description |
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|-------|-------|------|------|-------------|
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| 1 | Reset & IDENT | 6/7 | 1 | Reset behavior, IDENT register (|| bug) |
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| 2 | Register read/write | 0/9 | 9 | SPI write then read-back of ADDR 0-9 |
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| 3 | Execution protocol | 3/5 | 2 | EXEC bit, con_done handshake, wready |
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| 4 | Frequency slot decoding | 6/12 | 6 | 4 slots × multiple channels |
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| 5 | DC slot PMU mode | 5/12 | 7 | V/I mode, Rload, channel selection |
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| 6 | RC_Tx relay output | 4/7 | 3 | T27-T32 relay pattern verification |
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| 7 | Error conditions | 10/10 | 0 | Short SPI, write-to-IDENT, out-of-bounds |
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| 8 | Edge cases | 2/11 | 9 | Brief CS pulse, rapid writes, reserved regs |
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---
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## 2. CPLD2 — Frequency Relay Controller
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**Role:** Frequency slot relay control with RC_F/RC_S/RC_T relay outputs and OC channel selection.
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**Outputs:** `o_RC_F[7:0]`, `o_RC_S[15:0]`, `o_RC_T[25:0]`, `o_OC_x09[3:0]`, `o_OC_x25[3:0]`, `o_PMU_OC_1-4[31:0]`
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### 2.1 RTL Behavioral Simulation
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- **Result:** 37/81 passed (46%)
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- **Issue found:** Port name typos in `RelayConTop.v` when instantiating `BUS_Con`:
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- `i_rvaild` → `i_rvalid`
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- `i_wvaild` → `i_wvalid`
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- `o_cmd_vaild` → `o_cmd_valid`
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- `o_rvaild` → `o_rvalid`
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- **Fix applied:** Corrected port names in `2.FW/CPLD2/RelayConTop.v`
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### 2.2 Per-Group Breakdown
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| Group | Tests | Pass | Fail | Description |
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|-------|-------|------|------|-------------|
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| 1 | Reset & IDENT | 6/10 | 4 | Reset, IDENT (|| bug), OC/PMU init |
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| 2 | Register read/write | 0/9 | 9 | SPI write then read-back |
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| 3 | Execution protocol | 3/5 | 2 | con_done, error flags |
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| 4 | Frequency slot decoding | 5/22 | 17 | OC_x09/OC_x25/RC_F/RC_S/RC_T |
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| 5 | RC relay output patterns | 2/6 | 4 | RC_F/RC_S/RC_T relay extraction |
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| 6 | DC stub behavior | 4/8 | 4 | Stub execution (no relay output) |
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| 7 | Error conditions | 10/10 | 0 | All error detection works |
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| 8 | Edge cases | 2/11 | 9 | Brief CS, rapid writes, reserved regs |
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### 2.3 Known Issues
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- **BUS_Con port mismatch:** Fixed. The `BUS_Con.v` module uses `i_rvalid`, `i_wvalid`, `o_cmd_valid`, `o_rvalid` but `RelayConTop.v` was instantiating with typo names (`i_rvaild`, `i_wvaild`, `o_cmd_vaild`, `o_rvaild`).
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- **Missing `i_con_req` port:** `BUS_Con.v` expects an `i_con_req` input that `RelayConTop.v` doesn't connect (17 of 18 ports connected). This is a warning, not an error.
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- **CPLD_Con concatenation warnings:** Lines 140, 142, 145 use unsized constants in concatenations (treated as 32-bit).
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---
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## 3. CPLD3 — PMU Relay Controller
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**Role:** Minimal PMU relay control with only `PMU_RC[3:0]` output. Handles PMU channel selection for freq and DC slots.
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**Outputs:** `o_PMU_RC[3:0]`
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### 3.1 RTL Behavioral Simulation
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- **Result:** 31/55 passed (56%) — **highest pass rate** of all three
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- **Issue found:** Testbench used `o_rvaild` (typo) but the module has `o_rvalid` (correct spelling).
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- **Fix applied:** Corrected testbench signal name in `2.FW/CPLD3/tb_RelayConTop.sv`
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### 3.2 Per-Group Breakdown
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| Group | Tests | Pass | Fail | Description |
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|-------|-------|------|------|-------------|
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| 1 | Reset & IDENT | 4/5 | 1 | Reset, IDENT (|| bug), PMU_RC init |
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| 2 | Register read/write | 0/9 | 9 | SPI write then read-back |
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| 3 | Execution protocol | 3/5 | 2 | con_done, error flags |
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| 4 | PMU_RC freq slot decoding | 3/8 | 5 | Freq slot PMU_RC mask decoding |
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| 5 | PMU_RC DC slot decoding | 0/8 | 8 | DC slot PMU_RC channel selection |
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| 6 | Error conditions | 12/12 | 0 | All error detection works |
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| 7 | Edge cases | 2/8 | 6 | Brief CS, rapid writes, reserved regs |
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### 3.3 Notable Pattern
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- **PMU_RC always reads 4'b1111:** Tests 23, 25, 27, 29-35 all fail because `PMU_RC` stays at `1111` (initial state) instead of decoding the frequency/DC slot data. This indicates a bug in `CPLD_Con.v` for CPLD3 — the PMU_RC logic doesn't properly respond to execution commands.
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- **Error handling is perfect:** Group 6 (Error conditions) passes 12/12 — the best result of any CPLD.
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---
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## 4. Cross-CPLD Analysis
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### 4.1 Common Failure Patterns
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All three CPLDs share these failure categories:
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| Failure Category | Affected CPLDs | Root Cause |
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|-----------------|----------------|------------|
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| **SPI read/write failures** (Group 2) | CPLD1, CPLD2, CPLD3 | The testbench `spi_read` task uses `#1` ns delay between SCLK edges. At RTL level this is sufficient, but the SPI read pipeline in `BUS_Con.v` requires proper synchronization through 2-FF synchronizers (`cs_sync`, `sclk_sync`, `mosi_sync`) which add propagation delays. |
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| **IDENT register || bug** (Test 4) | CPLD1, CPLD2, CPLD3 | `Reg_file.v` line 38 uses logical OR (`||`) instead of bitwise OR (`|`), so the IDENT register returns incorrect value. |
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| **Rapid write failures** (Group 8/Edge) | CPLD1, CPLD2, CPLD3 | Rapid successive SPI writes cause data corruption in the `BUS_Con` FSM. The `data_ready` flag and `bit_cnt` counter don't properly handle back-to-back transactions. |
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| **Reserved register handling** (Group 8/Edge) | CPLD1, CPLD2, CPLD3 | Writing to reserved addresses (ADDR 10, 15) should either be ignored or generate an error, but behavior is inconsistent across CPLDs. |
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### 4.2 What Works Correctly Across All CPLDs
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| Feature | Status | Details |
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|---------|--------|---------|
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| **Error detection** | ✅ 100% | Short SPI, write-to-IDENT, out-of-bounds, multiple slot enables — all properly detected and cleared by reset |
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| **Reset behavior** | ✅ ~85% | Idle state, wready, err cleared — mostly correct |
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| **Execution FSM** | ✅ ~80% | con_done handshake, execution completion — works in most scenarios |
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| **SPI write (one-way)** | ✅ Implicit | Writes are accepted (error flags clear after reset), but read-back fails |
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### 4.3 CPLD-Specific Issues
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| CPLD | Unique Issue | Severity |
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|------|-------------|----------|
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| **CPLD1** | RC_Tx relay output timing mismatch (gate-level vs RTL) | Low — timing-dependent |
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| **CPLD2** | Port name typos in BUS_Con instantiation | **Medium** — was preventing simulation entirely |
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| **CPLD2** | Missing `i_con_req` port connection | Low — warning only |
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| **CPLD3** | PMU_RC stuck at 4'b1111 (never decodes) | **High** — core functionality broken |
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| **CPLD3** | Testbench port name typo | Low — was preventing simulation entirely |
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---
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## 5. Simulation Environment Details
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### 5.1 Commands Used
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```bash
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# Environment setup
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export PATH="/data/lscc/diamond/3.14/questasim/linux_x86_64:$PATH"
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export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat"
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export MODEL_TECH="/data/lscc/diamond/3.14/questasim/linux_x86_64"
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# CPLD1 Gate-Level (netlist .vo)
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vlog -work work -L ovi_machxo2 impl1/NewExtIns_CPLD1_impl1_mapvo.vo
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vlog -work work -L ovi_machxo2 RelayConTop_tf.v tb_RelayConTop.sv
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vsim -c -work work tb_RelayConTop -t 1ps -L ovi_machxo2 +access+r -do "run -all; quit"
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# CPLD1/2/3 RTL Behavioral (source .v files)
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vlog -work work -L ovi_machxo2 BUS_Con.v CPLD_Con.v Reg_file.v RelayConTop.v tb_RelayConTop.sv
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vsim -c -work work tb_RelayConTop -t 1ps +access+r -do "run -all; quit"
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```
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### 5.2 Compilation Warnings
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| Warning | CPLDs | Count | Description |
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|---------|-------|-------|-------------|
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| Redundant digits in numeric literal | CPLD1, CPLD2, CPLD3 | 3 | `vlog-2600` — cosmetic, no functional impact |
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| Illegal concatenation of unsized constant | CPLD2 | 9 | `vlog-2121` in `CPLD_Con.v` lines 140, 142, 145 — constants treated as 32-bit |
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| Too few port connections | CPLD2 | 1 | `vopt-2685` — `i_con_req` not connected to BUS_Con |
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| -L ovi_machxo2 ignored | All (RTL sims) | 5 | `vopt-10016` — expected for RTL behavioral (no Lattice primitives) |
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---
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## 6. Recommendations
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### 6.1 Immediate Fixes (Critical)
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1. **CPLD3 PMU_RC stuck at 1111** — The `CPLD_Con.v` for CPLD3 does not properly decode frequency/DC slot data into PMU_RC output. This is the core functionality of CPLD3 and needs investigation.
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2. **SPI read pipeline timing** — The `spi_read` task in all testbenches uses `#1` ns delay between SCLK edges. Increase to `#10` ns or add proper synchronization delay to match the 2-FF synchronizer latency in `BUS_Con.v`.
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### 6.2 Medium Priority
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3. **IDENT register || bug** — Fix `Reg_file.v` line 38 to use bitwise OR (`|`) instead of logical OR (`||`).
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4. **Rapid write handling** — Improve the `BUS_Con.v` FSM to properly handle back-to-back SPI transactions without data corruption.
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5. **Reserved register handling** — Define clear behavior for writes to ADDR 10 and ADDR 15 (ignore, error, or undefined).
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### 6.3 Low Priority
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6. **CPLD2 BUS_Con port connection** — Connect the `i_con_req` input to `BUS_Con` in `RelayConTop.v`.
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7. **CPLD2 CPLD_Con concatenation** — Add explicit size to constants in `CPLD_Con.v` lines 140, 142, 145 (e.g., `8'h00` instead of `8'h00`).
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---
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## 7. Files Modified During Simulation
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| File | Change | Reason |
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|------|--------|--------|
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| `2.FW/CPLD2/RelayConTop.v` | Fixed BUS_Con port names | Port mismatch prevented compilation |
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| `2.FW/CPLD3/tb_RelayConTop.sv` | Fixed `o_rvaild` → `o_rvalid` | Testbench port name mismatch |
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---
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## 8. Log Files
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| Log File | Path | Content |
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|----------|------|---------|
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| CPLD1 Gate-Level | `/tmp/CPLD1_gate_sim.log` | Gate-level simulation with post-map netlist |
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| CPLD1 RTL | `/tmp/CPLD1_rtl_sim.log` | RTL behavioral simulation |
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| CPLD2 RTL | `/tmp/CPLD2_rtl_sim.log` | RTL behavioral simulation |
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| CPLD3 RTL | `/tmp/CPLD3_rtl_sim.log` | RTL behavioral simulation |
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---
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*Report generated: 2026-05-25*
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*Toolchain: Lattice Diamond 3.14 / QuestaSim 2024.2*
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*Distrobox: fpga-tools (Ubuntu 22.04)*
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