diff --git a/2.FW/Zynq/proj_cal/Vitis/.analytics b/2.FW/Zynq/proj_cal/Vitis/.analytics
new file mode 100644
index 0000000..f839cb6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/.analytics
@@ -0,0 +1,3 @@
+timestamp=[2026-05-25 09:53:07], mode=WORKBENCH_START, duration=0:00:02.392, duration_ms=2392, data={}
+timestamp=[2026-05-25 09:53:07], mode=WORKBENCH_UI_INIT, duration=0:00:00.181, duration_ms=181, data={editors_count=0, platform_editors_count=0, projects_count=0, platform_projects_count=0, active_platform_editor=false, projects=}
+timestamp=[2026-05-25 09:53:08], mode=PLATFORM_REPOSITORY_INIT, duration=0:00:00.140, duration_ms=140, data={}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/.cproject b/2.FW/Zynq/proj_cal/Vitis/FSBL/.cproject
new file mode 100644
index 0000000..279e023
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/.cproject
@@ -0,0 +1,180 @@
+
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diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/.project b/2.FW/Zynq/proj_cal/Vitis/FSBL/.project
new file mode 100644
index 0000000..a1773cd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/.project
@@ -0,0 +1,33 @@
+
+
+ FSBL
+ Created by SDK v2018.3. FSBL_bsp - ps7_cortexa9_0
+
+ FSBL_bsp
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
+ src/ps7_init.c
+ 1
+ WORKSPACE_LOC/system_wrapper_hw_platform_0/ps7_init.c
+
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/FSBL.elf.size b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/FSBL.elf.size
new file mode 100644
index 0000000..713d4c4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/FSBL.elf.size
@@ -0,0 +1,2 @@
+ text data bss dec hex filename
+ 81496 10160 74712 166368 289e0 FSBL.elf
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/Xilinx.spec b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/Xilinx.spec
new file mode 100644
index 0000000..d7ab17f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/Xilinx.spec
@@ -0,0 +1,2 @@
+*startfile:
+crti%O%s crtbegin%O%s
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/makefile
new file mode 100644
index 0000000..0b346fd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/makefile
@@ -0,0 +1,65 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+ELFSIZE += \
+FSBL.elf.size \
+
+
+# All Target
+all: pre-build main-build
+
+# Main-build Target
+main-build: FSBL.elf secondary-outputs
+
+# Tool invocations
+FSBL.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: ARM v7 gcc linker'
+ arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../FSBL_bsp/ps7_cortexa9_0/lib -o "FSBL.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+FSBL.elf.size: FSBL.elf
+ @echo 'Invoking: ARM v7 Print Size'
+ arm-none-eabi-size FSBL.elf |tee "FSBL.elf.size"
+ @echo 'Finished building: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) $(EXECUTABLES)$(OBJS)$(S_UPPER_DEPS)$(C_DEPS)$(ELFSIZE) FSBL.elf
+ -@echo ' '
+
+pre-build:
+ -a9-linaro-pre-build-step
+ -@echo ' '
+
+secondary-outputs: $(ELFSIZE)
+
+.PHONY: all clean dependents
+.SECONDARY: main-build pre-build
+
+-include ../makefile.targets
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/objects.mk b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/objects.mk
new file mode 100644
index 0000000..b8cd19a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS := -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/sources.mk b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/sources.mk
new file mode 100644
index 0000000..8d2d45f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/sources.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+LD_SRCS :=
+OBJ_SRCS :=
+S_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+O_SRCS :=
+EXECUTABLES :=
+OBJS :=
+S_UPPER_DEPS :=
+C_DEPS :=
+ELFSIZE :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/src/subdir.mk b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/src/subdir.mk
new file mode 100644
index 0000000..60a1338
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/src/subdir.mk
@@ -0,0 +1,78 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+LD_SRCS += \
+../src/lscript.ld
+
+C_SRCS += \
+../src/fsbl_hooks.c \
+../src/image_mover.c \
+../src/main.c \
+../src/md5.c \
+../src/nand.c \
+../src/nor.c \
+../src/pcap.c \
+E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c \
+../src/qspi.c \
+../src/rsa.c \
+../src/sd.c
+
+S_UPPER_SRCS += \
+../src/fsbl_handoff.S
+
+OBJS += \
+./src/fsbl_handoff.o \
+./src/fsbl_hooks.o \
+./src/image_mover.o \
+./src/main.o \
+./src/md5.o \
+./src/nand.o \
+./src/nor.o \
+./src/pcap.o \
+./src/ps7_init.o \
+./src/qspi.o \
+./src/rsa.o \
+./src/sd.o
+
+S_UPPER_DEPS += \
+./src/fsbl_handoff.d
+
+C_DEPS += \
+./src/fsbl_hooks.d \
+./src/image_mover.d \
+./src/main.d \
+./src/md5.d \
+./src/nand.d \
+./src/nor.d \
+./src/pcap.d \
+./src/ps7_init.d \
+./src/qspi.d \
+./src/rsa.d \
+./src/sd.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.S
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM v7 gcc compiler'
+ arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+src/%.o: ../src/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM v7 gcc compiler'
+ arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+src/ps7_init.o: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM v7 gcc compiler'
+ arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/Xilinx.spec b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/Xilinx.spec
new file mode 100644
index 0000000..9c27dca
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/Xilinx.spec
@@ -0,0 +1,2 @@
+*startfile:
+crti%O%s crtbegin%O%s
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl.h
new file mode 100644
index 0000000..d864e5c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl.h
@@ -0,0 +1,559 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file fsbl.h
+*
+* Contains the function prototypes, defines and macros for the
+* First Stage Boot Loader (FSBL) functionality
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 03/04/11 Initial release
+* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
+* xparameters.h file
+* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
+* Added the debug levels
+* 4.00a sgd 02/28/13 Removed DDR initialization check
+* Removed DDR ECC initialization code
+* Modified hand off address check to 1MB
+* Added RSA authentication support
+* Removed LPBK_DLY_ADJ register setting code as we use
+* divisor 8
+* Removed check for Fabric is already initialized
+*
+* CR's fixed and description
+* 689026: FSBL doesn't hold PL resets active during
+* bit download
+* Resolution: PL resets are released just before
+* handoff
+*
+* 689077: FSBL hangs at Handoff clearing the
+* TX UART buffer
+* Resolution: STDOUT_BASEADDRESS macro value changes
+* based UART select, hence used STDOUT_BASEADDRESS
+* as UART base address
+*
+* 695578: FSBL failed to load standalone application
+* in secure bootmode
+* Resolution: Application will be placed at load address
+* instead of DDR temporary address
+*
+* 699475: FSBL functionality is broken and its
+* not able to boot in QSPI/NAND bootmode
+* Resolution: New flags are added DevCfg driver
+* for handling loopback
+* XDCFG_CONCURRENT_NONSEC_READ_WRITE
+* XDCFG_CONCURRENT_SECURE_READ_WRITE
+*
+* 683145: Define stack area for FIQ, UNDEF modes
+* in linker file
+* Resolution: FSBL linker modified to create stack area
+* for FIQ, UNDEF
+*
+* 705664: FSBL fails to decrypt the bitstream when
+* the image is AES encrypted using non-zero key value
+* Resolution: Fabric cleaning will not be done
+* for AES-E-Fuse encryption
+*
+* Watchdog disabled for AES E-Fuse encryption
+*
+* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
+* Added QSPI Flash Size > 128Mbit support
+* QSPI Dual Stack support
+* Added Md5 checksum support
+*
+* CR's fixed and description
+* 692045 FSBL: Linker script of FSBL has PHDR workaround,
+* this needs to be fixed
+* Resolution: Removed PHDR from Linker file
+*
+* 704287 FSBL: fsbl.h file has a few error codes that
+* are not used by FSBL, that needs to be removed
+* Resolution: Removed unused error codes
+*
+* 704379 FSBL: Check if DDR is in proper state before
+* handoff
+* Resolution: Added DDR initialization check
+*
+* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
+* the debug level is FSBL_DEBUG only.
+*
+* 710128 FSBL: Linux boot failing without load attribute
+* set for Linux partitions in BIF
+* Resolution: FSBL will load partitions with valid load
+* address and stop loading if any invalid load address
+*
+* 708728 Issues seen while making HP interconnect
+* 32 bit wide
+* Resolution: ps7_post_config function generated by PCW
+* will be called after Bit stream download
+* Added MMC support
+* 6.00a kc 07/31/2013 CR's fixed and description
+* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
+* for authenticating the Partition images
+* Resolution: FSBL now uses the PPK left by Boot ROM in
+* OCM for authencating the SPK
+*
+* 724165 Partition Header used by FSBL is not
+* authenticated
+* Resolution: FSBL now authenticates the partition header
+*
+* 691150 ps7_init does not check for peripheral
+* initialization failures or timeout on polls
+* Resolution: Return value of ps7_init() is now checked
+* by FSBL and prints the error string
+*
+* 708316 PS7_init.tcl file should have Error mechanism
+* for all mask_poll
+* Resolution: Return value of ps7_init() is now checked
+* by FSBL and prints the error string
+*
+* 732062 FSBL fails to build if UART not available
+* Resolution: Added define to call xil_printf only
+* if uart is defined
+*
+* 722979 Provide customer-friendly changelogs in FSBL
+* Resolution: Added CR description for all the files
+*
+* 732865 Backward compatibility for ps7_init function
+* Resolution: Added a new define for ps7_init success
+* and value is defined based on ps7_init define
+*
+* Fix for CR#739711 - FSBL not able to read Large
+* QSPI (512M) in IO Mode
+* Resolution: Modified the address calculation
+* algorithm in dual parallel mode for QSPI
+*
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+* 10/23/13 Support for armcc compiler added
+* 741003 FSBL has to check the HMAC error status after
+* decryption
+* Resolution: Added code for checking the error status
+* after PCAP completion
+* 739968 FSBL should do the QSPI config settings for
+* Dual parallel configuration in IO mode
+* Resolution: Added QSPI config settings in qspi.c
+* 724620 FSBL: How to handle PCAP_MODE after bitstream
+* configuration.
+* Resolution: PCAP_MODE and PCAP_PR bits are now cleared
+* after PCAP transfer completion
+* 726178 In the 14.6 FSBL function FabricInit() PROG_B
+* is kept active for 5mS.
+* Resolution: PROG_B is now kept active for 5mS only incase
+* if efuse is the aes key source.
+* 755245 FSBL does not load partition if eMMC has only
+* one partition
+* Resolution: Changed the if condition for MMC
+* 12/04/13 764382 FSBL: How to handle PCAP_MODE after bitstream
+* configuration
+* Resolution: Reverted back the changes of 724620. PCAP_MODE
+* and PCAP_PR bits are not changed
+* 8.00a kc 01/16/13 767798 Fsbl MD5 Checksum failiure for encrypted images
+* Resolution: For checksum enabled partitions, total
+* total partition image length is copied now.
+* 761895 FSBL should authenticate image only if
+* partition owner was not set to u-boot
+* Resolution: Partition owner check added in
+* image_mover.c
+* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
+* Resolution: Function argument is updated from value
+* to pointer to reflect updated value
+* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
+* unless FSBL* and FSBL are identical in length
+* Resolution: PPK is set only once now.
+* 785778 - FSBL takes 8 seconds to
+* authenticate (RSA) a bitstream on zc706
+* Resolution: Data Caches are enabled only for
+* authentication.
+* 791245 - Use of xilrsa in fsbl
+* Resolution: Rsa library is removed from fsbl source
+* and xilrsa is used from BSP
+* 10.00a kc 07/15/14 804595 Zynq FSBL - Issues with
+* fallback image offset handling using MD5
+* Resolution: Updated the checksum offset to add with
+* image base address
+* 782309 Fallback support for AES
+* encryption with E-Fuse - Enhancement
+* Resolution: Same as 773866
+* 809336 Minor code cleanup
+* Resolution Minor code changes
+* kc 08/27/14 820356 - FSBL compilation fails with IAR compiler
+* Resolution: Change of __asm__ to __asm
+* 11.00a kv 10/08/14 826030 - FSBL:LinearBootDeviceFlag is not initialized
+* in IO mode case.Due to which the variable is
+* remaining in unknown state.
+* Resolution: LinearBootDeviceFlag is initialized 0
+* in main.c
+* 12.00a ssc 12/11/14 839182 - FSBL -In the file sd.c, f_mount is called with
+* two arguments but f_mount is expecting the 3 arguments
+* from build 2015.1_1210_1, causing compilation error.
+* Resolution: Arguments for f_mount in InitSD() are
+* changed as per new signature.
+* 13.00a ssc 04/10/15 846899 - FSBL -In the file pcap.c, to clear DMA done
+* count, devcfg.INT_STS register is written to, which is
+* not correct.
+* Resolution: Corresponding fields in the devcfg.STATUS
+* register are written to, for clearing DMA done count.
+* 14.00a gan 01/13/16 869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
+* read command from LQSPI_CFG register instead of hard
+* coded read command (0x6B).
+* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* Fabric Initialization sequence is modified to check
+* the PL power before sequence starts and checking INIT_B
+* reset status twice in case of failure.
+* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
+* In pcap.c, check pl power through MCTRL register
+* for 3.0 and later versions of silicon.
+* 17.00a bsv 27/03/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
+* to enable level shifters in jtag boot mode.
+* 18.00a ka 10/29/18 Fix for CR# 1006294 Added macro for FORCE_USE_AES_EXCLUDE
+*
+*
+*
+*
+*
+* @note
+*
+* Flags in FSBL
+*
+* FSBL_PERF
+*
+* This Flag can be set at compilation time. This flag is set for
+* measuring the performance of FSBL.That is the time taken to execute is
+* measured.when this flag is set.Execution time with reference to
+* global timer is taken here
+*
+* Total Execution time is the time taken for executing FSBL till handoff
+* to any application .
+* If there is a bitstream in the partition header then the
+* execution time includes the copying of the bitstream to DDR
+* (in case of SD/NAND bootmode)
+* and programming the devcfg dma is accounted.
+*
+* FSBL provides two debug levels
+* DEBUG GENERAL - fsbl_printf under this category will appear only when the
+* FSBL_DEBUG flag is set during compilation
+* DEBUG_INFO - fsbl_printf under this category will appear when the
+* FSBL_DEBUG_INFO flag is set during compilation
+* For a more detailed output log can be used.
+* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
+* RSA functions
+* These macros are input to the fsbl_printf function
+*
+* DEBUG LEVELS
+* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
+* that are with the DEBUG_GENERAL argument are shown
+* FSBL_DEBUG_INFO is level 2, when this flag is set during the
+* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
+*
+* DEFAULT LEVEL
+* By default no print messages will appear.
+*
+* NON_PS_INSTANTIATED_BITSTREAM
+*
+* FSBL will not enable the level shifters for a NON PS instantiated
+* Bitstream.This flag can be set during compilation for a NON PS instantiated
+* bitstream
+*
+* ECC_ENABLE
+* This flag will be defined in the ps7_init.h file when ECC is enabled
+* in the DDR configuration (XPS GUI)
+*
+* RSA_SUPPORT
+* This flag is used to enable authentication feature
+* Default this macro disabled, reason to avoid increase in code size
+*
+* MMC_SUPPORT
+* This flag is used to enable MMC support feature
+*
+* JTAG_ENABLE_LEVEL_SHIFTERS
+* FSBL will not enable the level shifters for jtag boot mode. This flag can be
+* set during compilation for jtag boot mode to enable level shifters.
+*
+* FORCE_USE_AES_EXCLUDE
+* Defining this flag will exclude the feature, forcing every partition to be
+* encrypted when EFUSE_SEC_EN bit is set.
+* This flag can be set/unset during compilation.
+* By deafult this flag is unset/undefined which enables the above feature
+* Note : Changing the default behaviour is not recommended from
+* Security perspective.
+*
+*******************************************************************************/
+#ifndef XIL_FSBL_H
+#define XIL_FSBL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xparameters.h"
+#include "xpseudo_asm.h"
+#include "xil_printf.h"
+#include "pcap.h"
+#include "fsbl_debug.h"
+#include "ps7_init.h"
+#ifdef FSBL_PERF
+#include "xtime_l.h"
+#include
+#endif
+
+
+/************************** Constant Definitions *****************************/
+/*
+ * SDK release version
+ */
+#define SDK_RELEASE_YEAR 2018
+#define SDK_RELEASE_QUARTER 3
+
+#define WORD_LENGTH_SHIFT 2
+
+/*
+ * On a Successful handoff to an application FSBL sets this SUCCESS code
+ */
+#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
+
+/*
+ * Backward compatibility for ps7_init
+ */
+#ifdef NEW_PS7_ERR_CODE
+#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
+#else
+#define FSBL_PS7_INIT_SUCCESS (1)
+#endif
+
+/*
+ * ERROR CODES
+ * The following are the Error codes that FSBL uses
+ * If the Debug prints are enabled only then the error codes will be
+ * seen on the com port.Without the debug prints enabled no error codes will
+ * be visible.There are not saved in any register
+ * Boot Mode States used for error and status output
+ * Error codes are defined below
+ */
+#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
+#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
+#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
+#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
+#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
+#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
+#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
+#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
+#define NO_DDR 0xA008 /**< DDR missing */
+#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
+#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
+#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
+#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
+#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
+#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
+#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
+#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
+#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
+#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
+#define PARTITION_LOAD_FAIL 0xA013 /**< Partition load fail*/
+/*
+ * FSBL Exception error codes
+ */
+#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
+#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
+#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
+#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
+#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
+#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
+
+/*
+ * FSBL hook routine failures
+ */
+#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
+#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
+ download hook failed */
+#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
+ download hook failed */
+
+/*
+ * Watchdog related Error codes
+ */
+#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
+#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
+
+/*
+ * SLCR Registers
+ */
+#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
+#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
+#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
+#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
+#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
+#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
+#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
+
+/*
+ * Efuse Status Register
+ */
+#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
+#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
+
+/*
+ * PS reset control register define
+ */
+#define PS_RST_MASK 0x1 /**< PS software reset */
+
+/*
+ * SLCR BOOT Mode Register defines
+ */
+#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
+
+/*
+ * Boot Modes
+ */
+#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
+#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
+#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
+#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
+#define SD_MODE 0x00000005 /**< SD Boot Mode */
+#define MMC_MODE 0x00000006 /**< MMC Boot Device */
+
+#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
+#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
+
+/*
+ * Golden image offset
+ */
+#define GOLDEN_IMAGE_OFFSET 0x8000
+
+/*
+ * Silicon Version
+ */
+#define SILICON_VERSION_1 0
+#define SILICON_VERSION_2 1
+#define SILICON_VERSION_3 2
+#define SILICON_VERSION_3_1 3
+
+/*
+ * DDR start address for storing the data temporarily(1M)
+ * Need to finalize correct logic
+ */
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
+#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
+#else
+/*
+ * In case of PL DDR, this macros defined based PL DDR address
+ */
+#define DDR_START_ADDR 0x00
+#define DDR_END_ADDR 0x00
+#endif
+
+#define DDR_TEMP_START_ADDR DDR_START_ADDR
+/*
+ * DDR test pattern
+ */
+#define DDR_TEST_PATTERN 0xAA55AA55
+#define DDR_TEST_OFFSET 0x100000
+/*
+ *
+ */
+#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
+#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
+#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
+#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
+#define LQSPI_CFG_OFFSET 0xA0
+#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
+
+/*
+ * These are the SLCR lock and unlock macros
+ */
+#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
+#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
+
+#define IMAGE_HEADER_CHECKSUM_COUNT 10
+
+/* Boot ROM Image defines */
+#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
+#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
+#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
+#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
+#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
+#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
+#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
+#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
+#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
+#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
+#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
+#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
+
+/* Reboot status register defines:
+ * 0xF0000000 for FSBL fallback mask to notify Boot Rom
+ * 0x60000000 for FSBL to mark that FSBL has not handoff yet
+ * 0x00FFFFFF for user application to use across soft reset
+ */
+#define FSBL_FAIL_MASK 0xF0000000
+#define FSBL_IN_MASK 0x60000000
+
+/* The address that holds the base address for the image Boot ROM found */
+#define BASEADDR_HOLDER 0xFFFFFFF8
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void OutputStatus(u32 State);
+void FsblFallback(void);
+
+int FsblSetNextPartition(int Num);
+void *(memcpy_rom)(void * s1, const void * s2, u32 n);
+char *strcpy_rom(char *Dest, const char *Src);
+
+void ClearFSBLIn(void);
+void MarkFSBLIn(void);
+void FsblHandoff(u32 FsblStartAddr);
+u32 GetResetReason(void);
+
+#ifdef FSBL_PERF
+void FsblGetGlobalTime (XTime * tCur);
+void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
+#endif
+void GetSiliconVersion(void);
+void FsblHandoffExit(u32 FsblStartAddr);
+void FsblHandoffJtagExit();
+/************************** Variable Definitions *****************************/
+extern int SkipPartition;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_debug.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_debug.h
new file mode 100644
index 0000000..8dc0389
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_debug.h
@@ -0,0 +1,78 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file fsbl_debug.h
+*
+* This file contains the debug verbose information for FSBL print functionality
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a mb 01/09/12 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef _FSBL_DEBUG_H
+#define _FSBL_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define DEBUG_GENERAL 0x00000001 /* general debug messages */
+#define DEBUG_INFO 0x00000002 /* More debug information */
+
+#if defined (FSBL_DEBUG_INFO)
+#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
+#elif defined (FSBL_DEBUG)
+#define fsbl_dbg_current_types (DEBUG_GENERAL)
+#else
+#define fsbl_dbg_current_types 0
+#endif
+
+#ifdef STDOUT_BASEADDRESS
+#define fsbl_printf(type,...) \
+ if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
+#else
+#define fsbl_printf(type, ...)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FSBL_DEBUG_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_handoff.S b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_handoff.S
new file mode 100644
index 0000000..8434a10
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_handoff.S
@@ -0,0 +1,217 @@
+#ifdef __GNUC__
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file handoff.S
+*
+* Contains the code that does the handoff to the loaded application. This
+* code lives high in the ROM.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date.word Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 03/01/10 Initial release
+* 7.00a kc 10/23/13 Added support for armcc compiler
+*
+*
+* @note
+* Assumes that the starting address of the FSBL is provided by the calling routine
+* in R0.
+*
+******************************************************************************/
+
+.globl FsblHandoffJtagExit
+
+.globl FsblHandoffExit
+
+.section .handoff,"axS"
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+FsblHandoffJtagExit:
+ mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
+ mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
+
+ dsb
+ isb /* make sure it completes */
+
+ ldr r4, =0
+ mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
+
+ isb /* make sure it completes */
+Loop:
+ wfe
+ b Loop
+
+FsblHandoffExit:
+ mov lr, r0 /* move the destination address into link register */
+
+ mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
+ mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
+
+ dsb
+ isb /* make sure it completes */
+
+ ldr r4, =0
+ mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
+
+ isb /* make sure it completes */
+
+
+ bx lr /* force the switch, destination should have been in r0 */
+
+.Ldone: b .Ldone /* Paranoia: we should never get here */
+.end
+
+#elif defined (__IASMARM__)
+
+ PUBLIC FsblHandoffJtagExit
+
+ PUBLIC FsblHandoffExit
+
+ SECTION .handoff:CODE:NOROOT(2)
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+FsblHandoffJtagExit
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+Loop
+ wfe
+ b Loop
+
+FsblHandoffExit
+ mov lr, r0 ;/* move the destination address into link register */
+
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+
+
+ bx lr ;/* force the switch, destination should have been in r0 */
+
+.Ldone
+ b .Ldone ;/* Paranoia: we should never get here */
+
+ END
+
+
+#else
+ EXPORT FsblHandoffJtagExit
+
+ EXPORT FsblHandoffExit
+
+ AREA |.handoff|,CODE
+
+;/***************************** Include Files *********************************/
+
+;/************************** Constant Definitions *****************************/
+
+;/**************************** Type Definitions *******************************/
+
+;/***************** Macros (Inline Functions) Definitions *********************/
+
+;/************************** Function Prototypes ******************************/
+
+;/************************** Variable Definitions *****************************/
+
+
+FsblHandoffJtagExit
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+Loop
+ wfe
+ b Loop
+
+FsblHandoffExit
+ mov lr, r0 ;/* move the destination address into link register */
+
+ mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
+ mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
+
+ dsb
+ isb ;/* make sure it completes */
+
+ ldr r4, =0
+ mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
+
+ isb ;/* make sure it completes */
+
+
+ bx lr ;/* force the switch, destination should have been in r0 */
+
+Ldone b Ldone ;/* Paranoia: we should never get here */
+ END
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.c
new file mode 100644
index 0000000..c09e41a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.c
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************
+*
+* @file fsbl_hooks.c
+*
+* This file provides functions that serve as user hooks. The user can add the
+* additional functionality required into these routines. This would help retain
+* the normal FSBL flow unchanged.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a np 08/03/12 Initial release
+*
+*
+* @note
+*
+******************************************************************************/
+
+
+#include "fsbl.h"
+#include "xstatus.h"
+#include "fsbl_hooks.h"
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/******************************************************************************
+* This function is the hook which will be called before the bitstream download.
+* The user can add all the customized code required to be executed before the
+* bitstream download to this routine.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+****************************************************************************/
+u32 FsblHookBeforeBitstreamDload(void)
+{
+ u32 Status;
+
+ Status = XST_SUCCESS;
+
+ /*
+ * User logic to be added here. Errors to be stored in the status variable
+ * and returned
+ */
+ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
+
+ return (Status);
+}
+
+/******************************************************************************
+* This function is the hook which will be called after the bitstream download.
+* The user can add all the customized code required to be executed after the
+* bitstream download to this routine.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+****************************************************************************/
+u32 FsblHookAfterBitstreamDload(void)
+{
+ u32 Status;
+
+ Status = XST_SUCCESS;
+
+ /*
+ * User logic to be added here.
+ * Errors to be stored in the status variable and returned
+ */
+ fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
+
+ return (Status);
+}
+
+/******************************************************************************
+* This function is the hook which will be called before the FSBL does a handoff
+* to the application. The user can add all the customized code required to be
+* executed before the handoff to this routine.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+****************************************************************************/
+u32 FsblHookBeforeHandoff(void)
+{
+ u32 Status;
+
+ Status = XST_SUCCESS;
+
+ /*
+ * User logic to be added here.
+ * Errors to be stored in the status variable and returned
+ */
+ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
+
+ return (Status);
+}
+
+
+/******************************************************************************
+* This function is the hook which will be called in case FSBL fall back
+*
+* @param None
+*
+* @return None
+*
+****************************************************************************/
+void FsblHookFallback(void)
+{
+ /*
+ * User logic to be added here.
+ * Errors to be stored in the status variable and returned
+ */
+ fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
+ while(1);
+}
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.h
new file mode 100644
index 0000000..abb37aa
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.h
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file fsbl_hooks.h
+*
+* Contains the function prototypes, defines and macros required by fsbl_hooks.c
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a np/mb 10/08/12 Initial release
+* Corrected the prototype
+*
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef FSBL_HOOKS_H_
+#define FSBL_HOOKS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+
+
+/************************** Function Prototypes ******************************/
+
+/* FSBL hook function which is called before bitstream download */
+u32 FsblHookBeforeBitstreamDload(void);
+
+/* FSBL hook function which is called after bitstream download */
+u32 FsblHookAfterBitstreamDload(void);
+
+/* FSBL hook function which is called before handoff to the application */
+u32 FsblHookBeforeHandoff(void);
+
+/* FSBL hook function which is called in FSBL fallback */
+void FsblHookFallback(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.c
new file mode 100644
index 0000000..184ffab
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.c
@@ -0,0 +1,1348 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file image_mover.c
+*
+* Move partitions to either DDR to execute or to program FPGA.
+* It performs partition walk.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 05/24/11 Initial release
+* 2.00a jz 06/30/11 Updated partition header defs for 64-byte
+* alignment change in data2mem tool
+* 2.00a mb 05/25/12 Updated for standalone based bsp FSBL
+* Nand/SD encryption and review comments
+* 3.00a np 08/30/12 Added FSBL user hook calls
+* (before and after bitstream download.)
+* 4.00a sgd 02/28/13 Fix for CR#691148 Secure bootmode error in devcfg test
+* Fix for CR#695578 FSBL failed to load standalone
+* application in secure bootmode
+*
+* 4.00a sgd 04/23/13 Fix for CR#710128 FSBL failed to load standalone
+* application in secure bootmode
+* 5.00a kc 07/30/13 Fix for CR#724165 Partition Header used by FSBL
+* is not authenticated
+* Fix for CR#724166 FSBL doesn�t use PPK authenticated
+* by Boot ROM for authenticating the Partition images
+* Fix for CR#732062 FSBL fails to build if UART not
+* available
+* 7.00a kc 10/30/13 Fix for CR#755245 FSBL does not load partition
+* if eMMC has only one partition
+* 8.00a kc 01/16/13 Fix for CR#767798 FSBL MD5 Checksum failure
+* for encrypted images
+* Fix for CR#761895 FSBL should authenticate image
+* only if partition owner was not set to u-boot
+* 9.00a kc 04/16/14 Fix for CR#785778 FSBL takes 8 seconds to
+* authenticate (RSA) a bitstream on zc706
+* 10.00a kc 07/15/14 Fix for CR#804595 Zynq FSBL - Issues with
+* fallback image offset handling using MD5
+* Fix for PR#782309 Fallback support for AES
+* encryption with E-Fuse - Enhancement
+* 11.00a ka 10/12/18 Fix for CR#1006294 Zynq FSBL - Zynq FSBL does not check
+* USE_AES_ONLY eFuse
+*
+*
+*
+* @note
+* A partition is either an executable or a bitstream to program FPGA
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+#include "image_mover.h"
+#include "xil_printf.h"
+#include "xreg_cortexa9.h"
+#include "pcap.h"
+#include "fsbl_hooks.h"
+#include "md5.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+
+#ifdef RSA_SUPPORT
+#include "rsa.h"
+#include "xil_cache.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+/* We are 32-bit machine */
+#define MAXIMUM_IMAGE_WORD_LEN 0x40000000
+#define MD5_CHECKSUM_SIZE 16
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset);
+u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum);
+u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Partition information flags
+ */
+u8 EncryptedPartitionFlag;
+u8 PLPartitionFlag;
+u8 PSPartitionFlag;
+u8 SignedPartitionFlag;
+u8 PartitionChecksumFlag;
+u8 BitstreamFlag;
+u8 ApplicationFlag;
+
+u32 ExecutionAddress;
+ImageMoverType MoveImage;
+
+/*
+ * Header array
+ */
+PartHeader PartitionHeader[MAX_PARTITION_NUMBER];
+u32 PartitionCount;
+u32 FsblLength;
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+
+extern u32 Silicon_Version;
+extern u32 FlashReadBaseAddress;
+extern u8 LinearBootDeviceFlag;
+extern XDcfg *DcfgInstPtr;
+
+/*****************************************************************************/
+/**
+*
+* This function
+*
+* @param
+*
+* @return
+*
+*
+* @note None
+*
+****************************************************************************/
+u32 LoadBootImage(void)
+{
+ u32 RebootStatusRegister = 0;
+ u32 MultiBootReg = 0;
+ u32 ImageStartAddress = 0;
+ u32 PartitionNum;
+ u32 PartitionDataLength;
+ u32 PartitionImageLength;
+ u32 PartitionTotalSize;
+ u32 PartitionExecAddr;
+ u32 PartitionAttr;
+ u32 ExecAddress = 0;
+ u32 PartitionLoadAddr;
+ u32 PartitionStartAddr;
+ u32 PartitionChecksumOffset;
+ u8 ExecAddrFlag = 0 ;
+ u32 Status;
+ PartHeader *HeaderPtr;
+ u32 EfuseStatusRegValue;
+#ifdef RSA_SUPPORT
+ u32 HeaderSize;
+#endif
+#ifndef FORCE_USE_AES_EXCLUDE
+ u32 EncOnly;
+#endif
+ /*
+ * Resetting the Flags
+ */
+ BitstreamFlag = 0;
+ ApplicationFlag = 0;
+
+ RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
+ fsbl_printf(DEBUG_INFO,
+ "Reboot status register: 0x%08lx\r\n",RebootStatusRegister);
+
+ if (Silicon_Version == SILICON_VERSION_1) {
+ /*
+ * Clear out fallback mask from previous run
+ * We start from the first partition again
+ */
+ if ((RebootStatusRegister & FSBL_FAIL_MASK) ==
+ FSBL_FAIL_MASK) {
+ fsbl_printf(DEBUG_INFO,
+ "Reboot status shows previous run falls back\r\n");
+ RebootStatusRegister &= ~(FSBL_FAIL_MASK);
+ Xil_Out32(REBOOT_STATUS_REG, RebootStatusRegister);
+ }
+
+ /*
+ * Read the image start address
+ */
+ ImageStartAddress = *(u32 *)BASEADDR_HOLDER;
+ } else {
+ /*
+ * read the multiboot register
+ */
+ MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET);
+
+ fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08lx\r\n",MultiBootReg);
+
+ /*
+ * Compute the image start address
+ */
+ ImageStartAddress = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
+ * GOLDEN_IMAGE_OFFSET;
+ }
+
+ fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08lx\r\n",ImageStartAddress);
+
+ /*
+ * Get partitions header information
+ */
+ Status = GetPartitionHeaderInfo(ImageStartAddress);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Partition Header Load Failed\r\n");
+ OutputStatus(GET_HEADER_INFO_FAIL);
+ FsblFallback();
+ }
+
+ /*
+ * RSA is not implemented in 1.0 and 2.0
+ * silicon
+ */
+ if ((Silicon_Version != SILICON_VERSION_1) &&
+ (Silicon_Version != SILICON_VERSION_2)) {
+ /*
+ * Read Efuse Status Register
+ */
+ EfuseStatusRegValue = Xil_In32(EFUSE_STATUS_REG);
+ if (EfuseStatusRegValue & EFUSE_STATUS_RSA_ENABLE_MASK) {
+ fsbl_printf(DEBUG_GENERAL,"RSA enabled for Chip\r\n");
+#ifdef RSA_SUPPORT
+ /*
+ * Set the Ppk
+ */
+ SetPpk();
+
+ /*
+ * Read partition header with signature
+ */
+ Status = GetImageHeaderAndSignature(ImageStartAddress,
+ (u32 *)DDR_TEMP_START_ADDR);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,
+ "Read Partition Header signature Failed\r\n");
+ OutputStatus(GET_HEADER_INFO_FAIL);
+ FsblFallback();
+ }
+ HeaderSize=TOTAL_HEADER_SIZE+RSA_SIGNATURE_SIZE;
+
+ Status = AuthenticatePartition((u8 *)DDR_TEMP_START_ADDR, HeaderSize);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,
+ "Partition Header signature Failed\r\n");
+ OutputStatus(GET_HEADER_INFO_FAIL);
+ FsblFallback();
+ }
+#else
+ /*
+ * In case user not enabled RSA authentication feature
+ */
+ fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
+ OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
+ FsblFallback();
+#endif
+ }
+ }
+
+#ifdef MMC_SUPPORT
+ /*
+ * In case of MMC support
+ * boot image preset in MMC will not have FSBL partition
+ */
+ PartitionNum = 0;
+#else
+ /*
+ * First partition header was ignored by FSBL
+ * As it contain FSBL partition information
+ */
+ PartitionNum = 1;
+#endif
+
+ while (PartitionNum < PartitionCount) {
+
+ fsbl_printf(DEBUG_INFO, "Partition Number: %lu\r\n", PartitionNum);
+
+ HeaderPtr = &PartitionHeader[PartitionNum];
+
+ /*
+ * Print partition header information
+ */
+ HeaderDump(HeaderPtr);
+
+ /*
+ * Validate partition header
+ */
+ Status = ValidateHeader(HeaderPtr);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "INVALID_HEADER_FAIL\r\n");
+ OutputStatus(INVALID_HEADER_FAIL);
+ FsblFallback();
+ }
+
+ /*
+ * Load partition header information in to local variables
+ */
+ PartitionDataLength = HeaderPtr->DataWordLen;
+ PartitionImageLength = HeaderPtr->ImageWordLen;
+ PartitionExecAddr = HeaderPtr->ExecAddr;
+ PartitionAttr = HeaderPtr->PartitionAttr;
+ PartitionLoadAddr = HeaderPtr->LoadAddr;
+ PartitionChecksumOffset = HeaderPtr->CheckSumOffset;
+ PartitionStartAddr = HeaderPtr->PartitionStart;
+ PartitionTotalSize = HeaderPtr->PartitionWordLen;
+
+ /*
+ * Partition owner should be FSBL to validate the partition
+ */
+ if ((PartitionAttr & ATTRIBUTE_PARTITION_OWNER_MASK) !=
+ ATTRIBUTE_PARTITION_OWNER_FSBL) {
+ /*
+ * if FSBL is not the owner of partition,
+ * skip this partition, continue with next partition
+ */
+ fsbl_printf(DEBUG_INFO, "Skipping partition %0lx\r\n",
+ PartitionNum);
+ /*
+ * Increment partition number
+ */
+ PartitionNum++;
+ continue;
+ }
+
+ if (PartitionAttr & ATTRIBUTE_PL_IMAGE_MASK) {
+ fsbl_printf(DEBUG_INFO, "Bitstream\r\n");
+ PLPartitionFlag = 1;
+ PSPartitionFlag = 0;
+ BitstreamFlag = 1;
+ if (ApplicationFlag == 1) {
+#ifdef STDOUT_BASEADDRESS
+ xil_printf("\r\nFSBL Warning !!!"
+ "Bitstream not loaded into PL\r\n");
+ xil_printf("Partition order invalid\r\n");
+#endif
+ break;
+ }
+ }
+
+ if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) {
+ fsbl_printf(DEBUG_INFO, "Application\r\n");
+ PSPartitionFlag = 1;
+ PLPartitionFlag = 0;
+ ApplicationFlag = 1;
+ }
+
+ /*
+ * Encrypted partition will have different value
+ * for Image length and data length
+ */
+ if (PartitionDataLength != PartitionImageLength) {
+ fsbl_printf(DEBUG_INFO, "Encrypted\r\n");
+ EncryptedPartitionFlag = 1;
+ } else {
+ EncryptedPartitionFlag = 0;
+ }
+
+#ifndef FORCE_USE_AES_EXCLUDE
+ EncOnly = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_STATUS_OFFSET) &
+ XDCFG_STATUS_EFUSE_SEC_EN_MASK;
+ if ((EncOnly != 0) &&
+ (EncryptedPartitionFlag == 0)) {
+ fsbl_printf(DEBUG_GENERAL,"EFUSE_SEC_EN bit is set,"
+ " Encryption is mandatory\r\n");
+ OutputStatus(PARTITION_LOAD_FAIL);
+ FsblFallback();
+ }
+#endif
+ /*
+ * Check for partition checksum check
+ */
+ if (PartitionAttr & ATTRIBUTE_CHECKSUM_TYPE_MASK) {
+ PartitionChecksumFlag = 1;
+ } else {
+ PartitionChecksumFlag = 0;
+ }
+
+ /*
+ * RSA signature check
+ */
+ if (PartitionAttr & ATTRIBUTE_RSA_PRESENT_MASK) {
+ fsbl_printf(DEBUG_INFO, "RSA Signed\r\n");
+ SignedPartitionFlag = 1;
+ } else {
+ SignedPartitionFlag = 0;
+ }
+
+ /*
+ * Load address check
+ * Loop will break when PS load address zero and partition is
+ * un-signed or un-encrypted
+ */
+ if ((PSPartitionFlag == 1) && (PartitionLoadAddr < DDR_START_ADDR)) {
+ if ((PartitionLoadAddr == 0) &&
+ (!((SignedPartitionFlag == 1) ||
+ (EncryptedPartitionFlag == 1)))) {
+ break;
+ } else {
+ fsbl_printf(DEBUG_GENERAL,
+ "INVALID_LOAD_ADDRESS_FAIL\r\n");
+ OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
+ FsblFallback();
+ }
+ }
+
+ if (PSPartitionFlag && (PartitionLoadAddr > DDR_END_ADDR)) {
+ fsbl_printf(DEBUG_GENERAL,
+ "INVALID_LOAD_ADDRESS_FAIL\r\n");
+ OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
+ FsblFallback();
+ }
+
+ /*
+ * Load execution address of first PS partition
+ */
+ if (PSPartitionFlag && (!ExecAddrFlag)) {
+ ExecAddrFlag++;
+ ExecAddress = PartitionExecAddr;
+ }
+
+ /*
+ * FSBL user hook call before bitstream download
+ */
+ if (PLPartitionFlag) {
+ Status = FsblHookBeforeBitstreamDload();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAIL\r\n");
+ OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL);
+ FsblFallback();
+ }
+ }
+
+ /*
+ * Move partitions from boot device
+ */
+ Status = PartitionMove(ImageStartAddress, HeaderPtr);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PARTITION_MOVE_FAIL\r\n");
+ OutputStatus(PARTITION_MOVE_FAIL);
+ FsblFallback();
+ }
+
+ if ((SignedPartitionFlag) || (PartitionChecksumFlag)) {
+ if(PLPartitionFlag) {
+ /*
+ * PL partition loaded in to DDR temporary address
+ * for authentication and checksum verification
+ */
+ PartitionStartAddr = DDR_TEMP_START_ADDR;
+ } else {
+ PartitionStartAddr = PartitionLoadAddr;
+ }
+
+ if (PartitionChecksumFlag) {
+ /*
+ * Validate the partition data with checksum
+ */
+ Status = ValidateParition(PartitionStartAddr,
+ (PartitionTotalSize << WORD_LENGTH_SHIFT),
+ ImageStartAddress +
+ (PartitionChecksumOffset << WORD_LENGTH_SHIFT));
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PARTITION_CHECKSUM_FAIL\r\n");
+ OutputStatus(PARTITION_CHECKSUM_FAIL);
+ FsblFallback();
+ }
+
+ fsbl_printf(DEBUG_INFO, "Partition Validation Done\r\n");
+ }
+
+ /*
+ * Authentication Partition
+ */
+ if (SignedPartitionFlag == 1 ) {
+#ifdef RSA_SUPPORT
+ Xil_DCacheEnable();
+ Status = AuthenticatePartition((u8*)PartitionStartAddr,
+ (PartitionTotalSize << WORD_LENGTH_SHIFT));
+ if (Status != XST_SUCCESS) {
+ Xil_DCacheFlush();
+ Xil_DCacheDisable();
+ fsbl_printf(DEBUG_GENERAL,"AUTHENTICATION_FAIL\r\n");
+ OutputStatus(AUTHENTICATION_FAIL);
+ FsblFallback();
+ }
+ fsbl_printf(DEBUG_INFO,"Authentication Done\r\n");
+ Xil_DCacheFlush();
+ Xil_DCacheDisable();
+#else
+ /*
+ * In case user not enabled RSA authentication feature
+ */
+ fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
+ OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
+ FsblFallback();
+#endif
+ }
+
+ /*
+ * Decrypt PS partition
+ */
+ if (EncryptedPartitionFlag && PSPartitionFlag) {
+ Status = DecryptPartition(PartitionStartAddr,
+ PartitionDataLength,
+ PartitionImageLength);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"DECRYPTION_FAIL\r\n");
+ OutputStatus(DECRYPTION_FAIL);
+ FsblFallback();
+ }
+ }
+
+ /*
+ * Load Signed PL partition in Fabric
+ */
+ if (PLPartitionFlag) {
+ Status = PcapLoadPartition((u32*)PartitionStartAddr,
+ (u32*)PartitionLoadAddr,
+ PartitionImageLength,
+ PartitionDataLength,
+ EncryptedPartitionFlag);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"BITSTREAM_DOWNLOAD_FAIL\r\n");
+ OutputStatus(BITSTREAM_DOWNLOAD_FAIL);
+ FsblFallback();
+ }
+ }
+ }
+
+
+ /*
+ * FSBL user hook call after bitstream download
+ */
+ if (PLPartitionFlag) {
+ Status = FsblHookAfterBitstreamDload();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"FSBL_AFTER_BSTREAM_HOOK_FAIL\r\n");
+ OutputStatus(FSBL_AFTER_BSTREAM_HOOK_FAIL);
+ FsblFallback();
+ }
+ }
+ /*
+ * Increment partition number
+ */
+ PartitionNum++;
+ }
+
+ return ExecAddress;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function loads all partition header information in global array
+*
+* @param ImageAddress is the start address of the image
+*
+* @return - XST_SUCCESS if Get partition Header information successful
+* - XST_FAILURE if Get Partition Header information failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetPartitionHeaderInfo(u32 ImageBaseAddress)
+{
+ u32 PartitionHeaderOffset;
+ u32 Status;
+
+
+ /*
+ * Get the length of the FSBL from BootHeader
+ */
+ Status = GetFsblLength(ImageBaseAddress, &FsblLength);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Get the start address of the partition header table
+ */
+ Status = GetPartitionHeaderStartAddr(ImageBaseAddress,
+ &PartitionHeaderOffset);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Header offset on flash
+ */
+ PartitionHeaderOffset += ImageBaseAddress;
+
+ fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08lx\r\n",
+ PartitionHeaderOffset);
+
+ /*
+ * Load all partitions header data in to global variable
+ */
+ Status = LoadPartitionsHeaderInfo(PartitionHeaderOffset,
+ &PartitionHeader[0]);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Header Information Load Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Get partitions count from partitions header information
+ */
+ PartitionCount = GetPartitionCount(&PartitionHeader[0]);
+
+ fsbl_printf(DEBUG_INFO, "Partition Count: %lu\r\n", PartitionCount);
+
+ /*
+ * Partition Count check
+ */
+ if (PartitionCount >= MAX_PARTITION_NUMBER) {
+ fsbl_printf(DEBUG_GENERAL, "Invalid Partition Count\r\n");
+ return XST_FAILURE;
+#ifndef MMC_SUPPORT
+ } else if (PartitionCount <= 1) {
+ fsbl_printf(DEBUG_GENERAL, "There is no partition to load\r\n");
+ return XST_FAILURE;
+#endif
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function goes to the partition header of the specified partition
+*
+* @param ImageAddress is the start address of the image
+*
+* @return Offset Partition header address of the image
+*
+* @return - XST_SUCCESS if Get Partition Header start address successful
+* - XST_FAILURE if Get Partition Header start address failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset)
+{
+ u32 Status;
+
+ Status = MoveImage(ImageAddress + IMAGE_PHDR_OFFSET, (u32)Offset, 4);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function goes to the partition header of the specified partition
+*
+* @param ImageAddress is the start address of the image
+*
+* @return Offset to Image header table address of the image
+*
+* @return - XST_SUCCESS if Get Partition Header start address successful
+* - XST_FAILURE if Get Partition Header start address failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetImageHeaderStartAddr(u32 ImageAddress, u32 *Offset)
+{
+ u32 Status;
+
+ Status = MoveImage(ImageAddress + IMAGE_HDR_OFFSET, (u32)Offset, 4);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+*
+* This function gets the length of the FSBL
+*
+* @param ImageAddress is the start address of the image
+*
+* @return FsblLength is the length of the fsbl
+*
+* @return - XST_SUCCESS if fsbl length reading is successful
+* - XST_FAILURE if fsbl length reading failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength)
+{
+ u32 Status;
+
+ Status = MoveImage(ImageAddress + IMAGE_TOT_BYTE_LEN_OFFSET,
+ (u32)FsblLength, 4);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed reading FsblLength\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+#ifdef RSA_SUPPORT
+/*****************************************************************************/
+/**
+*
+* This function goes to read the image headers and its signature. Image
+* header consists of image header table, image headers, partition
+* headers
+*
+* @param ImageBaseAddress is the start address of the image header
+*
+* @return Offset Partition header address of the image
+*
+* @return - XST_SUCCESS if Get Partition Header start address successful
+* - XST_FAILURE if Get Partition Header start address failed
+*
+* @note None
+*
+****************************************************************************/
+u32 GetImageHeaderAndSignature(u32 ImageBaseAddress, u32 *Offset)
+{
+ u32 Status;
+ u32 ImageHeaderOffset;
+
+ /*
+ * Get the start address of the partition header table
+ */
+ Status = GetImageHeaderStartAddr(ImageBaseAddress, &ImageHeaderOffset);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ Status = MoveImage(ImageBaseAddress+ImageHeaderOffset, (u32)Offset,
+ TOTAL_HEADER_SIZE + RSA_SIGNATURE_SIZE);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+#endif
+/*****************************************************************************/
+/**
+*
+* This function get the header information of the all the partitions and load into
+* global array
+*
+* @param PartHeaderOffset Offset address where the header information present
+*
+* @param Header Partition header pointer
+*
+* @return - XST_SUCCESS if Load Partitions Header information successful
+* - XST_FAILURE if Load Partitions Header information failed
+*
+* @note None
+*
+****************************************************************************/
+u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header)
+{
+ u32 Status;
+
+ Status = MoveImage(PartHeaderOffset, (u32)Header, sizeof(PartHeader)*MAX_PARTITION_NUMBER);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function dumps the partition header.
+*
+* @param Header Partition header pointer
+*
+* @return None
+*
+* @note None
+*
+******************************************************************************/
+void HeaderDump(PartHeader *Header)
+{
+ fsbl_printf(DEBUG_INFO, "Header Dump\r\n");
+ fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08lx\r\n",
+ Header->ImageWordLen);
+ fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08lx\r\n",
+ Header->DataWordLen);
+ fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08lx\r\n",
+ Header->PartitionWordLen);
+ fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08lx\r\n",
+ Header->LoadAddr);
+ fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08lx\r\n",
+ Header->ExecAddr);
+ fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08lx\r\n",
+ Header->PartitionStart);
+ fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08lx\r\n",
+ Header->PartitionAttr);
+ fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08lx\r\n",
+ Header->CheckSumOffset);
+ fsbl_printf(DEBUG_INFO, "Section Count: 0x%08lx\r\n",
+ Header->SectionCount);
+ fsbl_printf(DEBUG_INFO, "Checksum: 0x%08lx\r\n",
+ Header->CheckSum);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function calculates the partitions count from header information
+*
+* @param Header Partition header pointer
+*
+* @return Count Partition count
+*
+* @note None
+*
+*******************************************************************************/
+u32 GetPartitionCount(PartHeader *Header)
+{
+ u32 Count=0;
+ struct HeaderArray *Hap;
+
+ for(Count = 0; Count < MAX_PARTITION_NUMBER; Count++) {
+ Hap = (struct HeaderArray *)&Header[Count];
+ if(IsLastPartition(Hap)!=XST_FAILURE)
+ break;
+ }
+
+ return Count;
+}
+
+/******************************************************************************/
+/**
+* This function check whether the current partition is the end of partitions
+*
+* The partition is the end of the partitions if it looks like this:
+* 0x00000000
+* 0x00000000
+* ....
+* 0x00000000
+* 0x00000000
+* 0xFFFFFFFF
+*
+* @param H is a pointer to struct HeaderArray
+*
+* @return
+* - XST_SUCCESS if it is the last partition
+* - XST_FAILURE if it is not last partition
+*
+****************************************************************************/
+u32 IsLastPartition(struct HeaderArray *H)
+{
+ int Index;
+
+ if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != 0xFFFFFFFF) {
+ return XST_FAILURE;
+ }
+
+ for (Index = 0; Index < PARTITION_HDR_WORD_COUNT - 1; Index++) {
+
+ if (H->Fields[Index] != 0x0) {
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function validates the partition header.
+*
+* @param Header Partition header pointer
+*
+* @return
+* - XST_FAILURE if bad header.
+* - XST_SUCCESS if successful.
+*
+* @note None
+*
+*******************************************************************************/
+u32 ValidateHeader(PartHeader *Header)
+{
+ struct HeaderArray *Hap;
+
+ Hap = (struct HeaderArray *)Header;
+
+ /*
+ * If there are no partitions to load, fail
+ */
+ if (IsEmptyHeader(Hap) == XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "IMAGE_HAS_NO_PARTITIONS\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Validate partition header checksum
+ */
+ if (ValidatePartitionHeaderChecksum(Hap) != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "PARTITION_HEADER_CORRUPTION\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Validate partition data size
+ */
+ if (Header->ImageWordLen > MAXIMUM_IMAGE_WORD_LEN) {
+ fsbl_printf(DEBUG_GENERAL, "INVALID_PARTITION_LENGTH\r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+* This function check whether the current partition header is empty.
+* A partition header is considered empty if image word length is 0 and the
+* last word is 0.
+*
+* @param H is a pointer to struct HeaderArray
+*
+* @return
+* - XST_SUCCESS , If the partition header is empty
+* - XST_FAILURE , If the partition header is NOT empty
+*
+* @note Caller is responsible to make sure the address is valid.
+*
+*
+****************************************************************************/
+u32 IsEmptyHeader(struct HeaderArray *H)
+{
+ int Index;
+
+ for (Index = 0; Index < PARTITION_HDR_WORD_COUNT; Index++) {
+ if (H->Fields[Index] != 0x0) {
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function checks the header checksum If the header checksum is not valid
+* XST_FAILURE is returned.
+*
+* @param H is a pointer to struct HeaderArray
+*
+* @return
+* - XST_SUCCESS is header checksum is ok
+* - XST_FAILURE if the header checksum is not correct
+*
+* @note None.
+*
+****************************************************************************/
+u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H)
+{
+ u32 Checksum;
+ u32 Count;
+
+ Checksum = 0;
+
+ for (Count = 0; Count < PARTITION_HDR_CHECKSUM_WORD_COUNT; Count++) {
+ /*
+ * Read the word from the header
+ */
+ Checksum += H->Fields[Count];
+ }
+
+ /*
+ * Invert checksum, last bit of error checking
+ */
+ Checksum ^= 0xFFFFFFFF;
+
+ /*
+ * Validate the checksum
+ */
+ if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) {
+ fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8lx != 0x%8.8lx\r\n",
+ Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function load the partition from boot device
+*
+* @param ImageBaseAddress Base address on flash
+* @param Header Partition header pointer
+*
+* @return
+* - XST_SUCCESS if partition move successful
+* - XST_FAILURE if check failed move failed
+*
+* @note None
+*
+*******************************************************************************/
+u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header)
+{
+ u32 SourceAddr;
+ u32 Status;
+ u8 SecureTransferFlag = 0;
+ u32 LoadAddr;
+ u32 ImageWordLen;
+ u32 DataWordLen;
+
+ SourceAddr = ImageBaseAddress;
+ SourceAddr += Header->PartitionStart<LoadAddr;
+ ImageWordLen = Header->ImageWordLen;
+ DataWordLen = Header->DataWordLen;
+
+ /*
+ * Add flash base address for linear boot devices
+ */
+ if (LinearBootDeviceFlag) {
+ SourceAddr += FlashReadBaseAddress;
+ }
+
+ /*
+ * Partition encrypted
+ */
+ if(EncryptedPartitionFlag) {
+ SecureTransferFlag = 1;
+ }
+
+ /*
+ * For Signed or checksum enabled partition,
+ * Total partition image need to copied to DDR
+ */
+ if (SignedPartitionFlag || PartitionChecksumFlag) {
+ ImageWordLen = Header->PartitionWordLen;
+ DataWordLen = Header->PartitionWordLen;
+ }
+
+ /*
+ * Encrypted and Signed PS partition need to be loaded on to DDR
+ * without decryption
+ */
+ if (PSPartitionFlag &&
+ (SignedPartitionFlag || PartitionChecksumFlag) &&
+ EncryptedPartitionFlag) {
+ SecureTransferFlag = 0;
+ }
+
+ /*
+ * CPU is used for data transfer in case of non-linear
+ * boot device
+ */
+ if (!LinearBootDeviceFlag) {
+ /*
+ * PL partition copied to DDR temporary location
+ */
+ if (PLPartitionFlag) {
+ LoadAddr = DDR_TEMP_START_ADDR;
+ }
+
+ Status = MoveImage(SourceAddr,
+ LoadAddr,
+ (ImageWordLen << WORD_LENGTH_SHIFT));
+ if(Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "Move Image Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * As image present at load address
+ */
+ SourceAddr = LoadAddr;
+ }
+
+ if ((LinearBootDeviceFlag && PLPartitionFlag &&
+ (SignedPartitionFlag || PartitionChecksumFlag)) ||
+ (LinearBootDeviceFlag && PSPartitionFlag) ||
+ ((!LinearBootDeviceFlag) && PSPartitionFlag && SecureTransferFlag)) {
+ /*
+ * PL signed partition copied to DDR temporary location
+ * using non-secure PCAP for linear boot device
+ */
+ if(PLPartitionFlag){
+ SecureTransferFlag = 0;
+ LoadAddr = DDR_TEMP_START_ADDR;
+ }
+
+ /*
+ * Data transfer using PCAP
+ */
+ Status = PcapDataTransfer((u32*)SourceAddr,
+ (u32*)LoadAddr,
+ ImageWordLen,
+ DataWordLen,
+ SecureTransferFlag);
+ if(Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "PCAP Data Transfer Failed\r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * As image present at load address
+ */
+ SourceAddr = LoadAddr;
+ }
+
+ /*
+ * Load Bitstream partition in to fabric only
+ * if checksum and authentication bits are not set
+ */
+ if (PLPartitionFlag && (!(SignedPartitionFlag || PartitionChecksumFlag))) {
+ Status = PcapLoadPartition((u32*)SourceAddr,
+ (u32*)Header->LoadAddr,
+ Header->ImageWordLen,
+ Header->DataWordLen,
+ EncryptedPartitionFlag);
+ if(Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL, "PCAP Bitstream Download Failed\r\n");
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function load the decrypts partition
+*
+* @param StartAddr Source start address
+* @param DataLength Data length in words
+* @param ImageLength Image length in words
+*
+* @return
+* - XST_SUCCESS if decryption successful
+* - XST_FAILURE if decryption failed
+*
+* @note None
+*
+*******************************************************************************/
+u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength)
+{
+ u32 Status;
+ u8 SecureTransferFlag =1;
+
+ /*
+ * Data transfer using PCAP
+ */
+ Status = PcapDataTransfer((u32*)StartAddr,
+ (u32*)StartAddr,
+ ImageLength,
+ DataLength,
+ SecureTransferFlag);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PCAP Data Transfer failed \r\n");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function Validate Partition Data by using checksum preset in image
+*
+* @param Partition header pointer
+* @param Partition check sum offset
+* @return
+* - XST_SUCCESS if partition data is ok
+* - XST_FAILURE if partition data is corrupted
+*
+* @note None
+*
+*******************************************************************************/
+u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset)
+{
+ u8 Checksum[MD5_CHECKSUM_SIZE];
+ u8 CalcChecksum[MD5_CHECKSUM_SIZE];
+ u32 Status;
+ u32 Index;
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * Get checksum from flash
+ */
+ Status = GetPartitionChecksum(ChecksumOffset, &Checksum[0]);
+ if(Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO, "Actual checksum\r\n");
+
+ for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
+ fsbl_printf(DEBUG_INFO, "0x%0x ",Checksum[Index]);
+ }
+
+ fsbl_printf(DEBUG_INFO, "\r\n");
+
+ /*
+ * Calculate checksum for the partition
+ */
+ Status = CalcPartitionChecksum(StartAddr, Length, &CalcChecksum[0]);
+ if(Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO, "Calculated checksum\r\n");
+
+ for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
+ fsbl_printf(DEBUG_INFO, "0x%0x ",CalcChecksum[Index]);
+ }
+
+ fsbl_printf(DEBUG_INFO, "\r\n");
+
+ /*
+ * Compare actual checksum with the calculated checksum
+ */
+ for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
+ if(Checksum[Index] != CalcChecksum[Index]) {
+ fsbl_printf(DEBUG_GENERAL, "Error: "
+ "Partition DataChecksum 0x%0x!= 0x%0x\r\n",
+ Checksum[Index], CalcChecksum[Index]);
+ return XST_FAILURE;
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function gets partition checksum from flash
+*
+* @param Check sum offset
+* @param Checksum pointer
+* @return
+* - XST_SUCCESS if checksum read success
+* - XST_FAILURE if unable get checksum
+*
+* @note None
+*
+*******************************************************************************/
+u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum)
+{
+ u32 Status;
+
+ Status = MoveImage(ChecksumOffset, (u32)Checksum, MD5_CHECKSUM_SIZE);
+ if(Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function calculates the checksum preset in image
+*
+* @param Start address
+* @param Length of the data
+* @param Checksum pointer
+*
+* @return
+* - XST_SUCCESS if Checksum calculate successful
+* - XST_FAILURE if Checksum calculate failed
+*
+* @note None
+*
+*******************************************************************************/
+u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum)
+{
+ /*
+ * Calculate checksum using MD5 algorithm
+ */
+ md5((u8*)SourceAddr, DataLength, Checksum, 0 );
+
+ return XST_SUCCESS;
+}
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.h
new file mode 100644
index 0000000..0a7a437
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.h
@@ -0,0 +1,157 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file image_mover.h
+*
+* This file contains the interface for moving the image from FLASH to OCM
+
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 03/04/11 Initial release
+* 2.00a jz 06/04/11 partition header expands to 12 words
+* 5.00a kc 07/30/13 Added defines for image header information
+* 8.00a kc 01/16/13 Added defines for partition owner attribute
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___IMAGE_MOVER_H___
+#define ___IMAGE_MOVER_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+
+/************************** Constant Definitions *****************************/
+#define PARTITION_NUMBER_SHIFT 24
+#define MAX_PARTITION_NUMBER (0xE)
+
+/* Boot Image Header defines */
+#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */
+#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */
+#define IMAGE_HEADER_SIZE (64)
+#define IMAGE_HEADER_TABLE_SIZE (64)
+#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
+#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
+#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \
+ TOTAL_IMAGE_HEADER_SIZE + \
+ TOTAL_PARTITION_HEADER_SIZE + 64)
+
+/* Partition Header defines */
+#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */
+#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */
+#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */
+#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */
+#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */
+#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */
+#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */
+#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */
+#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */
+#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */
+#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/
+
+/* Attribute word defines */
+#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */
+#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */
+#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */
+#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */
+#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */
+#define ATTRIBUTE_PARTITION_OWNER_MASK 0x30000 /* Partition Owner */
+
+#define ATTRIBUTE_PARTITION_OWNER_FSBL 0x00000 /* FSBL Partition Owner */
+
+
+/**************************** Type Definitions *******************************/
+typedef u32 (*ImageMoverType)( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthBytes);
+
+typedef struct StructPartHeader {
+ u32 ImageWordLen; /* 0x0 */
+ u32 DataWordLen; /* 0x4 */
+ u32 PartitionWordLen; /* 0x8 */
+ u32 LoadAddr; /* 0xC */
+ u32 ExecAddr; /* 0x10 */
+ u32 PartitionStart; /* 0x14 */
+ u32 PartitionAttr; /* 0x18 */
+ u32 SectionCount; /* 0x1C */
+ u32 CheckSumOffset; /* 0x20 */
+ u32 Pads1[1];
+ u32 ACOffset; /* 0x28 */
+ u32 Pads2[4];
+ u32 CheckSum; /* 0x3C */
+}PartHeader;
+
+struct HeaderArray {
+ u32 Fields[16];
+};
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MoverIn32 Xil_In32
+#define MoverOut32 Xil_Out32
+
+/************************** Function Prototypes ******************************/
+u32 LoadBootImage(void);
+u32 GetPartitionHeaderInfo(u32 ImageBaseAddress);
+u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header);
+u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H);
+u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset);
+u32 GetImageHeaderAndSignature(u32 ImageAddress, u32 *Offset);
+u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength);
+u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header);
+u32 IsEmptyHeader(struct HeaderArray *H);
+u32 IsLastPartition(struct HeaderArray *H);
+void HeaderDump(PartHeader *Header);
+u32 GetPartitionCount(PartHeader *Header);
+u32 ValidateHeader(PartHeader *Header);
+u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___IMAGE_MOVER_H___ */
+
+
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/lscript.ld b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/lscript.ld
new file mode 100644
index 0000000..f6dad63
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/lscript.ld
@@ -0,0 +1,309 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
+
+_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+ ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
+ ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+
+SECTIONS
+{
+.text : {
+ *(.vectors)
+ *(.boot)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu_warning)
+ *(.gcc_execpt_table)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.ARM.extab)
+ *(.gnu.linkonce.armextab.*)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.init : {
+ KEEP (*(.init))
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.fini : {
+ KEEP (*(.fini))
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.rodata : {
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.rodata1 : {
+ __rodata1_start = .;
+ *(.rodata1)
+ *(.rodata1.*)
+ __rodata1_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sdata2 : {
+ __sdata2_start = .;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ __sdata2_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sbss2 : {
+ __sbss2_start = .;
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ __sbss2_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.data : {
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ *(.jcr)
+ *(.got)
+ *(.got.plt)
+ __data_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.data1 : {
+ __data1_start = .;
+ *(.data1)
+ *(.data1.*)
+ __data1_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.got : {
+ *(.got)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.ctors : {
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.dtors : {
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.fixup : {
+ __fixup_start = .;
+ *(.fixup)
+ __fixup_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.eh_frame : {
+ *(.eh_frame)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.eh_framehdr : {
+ __eh_framehdr_start = .;
+ *(.eh_framehdr)
+ __eh_framehdr_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.mmu_tbl (ALIGN(0x4000)): {
+ __mmu_tbl_start = .;
+ *(.mmu_tbl)
+ __mmu_tbl_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ *(.gnu.linkonce.armexidix.*.*)
+ __exidx_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.preinit_array : {
+ __preinit_array_start = .;
+ KEEP (*(SORT(.preinit_array.*)))
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.init_array : {
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.fini_array : {
+ __fini_array_start = .;
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array))
+ __fini_array_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.rsa_ac : {
+ . = ALIGN(64);
+ __rsa_ac_start = .;
+ . += _RSA_AC_SIZE;
+ __rsa_ac_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.ARM.attributes : {
+ __ARM.attributes_start = .;
+ *(.ARM.attributes)
+ __ARM.attributes_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sdata : {
+ __sdata_start = .;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __sdata_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.sbss (NOLOAD) : {
+ __sbss_start = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ __sbss_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.tdata : {
+ __tdata_start = .;
+ *(.tdata)
+ *(.tdata.*)
+ *(.gnu.linkonce.td.*)
+ __tdata_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.tbss : {
+ __tbss_start = .;
+ *(.tbss)
+ *(.tbss.*)
+ *(.gnu.linkonce.tb.*)
+ __tbss_end = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.bss (NOLOAD) : {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end = .;
+ __bss_end__ = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+ . = ALIGN(16);
+ _heap = .;
+ HeapBase = .;
+ _heap_start = .;
+ . += _HEAP_SIZE;
+ _heap_end = .;
+ HeapLimit = .;
+} > ps7_ram_0_S_AXI_BASEADDR
+
+.stack (NOLOAD) : {
+ . = ALIGN(16);
+ _stack_end = .;
+ . += _STACK_SIZE;
+ _stack = .;
+ __stack = _stack;
+ . = ALIGN(16);
+ _irq_stack_end = .;
+ . += _STACK_SIZE;
+ __irq_stack = .;
+ _supervisor_stack_end = .;
+ . += _SUPERVISOR_STACK_SIZE;
+ . = ALIGN(16);
+ __supervisor_stack = .;
+ _abort_stack_end = .;
+ . += _ABORT_STACK_SIZE;
+ . = ALIGN(16);
+ __abort_stack = .;
+ _fiq_stack_end = .;
+ . += _FIQ_STACK_SIZE;
+ . = ALIGN(16);
+ __fiq_stack = .;
+ _undef_stack_end = .;
+ . += _UNDEF_STACK_SIZE;
+ . = ALIGN(16);
+ __undef_stack = .;
+} > ps7_ram_1_S_AXI_BASEADDR
+
+_end = .;
+}
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/main.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/main.c
new file mode 100644
index 0000000..51113a5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/main.c
@@ -0,0 +1,1543 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file main.c
+*
+* The main file for the First Stage Boot Loader (FSBL).
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 06/04/11 Initial release
+* 2.00a mb 25/05/12 standalone based FSBL
+* 3.00a np/mb 08/03/12 Added call to FSBL user hook - before handoff.
+* DDR ECC initialization added
+* fsbl print with verbose added
+* Performance measurement added
+* Flushed the UART Tx buffer
+* Added the performance time for ECC DDR init
+* Added clearing of ECC Error Code
+* Added the watchdog timer value
+* 4.00a sgd 02/28/13 Code Cleanup
+* Fix for CR#681014 - ECC init in FSBL should not
+* call fabric_init()
+* Fix for CR#689077 - FSBL hangs at Handoff clearing the
+* TX UART buffer when using UART0
+* instead of UART1
+* Fix for CR#694038 - FSBL debug logs always prints 14.3
+* as the Revision number - this is
+* incorrect
+* Fix for CR#694039 - FSBL prints "unsupported silicon
+* version for v3.0" 3.0 Silicon
+* Fix for CR#699475 - FSBL functionality is broken and
+* its not able to boot in QSPI/NAND
+* bootmode
+* Removed DDR initialization check
+* Removed DDR ECC initialization code
+* Modified hand off address check to 1MB
+* Added RSA authentication support
+* Watchdog disabled for AES E-Fuse encryption
+* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
+* Fix for CR#708728 - Issues seen while making HP
+* interconnect 32 bit wide
+* 6.00a kc 07/30/13 Fix for CR#708316 - PS7_init.tcl file should have
+* Error mechanism for all mask_poll
+* Fix for CR#691150 - ps7_init does not check for
+* peripheral initialization failures
+* or timeout on polls
+* Fix for CR#724165 - Partition Header used by FSBL is
+* not authenticated
+* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+* by Boot ROM for authenticating
+* the Partition images
+* Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* Fix for CR#732865 - Backward compatibility for ps7_init
+* function
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+* 8.00a kc 02/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
+* is not proper
+* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
+* fallback unless FSBL* and FSBL
+* are identical in length
+* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
+* kc 08/27/14 Fix for CR#820356 - FSBL compilation fails with
+* IAR compiler
+* 11.00a kv 10/08/14 Fix for CR#826030 - LinearBootDeviceFlag should
+* be initialized to 0 in IO mode
+* case
+* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
+* In pcap.c/pcap.h/main.c,
+* Fabric Initialization sequence
+* is modified to check the PL power
+* before sequence starts and checking
+* INIT_B reset status twice in case
+* of failure.
+* 16.00a bsv 03/26/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
+* to enable level shifters in jtag boot mode.
+*
+*
+* @note
+* FSBL runs from OCM, Based on the boot mode selected, FSBL will copy
+* the partitions from the flash device. If the partition is bitstream then
+* the bitstream is programmed in the Fabric and for an partition that is
+* an application , FSBL will copy the application into DDR and does a
+* handoff.The application should not be starting at the OCM address,
+* FSBL does not remap the DDR. Application should use DDR starting from 1MB
+*
+* FSBL can be stitched along with bitstream and application using bootgen
+*
+* Refer to fsbl.h file for details on the compilation flags supported in FSBL
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "fsbl.h"
+#include "qspi.h"
+#include "nand.h"
+#include "nor.h"
+#include "sd.h"
+#include "pcap.h"
+#include "image_mover.h"
+#include "xparameters.h"
+#include "xil_cache.h"
+#include "xil_exception.h"
+#include "xstatus.h"
+#include "fsbl_hooks.h"
+#include "xtime_l.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+
+#ifdef STDOUT_BASEADDRESS
+#ifdef XPAR_XUARTPS_0_BASEADDR
+#include "xuartps_hw.h"
+#endif
+#endif
+
+#ifdef RSA_SUPPORT
+#include "rsa.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#define WDT_DEVICE_ID XPAR_XWDTPS_0_DEVICE_ID
+#define WDT_EXPIRE_TIME 100
+#define WDT_CRV_SHIFT 12
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+/************************** Function Prototypes ******************************/
+extern int ps7_init();
+extern char* getPS7MessageInfo(unsigned key);
+#ifdef PS7_POST_CONFIG
+extern int ps7_post_config();
+#endif
+
+static void Update_MultiBootRegister(void);
+/* Exception handlers */
+static void RegisterHandlers(void);
+static void Undef_Handler (void);
+static void SVC_Handler (void);
+static void PreFetch_Abort_Handler (void);
+static void Data_Abort_Handler (void);
+static void IRQ_Handler (void);
+static void FIQ_Handler (void);
+
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+int InitWatchDog(void);
+u32 ConvertTime_WdtCounter(u32 seconds);
+void CheckWDTReset(void);
+#endif
+
+u32 NextValidImageCheck(void);
+
+u32 DDRInitCheck(void);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Base Address for the Read Functionality for Image Processing
+ */
+u32 FlashReadBaseAddress = 0;
+/*
+ * Silicon Version
+ */
+u32 Silicon_Version;
+
+/*
+ * Boot Device flag
+ */
+u8 LinearBootDeviceFlag=0;
+
+u32 PcapCtrlRegVal;
+
+u8 SystemInitFlag;
+
+extern ImageMoverType MoveImage;
+extern XDcfg *DcfgInstPtr;
+extern u8 BitstreamFlag;
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+extern u32 QspiFlashSize;
+#endif
+/*****************************************************************************/
+/**
+*
+* This is the main function for the FSBL ROM code.
+*
+*
+* @param None.
+*
+* @return
+* - XST_SUCCESS to indicate success
+* - XST_FAILURE.to indicate failure
+*
+* @note
+*
+****************************************************************************/
+int main(void)
+{
+ u32 BootModeRegister = 0;
+ u32 HandoffAddress = 0;
+ u32 Status = XST_SUCCESS;
+ u32 RegVal;
+ /*
+ * PCW initialization for MIO,PLL,CLK and DDR
+ */
+ Status = ps7_init();
+ if (Status != FSBL_PS7_INIT_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"PS7_INIT_FAIL : %s\r\n",
+ getPS7MessageInfo(Status));
+ OutputStatus(PS7_INIT_FAIL);
+ /*
+ * Calling FsblHookFallback instead of Fallback
+ * since, devcfg driver is not yet initialized
+ */
+ FsblHookFallback();
+ }
+
+ /*
+ * Unlock SLCR for SLCR register write
+ */
+ SlcrUnlock();
+
+ /* If Performance measurement is required
+ * then read the Global Timer value , Please note that the
+ * time taken for mio, clock and ddr initialisation
+ * done in the ps7_init function is not accounted in the FSBL
+ *
+ */
+#ifdef FSBL_PERF
+ XTime tCur = 0;
+ FsblGetGlobalTime(&tCur);
+#endif
+
+ /*
+ * Flush the Caches
+ */
+ Xil_DCacheFlush();
+
+ /*
+ * Disable Data Cache
+ */
+ Xil_DCacheDisable();
+
+ /*
+ * Register the Exception handlers
+ */
+ RegisterHandlers();
+
+ /*
+ * Print the FSBL Banner
+ */
+ fsbl_printf(DEBUG_GENERAL,"\n\rXilinx First Stage Boot Loader \n\r");
+ fsbl_printf(DEBUG_GENERAL,"Release %d.%d %s-%s\r\n",
+ SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER,
+ __DATE__,__TIME__);
+
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+
+ /*
+ * DDR Read/write test
+ */
+ Status = DDRInitCheck();
+ if (Status == XST_FAILURE) {
+ fsbl_printf(DEBUG_GENERAL,"DDR_INIT_FAIL \r\n");
+ /* Error Handling here */
+ OutputStatus(DDR_INIT_FAIL);
+ /*
+ * Calling FsblHookFallback instead of Fallback
+ * since, devcfg driver is not yet initialized
+ */
+ FsblHookFallback();
+ }
+
+
+ /*
+ * PCAP initialization
+ */
+ Status = InitPcap();
+ if (Status == XST_FAILURE) {
+ fsbl_printf(DEBUG_GENERAL,"PCAP_INIT_FAIL \n\r");
+ OutputStatus(PCAP_INIT_FAIL);
+ /*
+ * Calling FsblHookFallback instead of Fallback
+ * since, devcfg driver is not yet initialized
+ */
+ FsblHookFallback();
+ }
+
+ fsbl_printf(DEBUG_INFO,"Devcfg driver initialized \r\n");
+
+ /*
+ * Get the Silicon Version
+ */
+ GetSiliconVersion();
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Check if WDT Reset has occurred or not
+ */
+ CheckWDTReset();
+
+ /*
+ * Initialize the Watchdog Timer so that it is ready to use
+ */
+ Status = InitWatchDog();
+ if (Status == XST_FAILURE) {
+ fsbl_printf(DEBUG_GENERAL,"WATCHDOG_INIT_FAIL \n\r");
+ OutputStatus(WDT_INIT_FAIL);
+ FsblFallback();
+ }
+ fsbl_printf(DEBUG_INFO,"Watchdog driver initialized \r\n");
+#endif
+
+ /*
+ * Get PCAP controller settings
+ */
+ PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * For E-Fuse AES encryption Watch dog Timer disabled and
+ * User not allowed to do system reset
+ */
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ fsbl_printf(DEBUG_INFO,"Watchdog Timer Disabled\r\n");
+ XWdtPs_Stop(&Watchdog);
+#endif
+ fsbl_printf(DEBUG_INFO,"User not allowed to do "
+ "any system resets\r\n");
+ }
+
+ /*
+ * Store FSBL run state in Reboot Status Register
+ */
+ MarkFSBLIn();
+
+ /*
+ * Read bootmode register
+ */
+ BootModeRegister = Xil_In32(BOOT_MODE_REG);
+ BootModeRegister &= BOOT_MODES_MASK;
+
+ /*
+ * QSPI BOOT MODE
+ */
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+
+#ifdef MMC_SUPPORT
+ /*
+ * To support MMC boot
+ * QSPI boot mode detection ignored
+ */
+ if (BootModeRegister == QSPI_MODE) {
+ BootModeRegister = MMC_MODE;
+ }
+#endif
+
+ if (BootModeRegister == QSPI_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is QSPI\n\r");
+ InitQspi();
+ MoveImage = QspiAccess;
+ fsbl_printf(DEBUG_INFO,"QSPI Init Done \r\n");
+ } else
+#endif
+
+ /*
+ * NAND BOOT MODE
+ */
+#ifdef XPAR_PS7_NAND_0_BASEADDR
+ if (BootModeRegister == NAND_FLASH_MODE) {
+ /*
+ * Boot ROM always initialize the nand at lower speed
+ * This is the chance to put it to an optimum speed for your nand
+ * device
+ */
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is NAND\n");
+
+ Status = InitNand();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"NAND_INIT_FAIL \r\n");
+ /*
+ * Error Handling here
+ */
+ OutputStatus(NAND_INIT_FAIL);
+ FsblFallback();
+ }
+ MoveImage = NandAccess;
+ fsbl_printf(DEBUG_INFO,"NAND Init Done \r\n");
+ } else
+#endif
+
+ /*
+ * NOR BOOT MODE
+ */
+ if (BootModeRegister == NOR_FLASH_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is NOR\n\r");
+ /*
+ * Boot ROM always initialize the nor at lower speed
+ * This is the chance to put it to an optimum speed for your nor
+ * device
+ */
+ InitNor();
+ fsbl_printf(DEBUG_INFO,"NOR Init Done \r\n");
+ MoveImage = NorAccess;
+ } else
+
+ /*
+ * SD BOOT MODE
+ */
+#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
+
+ if (BootModeRegister == SD_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is SD\r\n");
+
+ /*
+ * SD initialization returns file open error or success
+ */
+ Status = InitSD("BOOT.BIN");
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"SD_INIT_FAIL\r\n");
+ OutputStatus(SD_INIT_FAIL);
+ FsblFallback();
+ }
+ MoveImage = SDAccess;
+ fsbl_printf(DEBUG_INFO,"SD Init Done \r\n");
+ } else
+
+ if (BootModeRegister == MMC_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Booting Device is MMC\r\n");
+
+ /*
+ * MMC initialization returns file open error or success
+ */
+ Status = InitSD("BOOT.BIN");
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"MMC_INIT_FAIL\r\n");
+ OutputStatus(SD_INIT_FAIL);
+ FsblFallback();
+ }
+ MoveImage = SDAccess;
+ fsbl_printf(DEBUG_INFO,"MMC Init Done \r\n");
+ } else
+
+#endif
+
+ /*
+ * JTAG BOOT MODE
+ */
+ if (BootModeRegister == JTAG_MODE) {
+ fsbl_printf(DEBUG_GENERAL,"Boot mode is JTAG\r\n");
+
+ RegVal = Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET);
+ /** If bitstream was loaded in jtag boot mode prior to running FSBL */
+ if(RegVal & XDCFG_IXR_PCFG_DONE_MASK)
+ {
+#ifdef PS7_POST_CONFIG
+ ps7_post_config();
+ /*
+ * Unlock SLCR for SLCR register write
+ */
+ SlcrUnlock();
+#endif
+ }
+ /*
+ * Stop the Watchdog before JTAG handoff
+ */
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ XWdtPs_Stop(&Watchdog);
+#endif
+ /*
+ * Clear our mark in reboot status register
+ */
+ ClearFSBLIn();
+
+ /*
+ * SLCR lock
+ */
+ SlcrLock();
+
+ FsblHandoffJtagExit();
+ } else {
+ fsbl_printf(DEBUG_GENERAL,"ILLEGAL_BOOT_MODE \r\n");
+ OutputStatus(ILLEGAL_BOOT_MODE);
+ /*
+ * fallback starts, no return
+ */
+ FsblFallback();
+ }
+
+ fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08lx\r\n", FlashReadBaseAddress);
+
+ /*
+ * Check for valid flash address
+ */
+ if ((FlashReadBaseAddress != XPS_QSPI_LINEAR_BASEADDR) &&
+ (FlashReadBaseAddress != XPS_NAND_BASEADDR) &&
+ (FlashReadBaseAddress != XPS_NOR_BASEADDR) &&
+ (FlashReadBaseAddress != XPS_SDIO0_BASEADDR)) {
+ fsbl_printf(DEBUG_GENERAL,"INVALID_FLASH_ADDRESS \r\n");
+ OutputStatus(INVALID_FLASH_ADDRESS);
+ FsblFallback();
+ }
+
+ /*
+ * NOR and QSPI (parallel) are linear boot devices
+ */
+ if ((FlashReadBaseAddress == XPS_NOR_BASEADDR)) {
+ fsbl_printf(DEBUG_INFO, "Linear Boot Device\r\n");
+ LinearBootDeviceFlag = 1;
+ }
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * This used only in case of E-Fuse encryption
+ * For image search
+ */
+ SystemInitFlag = 1;
+
+ /*
+ * Load boot image
+ */
+ HandoffAddress = LoadBootImage();
+
+ fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08lx\r\n",HandoffAddress);
+
+ /*
+ * For Performance measurement
+ */
+#ifdef FSBL_PERF
+ XTime tEnd = 0;
+ fsbl_printf(DEBUG_GENERAL,"Total Execution time is ");
+ FsblMeasurePerfTime(tCur,tEnd);
+#endif
+
+ /*
+ * FSBL handoff to valid handoff address or
+ * exit in JTAG
+ */
+ FsblHandoff(HandoffAddress);
+
+#else
+ OutputStatus(NO_DDR);
+ FsblFallback();
+#endif
+
+ return Status;
+}
+
+/******************************************************************************/
+/**
+*
+* This function reset the CPU and goes for Boot ROM fallback handling
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void FsblFallback(void)
+{
+ u32 RebootStatusReg;
+ u32 Status;
+ u32 HandoffAddr;
+ u32 BootModeRegister;
+
+ /*
+ * Read bootmode register
+ */
+ BootModeRegister = Xil_In32(BOOT_MODE_REG);
+ BootModeRegister &= BOOT_MODES_MASK;
+
+ /*
+ * Fallback support check
+ */
+ if (!((BootModeRegister == QSPI_MODE) ||
+ (BootModeRegister == NAND_FLASH_MODE) ||
+ (BootModeRegister == NOR_FLASH_MODE))) {
+ fsbl_printf(DEBUG_INFO,"\r\n"
+ "This Boot Mode Doesn't Support Fallback\r\n");
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+
+ /*
+ * update the Multiboot Register for Golden search hunt
+ */
+ Update_MultiBootRegister();
+
+ /*
+ * Notify Boot ROM something is wrong
+ */
+ RebootStatusReg = Xil_In32(REBOOT_STATUS_REG);
+
+ /*
+ * Set the FSBL Fail mask
+ */
+ Xil_Out32(REBOOT_STATUS_REG, RebootStatusReg | FSBL_FAIL_MASK);
+
+ /*
+ * Barrier for synchronization
+ */
+ __asm(
+ "dsb\n\t"
+ "isb"
+ );
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * Next valid image search can happen only
+ * when system initialization done
+ */
+ if (SystemInitFlag == 1) {
+ /*
+ * Clean the Fabric
+ */
+ Status = FabricInit();
+ if(Status != XST_SUCCESS){
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+
+#ifdef RSA_SUPPORT
+
+ /*
+ * Making sure PPK is set for efuse error cases
+ */
+ SetPpk();
+#endif
+
+ /*
+ * Search for next valid image
+ */
+ Status = NextValidImageCheck();
+ if(Status != XST_SUCCESS){
+ fsbl_printf(DEBUG_INFO,"\r\nNo Image Found\r\n");
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+
+ /*
+ * Load next valid image
+ */
+ HandoffAddr = LoadBootImage();
+
+ /*
+ * Handoff to next image
+ */
+ FsblHandoff(HandoffAddr);
+ } else {
+ fsbl_printf(DEBUG_INFO,"System Initialization Failed\r\n");
+ fsbl_printf(DEBUG_INFO,"\r\nNo Image Search\r\n");
+ ClearFSBLIn();
+ FsblHookFallback();
+ }
+ }
+
+ /*
+ * Reset PS, so Boot ROM will restart
+ */
+ Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function hands the A9/PS to the loaded user code.
+*
+* @param none
+*
+* @return none
+*
+* @note This function does not return.
+*
+****************************************************************************/
+void FsblHandoff(u32 FsblStartAddr)
+{
+ u32 Status;
+
+ /*
+ * Enable level shifter
+ */
+ if(BitstreamFlag) {
+ /*
+ * FSBL will not enable the level shifters for a NON PS instantiated
+ * Bitstream
+ * CR# 671028
+ * This flag can be set during compilation for a NON PS instantiated
+ * bitstream
+ */
+#ifndef NON_PS_INSTANTIATED_BITSTREAM
+#ifdef PS7_POST_CONFIG
+ ps7_post_config();
+ /*
+ * Unlock SLCR for SLCR register write
+ */
+ SlcrUnlock();
+#else
+ /*
+ * Set Level Shifters DT618760
+ */
+ Xil_Out32(PS_LVL_SHFTR_EN, LVL_PL_PS);
+ fsbl_printf(DEBUG_INFO,"Enabling Level Shifters PL to PS "
+ "Address = 0x%x Value = 0x%x \n\r",
+ PS_LVL_SHFTR_EN, Xil_In32(PS_LVL_SHFTR_EN));
+
+ /*
+ * Enable AXI interface
+ */
+ Xil_Out32(FPGA_RESET_REG, 0);
+ fsbl_printf(DEBUG_INFO,"AXI Interface enabled \n\r");
+ fsbl_printf(DEBUG_INFO, "FPGA Reset Register "
+ "Address = 0x%x , Value = 0x%x \r\n",
+ FPGA_RESET_REG ,Xil_In32(FPGA_RESET_REG));
+#endif
+#endif
+ }
+
+ /*
+ * FSBL user hook call before handoff to the application
+ */
+ Status = FsblHookBeforeHandoff();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"FSBL_HANDOFF_HOOK_FAIL\r\n");
+ OutputStatus(FSBL_HANDOFF_HOOK_FAIL);
+ FsblFallback();
+ }
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ XWdtPs_Stop(&Watchdog);
+#endif
+
+ /*
+ * Clear our mark in reboot status register
+ */
+ ClearFSBLIn();
+
+ if(FsblStartAddr == 0) {
+ /*
+ * SLCR lock
+ */
+ SlcrLock();
+
+ fsbl_printf(DEBUG_INFO,"No Execution Address JTAG handoff \r\n");
+ FsblHandoffJtagExit();
+ } else {
+ fsbl_printf(DEBUG_GENERAL,"SUCCESSFUL_HANDOFF\r\n");
+ OutputStatus(SUCCESSFUL_HANDOFF);
+ FsblHandoffExit(FsblStartAddr);
+ }
+
+ OutputStatus(ILLEGAL_RETURN);
+
+ FsblFallback();
+}
+
+/******************************************************************************/
+/**
+*
+* This function outputs the status for the provided State in the boot process.
+*
+* @param State is where in the boot process the output is desired.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void OutputStatus(u32 State)
+{
+#ifdef STDOUT_BASEADDRESS
+#ifdef XPAR_XUARTPS_0_BASEADDR
+ u32 UartReg = 0;
+#endif
+
+ fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4lx\r\n", State);
+ /*
+ * The TX buffer needs to be flushed out
+ * If this is not done some of the prints will not appear on the
+ * serial output
+ */
+#ifdef XPAR_XUARTPS_0_BASEADDR
+ UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
+ while ((UartReg & XUARTPS_SR_TXEMPTY) != XUARTPS_SR_TXEMPTY) {
+ UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
+ }
+#endif
+#endif
+}
+
+/******************************************************************************/
+/**
+*
+* This function handles the error and lockdown processing and outputs the status
+* for the provided State in the boot process.
+*
+* This function is called upon exceptions.
+*
+* @param State - where in the boot process the error occured.
+*
+* @return None.
+*
+* @note This function does not return, the PS block is reset
+*
+****************************************************************************/
+void ErrorLockdown(u32 State)
+{
+ /*
+ * Store the error status
+ */
+ OutputStatus(State);
+
+ /*
+ * Fall back
+ */
+ FsblFallback();
+}
+
+/******************************************************************************/
+/**
+*
+* This function copies a memory region to another memory region
+*
+* @param s1 is starting address for destination
+* @param s2 is starting address for the source
+* @param n is the number of bytes to copy
+*
+* @return Starting address for destination
+*
+****************************************************************************/
+void *(memcpy_rom)(void * s1, const void * s2, u32 n)
+{
+ char *dst = (char *)s1;
+ const char *src = (char *)s2;
+
+ /*
+ * Loop and copy
+ */
+ while (n-- != 0)
+ *dst++ = *src++;
+ return s1;
+}
+/******************************************************************************/
+/**
+*
+* This function copies a string to another, the source string must be null-
+* terminated.
+*
+* @param Dest is starting address for the destination string
+* @param Src is starting address for the source string
+*
+* @return Starting address for the destination string
+*
+****************************************************************************/
+char *strcpy_rom(char *Dest, const char *Src)
+{
+ unsigned i;
+ for (i=0; Src[i] != '\0'; ++i)
+ Dest[i] = Src[i];
+ Dest[i] = '\0';
+ return Dest;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function sets FSBL is running mask in reboot status register
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void MarkFSBLIn(void)
+{
+ Xil_Out32(REBOOT_STATUS_REG,
+ Xil_In32(REBOOT_STATUS_REG) | FSBL_IN_MASK);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function clears FSBL is running mask in reboot status register
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void ClearFSBLIn(void)
+{
+ Xil_Out32(REBOOT_STATUS_REG,
+ (Xil_In32(REBOOT_STATUS_REG)) & ~(FSBL_FAIL_MASK));
+}
+
+/******************************************************************************/
+/**
+*
+* This function Registers the Exception Handlers
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+static void RegisterHandlers(void)
+{
+ Xil_ExceptionInit();
+
+ /*
+ * Initialize the vector table. Register the stub Handler for each
+ * exception.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
+ (Xil_ExceptionHandler)Undef_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT,
+ (Xil_ExceptionHandler)SVC_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
+ (Xil_ExceptionHandler)PreFetch_Abort_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
+ (Xil_ExceptionHandler)Data_Abort_Handler,
+ (void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)IRQ_Handler,(void *) 0);
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
+ (Xil_ExceptionHandler)FIQ_Handler,(void *) 0);
+
+ Xil_ExceptionEnable();
+
+}
+
+static void Undef_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"UNDEFINED_HANDLER\r\n");
+ ErrorLockdown (EXCEPTION_ID_UNDEFINED_INT);
+}
+
+static void SVC_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"SVC_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_SWI_INT);
+}
+
+static void PreFetch_Abort_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"PREFETCH_ABORT_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_PREFETCH_ABORT_INT);
+}
+
+static void Data_Abort_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"DATA_ABORT_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_DATA_ABORT_INT);
+}
+
+static void IRQ_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"IRQ_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_IRQ_INT);
+}
+
+static void FIQ_Handler (void)
+{
+ fsbl_printf(DEBUG_GENERAL,"FIQ_HANDLER \r\n");
+ ErrorLockdown (EXCEPTION_ID_FIQ_INT);
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function Updates the Multi boot Register to enable golden image
+* search for boot rom
+*
+* @param None
+*
+* @return
+* return none
+*
+****************************************************************************/
+static void Update_MultiBootRegister(void)
+{
+ u32 MultiBootReg = 0;
+
+ if (Silicon_Version != SILICON_VERSION_1) {
+ /*
+ * Read the mulitboot register
+ */
+ MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET);
+
+ /*
+ * Incrementing multiboot register by one
+ */
+ MultiBootReg++;
+
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET,
+ MultiBootReg);
+
+ fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08lx\r\n",
+ MultiBootReg);
+ }
+}
+
+
+/******************************************************************************
+*
+* This function reset the CPU and goes for Boot ROM fallback handling
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+*******************************************************************************/
+
+u32 GetResetReason(void)
+{
+ u32 Regval;
+
+ /* We are using REBOOT_STATUS_REG, we have to use bits 23:16 */
+ /* for storing the RESET_REASON register value*/
+ Regval = ((Xil_In32(REBOOT_STATUS_REG) >> 16) & 0xFF);
+
+ return Regval;
+}
+
+
+/******************************************************************************
+*
+* This function Gets the ticks from the Global Timer
+*
+* @param Current time
+*
+* @return
+* None
+*
+* @note None
+*
+*******************************************************************************/
+#ifdef FSBL_PERF
+void FsblGetGlobalTime (XTime *tCur)
+{
+ XTime_GetTime(tCur);
+}
+
+
+/******************************************************************************
+*
+* This function Measures the execution time
+*
+* @param Current time , End time
+*
+* @return
+* None
+*
+* @note None
+*
+*******************************************************************************/
+void FsblMeasurePerfTime (XTime tCur, XTime tEnd)
+{
+ double tDiff = 0.0;
+ double tPerfSeconds;
+ XTime_GetTime(&tEnd);
+ tDiff = (double)tEnd - (double)tCur;
+
+ /*
+ * Convert tPerf into Seconds
+ */
+ tPerfSeconds = tDiff/COUNTS_PER_SECOND;
+
+#if defined(STDOUT_BASEADDRESS)
+ printf("%f seconds \r\n",tPerfSeconds);
+#endif
+
+}
+#endif
+
+/******************************************************************************
+*
+* This function initializes the Watchdog driver and starts the timer
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if the Watchdog driver is initialized
+* - XST_FAILURE if Watchdog driver initialization fails
+*
+* @note None
+*
+*******************************************************************************/
+#ifdef XPAR_XWDTPS_0_BASEADDR
+int InitWatchDog(void)
+{
+ u32 Status = XST_SUCCESS;
+ XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */
+ u32 CounterValue = 1;
+
+ ConfigPtr = XWdtPs_LookupConfig(WDT_DEVICE_ID);
+ Status = XWdtPs_CfgInitialize(&Watchdog,
+ ConfigPtr,
+ ConfigPtr->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"Watchdog Driver init Failed \n\r");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Setting the divider value
+ */
+ XWdtPs_SetControlValue(&Watchdog,
+ XWDTPS_CLK_PRESCALE,
+ XWDTPS_CCR_PSCALE_4096);
+ /*
+ * Convert time to Watchdog counter reset value
+ */
+ CounterValue = ConvertTime_WdtCounter(WDT_EXPIRE_TIME);
+
+ /*
+ * Set the Watchdog counter reset value
+ */
+ XWdtPs_SetControlValue(&Watchdog,
+ XWDTPS_COUNTER_RESET,
+ CounterValue);
+ /*
+ * enable reset output, as we are only using this as a basic counter
+ */
+ XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL);
+
+ /*
+ * Start the Watchdog timer
+ */
+ XWdtPs_Start(&Watchdog);
+
+ XWdtPs_RestartWdt(&Watchdog);
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function checks whether WDT reset has happened during FSBL run
+*
+* If WDT reset happened during FSBL run, then need to fallback
+*
+* @param None.
+*
+* @return
+* None
+*
+* @note None
+*
+****************************************************************************/
+void CheckWDTReset(void)
+{
+ u32 ResetReason;
+ u32 RebootStatusRegister;
+
+ RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
+
+ /*
+ * For 1.0 Silicon the reason for Reset is in the ResetReason Register
+ * Hence this register can be read to know the cause for previous reset
+ * that happened.
+ * Check if that reset is a Software WatchDog reset that happened
+ */
+ if (Silicon_Version == SILICON_VERSION_1) {
+ ResetReason = Xil_In32(RESET_REASON_REG);
+ } else {
+ ResetReason = GetResetReason();
+ }
+ /*
+ * If the FSBL_IN_MASK Has not been cleared, WDT happened
+ * before FSBL exits
+ */
+ if ((ResetReason & RESET_REASON_SWDT) == RESET_REASON_SWDT ) {
+ if ((RebootStatusRegister & FSBL_FAIL_MASK) == FSBL_IN_MASK) {
+ /*
+ * Clear the SWDT Reset bit
+ */
+ ResetReason &= ~RESET_REASON_SWDT;
+ if (Silicon_Version == SILICON_VERSION_1) {
+ /*
+ * for 1.0 Silicon we need to write
+ * 1 to the RESET REASON Clear register
+ */
+ Xil_Out32(RESET_REASON_CLR, 1);
+ } else {
+ Xil_Out32(REBOOT_STATUS_REG, ResetReason);
+ }
+
+ fsbl_printf(DEBUG_GENERAL,"WDT_RESET_OCCURED \n\r");
+ }
+ }
+}
+
+
+/******************************************************************************
+*
+* This function converts time into Watchdog counter value
+*
+* @param watchdog expire time in seconds
+*
+* @return
+* Counter value for Watchdog
+*
+* @note None
+*
+*******************************************************************************/
+u32 ConvertTime_WdtCounter(u32 seconds)
+{
+ double time = 0.0;
+ double CounterValue;
+ u32 Crv = 0;
+ u32 Prescaler,PrescalerValue;
+
+ Prescaler = XWdtPs_GetControlValue(&Watchdog, XWDTPS_CLK_PRESCALE);
+
+ if (Prescaler == XWDTPS_CCR_PSCALE_0008)
+ PrescalerValue = 8;
+ if (Prescaler == XWDTPS_CCR_PSCALE_0064)
+ PrescalerValue = 64;
+ if (Prescaler == XWDTPS_CCR_PSCALE_4096)
+ PrescalerValue = 4096;
+
+ time = (double)(PrescalerValue) / (double)XPAR_PS7_WDT_0_WDT_CLK_FREQ_HZ;
+
+ CounterValue = seconds / time;
+
+ Crv = (u32)CounterValue;
+ Crv >>= WDT_CRV_SHIFT;
+
+ return Crv;
+}
+
+#endif
+
+
+/******************************************************************************
+*
+* This function Gets the Silicon Version stores in global variable
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+*******************************************************************************/
+void GetSiliconVersion(void)
+{
+ /*
+ * Get the silicon version
+ */
+ Silicon_Version = XDcfg_GetPsVersion(DcfgInstPtr);
+ if(Silicon_Version == SILICON_VERSION_3_1) {
+ fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n");
+ } else {
+ fsbl_printf(DEBUG_GENERAL,"Silicon Version %lu.0\r\n",
+ Silicon_Version + 1);
+ }
+}
+
+
+/******************************************************************************
+*
+* This function HeaderChecksum will calculates the header checksum and
+* compares with checksum read from flash
+*
+* @param FlashOffsetAddress Flash offset address
+*
+* @return
+* - XST_SUCCESS if ID matches
+* - XST_FAILURE if ID mismatches
+*
+* @note None
+*
+*******************************************************************************/
+u32 HeaderChecksum(u32 FlashOffsetAddress){
+ u32 Checksum = 0;
+ u32 Count;
+ u32 TempValue = 0;
+
+ for (Count = 0; Count < IMAGE_HEADER_CHECKSUM_COUNT; Count++) {
+ /*
+ * Read the word from the header
+ */
+ MoveImage(FlashOffsetAddress + IMAGE_WIDTH_CHECK_OFFSET + (Count*4), (u32)&TempValue, 4);
+
+ /*
+ * Update checksum
+ */
+ Checksum += TempValue;
+ }
+
+ /*
+ * Invert checksum, last bit of error checking
+ */
+ Checksum ^= 0xFFFFFFFF;
+ MoveImage(FlashOffsetAddress + IMAGE_CHECKSUM_OFFSET, (u32)&TempValue, 4);
+
+ /*
+ * Validate the checksum
+ */
+ if (TempValue != Checksum){
+ fsbl_printf(DEBUG_INFO, "Checksum = %8.8lx\r\n", Checksum);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************
+*
+* This function ImageCheckID will do check for XLNX pattern
+*
+* @param FlashOffsetAddress Flash offset address
+*
+* @return
+* - XST_SUCCESS if ID matches
+* - XST_FAILURE if ID mismatches
+*
+* @note None
+*
+*******************************************************************************/
+u32 ImageCheckID(u32 FlashOffsetAddress){
+ u32 ID;
+
+ /*
+ * Read in the header info
+ */
+ MoveImage(FlashOffsetAddress + IMAGE_IDENT_OFFSET, (u32)&ID, 4);
+
+ /*
+ * Check the ID, make sure image is XLNX format
+ */
+ if (ID != IMAGE_IDENT){
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************
+*
+* This function NextValidImageCheck search for valid boot image
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if valid image found
+* - XST_FAILURE if no image found
+*
+* @note None
+*
+*******************************************************************************/
+u32 NextValidImageCheck(void)
+{
+ u32 ImageBaseAddr;
+ u32 MultiBootReg;
+ u32 BootDevMaxSize=0;
+
+ fsbl_printf(DEBUG_GENERAL, "Searching For Next Valid Image");
+
+ /*
+ * Setting variable with maximum flash size based on boot mode
+ */
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+ if (FlashReadBaseAddress == XPS_QSPI_LINEAR_BASEADDR) {
+ BootDevMaxSize = QspiFlashSize;
+ }
+#endif
+
+ if (FlashReadBaseAddress == XPS_NAND_BASEADDR) {
+ BootDevMaxSize = NAND_FLASH_SIZE;
+ }
+
+ if (FlashReadBaseAddress == XPS_NOR_BASEADDR) {
+ BootDevMaxSize = NOR_FLASH_SIZE;
+ }
+
+ /*
+ * Read the multiboot register
+ */
+ MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET);
+
+ /*
+ * Compute the image start address
+ */
+ ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
+ * GOLDEN_IMAGE_OFFSET;
+
+ /*
+ * Valid image search continue till end of the flash
+ * With increment 32KB in each iteration
+ */
+ while (ImageBaseAddr < BootDevMaxSize) {
+
+ fsbl_printf(DEBUG_INFO,".");
+
+ /*
+ * Valid image search using XLNX pattern at fixed offset
+ * and header checksum
+ */
+ if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) &&
+ (HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) {
+
+ fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8lx\r\n",
+ ImageBaseAddr);
+ /*
+ * Update multiboot register
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_MULTIBOOT_ADDR_OFFSET,
+ MultiBootReg);
+
+ return XST_SUCCESS;
+ }
+
+ /*
+ * Increment mulitboot count
+ */
+ MultiBootReg++;
+
+ /*
+ * Compute the image start address
+ */
+ ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
+ * GOLDEN_IMAGE_OFFSET;
+ }
+
+ return XST_FAILURE;
+}
+
+/******************************************************************************/
+/**
+*
+* This function Checks for the ddr initialization completion
+*
+* @param None.
+*
+* @return
+* - XST_SUCCESS if the initialization is successful
+* - XST_FAILURE if the initialization is NOT successful
+*
+* @note None.
+*
+****************************************************************************/
+u32 DDRInitCheck(void)
+{
+ u32 ReadVal;
+
+ /*
+ * Write and Read from the DDR location for sanity checks
+ */
+ Xil_Out32(DDR_START_ADDR, DDR_TEST_PATTERN);
+ ReadVal = Xil_In32(DDR_START_ADDR);
+ if (ReadVal != DDR_TEST_PATTERN) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Write and Read from the DDR location for sanity checks
+ */
+ Xil_Out32(DDR_START_ADDR + DDR_TEST_OFFSET, DDR_TEST_PATTERN);
+ ReadVal = Xil_In32(DDR_START_ADDR + DDR_TEST_OFFSET);
+ if (ReadVal != DDR_TEST_PATTERN) {
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.c
new file mode 100644
index 0000000..e7cf7ea
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.c
@@ -0,0 +1,484 @@
+/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+ * All rights reserved.
+ *
+ * This package is an SSL implementation written
+ * by Eric Young (eay@cryptsoft.com).
+ * The implementation was written so as to conform with Netscapes SSL.
+ *
+ * This library is free for commercial and non-commercial use as long as
+ * the following conditions are aheared to. The following conditions
+ * apply to all code found in this distribution, be it the RC4, RSA,
+ * lhash, DES, etc., code; not just the SSL code. The SSL documentation
+ * included with this distribution is covered by the same copyright terms
+ * except that the holder is Tim Hudson (tjh@cryptsoft.com).
+ *
+ * Copyright remains Eric Young's, and as such any Copyright notices in
+ * the code are not to be removed.
+ * If this package is used in a product, Eric Young should be given attribution
+ * as the author of the parts of the library used.
+ * This can be in the form of a textual message at program startup or
+ * in documentation (online or textual) provided with the package.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * "This product includes cryptographic software written by
+ * Eric Young (eay@cryptsoft.com)"
+ * The word 'cryptographic' can be left out if the rouines from the library
+ * being used are not cryptographic related :-).
+ * 4. If you include any Windows specific code (or a derivative thereof) from
+ * the apps directory (application code) you must include an acknowledgement:
+ * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
+ *
+ * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * The licence and distribution terms for any publically available version or
+ * derivative of this code cannot be changed. i.e. this code cannot simply be
+ * copied and put under another distribution licence
+ * [including the GNU Public Licence.]
+ */
+/*****************************************************************************/
+/**
+*
+* @file md5.c
+*
+* Contains code to calculate checksum using md5 algorithm
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd 05/17/13 Initial release
+*
+*
+*
+*
+* @note
+*
+******************************************************************************/
+/****************************** Include Files *********************************/
+
+#include "md5.h"
+
+/******************************************************************************/
+/**
+*
+* This function sets the memory
+*
+* @param dest
+*
+* @param ch
+*
+* @param count
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void * MD5Memset( void *dest, int ch, u32 count )
+{
+ register char *dst8 = (char*)dest;
+
+ while( count-- )
+ *dst8++ = ch;
+
+ return dest;
+}
+
+/******************************************************************************/
+/**
+*
+* This function copy the memory
+*
+* @param dest
+*
+* @param ch
+*
+* @param count
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void * MD5Memcpy( void *dest, const void *src,
+ u32 count, boolean doByteSwap )
+{
+ register char * dst8 = (char*)dest;
+ register char * src8 = (char*)src;
+
+ if( doByteSwap == FALSE ) {
+ while( count-- )
+ *dst8++ = *src8++;
+ } else {
+ count /= sizeof( u32 );
+
+ while( count-- ) {
+ dst8[ 0 ] = src8[ 3 ];
+ dst8[ 1 ] = src8[ 2 ];
+ dst8[ 2 ] = src8[ 1 ];
+ dst8[ 3 ] = src8[ 0 ];
+
+ dst8 += 4;
+ src8 += 4;
+ }
+ }
+
+ return dest;
+}
+
+/******************************************************************************/
+/**
+*
+* This function is the core of the MD5 algorithm,
+* this alters an existing MD5 hash to
+* reflect the addition of 16 longwords of new data. MD5Update blocks
+* the data and converts bytes into longwords for this routine.
+*
+* Use binary integer part of the sine of integers (Radians) as constants.
+* Calculated as:
+*
+* for( i = 0; i < 63; i++ )
+* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
+*
+* Following number is the per-round shift amount.
+*
+* @param dest
+*
+* @param ch
+*
+* @param count
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void MD5Transform( u32 *buffer, u32 *intermediate )
+{
+ register u32 a, b, c, d;
+
+ a = buffer[ 0 ];
+ b = buffer[ 1 ];
+ c = buffer[ 2 ];
+ d = buffer[ 3 ];
+
+ MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
+ MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
+ MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
+ MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
+ MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
+ MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
+ MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
+
+ MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
+ MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
+ MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
+ MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
+ MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
+ MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
+ MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
+
+ MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
+ MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
+ MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
+ MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
+ MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
+ MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
+ MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
+
+ MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
+ MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
+ MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
+ MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
+ MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
+ MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
+ MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
+
+ buffer[ 0 ] += a;
+ buffer[ 1 ] += b;
+ buffer[ 2 ] += c;
+ buffer[ 3 ] += d;
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function Start MD5 accumulation
+* Set bit count to 0 and buffer to mysterious initialization constants
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void MD5Init( MD5Context *context )
+{
+
+ context->buffer[ 0 ] = 0x67452301;
+ context->buffer[ 1 ] = 0xefcdab89;
+ context->buffer[ 2 ] = 0x98badcfe;
+ context->buffer[ 3 ] = 0x10325476;
+
+ context->bits[ 0 ] = 0;
+ context->bits[ 1 ] = 0;
+
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function updates context to reflect the concatenation of another
+* buffer full of bytes
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void MD5Update( MD5Context *context, u8 *buffer,
+ u32 len, boolean doByteSwap )
+{
+ register u32 temp;
+ register u8 * p;
+
+ /*
+ * Update bitcount
+ */
+
+ temp = context->bits[ 0 ];
+
+ if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
+ /*
+ * Carry from low to high
+ */
+ context->bits[ 1 ]++;
+ }
+
+ context->bits[ 1 ] += len >> 29;
+
+ /*
+ * Bytes already in shsInfo->data
+ */
+
+ temp = ( temp >> 3 ) & 0x3f;
+
+ /*
+ * Handle any leading odd-sized chunks
+ */
+
+ if( temp ) {
+ p = (u8 *)context->intermediate + temp;
+
+ temp = MD5_SIGNATURE_BYTE_SIZE - temp;
+
+ if( len < temp ) {
+ MD5Memcpy( p, buffer, len, doByteSwap );
+ return;
+ }
+
+ MD5Memcpy( p, buffer, temp, doByteSwap );
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ buffer += temp;
+ len -= temp;
+
+ }
+
+ /*
+ * Process data in 64-byte, 512 bit, chunks
+ */
+
+ while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
+ MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
+ doByteSwap );
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ buffer += MD5_SIGNATURE_BYTE_SIZE;
+ len -= MD5_SIGNATURE_BYTE_SIZE;
+
+ }
+
+ /*
+ * Handle any remaining bytes of data
+ */
+ MD5Memcpy( context->intermediate, buffer, len, doByteSwap );
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function final wrap-up - pad to 64-byte boundary with the bit pattern
+* 1 0* (64-bit count of bits processed, MSB-first
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+inline void MD5Final( MD5Context *context, u8 *digest,
+ boolean doByteSwap )
+{
+ u32 count;
+ u8 * p;
+
+ /*
+ * Compute number of bytes mod 64
+ */
+ count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
+
+ /*
+ * Set the first char of padding to 0x80. This is safe since there is
+ * always at least one byte free
+ */
+ p = context->intermediate + count;
+ *p++ = 0x80;
+
+ /*
+ * Bytes of padding needed to make 64 bytes
+ */
+ count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
+
+ /*
+ * Pad out to 56 mod 64
+ */
+ if( count < 8 ) {
+ /*
+ * Two lots of padding: Pad the first block to 64 bytes
+ */
+ MD5Memset( p, 0, count );
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ /*
+ * Now fill the next block with 56 bytes
+ */
+ MD5Memset( context->intermediate, 0, 56 );
+ } else {
+ /*
+ * Pad block to 56 bytes
+ */
+ MD5Memset( p, 0, count - 8 );
+ }
+
+ /*
+ * Append length in bits and transform
+ */
+ ( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
+ ( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
+
+ MD5Transform( context->buffer, (u32 *)context->intermediate );
+
+ /*
+ * Now return the digest
+ */
+ MD5Memcpy( digest, context->buffer, 16, doByteSwap );
+}
+
+/******************************************************************************/
+/**
+*
+* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
+* 'input'. 'digest' must have enough space to hold 16 bytes
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @param
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
+{
+ MD5Context context;
+
+ MD5Init( &context );
+
+ MD5Update( &context, input, len, doByteSwap );
+
+ MD5Final( &context, digest, doByteSwap );
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.h
new file mode 100644
index 0000000..55f07db
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file md5.h
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd 05/17/13 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___MD5_H___
+#define ___MD5_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define MD5_SIGNATURE_BYTE_SIZE 64
+
+/**************************** Type Definitions *******************************/
+
+typedef u8 boolean;
+typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
+
+struct MD5Context
+ {
+ u32 buffer[ 4 ];
+ u32 bits[ 2 ];
+ signature intermediate;
+ };
+typedef struct MD5Context MD5Context;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * The four core functions - F1 is optimized somewhat
+ */
+#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
+#define F2( x, y, z ) F1( z, x, y )
+#define F3( x, y, z ) ( x ^ y ^ z )
+#define F4( x, y, z ) ( y ^ ( x | ~z ) )
+
+
+/*
+ * This is the central step in the MD5 algorithm
+ */
+#define MD5_STEP( f, w, x, y, z, data, s ) \
+ ( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
+
+
+/************************** Function Prototypes ******************************/
+
+void * MD5Memset( void *dest, int ch, u32 count );
+
+void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
+
+void MD5Transform( u32 *buffer, u32 *intermediate );
+
+void MD5Init( MD5Context *context );
+
+void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
+
+void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
+
+void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___MD5_H___ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.c
new file mode 100644
index 0000000..e086386
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.c
@@ -0,0 +1,291 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nand.c
+*
+* Contains code for the NAND FLASH functionality. Bad Block management
+* is simple: skip the bad blocks and keep going.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 2.00a mb 25/05/12 fsbl changes for standalone bsp based
+* 3.00a sgd 30/01/13 Code cleanup
+* 5.00a sgd 17/05/13 Support for Multi Boot
+*
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "fsbl.h"
+#ifdef XPAR_PS7_NAND_0_BASEADDR
+#include "nand.h"
+#include "xnandps_bbm.h"
+
+
+/************************** Constant Definitions *****************************/
+
+#define NAND_DEVICE_ID XPAR_XNANDPS_0_DEVICE_ID
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
+ u64 Offset,
+ u32 Length);
+
+/************************** Variable Definitions *****************************/
+
+extern u32 FlashReadBaseAddress;
+extern u32 FlashOffsetAddress;
+
+XNandPs *NandInstPtr;
+XNandPs NandInstance; /* XNand Instance. */
+
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the NAND FLASH interface.
+*
+* @param none
+*
+* @return
+* - XST_SUCCESS if the controller initializes correctly
+* - XST_FAILURE if the controller fails to initializes correctly
+*
+* @note none.
+*
+****************************************************************************/
+u32 InitNand(void)
+{
+
+ u32 Status;
+ XNandPs_Config *ConfigPtr;
+
+ /*
+ * Set up pointers to instance and the config structure
+ */
+ NandInstPtr = &NandInstance;
+
+ /*
+ * Initialize the flash driver.
+ */
+ ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE_ID);
+
+ if (ConfigPtr == NULL) {
+ fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r");
+ return XST_FAILURE;
+ }
+
+ Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr,
+ ConfigPtr->SmcBase,ConfigPtr->FlashBase);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"NAND intialization failed \n \r");
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set up base address for access
+ */
+ FlashReadBaseAddress = XPS_NAND_BASEADDR;
+
+ fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n",
+ NandInstPtr->Geometry.FlashWidth);
+
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n",
+ Status);
+ return XST_FAILURE;
+ }
+
+ /*
+ * set up the FLASH access pointers
+ */
+ fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r");
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the NAND FLASH interface for the Simplified header
+* functionality. This function handles bad blocks.
+*
+* The source address is the absolute good address, bad blocks are skipped
+* without incrementing the source address.
+*
+* @param SourceAddress is address in FLASH data space, absolute good address
+* @param DestinationAddress is address in OCM data space
+*
+* @return XST_SUCCESS if the transfer completes correctly
+* XST_FAILURE if the transfer fails to completes correctly
+*
+* @note none.
+*
+****************************************************************************/
+u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+ u32 ActLen;
+ u32 BlockOffset;
+ u32 Block;
+ u32 Status;
+ u32 BytesLeft = LengthBytes;
+ u32 BlockSize = NandInstPtr->Geometry.BlockSize;
+ u8 *BufPtr = (u8 *)DestinationAddress;
+ u32 ReadLen;
+ u32 BlockReadLen;
+ u32 Offset;
+ u32 TmpAddress = 0 ;
+ u32 BlockCount = 0;
+ u32 BadBlocks = 0;
+
+ /*
+ * First get bad blocks before the source address
+ */
+ while (TmpAddress < SourceAddress) {
+ while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) ==
+ XST_SUCCESS) {
+ BlockCount ++;
+ BadBlocks ++;
+ }
+
+ TmpAddress += BlockSize;
+ BlockCount ++;
+ }
+
+ Offset = SourceAddress + BadBlocks * BlockSize;
+
+ /*
+ * Calculate the actual length including bad blocks
+ */
+ ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes);
+
+ /*
+ * Check if the actual length cross flash size
+ */
+ if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) {
+ return XST_FAILURE;
+ }
+
+ while (BytesLeft > 0) {
+ BlockOffset = Offset & (BlockSize - 1);
+ Block = (Offset & ~(BlockSize - 1))/BlockSize;
+ BlockReadLen = BlockSize - BlockOffset;
+
+ Status = XNandPs_IsBlockBad(NandInstPtr, Block);
+ if (Status == XST_SUCCESS) {
+ /* Move to next block */
+ Offset += BlockReadLen;
+ continue;
+ }
+
+ /*
+ * Check if we cross block boundary
+ */
+ if (BytesLeft < BlockReadLen) {
+ ReadLen = BytesLeft;
+ } else {
+ ReadLen = BlockReadLen;
+ }
+
+ /*
+ * Read from the NAND flash
+ */
+ Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+ BytesLeft -= ReadLen;
+ Offset += ReadLen;
+ BufPtr += ReadLen;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the length including bad blocks from a given offset and
+* length.
+*
+* @param NandInstPtr is the pointer to the XNandPs instance.
+* @param Offset is the flash data address to read from.
+* @param Length is number of bytes to read.
+*
+* @return
+* - Return actual length including bad blocks.
+*
+* @note None.
+*
+******************************************************************************/
+static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
+ u64 Offset,
+ u32 Length)
+{
+ u32 BlockSize = NandInstPtr->Geometry.BlockSize;
+ u32 CurBlockLen;
+ u32 CurBlock;
+ u32 Status;
+ u32 TempLen = 0;
+ u32 ActLen = 0;
+
+ while (TempLen < Length) {
+ CurBlockLen = BlockSize - (Offset & (BlockSize - 1));
+ CurBlock = (Offset & ~(BlockSize - 1))/BlockSize;
+
+ /*
+ * Check if the block is bad
+ */
+ Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock);
+ if (Status != XST_SUCCESS) {
+ /* Good Block */
+ TempLen += CurBlockLen;
+ }
+ ActLen += CurBlockLen;
+ Offset += CurBlockLen;
+ if (Offset >= NandInstPtr->Geometry.DeviceSize) {
+ break;
+ }
+ }
+
+ return ActLen;
+}
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.h
new file mode 100644
index 0000000..1421d68
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.h
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nand.h
+*
+* This file contains the interface for the NAND FLASH functionality
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 2.00a mb 30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___NAND_H___
+#define ___NAND_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+
+#ifdef XPAR_PS7_NAND_0_BASEADDR
+
+#include "xnandps.h"
+#include "xnandps_bbm.h"
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 InitNand(void);
+
+u32 NandAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthWords);
+#endif
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___NAND_H___ */
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.c
new file mode 100644
index 0000000..3eca61c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.c
@@ -0,0 +1,140 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nor.c
+*
+* Contains code for the NOR FLASH functionality.
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+#include "nor.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 FlashReadBaseAddress;
+
+/******************************************************************************/
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the NOR FLASH interface.
+*
+* @param None
+*
+* @return None
+*
+* @note None.
+*
+****************************************************************************/
+void InitNor(void)
+{
+
+ /*
+ * Set up the base address for access
+ */
+ FlashReadBaseAddress = XPS_NOR_BASEADDR;
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the NOR FLASH interface for the Simplified header
+* functionality.
+*
+* @param SourceAddress is address in FLASH data space
+* @param DestinationAddress is address in OCM data space
+* @param LengthBytes is the data length to transfer in bytes
+*
+* @return
+* - XST_SUCCESS if the write completes correctly
+* - XST_FAILURE if the write fails to completes correctly
+*
+* @note None.
+*
+****************************************************************************/
+u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+ u32 Data;
+ u32 Count;
+ u32 *SourceAddr;
+ u32 *DestAddr;
+ u32 LengthWords;
+
+ /*
+ * check for non-word tail
+ * add bytes to cover the end
+ */
+ if ((LengthBytes%4) != 0){
+
+ LengthBytes += (4 - (LengthBytes & 0x00000003));
+ }
+
+ LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
+
+ SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
+ DestAddr = (u32 *)(DestinationAddress);
+
+ /*
+ * Word transfers, endianism isn't an issue
+ */
+ for (Count=0; Count < LengthWords; Count++){
+
+ Data = Xil_In32((u32)(SourceAddr++));
+ Xil_Out32((u32)(DestAddr++), Data);
+ }
+
+ return XST_SUCCESS;
+}
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.h
new file mode 100644
index 0000000..b57dab4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.h
@@ -0,0 +1,83 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file nor.h
+*
+* This file contains the interface for the NOR FLASH functionality
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+*
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___NOR_H___
+#define ___NOR_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+
+void InitNor(void);
+
+u32 NorAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthBytes);
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___NOR_H___ */
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.c
new file mode 100644
index 0000000..83e1b4e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.c
@@ -0,0 +1,812 @@
+/*****************************************************************************
+*
+* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file pcap.c
+*
+* Contains code for enabling and accessing the PCAP
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 02/10/10 Initial release
+* 2.00a jz 05/28/11 Add SD support
+* 2.00a mb 25/05/12 using the EDK provided devcfg driver
+* Nand/SD encryption and review comments
+* 3.00a mb 16/08/12 Added the poll function
+* Removed the FPGA_RST_CTRL define
+* Added the flag for NON PS instantiated bitstream
+* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
+* fabric_init()
+* Fix for CR#689026 - FSBL doesn't hold PL resets active
+* during bit download
+* Fix for CR#699475 - FSBL functionality is broken and
+* its not able to boot in QSPI/NAND
+* bootmode
+* Fix for CR#705664 - FSBL fails to decrypt the
+* bitstream when the image is AES
+* encrypted using non-zero key value
+* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* 7.00a kc 10/25/13 Fix for CR#724620 - How to handle PCAP_MODE after
+* bitstream configuration
+* Fix for CR#726178 - FabricInit() PROG_B is kept active
+* for 5mS.
+* Fix for CR#731839 - FSBL has to check the
+* HMAC error status after decryption
+* 12/04/13 Fix for CR#764382 - How to handle PCAP_MODE after
+* bitstream configuration - PCAP_MODE
+* and PCAP_PR bits are not modified
+* 8.00a kc 2/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
+* is not proper
+* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
+* 13.00a ssc 04/10/15 Fix for CR#846899 - Corrected logic to clear
+* DMA done count
+* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
+* In pcap.c/pcap.h/main.h,
+* Fabric Initialization sequence
+* is modified to check the PL power
+* before sequence starts and checking
+* INIT_B reset status twice in case
+* of failure.
+* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
+* In pcap.c, check pl power
+* through MCTRL register for
+* 3.0 and later versions of silicon.
+*
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "pcap.h"
+#include "nand.h" /* For NAND geometry information */
+#include "fsbl.h"
+#include "image_mover.h" /* For MoveImage */
+#include "xparameters.h"
+#include "xil_exception.h"
+#include "xdevcfg.h"
+#include "sleep.h"
+#include "xtime_l.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+/************************** Constant Definitions *****************************/
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+
+#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
+
+/************************** Variable Definitions *****************************/
+/* Devcfg driver instance */
+static XDcfg DcfgInstance;
+XDcfg *DcfgInstPtr;
+extern u32 Silicon_Version;
+#ifdef XPAR_XWDTPS_0_BASEADDR
+extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+
+/******************************************************************************/
+/**
+*
+* This function transfer data using PCAP
+*
+* @param SourceDataPtr is a pointer to where the data is read from
+* @param DestinationDataPtr is a pointer to where the data is written to
+* @param SourceLength is the length of the data to be moved in words
+* @param DestinationLength is the length of the data to be moved in words
+* @param SecureTransfer indicated the encryption key location, 0 for
+* non-encrypted
+*
+* @return
+* - XST_SUCCESS if the transfer is successful
+* - XST_FAILURE if the transfer fails
+*
+* @note None
+*
+****************************************************************************/
+u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
+ u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
+{
+ u32 Status;
+ u32 IntrStsReg;
+ u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
+
+ /*
+ * Check for secure transfer
+ */
+ if (SecureTransfer) {
+ PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
+ }
+
+#ifdef FSBL_PERF
+ XTime tXferCur = 0;
+ FsblGetGlobalTime(&tXferCur);
+#endif
+
+ /*
+ * Clear the PCAP status registers
+ */
+ Status = ClearPcapStatus();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * PCAP single DMA transfer setup
+ */
+ SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
+ DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
+
+ /*
+ * Transfer using Device Configuration
+ */
+ Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
+ SourceLength,
+ (u8 *)DestinationDataPtr,
+ DestinationLength, PcapTransferType);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
+ return XST_FAILURE;
+ }
+
+ /*
+ * Dump the PCAP registers
+ */
+ PcapDumpRegisters();
+
+ /*
+ * Poll for the DMA done
+ */
+ Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
+
+ /*
+ * Check for errors
+ */
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * For Performance measurement
+ */
+#ifdef FSBL_PERF
+ XTime tXferEnd = 0;
+ fsbl_printf(DEBUG_GENERAL,"Time taken is ");
+ FsblMeasurePerfTime(tXferCur,tXferEnd);
+#endif
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+/**
+*
+* This function loads PL partition using PCAP
+*
+* @param SourceDataPtr is a pointer to where the data is read from
+* @param DestinationDataPtr is a pointer to where the data is written to
+* @param SourceLength is the length of the data to be moved in words
+* @param DestinationLength is the length of the data to be moved in words
+* @param SecureTransfer indicated the encryption key location, 0 for
+* non-encrypted
+*
+* @return
+* - XST_SUCCESS if the transfer is successful
+* - XST_FAILURE if the transfer fails
+*
+* @note None
+*
+****************************************************************************/
+u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
+ u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
+{
+ u32 Status;
+ u32 IntrStsReg;
+ u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
+
+ /*
+ * Check for secure transfer
+ */
+ if (SecureTransfer) {
+ PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
+ }
+
+#ifdef FSBL_PERF
+ XTime tXferCur = 0;
+ FsblGetGlobalTime(&tXferCur);
+#endif
+
+ /*
+ * Clear the PCAP status registers
+ */
+ Status = ClearPcapStatus();
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * For Bitstream case destination address will be 0xFFFFFFFF
+ */
+ DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
+
+ /*
+ * New Bitstream download initialization sequence
+ */
+ Status = FabricInit();
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+ /*
+ * Prevent WDT reset
+ */
+ XWdtPs_RestartWdt(&Watchdog);
+#endif
+
+ /*
+ * PCAP single DMA transfer setup
+ */
+ SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
+ DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
+
+ /*
+ * Transfer using Device Configuration
+ */
+ Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
+ SourceLength,
+ (u8 *)DestinationDataPtr,
+ DestinationLength, PcapTransferType);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
+ return XST_FAILURE;
+ }
+
+
+ /*
+ * Dump the PCAP registers
+ */
+ PcapDumpRegisters();
+
+
+ /*
+ * Poll for the DMA done
+ */
+ Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
+
+ /*
+ * Poll for FPGA Done
+ */
+ Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
+
+ /*
+ * Check for errors
+ */
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
+ return XST_FAILURE;
+ }
+
+ /*
+ * For Performance measurement
+ */
+#ifdef FSBL_PERF
+ XTime tXferEnd = 0;
+ fsbl_printf(DEBUG_GENERAL,"Time taken is ");
+ FsblMeasurePerfTime(tXferCur,tXferEnd);
+#endif
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function Initializes the PCAP driver.
+*
+* @param none
+*
+* @return
+* - XST_SUCCESS if the pcap driver initialization is successful
+* - XST_FAILURE if the pcap driver initialization fails
+*
+* @note none
+*
+****************************************************************************/
+int InitPcap(void)
+{
+ XDcfg_Config *ConfigPtr;
+ int Status = XST_SUCCESS;
+ DcfgInstPtr = &DcfgInstance;
+
+ /*
+ * Initialize the Device Configuration Interface driver.
+ */
+ ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
+
+ Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
+ ConfigPtr->BaseAddr);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+/******************************************************************************/
+/**
+*
+* This function programs the Fabric for use.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if the Fabric initialization is successful
+* - XST_FAILURE if the Fabric initialization fails
+* @note None
+*
+****************************************************************************/
+u32 FabricInit(void)
+{
+ u32 PcapReg;
+ u32 PcapCtrlRegVal;
+ u32 StatusReg;
+ u32 MctrlReg;
+ u32 PcfgInit;
+ u32 TimerExpired=0;
+ XTime tCur=0;
+ XTime tEnd=0;
+
+
+ /*
+ * Set Level Shifters DT618760 - PS to PL enabling
+ */
+ Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
+ fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n",
+ Xil_In32(PS_LVL_SHFTR_EN));
+
+ /*
+ * Get DEVCFG controller settings
+ */
+ PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ /*
+ * Check the PL power status
+ */
+ if(Silicon_Version >= SILICON_VERSION_3)
+ {
+ MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr);
+
+ if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) !=
+ XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK)
+ {
+ fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n");
+ return XST_FAILURE;
+ }
+ }
+
+
+ /*
+ * Setting PCFG_PROG_B signal to high
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+
+ /*
+ * Setting PCFG_PROG_B signal to low
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+
+ /*
+ * Polling the PCAP_INIT status for Reset or timeout
+ */
+
+ XTime_GetTime(&tCur);
+ do
+ {
+ PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
+ XDCFG_STATUS_PCFG_INIT_MASK);
+ if(PcfgInit == 0)
+ {
+ break;
+ }
+ XTime_GetTime(&tEnd);
+ if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
+ {
+ TimerExpired = 1;
+ }
+
+ } while(!TimerExpired);
+
+ if(TimerExpired == 1)
+ {
+ TimerExpired = 0;
+ /*
+ * Came here due to expiration and PCAP_INIT is set.
+ * Retry PCFG_PROG_B High -> Low again
+ */
+
+ /*
+ * Setting PCFG_PROG_B signal to high
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+
+ /*
+ * Setting PCFG_PROG_B signal to low
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Check for AES source key
+ */
+ if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
+ /*
+ * 5msec delay
+ */
+ usleep(5000);
+ }
+ /*
+ * Polling the PCAP_INIT status for Reset or timeout (second iteration)
+ */
+
+ XTime_GetTime(&tCur);
+ do
+ {
+ PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
+ XDCFG_STATUS_PCFG_INIT_MASK);
+ if(PcfgInit == 0)
+ {
+ break;
+ }
+ XTime_GetTime(&tEnd);
+ if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
+ {
+ TimerExpired = 1;
+ }
+
+ } while(!TimerExpired);
+
+ if(TimerExpired == 1)
+ {
+ /*
+ * Came here due to PCAP_INIT is not getting reset
+ * for PCFG_PROG_B signal High -> Low
+ */
+ fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n");
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * Setting PCFG_PROG_B signal to high
+ */
+ XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
+
+ /*
+ * Polling the PCAP_INIT status for Set
+ */
+ while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
+ XDCFG_STATUS_PCFG_INIT_MASK));
+
+ /*
+ * Get Device configuration status
+ */
+ StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
+ fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg);
+
+ fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
+
+ return XST_SUCCESS;
+}
+/******************************************************************************/
+/**
+*
+* This function Clears the PCAP status registers.
+*
+* @param None
+*
+* @return
+* - XST_SUCCESS if the pcap status registers are cleared
+* - XST_FAILURE if errors are there
+* - XST_DEVICE_BUSY if Pcap device is busy
+* @note None
+*
+****************************************************************************/
+u32 ClearPcapStatus(void)
+{
+
+ u32 StatusReg;
+ u32 IntStatusReg;
+
+ /*
+ * Clear it all, so if Boot ROM comes back, it can proceed
+ */
+ XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
+
+ /*
+ * Get PCAP Interrupt Status Register
+ */
+ IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
+ IntStatusReg);
+ return XST_FAILURE;
+ }
+
+ /*
+ * Read the PCAP status register for DMA status
+ */
+ StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
+
+ fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg);
+
+ /*
+ * If the queue is full, return w/ XST_DEVICE_BUSY
+ */
+ if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
+ XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
+
+ fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
+ return XST_DEVICE_BUSY;
+ }
+
+ fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
+
+ /*
+ * There are unacknowledged DMA commands outstanding
+ */
+ if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
+ XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
+
+ IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+
+ if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
+ XDCFG_IXR_DMA_DONE_MASK){
+ /*
+ * Error state, transfer cannot occur
+ */
+ fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
+ return XST_FAILURE;
+ }
+ else {
+ /*
+ * clear out the status
+ */
+ XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
+ }
+ }
+
+ if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
+ XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg |
+ XDCFG_STATUS_DMA_DONE_CNT_MASK);
+ }
+
+ fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************/
+/**
+*
+* This function prints PCAP register status.
+*
+* @param none
+*
+* @return none
+*
+* @note none
+*
+****************************************************************************/
+void PcapDumpRegisters (void) {
+
+ fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
+
+ fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
+ fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n",
+ XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
+ Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
+}
+
+/******************************************************************************/
+/**
+*
+* This function Polls for the DMA done or FPGA done.
+*
+* @param none
+*
+* @return
+* - XST_SUCCESS if polling for DMA/FPGA done is successful
+* - XST_FAILURE if polling for DMA/FPGA done fails
+*
+* @note none
+*
+****************************************************************************/
+int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
+{
+ int Count = MaxCount;
+ u32 IntrStsReg = 0;
+
+ /*
+ * poll for the DMA done
+ */
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ while ((IntrStsReg & MaskValue) !=
+ MaskValue) {
+ IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
+ Count -=1;
+
+ if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
+ fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
+ IntrStsReg);
+ PcapDumpRegisters();
+ return XST_FAILURE;
+ }
+
+ if(!Count) {
+ fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
+ return XST_FAILURE;
+ }
+ if (Count > (MAX_COUNT-100)) {
+ fsbl_printf(DEBUG_GENERAL,".");
+ }
+ }
+
+ fsbl_printf(DEBUG_GENERAL,"\n\r");
+
+ XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
+
+ return XST_SUCCESS;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.h
new file mode 100644
index 0000000..aff5c7d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.h
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file pcap.h
+*
+* This file contains the interface for intiializing and accessing the PCAP
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 02/10/10 Initial release
+* 2.00a mb 16/08/12 Added the macros and function prototypes
+* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* Fabric Initialization sequence is modified to check
+* the PL power before sequence starts and checking INIT_B
+* reset status twice in case of failure.
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___PCAP_H___
+#define ___PCAP_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xdevcfg.h"
+
+/************************** Function Prototypes ******************************/
+
+
+/* Multiboot register offset mask */
+#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF
+#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000
+/*Miscellaneous Control Register mask*/
+#define XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK 0x00000100
+#define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000)
+
+#define PCAP_LAST_TRANSFER 1
+#define MAX_COUNT 1000000000
+#define LVL_PL_PS 0x0000000F
+#define LVL_PS_PL 0x0000000A
+
+/* Fix for #672779 */
+#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+int InitPcap(void);
+void PcapDumpRegisters(void);
+u32 ClearPcapStatus(void);
+u32 FabricInit(void);
+int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
+u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
+ u32 DestinationLength, u32 Flags);
+u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
+ u32 DestinationLength, u32 Flags);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___PCAP_H___ */
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.c
new file mode 100644
index 0000000..18741d9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.c
@@ -0,0 +1,877 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file qspi.c
+*
+* Contains code for the QSPI FLASH functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
+* are set
+* 4.00a sg 02/28/13 Cleanup
+* Removed LPBK_DLY_ADJ register setting code as we use
+* divisor 8
+* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
+* Dual Stack support
+* Fix for CR:721674 - FSBL- Failed to boot from Dual
+* stacked QSPI
+* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* Fix for CR#739711 - FSBL not able to read Large QSPI
+* (512M) in IO Mode
+* 7.00a kc 10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
+* settings for Dual parallel
+* configuration in IO mode
+* 14.0 gan 01/13/16 Fix for CR#869081 - (2016.1)FSBL picks the qspi read
+* command from LQSPI_CFG register
+* instead of hard coded read
+* command (0x6B).
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "qspi.h"
+#include "image_mover.h"
+
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
+
+/*
+ * The following constants define the commands which may be sent to the FLASH
+ * device.
+ */
+#define QUAD_READ_CMD 0x6B
+#define READ_ID_CMD 0x9F
+
+#define WRITE_ENABLE_CMD 0x06
+#define BANK_REG_RD 0x16
+#define BANK_REG_WR 0x17
+/* Bank register is called Extended Address Reg in Micron */
+#define EXTADD_REG_RD 0xC8
+#define EXTADD_REG_WR 0xC5
+
+#define COMMAND_OFFSET 0 /* FLASH instruction */
+#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
+#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
+#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
+#define DATA_OFFSET 4 /* Start of Data for Read/Write */
+#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
+ reads */
+#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
+ quad reads */
+#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
+#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
+#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
+/*
+ * The following constants specify the extra bytes which are sent to the
+ * FLASH on the QSPI interface, that are not data, but control information
+ * which includes the command and address
+ */
+#define OVERHEAD_SIZE 4
+
+/*
+ * The following constants specify the max amount of data and the size of the
+ * the buffer required to hold the data and overhead to transfer the data to
+ * and from the FLASH.
+ */
+#define DATA_SIZE 4096
+
+/*
+ * The following defines are for dual flash interface.
+ */
+#define LQSPI_CR_FAST_READ 0x0000000B
+#define LQSPI_CR_FAST_DUAL_READ 0x0000003B
+#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
+#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
+ address and return data */
+
+#define SINGLE_QSPI_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_READ)
+
+#define SINGLE_QSPI_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_DUAL_READ)
+
+#define SINGLE_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define DUAL_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define DUAL_STACK_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_READ)
+
+#define DUAL_STACK_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_DUAL_READ)
+
+#define DUAL_STACK_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define SINGLE_QSPI_IO_CONFIG_FAST_READ (LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_READ)
+
+#define SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ (LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_DUAL_READ)
+
+#define SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
+ XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
+ LQSPI_CR_1_DUMMY_BYTE | \
+ LQSPI_CR_FAST_QUAD_READ)
+
+#define QSPI_BUSWIDTH_ONE 0U
+#define QSPI_BUSWIDTH_TWO 1U
+#define QSPI_BUSWIDTH_FOUR 2U
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+XQspiPs QspiInstance;
+XQspiPs *QspiInstancePtr;
+u32 QspiFlashSize;
+u32 QspiFlashMake;
+extern u32 FlashReadBaseAddress;
+extern u8 LinearBootDeviceFlag;
+
+/*
+ * The following variables are used to read and write to the eeprom and they
+ * are global to avoid having large buffers on the stack
+ */
+u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
+u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
+
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the QSPI interface.
+*
+* @param None
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+u32 InitQspi(void)
+{
+ XQspiPs_Config *QspiConfig;
+ int Status;
+ u32 ConfigCmd;
+
+ QspiInstancePtr = &QspiInstance;
+
+ /*
+ * Set up the base address for access
+ */
+ FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
+
+ /*
+ * Initialize the QSPI driver so that it's ready to use
+ */
+ QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
+ if (NULL == QspiConfig) {
+ return XST_FAILURE;
+ }
+
+ Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
+ QspiConfig->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set Manual Chip select options and drive HOLD_B pin high.
+ */
+ XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
+ XQSPIPS_HOLD_B_DRIVE_OPTION);
+
+ /*
+ * Set the prescaler for QSPI clock
+ */
+ XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
+
+ /*
+ * Assert the FLASH chip select.
+ */
+ XQspiPs_SetSlaveSelect(QspiInstancePtr);
+
+ /*
+ * Read Flash ID and extract Manufacture and Size information
+ */
+ Status = FlashReadID();
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ if (XPAR_XQSPIPS_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) {
+
+ fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
+ /*
+ * For Flash size <128Mbit controller configured in linear mode
+ */
+ if (QspiFlashSize <= FLASH_SIZE_16MB) {
+ LinearBootDeviceFlag = 1;
+
+ /*
+ * Enable linear mode
+ */
+ XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
+ XQSPIPS_HOLD_B_DRIVE_OPTION);
+
+ switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
+
+ case QSPI_BUSWIDTH_ONE:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_CONFIG_FAST_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_TWO:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_CONFIG_FAST_DUAL_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_FOUR:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_CONFIG_FAST_QUAD_READ;
+ }
+ break;
+
+ }
+
+ /*
+ * Single linear read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+ } else {
+
+ switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
+
+ case QSPI_BUSWIDTH_ONE:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_TWO:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_FOUR:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
+ ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ;
+ }
+ break;
+
+ }
+ /*
+ * Single flash IO read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+ }
+ }
+
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+
+ fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
+ /*
+ * For Single Flash size <128Mbit controller configured in linear mode
+ */
+ if (QspiFlashSize <= FLASH_SIZE_16MB) {
+ /*
+ * Setting linear access flag
+ */
+ LinearBootDeviceFlag = 1;
+
+ /*
+ * Enable linear mode
+ */
+ XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
+ XQSPIPS_HOLD_B_DRIVE_OPTION);
+
+ /*
+ * Dual linear read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_FAST_QUAD_READ);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+ } else {
+ /*
+ * Dual flash IO read
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ);
+
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(QspiInstancePtr);
+
+ }
+
+ /*
+ * Total flash size is two time of single flash size
+ */
+ QspiFlashSize = 2 * QspiFlashSize;
+ }
+
+ /*
+ * It is expected to same flash size for both chip selection
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
+
+ fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
+
+ QspiFlashSize = 2 * QspiFlashSize;
+
+ /*
+ * Enable two flash memories on separate buses
+ */
+ switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
+
+ case QSPI_BUSWIDTH_ONE:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
+ ConfigCmd = DUAL_STACK_CONFIG_FAST_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_TWO:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
+ ConfigCmd = DUAL_STACK_CONFIG_FAST_DUAL_READ;
+ }
+ break;
+
+ case QSPI_BUSWIDTH_FOUR:
+ {
+ fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
+ ConfigCmd = DUAL_STACK_CONFIG_FAST_QUAD_READ;
+ }
+ break;
+
+ }
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
+ }
+
+ return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* This function reads serial FLASH ID connected to the SPI interface.
+* It then deduces the make and size of the flash and obtains the
+* connection mode to point to corresponding parameters in the flash
+* configuration table. The flash driver will function based on this and
+* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
+* Winbond 128Mbit
+*
+* @param none
+*
+* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
+*
+* @note None.
+*
+******************************************************************************/
+u32 FlashReadID(void)
+{
+ u32 Status;
+
+ /*
+ * Read ID in Auto mode.
+ */
+ WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
+ WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
+ WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
+ WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
+
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ RD_ID_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
+
+ fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
+ ReadBuffer[2],
+ ReadBuffer[3]);
+
+ /*
+ * Deduce flash make
+ */
+ if (ReadBuffer[1] == MICRON_ID) {
+ QspiFlashMake = MICRON_ID;
+ fsbl_printf(DEBUG_INFO, "MICRON ");
+ } else if(ReadBuffer[1] == SPANSION_ID) {
+ QspiFlashMake = SPANSION_ID;
+ fsbl_printf(DEBUG_INFO, "SPANSION ");
+ } else if(ReadBuffer[1] == WINBOND_ID) {
+ QspiFlashMake = WINBOND_ID;
+ fsbl_printf(DEBUG_INFO, "WINBOND ");
+ } else if(ReadBuffer[1] == MACRONIX_ID) {
+ QspiFlashMake = MACRONIX_ID;
+ fsbl_printf(DEBUG_INFO, "MACRONIX ");
+ } else if(ReadBuffer[0] == ISSI_ID) {
+ QspiFlashMake = ISSI_ID;
+ fsbl_printf(DEBUG_INFO, "ISSI ");
+ }
+
+ /*
+ * Deduce flash Size
+ */
+ if (ReadBuffer[2] == FLASH_SIZE_ID_8M) {
+ QspiFlashSize = FLASH_SIZE_8M;
+ fsbl_printf(DEBUG_INFO, "8M Bits\r\n");
+ } else if (ReadBuffer[2] == FLASH_SIZE_ID_16M) {
+ QspiFlashSize = FLASH_SIZE_16M;
+ fsbl_printf(DEBUG_INFO, "16M Bits\r\n");
+ } else if (ReadBuffer[2] == FLASH_SIZE_ID_32M) {
+ QspiFlashSize = FLASH_SIZE_32M;
+ fsbl_printf(DEBUG_INFO, "32M Bits\r\n");
+ } else if (ReadBuffer[2] == FLASH_SIZE_ID_64M) {
+ QspiFlashSize = FLASH_SIZE_64M;
+ fsbl_printf(DEBUG_INFO, "64M Bits\r\n");
+ } else if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
+ QspiFlashSize = FLASH_SIZE_128M;
+ fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
+ } else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
+ QspiFlashSize = FLASH_SIZE_256M;
+ fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
+ } else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M)
+ || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) {
+ QspiFlashSize = FLASH_SIZE_512M;
+ fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
+ } else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G)
+ || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) {
+ QspiFlashSize = FLASH_SIZE_1G;
+ fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/******************************************************************************
+*
+* This function reads from the serial FLASH connected to the
+* QSPI interface.
+*
+* @param Address contains the address to read data from in the FLASH.
+* @param ByteCount contains the number of bytes to read.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void FlashRead(u32 Address, u32 ByteCount)
+{
+ /*
+ * Setup the write command with the specified address and data for the
+ * FLASH
+ */
+ u32 LqspiCrReg;
+ u8 ReadCommand;
+
+ LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
+ ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK);
+ WriteBuffer[COMMAND_OFFSET] = ReadCommand;
+ WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
+ WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
+ WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
+
+ ByteCount += DUMMY_SIZE;
+
+ /*
+ * Send the read command to the FLASH to read the specified number
+ * of bytes from the FLASH, send the read command and address and
+ * receive the specified number of bytes of data in the data buffer
+ */
+ XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ ByteCount + OVERHEAD_SIZE);
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the QSPI FLASH interface for the Simplified header
+* functionality.
+*
+* @param SourceAddress is address in FLASH data space
+* @param DestinationAddress is address in DDR data space
+* @param LengthBytes is the length of the data in Bytes
+*
+* @return
+* - XST_SUCCESS if the write completes correctly
+* - XST_FAILURE if the write fails to completes correctly
+*
+* @note none.
+*
+****************************************************************************/
+u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+ u8 *BufferPtr;
+ u32 Length = 0;
+ u32 BankSel = 0;
+ u32 LqspiCrReg;
+ u32 Status;
+ u8 BankSwitchFlag = 1;
+
+ /*
+ * Linear access check
+ */
+ if (LinearBootDeviceFlag == 1) {
+ /*
+ * Check for non-word tail, add bytes to cover the end
+ */
+ if ((LengthBytes%4) != 0){
+ LengthBytes += (4 - (LengthBytes & 0x00000003));
+ }
+
+ memcpy((void*)DestinationAddress,
+ (const void*)(SourceAddress + FlashReadBaseAddress),
+ (size_t)LengthBytes);
+ } else {
+ /*
+ * Non Linear access
+ */
+ BufferPtr = (u8*)DestinationAddress;
+
+ /*
+ * Dual parallel connection actual flash is half
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+ SourceAddress = SourceAddress/2;
+ }
+
+ while(LengthBytes > 0) {
+ /*
+ * Local of DATA_SIZE size used for read/write buffer
+ */
+ if(LengthBytes > DATA_SIZE) {
+ Length = DATA_SIZE;
+ } else {
+ Length = LengthBytes;
+ }
+
+ /*
+ * Dual stack connection
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
+ /*
+ * Get the current LQSPI configuration value
+ */
+ LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
+
+ /*
+ * Select lower or upper Flash based on sector address
+ */
+ if (SourceAddress >= (QspiFlashSize/2)) {
+ /*
+ * Set selection to U_PAGE
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
+ LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
+
+ /*
+ * Subtract first flash size when accessing second flash
+ */
+ SourceAddress = SourceAddress - (QspiFlashSize/2);
+
+ fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
+
+ /*
+ * Assert the FLASH chip select.
+ */
+ XQspiPs_SetSlaveSelect(QspiInstancePtr);
+ }
+ }
+
+ /*
+ * Select bank
+ */
+ if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
+ BankSel = SourceAddress/FLASH_SIZE_16MB;
+
+ fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel);
+
+ Status = SendBankSelect(BankSel);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
+ return XST_FAILURE;
+ }
+
+ BankSwitchFlag = 0;
+ }
+
+ /*
+ * If data to be read spans beyond the current bank, then
+ * calculate length in current bank else no change in length
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+ /*
+ * In dual parallel mode, check should be for half
+ * the length.
+ */
+ if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
+ {
+ Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
+ /*
+ * Above length calculated is for single flash
+ * Length should be doubled since dual parallel
+ */
+ Length = Length * 2;
+ BankSwitchFlag = 1;
+ }
+ } else {
+ if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
+ {
+ Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
+ BankSwitchFlag = 1;
+ }
+ }
+
+ /*
+ * Copying the image to local buffer
+ */
+ FlashRead(SourceAddress, Length);
+
+ /*
+ * Moving the data from local buffer to DDR destination address
+ */
+ memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
+
+ /*
+ * Updated the variables
+ */
+ LengthBytes -= Length;
+
+ /*
+ * For Dual parallel connection address increment should be half
+ */
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
+ SourceAddress += Length/2;
+ } else {
+ SourceAddress += Length;
+ }
+
+ BufferPtr = (u8*)((u32)BufferPtr + Length);
+ }
+
+ /*
+ * Reset Bank selection to zero
+ */
+ Status = SendBankSelect(0);
+ if (Status != XST_SUCCESS) {
+ fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
+ return XST_FAILURE;
+ }
+
+ if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
+
+ /*
+ * Reset selection to L_PAGE
+ */
+ XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
+ LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
+
+ fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
+
+ /*
+ * Assert the FLASH chip select.
+ */
+ XQspiPs_SetSlaveSelect(QspiInstancePtr);
+ }
+ }
+
+ return XST_SUCCESS;
+}
+
+
+
+/******************************************************************************
+*
+* This functions selects the current bank
+*
+* @param BankSel is the bank to be selected in the flash device(s).
+*
+* @return XST_SUCCESS if bank selected
+* XST_FAILURE if selection failed
+* @note None.
+*
+******************************************************************************/
+u32 SendBankSelect(u8 BankSel)
+{
+ u32 Status;
+
+ /*
+ * bank select commands for Micron and Spansion are different
+ * Macronix bank select is same as Micron
+ */
+ if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
+ /*
+ * For micron command WREN should be sent first
+ * except for some specific feature set
+ */
+ WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
+ WRITE_ENABLE_CMD_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
+ WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ if (QspiFlashMake == SPANSION_ID) {
+ WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
+ WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * For testing - Read bank to verify
+ */
+ if (QspiFlashMake == SPANSION_ID) {
+ WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
+ WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
+ WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
+ WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
+
+ /*
+ * Send the Extended address register write command
+ * written, no receive buffer required
+ */
+ Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
+ BANK_SEL_SIZE);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+ }
+
+ if (ReadBuffer[1] != BankSel) {
+ fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
+ ReadBuffer[1]);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+#endif
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.h
new file mode 100644
index 0000000..1221726
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.h
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file qspi.h
+*
+* This file contains the interface for the QSPI FLASH functionality
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm 01/10/10 Initial release
+* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
+* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
+* Dual Stack support
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___QSPI_H___
+#define ___QSPI_H___
+
+#include "fsbl.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "fsbl.h"
+
+/************************** Constant Definitions *****************************/
+#define SINGLE_FLASH_CONNECTION 0
+#define DUAL_STACK_CONNECTION 1
+#define DUAL_PARALLEL_CONNECTION 2
+#define FLASH_SIZE_16MB 0x1000000
+
+/*
+ * Bank mask
+ */
+#define BANKMASK 0xF000000
+
+/*
+ * Identification of Flash
+ * Micron:
+ * Byte 0 is Manufacturer ID;
+ * Byte 1 is first byte of Device ID - 0xBB or 0xBA
+ * Byte 2 is second byte of Device ID describes flash size:
+ * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
+ * Spansion:
+ * Byte 0 is Manufacturer ID;
+ * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
+ * Byte 2 is second byte of Device ID describes flash size:
+ * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
+ */
+
+#define MICRON_ID 0x20
+#define SPANSION_ID 0x01
+#define WINBOND_ID 0xEF
+#define MACRONIX_ID 0xC2
+#define ISSI_ID 0x9D
+
+#define FLASH_SIZE_ID_8M 0x14
+#define FLASH_SIZE_ID_16M 0x15
+#define FLASH_SIZE_ID_32M 0x16
+#define FLASH_SIZE_ID_64M 0x17
+#define FLASH_SIZE_ID_128M 0x18
+#define FLASH_SIZE_ID_256M 0x19
+#define FLASH_SIZE_ID_512M 0x20
+#define FLASH_SIZE_ID_1G 0x21
+/* Macronix size constants are different for 512M and 1G */
+#define MACRONIX_FLASH_SIZE_ID_512M 0x1A
+#define MACRONIX_FLASH_SIZE_ID_1G 0x1B
+
+/*
+ * Size in bytes
+ */
+#define FLASH_SIZE_8M 0x0100000
+#define FLASH_SIZE_16M 0x0200000
+#define FLASH_SIZE_32M 0x0400000
+#define FLASH_SIZE_64M 0x0800000
+#define FLASH_SIZE_128M 0x1000000
+#define FLASH_SIZE_256M 0x2000000
+#define FLASH_SIZE_512M 0x4000000
+#define FLASH_SIZE_1G 0x8000000
+
+/************************** Function Prototypes ******************************/
+u32 InitQspi(void);
+
+u32 QspiAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthBytes);
+
+u32 FlashReadID(void);
+u32 SendBankSelect(u8 BankSel);
+/************************** Variable Definitions *****************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___QSPI_H___ */
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/rsa.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/rsa.c
new file mode 100644
index 0000000..6ddaa02
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/rsa.c
@@ -0,0 +1,357 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file rsa.c
+*
+* Contains code for the RSA authentication
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.00a sgd 02/28/13 Initial release
+* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
+* Fix for CR#724165 - Partition Header used by FSBL is
+* not authenticated
+* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+* by Boot ROM for authenticating
+* the Partition images
+* Fix for CR#722979 - Provide customer-friendly
+* changelogs in FSBL
+* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
+* fallback unless FSBL* and FSBL are
+* identical in length
+* Fix for CR#791245 - Use of xilrsa in FSBL
+*
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef RSA_SUPPORT
+#include "fsbl.h"
+#include "rsa.h"
+#include "xilrsa.h"
+
+#ifdef XPAR_XWDTPS_0_BASEADDR
+#include "xwdtps.h"
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+#ifdef XPAR_XWDTPS_0_BASEADDR
+extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
+#endif
+
+
+/************************** Variable Definitions *****************************/
+
+static u8 *PpkModular;
+static u8 *PpkModularEx;
+static u32 PpkExp;
+static u32 PpkAlreadySet=0;
+
+extern u32 FsblLength;
+
+void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
+{
+#ifdef FSBL_DEBUG_RSA
+ int Index;
+ fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
+ for (Index=0;Index
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.00a sg 02/28/13 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___RSA_H___
+#define ___RSA_H___
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************************** Include Files *********************************/
+
+
+#define RSA_PPK_MODULAR_SIZE 256
+#define RSA_PPK_MODULAR_EXT_SIZE 256
+#define RSA_PPK_EXPO_SIZE 64
+#define RSA_SPK_MODULAR_SIZE 256
+#define RSA_SPK_MODULAR_EXT_SIZE 256
+#define RSA_SPK_EXPO_SIZE 64
+#define RSA_SPK_SIGNATURE_SIZE 256
+#define RSA_PARTITION_SIGNATURE_SIZE 256
+#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */
+#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
+#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
+
+void SetPpk(void );
+u32 AuthenticatePartition(u8 *Buffer, u32 Size);
+u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___RSA_H___ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.c b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.c
new file mode 100644
index 0000000..5b2048e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.c
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file sd.c
+*
+* Contains code for the SD card FLASH functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz 04/28/11 Initial release
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+* 12.00a ssc 12/11/14 Fix for CR# 839182
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "fsbl.h"
+
+#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
+
+#ifndef XPAR_PS7_SD_0_S_AXI_BASEADDR
+#define XPAR_PS7_SD_0_S_AXI_BASEADDR XPAR_XSDPS_0_BASEADDR
+#endif
+
+#include "xstatus.h"
+
+#include "ff.h"
+#include "sd.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 FlashReadBaseAddress;
+
+
+static FIL fil; /* File object */
+static FATFS fatfs;
+static char buffer[32];
+static char *boot_file = buffer;
+
+/******************************************************************************/
+/******************************************************************************/
+/**
+*
+* This function initializes the controller for the SD FLASH interface.
+*
+* @param filename of the file that is to be used
+*
+* @return
+* - XST_SUCCESS if the controller initializes correctly
+* - XST_FAILURE if the controller fails to initializes correctly
+*
+* @note None.
+*
+****************************************************************************/
+u32 InitSD(const char *filename)
+{
+
+ FRESULT rc;
+ TCHAR *path = "0:/"; /* Logical drive number is 0 */
+
+ /* Register volume work area, initialize device */
+ rc = f_mount(&fatfs, path, 0);
+ fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc);
+
+ if (rc != FR_OK) {
+ return XST_FAILURE;
+ }
+
+ strcpy_rom(buffer, filename);
+ boot_file = (char *)buffer;
+ FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR;
+
+ rc = f_open(&fil, boot_file, FA_READ);
+ if (rc) {
+ fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc);
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+
+}
+
+/******************************************************************************/
+/**
+*
+* This function provides the SD FLASH interface for the Simplified header
+* functionality.
+*
+* @param SourceAddress is address in FLASH data space
+* @param DestinationAddress is address in OCM data space
+* @param LengthBytes is the number of bytes to move
+*
+* @return
+* - XST_SUCCESS if the write completes correctly
+* - XST_FAILURE if the write fails to completes correctly
+*
+* @note None.
+*
+****************************************************************************/
+u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
+{
+
+ FRESULT rc; /* Result code */
+ UINT br;
+
+ rc = f_lseek(&fil, SourceAddress);
+ if (rc) {
+ fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress);
+ return XST_FAILURE;
+ }
+
+ rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br);
+
+ if (rc) {
+ fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc);
+ }
+
+ return XST_SUCCESS;
+
+} /* End of SDAccess */
+
+
+/******************************************************************************/
+/**
+*
+* This function closes the file object
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void ReleaseSD(void) {
+
+ f_close(&fil);
+ return;
+
+
+}
+#endif
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.h b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.h
new file mode 100644
index 0000000..f130bc7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.h
@@ -0,0 +1,75 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file sd.h
+*
+* This file contains the interface for the Secure Digital (SD) card
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bh 03/10/11 Initial release
+* 7.00a kc 10/18/13 Integrated SD/MMC driver
+*
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___SD_H___
+#define ___SD_H___
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/************************** Function Prototypes ******************************/
+
+#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
+u32 InitSD(const char *);
+
+u32 SDAccess( u32 SourceAddress,
+ u32 DestinationAddress,
+ u32 LengthWords);
+
+void ReleaseSD(void);
+#endif
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ___SD_H___ */
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.cproject b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.cproject
new file mode 100644
index 0000000..b1ffa4f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.cproject
@@ -0,0 +1,13 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.project b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.project
new file mode 100644
index 0000000..1d8f46c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.project
@@ -0,0 +1,75 @@
+
+
+ FSBL_bsp
+ Created by SDK v2018.3
+
+
+
+
+ org.eclipse.cdt.make.core.makeBuilder
+
+
+ org.eclipse.cdt.core.errorOutputParser
+ org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;
+
+
+ org.eclipse.cdt.make.core.append_environment
+ true
+
+
+ org.eclipse.cdt.make.core.build.arguments
+
+
+
+ org.eclipse.cdt.make.core.build.command
+ make
+
+
+ org.eclipse.cdt.make.core.build.target.auto
+ all
+
+
+ org.eclipse.cdt.make.core.build.target.clean
+ clean
+
+
+ org.eclipse.cdt.make.core.build.target.inc
+ all
+
+
+ org.eclipse.cdt.make.core.enableAutoBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableCleanBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableFullBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enabledIncrementalBuild
+ true
+
+
+ org.eclipse.cdt.make.core.environment
+
+
+
+ org.eclipse.cdt.make.core.stopOnError
+ false
+
+
+ org.eclipse.cdt.make.core.useDefaultBuildCmd
+ true
+
+
+
+
+
+ com.xilinx.sdk.sw.SwProjectNature
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.make.core.makeNature
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.sdkproject b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.sdkproject
new file mode 100644
index 0000000..923eee0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/.sdkproject
@@ -0,0 +1,4 @@
+THIRPARTY=false
+HW_PROJECT_REFERENCE=system_wrapper_hw_platform_0
+PROCESSOR=ps7_cortexa9_0
+MSS_FILE=system.mss
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/Makefile
new file mode 100644
index 0000000..db5fc27
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/Makefile
@@ -0,0 +1,35 @@
+# Makefile generated by Xilinx.
+
+PROCESSOR = ps7_cortexa9_0
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
+
+all: libs
+ @echo 'Finished building libraries'
+
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+libs: $(addsuffix /make.libs,$(SUBDIRS))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+ cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+ @echo "Running Make include in $(subst /make.include,,$@)"
+ $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
+
+%/make.libs: include
+ @echo "Running Make libs in $(subst /make.libs,,$@)"
+ $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
+
+%/make.clean:
+ $(MAKE) -C $(subst /make.clean,,$@) -s clean
+clean:
+ rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
new file mode 100644
index 0000000..1647600
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
@@ -0,0 +1,308 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+* Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+# define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+# define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+ ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
+ (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
+ ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+ (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
+ ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ * 1. XTime_PITDisableInterrupt() ;
+ * 2. Store the remaining timer clk tick
+ * 3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
+ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
+ mtspr(XREG_SPR_PIT, 0); \
+ }
+#else
+#define disable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ * 1. Load the remaining timer clk ticks
+ * 2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
+ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+ }
+#else
+#define enable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 1. Load the timer clk ticks
+ * 2. Enable AutoReload and Interrupt
+ * 3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack() \
+ { \
+ u32 val; \
+ mtspr(XREG_SPR_PIT, timer_clk_ticks); \
+ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+ }
+#else
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
+ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
+ }
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(Addr); \
+ tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+ u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+ OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ OutAddr += (u32)XTC_TCSR_OFFSET; \
+ ProfIo_Out32(OutAddr, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = (u32)ProfIo_In32(Addr); \
+ tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
+ ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
+ }
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+{ \
+ Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+ (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/bspconfig.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/bspconfig.h
new file mode 100644
index 0000000..69c1dc8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/bspconfig.h
@@ -0,0 +1,44 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+/* Definition for hard-float ABI */
+#define FPU_HARD_FLOAT_ABI_ENABLED 1
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/diskio.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/diskio.h
new file mode 100644
index 0000000..e8cb253
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/diskio.h
@@ -0,0 +1,79 @@
+/*-----------------------------------------------------------------------/
+/ Low level disk interface modlue include file (C)ChaN, 2014 /
+/-----------------------------------------------------------------------*/
+
+#ifndef DISKIO_DEFINED
+#define DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USE_WRITE 1 /* 1: Enable disk_write function */
+#define USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
+
+#include "integer.h"
+#include "xil_types.h"
+
+/* Status of Disk Functions */
+typedef BYTE DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+ RES_OK = 0, /* 0: Successful */
+ RES_ERROR, /* 1: R/W Error */
+ RES_WRPRT, /* 2: Write Protected */
+ RES_NOTRDY, /* 3: Not Ready */
+ RES_PARERR /* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT 0x01U /* Drive not initialized */
+#define STA_NODISK 0x02U /* No medium in the drive */
+#define STA_PROTECT 0x04U /* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (used by FatFs) */
+#define CTRL_SYNC 0U /* Flush disk cache (for write functions) */
+#define GET_SECTOR_COUNT 1U /* Get media size (for only f_mkfs()) */
+#define GET_SECTOR_SIZE 2U /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
+#define GET_BLOCK_SIZE 3U /* Get erase block size (for only f_mkfs()) */
+#define CTRL_ERASE_SECTOR 4U /* Force erased a block of sectors (for only _USE_ERASE) */
+
+/* Generic command (not used by FatFs) */
+#define CTRL_POWER 5U /* Get/Set power status */
+#define CTRL_LOCK 6U /* Lock/Unlock media removal */
+#define CTRL_EJECT 7U /* Eject media */
+#define CTRL_FORMAT 8U /* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE 10U /* Get card type */
+#define MMC_GET_CSD 11U /* Get CSD */
+#define MMC_GET_CID 12U /* Get CID */
+#define MMC_GET_OCR 13U /* Get OCR */
+#define MMC_GET_SDSTAT 14U /* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV 20U /* Get F/W revision */
+#define ATA_GET_MODEL 21U /* Get model name */
+#define ATA_GET_SN 22U /* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/ff.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/ff.h
new file mode 100644
index 0000000..cc4bee7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/ff.h
@@ -0,0 +1,424 @@
+/*----------------------------------------------------------------------------/
+/ FatFs - Generic FAT Filesystem module R0.13b /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2018, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/ this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef FF_DEFINED
+#define FF_DEFINED 63463 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "integer.h" /* Basic integer types */
+#include "ffconf.h" /* FatFs configuration options */
+
+#if FF_DEFINED != FFCONF_DEF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if FF_MULTI_PARTITION /* Multiple partition configuration */
+typedef struct {
+ BYTE pd; /* Physical drive number */
+ BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifndef FF_VOLUME_STRS
+extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
+#endif
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#ifndef _INC_TCHAR
+#define _INC_TCHAR
+
+#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
+typedef char TCHAR;
+#define _T(x) u8 ## x
+#define _TEXT(x) u8 ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
+typedef DWORD TCHAR;
+#define _T(x) U ## x
+#define _TEXT(x) U ## x
+#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
+#error Wrong FF_LFN_UNICODE setting
+#else /* ANSI/OEM code in SBCS/DBCS */
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* Type of file size variables */
+
+#if FF_FS_EXFAT
+typedef QWORD FSIZE_t;
+#else
+typedef DWORD FSIZE_t;
+#endif
+
+
+
+/* Filesystem object structure (FATFS) */
+
+typedef struct {
+ BYTE fs_type; /* Filesystem type (0:N/A) */
+ BYTE pdrv; /* Physical drive number */
+ BYTE n_fats; /* Number of FATs (1 or 2) */
+ BYTE wflag; /* win[] flag (b0:dirty) */
+ BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
+ WORD id; /* Volume mount ID */
+ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
+ WORD csize; /* Cluster size [sectors] */
+#if FF_MAX_SS != FF_MIN_SS
+ WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if FF_USE_LFN
+ WCHAR* lfnbuf; /* LFN working buffer */
+#endif
+#if FF_FS_EXFAT
+ BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
+#endif
+#if FF_FS_REENTRANT
+ FF_SYNC_t sobj; /* Identifier of sync object */
+#endif
+#if !FF_FS_READONLY
+ DWORD last_clst; /* Last allocated cluster */
+ DWORD free_clst; /* Number of free clusters */
+#endif
+#if FF_FS_RPATH
+ DWORD cdir; /* Current directory start cluster (0:root) */
+#if FF_FS_EXFAT
+ DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
+ DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
+ DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+ DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
+ DWORD fsize; /* Size of an FAT [sectors] */
+ DWORD volbase; /* Volume base sector */
+ DWORD fatbase; /* FAT base sector */
+ DWORD dirbase; /* Root directory base sector/cluster */
+ DWORD database; /* Data base sector */
+ DWORD winsect; /* Current sector appearing in the win[] */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ BYTE win[FF_MAX_SS];
+#pragma data_alignment = 4
+#else
+#ifdef __aarch64__
+ BYTE win[FF_MAX_SS] __attribute__ ((aligned(64))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
+#else
+ BYTE win[FF_MAX_SS] __attribute__ ((aligned(32))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
+#endif
+#endif
+} FATFS;
+
+
+
+/* Object ID and allocation information (FFOBJID) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the hosting volume of this object */
+ WORD id; /* Hosting volume mount ID */
+ BYTE attr; /* Object attribute */
+ BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
+ DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
+ FSIZE_t objsize; /* Object size (valid when sclust != 0) */
+#if FF_FS_EXFAT
+ DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
+ DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
+ DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
+ DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+ DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
+#endif
+#if FF_FS_LOCK
+ UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} FFOBJID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+ FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
+ BYTE flag; /* File status flags */
+ BYTE err; /* Abort flag (error code) */
+ FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
+ DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
+ DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
+#if !FF_FS_READONLY
+ DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
+ BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
+#endif
+#if FF_USE_FASTSEEK
+ DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !FF_FS_TINY
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ BYTE buf[FF_MAX_SS]; /* File private data read/write window */
+#pragma data_alignment = 4
+#else
+#ifdef __aarch64__
+ BYTE buf[FF_MAX_SS] __attribute__ ((aligned(64))); /* File private data read/write window */
+#else
+ BYTE buf[FF_MAX_SS] __attribute__ ((aligned(32))); /* File private data read/write window */
+#endif
+#endif
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+ FFOBJID obj; /* Object identifier */
+ DWORD dptr; /* Current read/write offset */
+ DWORD clust; /* Current cluster */
+ DWORD sect; /* Current sector (0:Read operation has terminated) */
+ BYTE* dir; /* Pointer to the directory item in the win[] */
+ BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
+#if FF_USE_LFN
+ DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if FF_USE_FIND
+ const TCHAR* pat; /* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+ FSIZE_t fsize; /* File size */
+ WORD fdate; /* Modified date */
+ WORD ftime; /* Modified time */
+ BYTE fattrib; /* File attribute */
+#if FF_USE_LFN
+ TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
+ TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
+#else
+ TCHAR fname[12 + 1]; /* File name */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+ FR_OK = 0, /* (0) Succeeded */
+ FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
+ FR_INT_ERR, /* (2) Assertion failed */
+ FR_NOT_READY, /* (3) The physical drive cannot work */
+ FR_NO_FILE, /* (4) Could not find the file */
+ FR_NO_PATH, /* (5) Could not find the path */
+ FR_INVALID_NAME, /* (6) The path name format is invalid */
+ FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
+ FR_EXIST, /* (8) Access denied due to prohibited access */
+ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
+ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
+ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
+ FR_NOT_ENABLED, /* (12) The volume has no work area */
+ FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
+ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
+ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
+ FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
+ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
+ FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
+ FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
+FRESULT f_close (FIL* fp); /* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp); /* Truncate the file */
+FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
+FRESULT f_closedir (DIR* dp); /* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
+FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path); /* Change current directory */
+FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
+FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
+FRESULT f_setcp (WORD cp); /* Set current code page */
+int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, s32 len, FIL* fp); /* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+#define f_unmount(path) f_mount(0, path, 0)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions */
+
+/* RTC function */
+#if !FF_FS_READONLY && !FF_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* LFN support functions */
+#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
+WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
+WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
+DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
+#endif
+#if FF_USE_LFN == 3 /* Dynamic memory allocation */
+void* ff_memalloc (UINT msize); /* Allocate memory block */
+void ff_memfree (void* mblock); /* Free memory block */
+#endif
+
+/* Sync functions */
+#if FF_FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
+int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
+void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
+int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address */
+
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define FA_READ 0x01
+#define FA_WRITE 0x02
+#define FA_OPEN_EXISTING 0x00
+#define FA_CREATE_NEW 0x04
+#define FA_CREATE_ALWAYS 0x08
+#define FA_OPEN_ALWAYS 0x10
+#define FA_OPEN_APPEND 0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT 0x01
+#define FM_FAT32 0x02
+#define FM_EXFAT 0x04
+#define FM_ANY 0x07
+#define FM_SFD 0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12 1
+#define FS_FAT16 2
+#define FS_FAT32 3
+#define FS_EXFAT 4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define AM_RDO 0x01 /* Read only */
+#define AM_HID 0x02 /* Hidden */
+#define AM_SYS 0x04 /* System */
+#define AM_DIR 0x10 /* Directory */
+#define AM_ARC 0x20 /* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FF_DEFINED */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/ffconf.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/ffconf.h
new file mode 100644
index 0000000..857d978
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/ffconf.h
@@ -0,0 +1,403 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - Configuration file
+/---------------------------------------------------------------------------*/
+
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#define FFCONF_DEF 63463 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xparameters.h"
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+#ifdef FILE_SYSTEM_READ_ONLY
+#define FF_FS_READONLY 1 /* 1:Read only */
+#else
+#define FF_FS_READONLY 0 /* 0:Read/Write */
+#endif
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/ Read-only configuration removes writing API functions, f_write(), f_sync(),
+/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/ and optional writing functions as well. */
+
+
+#define FF_FS_MINIMIZE 0
+/* This option defines minimization level to remove some basic API functions.
+/
+/ 0: Basic functions are fully enabled.
+/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/ are removed.
+/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/ 3: f_lseek() function is removed in addition to 2. */
+
+
+#if FILE_SYSTEM_USE_STRFUNC == 0
+#define FF_USE_STRFUNC 0 /* 0:Disable */
+#elif FILE_SYSTEM_USE_STRFUNC == 1
+#define FF_USE_STRFUNC 1 /* 1:Enable */
+#elif FILE_SYSTEM_USE_STRFUNC == 2
+#define FF_USE_STRFUNC 2 /* 2:Enable */
+#endif
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
+/
+/ 0: Disable string functions.
+/ 1: Enable without LF-CRLF conversion.
+/ 2: Enable with LF-CRLF conversion. */
+
+
+#define FF_USE_FIND 0
+/* This option switches filtered directory read functions, f_findfirst() and
+/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#ifdef FILE_SYSTEM_USE_MKFS
+#define FF_USE_MKFS 1 /* 1:Enable */
+#else
+#define FF_USE_MKFS 0 /* 0:Disable */
+#endif
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FASTSEEK 0
+/* This option switches fast seek function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_EXPAND 0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_CHMOD 0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
+
+
+#define FF_USE_LABEL 0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/ (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FORWARD 0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_CODE_PAGE 932
+/* This option specifies the OEM code page to be used on the target system.
+/ Incorrect code page setting can cause a file open failure.
+/
+/ 437 - U.S.
+/ 720 - Arabic
+/ 737 - Greek
+/ 771 - KBL
+/ 775 - Baltic
+/ 850 - Latin 1
+/ 852 - Latin 2
+/ 855 - Cyrillic
+/ 857 - Turkish
+/ 860 - Portuguese
+/ 861 - Icelandic
+/ 862 - Hebrew
+/ 863 - Canadian French
+/ 864 - Arabic
+/ 865 - Nordic
+/ 866 - Russian
+/ 869 - Greek 2
+/ 932 - Japanese (DBCS)
+/ 936 - Simplified Chinese (DBCS)
+/ 949 - Korean (DBCS)
+/ 950 - Traditional Chinese (DBCS)
+/ 0 - Include all code pages above and configured by f_setcp()
+*/
+
+
+#ifdef FILE_SYSTEM_USE_LFN
+#define FF_USE_LFN 1 /* 0 to 3 */
+#else
+#define FF_USE_LFN 0 /* 0 to 3 */
+#endif
+#define FF_MAX_LFN 255
+/* The FF_USE_LFN switches the support for LFN (long file name).
+/
+/ 0: Disable LFN. FF_MAX_LFN has no effect.
+/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/ 2: Enable LFN with dynamic working buffer on the STACK.
+/ 3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
+/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
+/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
+/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
+/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
+/ specification.
+/ When use stack for the working buffer, take care on stack overflow. When use heap
+/ memory for the working buffer, memory management functions, ff_memalloc() and
+/ ff_memfree() in ffsystem.c, need to be added to the project. */
+
+
+#define FF_LFN_UNICODE 0
+/* This option switches the character encoding on the API when LFN is enabled.
+/
+/ 0: ANSI/OEM in current CP (TCHAR = char)
+/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
+/ 2: Unicode in UTF-8 (TCHAR = char)
+/ 3: Unicode in UTF-32 (TCHAR = DWORD)
+/
+/ Also behavior of string I/O functions will be affected by this option.
+/ When LFN is not enabled, this option has no effect. */
+
+
+#define FF_LFN_BUF 255
+#define FF_SFN_BUF 12
+/* This set of options defines size of file name members in the FILINFO structure
+/ which is used to read out directory items. These values should be suffcient for
+/ the file names to read. The maximum possible length of the read file name depends
+/ on character encoding. When LFN is not enabled, these options have no effect. */
+
+
+#define FF_STRF_ENCODE 3
+/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
+/ f_putc(), f_puts and f_printf() convert the character encoding in it.
+/ This option selects assumption of character encoding ON THE FILE to be
+/ read/written via those functions.
+/
+/ 0: ANSI/OEM in current CP
+/ 1: Unicode in UTF-16LE
+/ 2: Unicode in UTF-16BE
+/ 3: Unicode in UTF-8
+*/
+
+
+#if FILE_SYSTEM_SET_FS_RPATH == 0
+#define FF_FS_RPATH 0U
+#elif FILE_SYSTEM_SET_FS_RPATH == 1
+#define FF_FS_RPATH 1U
+#elif FILE_SYSTEM_SET_FS_RPATH == 2
+#define FF_FS_RPATH 2U
+#endif
+/* This option configures support for relative path.
+/
+/ 0: Disable relative path and remove related functions.
+/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
+/ 2: f_getcwd() function is available in addition to 1.
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#if FILE_SYSTEM_NUM_LOGIC_VOL == 1
+#define FF_VOLUMES 1U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 2
+#define FF_VOLUMES 2U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 3
+#define FF_VOLUMES 3U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 4
+#define FF_VOLUMES 4U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 5
+#define FF_VOLUMES 5U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 6
+#define FF_VOLUMES 6U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 7
+#define FF_VOLUMES 7U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 8
+#define FF_VOLUMES 8U
+#elif FILE_SYSTEM_NUM_LOGIC_VOL == 9
+#define FF_VOLUMES 9U
+#else
+#define FF_VOLUMES 10U
+#endif
+/* Number of volumes (logical drives) to be used. (1-10) */
+
+
+#define FF_STR_VOLUME_ID 0
+#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
+/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
+/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
+/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
+/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
+/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
+/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
+/ not defined, a user defined volume string table needs to be defined as:
+/
+/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
+*/
+
+
+#ifdef FILE_SYSTEM_MULTI_PARTITION
+#define FF_MULTI_PARTITION 1 /* 1:Enable multiple partition */
+#else
+#define FF_MULTI_PARTITION 0 /* 0:Single partition */
+#endif
+/* This option switches support for multiple volumes on the physical drive.
+/ By default (0), each logical drive number is bound to the same physical drive
+/ number and only an FAT volume found on the physical drive will be mounted.
+/ When this function is enabled (1), each logical drive number can be bound to
+/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/ funciton will be available. */
+
+
+#define FF_MIN_SS 512
+#define FF_MAX_SS 512
+/* This set of options configures the range of sector size to be supported. (512,
+/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
+/ harddisk. But a larger value may be required for on-board flash memory and some
+/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
+/ for variable sector size mode and disk_ioctl() function needs to implement
+/ GET_SECTOR_SIZE command. */
+
+
+#define FF_USE_TRIM 0
+/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
+/ To enable Trim function, also CTRL_TRIM command should be implemented to the
+/ disk_ioctl() function. */
+
+
+#define FF_FS_NOFSINFO 0
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/ option, and f_getfree() function at first time after volume mount will force
+/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/ bit0=0: Use free cluster count in the FSINFO if available.
+/ bit0=1: Do not trust free cluster count in the FSINFO.
+/ bit1=0: Use last allocated cluster number in the FSINFO if available.
+/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_TINY 0
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
+/ Instead of private sector buffer eliminated from the file object, common sector
+/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
+
+
+#ifdef FILE_SYSTEM_FS_EXFAT
+#define FF_FS_EXFAT 1
+#else
+#define FF_FS_EXFAT 0
+#endif
+/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
+/ To enable exFAT, also LFN needs to be enabled.
+/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
+
+
+#define FF_FS_NORTC 0
+#define FF_NORTC_MON 1
+#define FF_NORTC_MDAY 1
+#define FF_NORTC_YEAR 2018
+/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
+/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
+/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
+/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
+/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
+/ added to the project to read current time form real-time clock. FF_NORTC_MON,
+/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
+/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
+
+
+#define FF_FS_LOCK 0
+/* The option FF_FS_LOCK switches file lock function to control duplicated file open
+/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
+/ is 1.
+/
+/ 0: Disable file lock function. To avoid volume corruption, application program
+/ should avoid illegal open, remove and rename to the open objects.
+/ >0: Enable file lock function. The value defines how many files/sub-directories
+/ can be opened simultaneously under file lock control. Note that the file
+/ lock control is independent of re-entrancy. */
+
+
+#define FF_FS_REENTRANT 0
+#define FF_FS_TIMEOUT 1000
+#define FF_SYNC_t HANDLE
+/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/ module itself. Note that regardless of this option, file access to different
+/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/ and f_fdisk() function, are always not re-entrant. Only file/directory access
+/ to the same volume is under control of this function.
+/
+/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
+/ 1: Enable re-entrancy. Also user provided synchronization handlers,
+/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/ function, must be added to the project. Samples are available in
+/ option/syscall.c.
+/
+/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
+/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
+/ included somewhere in the scope of ff.h. */
+
+/* #include // O/S definitions */
+
+#ifdef FILE_SYSTEM_WORD_ACCESS
+#define FF_WORD_ACCESS 1
+#else
+#define FF_WORD_ACCESS 0
+#endif
+/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
+/ which access method is used to the word data on the FAT volume.
+/
+/ 0: Byte-by-byte access. Always compatible with all platforms.
+/ 1: Word access. Do not choose this unless under both the following conditions.
+/
+/ * Address misaligned memory access is always allowed for ALL instructions.
+/ * Byte order on the memory is little-endian.
+/
+/ If it is the case, FF_WORD_ACCESS can also be set to 1 to improve performance and
+/ reduce code size. Following table shows an example of some processor types.
+/
+/ ARM7TDMI 0 ColdFire 0 V850E 0
+/ Cortex-M3 0 Z80 0/1 V850ES 0/1
+/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
+/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
+/ AVR32 0 RL78 0 R32C 0
+/ PIC18 0/1 SH-2 0 M16C 0/1
+/ PIC24 0 H8S 0 MSP430 0
+/ PIC32 0 H8/300H 0 x86 0/1
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/*--- End of configuration options ---*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/integer.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/integer.h
new file mode 100644
index 0000000..b3c70ca
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/integer.h
@@ -0,0 +1,36 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef FF_INTEGER
+#define FF_INTEGER
+
+#ifdef _WIN32 /* FatFs development platform */
+
+#include
+typedef unsigned __int64 QWORD;
+
+#else /* Embedded platform */
+
+/* These types MUST be 16-bit or 32-bit */
+typedef int INT;
+typedef unsigned int UINT;
+
+/* This type MUST be 8-bit */
+typedef unsigned char BYTE;
+
+/* These types MUST be 16-bit */
+typedef short SHORT;
+typedef unsigned short WORD;
+typedef unsigned short WCHAR;
+
+/* These types MUST be 32-bit */
+typedef long LONG;
+typedef unsigned long DWORD;
+
+/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
+typedef unsigned long long QWORD;
+
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
new file mode 100644
index 0000000..807dda3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char byte;
+typedef short half;
+typedef int word;
+typedef unsigned char ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int uword;
+typedef ubyte boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/profile.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/profile.h
new file mode 100644
index 0000000..63f503a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/profile.h
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef PROFILE_H
+#define PROFILE_H 1
+
+#include
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define HISTCOUNTER u16
+
+struct tostruct {
+ u32 selfpc;
+ s32 count;
+ s16 link;
+ u16 pad;
+};
+
+struct fromstruct {
+ u32 frompc ;
+ s16 link ;
+ u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y) (((x)/(y))*(y))
+#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+ s32 state;
+
+ /* Histogram Information */
+ u16 *kcount; /* No. of bins in histogram */
+ u32 kcountsize; /* Histogram samples */
+
+ /* Call-graph Information */
+ struct fromstruct *froms;
+ u32 fromssize;
+ struct tostruct *tos;
+ u32 tossize;
+
+ /* Initialization I/Ps */
+ u32 lowpc;
+ u32 highpc;
+ u32 textsize;
+ /* u32 cg_froms, */
+ /* u32 cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define GMON_PROF_ON 0
+#define GMON_PROF_BUSY 1
+#define GMON_PROF_ERROR 2
+#define GMON_PROF_OFF 3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define GPROF_STATE 0 /* int: profiling enabling variable */
+#define GPROF_COUNT 1 /* struct: profile tick count buffer */
+#define GPROF_FROMS 2 /* struct: from location hash bucket */
+#define GPROF_TOS 3 /* struct: destination/count structure */
+#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PROFILE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/sleep.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/sleep.h
new file mode 100644
index 0000000..f3a632b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/sleep.h
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep rountines
+* function prototypes.
+*
+*
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/smc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/smc.h
new file mode 100644
index 0000000..f7cc91c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/smc.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 11/03/09 Initial release.
+* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+* as smc.c is removed
+*
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET 0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/vectors.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/vectors.h
new file mode 100644
index 0000000..56bacbc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/vectors.h
@@ -0,0 +1,84 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xadcps.h
new file mode 100644
index 0000000..900edf0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xadcps.h
@@ -0,0 +1,589 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_3
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+* - 10-bit, 200-KSPS (kilo samples per second)
+* Analog-to-Digital Converter (ADC)
+* - Monitoring of on-chip supply voltages and temperature
+* - 1 dedicated differential analog-input pair and
+* 16 auxiliary differential analog-input pairs
+* - Automatic alarms based on user defined limits for the on-chip
+* supply voltages and temperature
+* - Automatic Channel Sequencer, programmable averaging, programmable
+* acquisition time for the external inputs, unipolar or differential
+* input selection for the external inputs
+* - Inbuilt Calibration
+* - Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* XADC Channel Sequencer Modes
+*
+* The XADC Channel Sequencer supports the following operating modes:
+*
+* - Default : This is the default mode after power up.
+* In this mode of operation the XADC operates in
+* a sequence mode, monitoring the on chip sensors:
+* Temperature, VCCINT, and VCCAUX.
+* - One pass through sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers for a single pass and then stops.
+* - Continuous cycling of sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers continuously.
+* - Single channel mode: In this mode the XADC Channel
+* Sequencer is disabled and the XADC operates in a
+* Single Channel Mode.
+* The XADC can operate either in a Continuous or Event
+* driven sampling mode in the single channel mode.
+* - Simultaneous Sampling Mode: In this mode the XADC Channel
+* Sequencer will automatically sequence through eight fixed pairs
+* of auxiliary analog input channels for simulataneous conversion.
+* - Independent ADC mode: In this mode the first ADC (A) is used to
+* is used to implement a fixed monitoring mode similar to the
+* default mode but the alarm fucntions ar eenabled.
+* The second ADC (B) is available to be used with external analog
+* input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* Building the driver
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* Limitations of the driver
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* in xadcps.c to fix CR #693371
+* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
+* CR#749687
+* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+* functions.
+* Modified Assert for XAdcPs_SetSingleChParams in
+* xadcps.c to fix CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
+* xadcps.c (CR#854437).
+* ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
+* 2.3 mn 07/09/18 Fix Doxygen warning
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
+#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
+#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP 0x4 /**< VREFP */
+#define XADCPS_CH_VREFN 0x5 /**< VREFN */
+#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
+#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
+#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
+#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XAdcPs_Config Config; /**< XAdcPs_Config of current device */
+ u32 IsReady; /**< Device is initialized and ready */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in Event Sampling Mode.
+* - FALSE if the device is in Continuous Sampling Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
+ TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in External Mux Mode.
+* - FALSE if the device is NOT in External Mux Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
+ TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param AdcData is the Raw ADC Data from XADC.
+*
+* @return The Temperature in centigrades.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData) \
+ ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param AdcData is the XADC/ADC Raw Data.
+*
+* @return The Voltage in volts.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) \
+ ((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param Temperature is the Temperature in centigrades to be
+* converted to XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature) \
+ ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param Voltage is the Voltage in volts to be converted to
+* XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage) \
+ ((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the value to be written to XADC register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data) \
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Data read from the FIFO
+*
+* @note C-Style signature:
+* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr) \
+ XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+ XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xadcps_hw.h
new file mode 100644
index 0000000..dd51473
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xadcps_hw.h
@@ -0,0 +1,498 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note None.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
+* CR#749687
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+ * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
+ * successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+ *
+ * The definitions are same for the Interrupt Status Register and
+ * Interrupt Mask Register. They are defined only once.
+ * @{
+ */
+#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
+#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
+#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
+#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
+#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
+#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
+#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
+#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+ * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
+#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
+#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
+#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
+#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
+#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
+#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
+#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
+ * Continuous mode selection
+ */
+#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
+ Supply Gain/Offset
+ Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
+ Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+ Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
+ Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+*
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
new file mode 100644
index 0000000..70b8aad
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_4
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
new file mode 100644
index 0000000..e4a5e28
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_7
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
+# extra compiler flags. Now, user can remove default flags
+# from extra compiler flags. It fixes CR#998768.
+******************************************************************************/
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xddrps.h
new file mode 100644
index 0000000..b4d1f56
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xddrps.h
@@ -0,0 +1,62 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ *
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdebug.h
new file mode 100644
index 0000000..650946b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdevcfg.h
new file mode 100644
index 0000000..6586370
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdevcfg.h
@@ -0,0 +1,399 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* Interrupts
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
new file mode 100644
index 0000000..80b6678
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
@@ -0,0 +1,391 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdmaps.h
new file mode 100644
index 0000000..73e2b1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdmaps.h
@@ -0,0 +1,349 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_4
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
+*
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+int XDmaPs_Instr_DMARMB(char *DmaProg);
+int XDmaPs_Instr_DMAWMB(char *DmaProg);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
new file mode 100644
index 0000000..42dfe69
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
@@ -0,0 +1,289 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+*
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps.h
new file mode 100644
index 0000000..c22354f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps.h
@@ -0,0 +1,807 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_8
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * Driver Description
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * Initialization & Configuration
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * Interrupts and Asynchronous Callbacks
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * Virtual Memory
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * DMA
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * Alignment & Data Cache Restrictions
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * Buffer Copying
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * Checksum Offloading
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * PHY Interfaces
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * Asserts
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
+ * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_bd.h
new file mode 100644
index 0000000..2b22223
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_bd.h
@@ -0,0 +1,784 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_8
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * Buffer Descriptors
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * Performance
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
+ * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+ *
+ *
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param InstancePtr is the pointer to XEmacps instance
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
new file mode 100644
index 0000000..ed8ce2a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
@@ -0,0 +1,237 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_hw.h
new file mode 100644
index 0000000..4a01aea
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xemacps_hw.h
@@ -0,0 +1,653 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 3.8 hk 09/17/18 Fix PTP interrupt masks.
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
+
+#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
+
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xenv.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xenv.h
new file mode 100644
index 0000000..9c7c4c3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xenv.h
@@ -0,0 +1,183 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+*
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xenv_standalone.h
new file mode 100644
index 0000000..ef905af
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xenv_standalone.h
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implemention MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xgpiops.h
new file mode 100644
index 0000000..3ab40b9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xgpiops.h
@@ -0,0 +1,274 @@
+
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_4
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
new file mode 100644
index 0000000..59ec921
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_assert.h
new file mode 100644
index 0000000..917de31
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_assert.h
@@ -0,0 +1,191 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+*
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accomodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache.h
new file mode 100644
index 0000000..ce6fcf4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache.h
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache_l.h
new file mode 100644
index 0000000..b6ff809
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache_l.h
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
new file mode 100644
index 0000000..7e2a7d9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
@@ -0,0 +1,89 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_errata.h
new file mode 100644
index 0000000..8ac0795
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_errata.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+*
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_exception.h
new file mode 100644
index 0000000..4da1b73
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_exception.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_hal.h
new file mode 100644
index 0000000..720adf9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_hal.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_io.h
new file mode 100644
index 0000000..00207cf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_io.h
@@ -0,0 +1,341 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+*
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_macroback.h
new file mode 100644
index 0000000..cdc2fe2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_macroback.h
@@ -0,0 +1,1048 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_mem.h
new file mode 100644
index 0000000..afc0f8b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_mem.h
@@ -0,0 +1,55 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+*
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
new file mode 100644
index 0000000..3a26175
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
@@ -0,0 +1,273 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_mmu.h
new file mode 100644
index 0000000..3b63c0b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_mmu.h
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_printf.h
new file mode 100644
index 0000000..016ae3b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+#include
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
new file mode 100644
index 0000000..4449ba6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+*
+*
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testcache.h
new file mode 100644
index 0000000..8289ca9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testcache.h
@@ -0,0 +1,67 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+*
Cache test
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testio.h
new file mode 100644
index 0000000..6f0fc1c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testio.h
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+*
I/O test
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testmem.h
new file mode 100644
index 0000000..ecce6b7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_testmem.h
@@ -0,0 +1,154 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+*
Memory test
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+* - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+* @endcode
+*
+* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*@endcode
+*
+* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_types.h
new file mode 100644
index 0000000..8adaf1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xil_types.h
@@ -0,0 +1,205 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#include
+#include
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xilrsa.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xilrsa.h
new file mode 100644
index 0000000..8b138e6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xilrsa.h
@@ -0,0 +1,252 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 17 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xilrsa.h
+* @addtogroup xilrsa_apis XilRSA APIs and Descriptions
+* @{
+* @cond xilrsa_internal
+* This file contains the RSA algorithm functions
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 hk 27/01/14 First release
+* 1.4 vns 07/06/17 Added dooxygen tags.
+*
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___XIL_RSA_H___
+#define ___XIL_RSA_H___
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************************** Include Files *********************************/
+
+/*
+ * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
+ * 32-bit digits are approximately 4 times faster
+ */
+
+//#define RSA_DIGIT_16
+#define RSA_DIGIT_32
+
+/*
+ * RSA loop unrolling selection
+ * RSA main loop can be unrolled 2, 4 or 8 ways
+ */
+#define RSA_UNROLL 1
+
+/*
+ * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
+ */
+//#define RSA_ARM_OPTIMIZED
+
+/*
+ * Check the compatibility of the selection
+ */
+#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
+ #error Please select a digit size
+#endif
+#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
+ #error Please select just one digit size
+#endif
+#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
+ #error Assembly level code is only supported for the GCC/ARM combination
+#endif
+#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
+ #error Only 1, 2, 4, and 8 unrolling are supported
+#endif
+
+#ifdef RSA_DIGIT_16
+#define RSA_DIGIT unsigned short
+#define RSA_SDIGIT short
+#define RSA_DDIGIT unsigned long
+#endif
+#ifdef RSA_DIGIT_32
+#define RSA_DIGIT unsigned long
+#define RSA_SDIGIT long
+#define RSA_DDIGIT unsigned long long
+#endif
+
+#define RSA_NUMBER RSA_DIGIT *
+#define RSA_NBITS 2048
+#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
+#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
+
+/*
+ * Double-digit to single digit conversion
+ */
+#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
+#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
+
+#define SHA_BLKSIZE 512
+#define SHA_BLKBYTES (SHA_BLKSIZE/8)
+#define SHA_BLKWORDS (SHA_BLKBYTES/4)
+
+#define SHA_VALSIZE 256
+#define SHA_VALBYTES (SHA_VALSIZE/8)
+#define SHA_VALWORDS (SHA_VALBYTES/4)
+
+/*
+ * SHA-256 context structure
+ * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
+ * total byte length counter (used both to manage the buffer and for padding)
+ */
+ //! [sha2_context]
+typedef struct
+{
+ unsigned int state[8];
+ unsigned char buffer[SHA_BLKBYTES];
+ unsigned long long bytes;
+} sha2_context;
+//! [sha2_context]
+/** @}
+@endcond */
+
+/*
+ * RSA-2048 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to encrypt the data using 2048 bit private key.
+ *
+ * @param modular A char pointer which contains the key modulus
+ * @param modular_ext A char pointer which contains the key modulus
+ * extension
+ * @param exponent A char pointer which contains the private key
+ * exponent
+ * @param result A char pointer which contains the encrypted data
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
+ const unsigned char *modular_ext, const unsigned char *exponent,
+ unsigned char *result);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to decrypt the data using 2048 bit public key
+ *
+ * @param a RSA_NUMBER containing the decrypted data.
+ * @param x RSA_NUMBER containing the input data
+ * @param e Unsigned number containing the public key exponent
+ * @param m RSA_NUMBER containing the public key modulus
+ * @param rrm RSA_NUMBER containing the public key modulus extension.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
+ unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
+
+/*
+ * SHA-256 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function calculates the hash for the input data using SHA-256
+ * algorithm. This function internally calls the sha2_init, updates and
+ * finishes functions and updates the result.
+ *
+ * @param In Char pointer which contains the input data.
+ * @param Size Length of the input data
+ * @param Out Pointer to location where resulting hash will be
+ * written.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function initializes the SHA2 context.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_starts(sha2_context *ctx);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function adds the input data to SHA256 calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param input Pointer to the data to add.
+ * @param Out Length of the input data.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function finishes the SHA calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param output Pointer to the calculated hash data.
+ *
+ * @return None
+ *
+ *
+ ******************************************************************************/
+void sha2_finish(sha2_context *ctx, unsigned char* output);
+
+/*
+ * Preprocessing interface (pre-computation of R*R mod M)
+ */
+/**@cond xilrsa_internal */
+void modular_ext(const unsigned char *modular, unsigned char *res);
+/** @}
+@endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___XIL_RSA_H___ */
+/** @} */
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xl2cc.h
new file mode 100644
index 0000000..22373c1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xl2cc.h
@@ -0,0 +1,168 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
new file mode 100644
index 0000000..b8d768f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO 0x1
+#define XL2CC_DRHIT 0x2
+#define XL2CC_DRREQ 0x3
+#define XL2CC_DWHIT 0x4
+#define XL2CC_DWREQ 0x5
+#define XL2CC_DWTREQ 0x6
+#define XL2CC_IRHIT 0x7
+#define XL2CC_IRREQ 0x8
+#define XL2CC_WA 0x9
+#define XL2CC_IPFALLOC 0xa
+#define XL2CC_EPFHIT 0xb
+#define XL2CC_EPFALLOC 0xc
+#define XL2CC_SRRCVD 0xd
+#define XL2CC_SRCONF 0xe
+#define XL2CC_EPFRCVD 0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xparameters.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xparameters.h
new file mode 100644
index 0000000..7e4d5fc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xparameters.h
@@ -0,0 +1,413 @@
+#ifndef XPARAMETERS_H /* prevent circular inclusions */
+#define XPARAMETERS_H /* by using protection macros */
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0U
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+
+
+/******************************************************************/
+
+#include "xparameters_ps.h"
+
+#define STDIN_BASEADDRESS 0xE0001000
+#define STDOUT_BASEADDRESS 0xE0001000
+
+/******************************************************************/
+
+/* Platform specific definitions */
+#define PLATFORM_ZYNQ
+
+/* Definitions for sleep timer configuration */
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER
+
+
+/******************************************************************/
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
+#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
+#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
+#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral MYDNA_READ_V1_0_0 */
+#define XPAR_MYDNA_READ_V1_0_0_BASEADDR 0x43C00000
+#define XPAR_MYDNA_READ_V1_0_0_HIGHADDR 0x43C0FFFF
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 142857132
+#define XPAR_PS7_QSPI_0_QSPI_MODE 0
+#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 142857132
+#define XPAR_XQSPIPS_0_QSPI_MODE 0
+#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUTIMER */
+#define XPAR_XSCUTIMER_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
+#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver SDPS */
+#define XPAR_XSDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
+#define XPAR_PS7_SD_0_BUS_WIDTH 0
+#define XPAR_PS7_SD_0_MIO_BANK 0
+#define XPAR_PS7_SD_0_HAS_EMIO 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_XSDPS_0_BASEADDR 0xE0100000
+#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 0
+#define XPAR_XSDPS_0_MIO_BANK 0
+#define XPAR_XSDPS_0_HAS_EMIO 0
+#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Xilinx FAT File System Library (XilFFs) User Settings */
+#define FILE_SYSTEM_INTERFACE_SD
+#define FILE_SYSTEM_USE_MKFS
+#define FILE_SYSTEM_NUM_LOGIC_VOL 2
+#define FILE_SYSTEM_USE_STRFUNC 0
+#define FILE_SYSTEM_SET_FS_RPATH 0
+#define FILE_SYSTEM_WORD_ACCESS
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xparameters_ps.h
new file mode 100644
index 0000000..2a6a0e0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xparameters_ps.h
@@ -0,0 +1,334 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xplatform_info.h
new file mode 100644
index 0000000..771d4ba
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xplatform_info.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+*
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info(void);
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpm_counter.h
new file mode 100644
index 0000000..39db7d8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpm_counter.h
@@ -0,0 +1,572 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
new file mode 100644
index 0000000..8000a68
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..85b067d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
@@ -0,0 +1,252 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+*
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xqspips.h
new file mode 100644
index 0000000..302c870
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xqspips.h
@@ -0,0 +1,797 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_5
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* Linear Mode
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device. The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+* static configuration structure defined in xqspips_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+* is written into the TXFIFO and de asserted when the TXFIFO becomes
+* empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+* TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+* the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+* TXFIFO write otherwise there could be a race condition where the TXFIFO
+* becomes empty before the new word is written. In that case the
+* transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+* This results in a single transaction to be split into multiple pieces each
+* with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data. The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+* in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* Removed code related to mode fault for CR 671468
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added a flag ShiftReadData to the instance structure
+*. and is used in the XQspiPs_GetReadData API.
+* The ShiftReadData Flag indicates whether the data
+* read from the Rx FIFO needs to be shifted
+* in cases where the data is less than 4 bytes
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* This version of the driver fixes CRs 670197/663787/
+* 670297/671468.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Added macros for Set/Get Rx Watermark. Changed QSPI
+* Enable/Disable macro argument from BaseAddress to
+* Instance Pointer. Added DelayNss argument to SetDelays
+* and GetDelays API's.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+* SetDelays and GetDelays API's include DelayNss parameter.
+* Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register. Renamed Fixed burst error to
+* data FSM error in LQSPI Status register.
+*
+* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
+* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+* Added enable and disable to the XQspiPs_LqspiRead() function
+* Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set.
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added prefix to constant definitions for ConnectionMode
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added API's for QSPI reset and
+* linear mode initialization for boot.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* Updated linear init API for parallel and stacked modes.
+* CR#737760.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
+* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_H /* prevent circular inclusions */
+#define XQSPIPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device. Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats. A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver. These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+ * RX FIFO full
+ */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
+#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
+#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
+#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
+#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
+#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
+#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
+#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
+#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
+#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
+#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
+#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
+#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 1
+#define XQSPIPS_SIZE_TWO 2
+#define XQSPIPS_SIZE_THREE 3
+#define XQSPIPS_SIZE_FOUR 4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE 0
+#define XQSPIPS_CONNECTION_MODE_STACKED 1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param CallBackRef is the callback reference passed in by the upper
+ * layer when setting the callback functions, and passed back to
+ * the upper layer when the callback is invoked. Its type is
+ * not important to the driver, so it is a void pointer.
+ * @param StatusEvent holds one or more status events that have occurred.
+ * See the XQspiPs_SetStatusHandler() for details on the status
+ * events that can be passed in the callback.
+ * @param ByteCount indicates how many bytes of data were successfully
+ * transferred. This may be less than the number of bytes
+ * requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XQspiPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ u8 *SendBufferPtr; /**< Buffer to send (state) */
+ u8 *RecvBufferPtr; /**< Buffer to receive (state) */
+ int RequestedBytes; /**< Number of bytes to transfer (state) */
+ int RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 IsBusy; /**< A transfer is in progress (state) */
+ XQspiPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+ u32 ShiftReadData; /**< Flag to indicate whether the data
+ * read from the Rx FIFO needs to be shifted
+ * in cases where the data is less than 4
+ * bytes
+ */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are
+* 0-255.
+*
+* @return None
+*
+* @note C-Style signature:
+* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return An 8-bit value representing Slave Idle Count.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr) \
+ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Tx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Rx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+ XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written to the Linear QSPI
+* configuration register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 32-bit value representing the contents of the LQSPI Config
+* register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
+ u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xqspips_hw.h
new file mode 100644
index 0000000..9a47979
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xqspips_hw.h
@@ -0,0 +1,419 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a ka 07/25/12 Added a few register defines for CR 670297
+* and removed some defines of reserved fields for
+* CR 671468
+* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+* bit in Configuration register.
+* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register.
+* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
+* linear mode initialization for boot. Added related
+* constant definitions.
+* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
+#define XQSPIPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+ Enable */
+#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
+ transferred */
+#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
+ XQSPIPS_CR_SSCTRL_MASK | \
+ XQSPIPS_CR_DATA_SZ_MASK | \
+ XQSPIPS_CR_MSTREN_MASK | \
+ XQSPIPS_CR_SSFORCE_MASK | \
+ XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
+ XQSPIPS_CR_CPHA_MASK | \
+ XQSPIPS_CR_PRESC_MASK | \
+ XQSPIPS_CR_MANSTRTEN_MASK | \
+ XQSPIPS_CR_MANSTRT_MASK | \
+ XQSPIPS_CR_ENDIAN_MASK | \
+ XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Disable Register
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
+ mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
+ need write to clear */
+#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
+ between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
+ between two words shift */
+#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
+ mask */
+#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
+ or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
+ between addr and return
+ read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
+ received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
+ received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+ XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
new file mode 100644
index 0000000..ad93665
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
@@ -0,0 +1,587 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+*
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscugic.h
new file mode 100644
index 0000000..befa209
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscugic.h
@@ -0,0 +1,369 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_10
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+* - specific individual interrupt enabling/disabling
+* - specific individual interrupt acknowledging
+* - attaching specific callback function to handle interrupt source
+* - assigning desired priority to interrupt source if default is not
+* acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* Interrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs. The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/00 First release
+* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+* The HandlerTable (of type XScuGic_VectorTableEntry) is
+* moved to XScuGic_Config structure from XScuGic structure.
+*
+* The "Config" entry in XScuGic structure is made as
+* pointer for better efficiency.
+*
+* A new file named as xscugic_hw.c is now added. It is
+* to implement low level driver routines without using
+* any xscugic instance pointer. They are useful when the
+* user wants to use xscugic through device id or
+* base address. The driver routines provided are explained
+* below.
+* XScuGic_DeviceInitialize that takes device id as
+* argument and initializes the device (without calling
+* XScuGic_CfgInitialize).
+* XScuGic_DeviceInterruptHandler that takes device id
+* as argument and calls appropriate handlers from the
+* HandlerTable.
+* XScuGic_RegisterHandler that registers a new handler
+* by taking xscugic hardware base address as argument.
+* LookupConfigByBaseAddress is used to return the
+* corresponding config structure from XScuGic_ConfigTable
+* based on the scugic base address passed.
+* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+* structure.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+* *_hw.h
+* Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+* xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET 0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config *Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32 XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscugic_hw.h
new file mode 100644
index 0000000..54f1035
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscugic_hw.h
@@ -0,0 +1,648 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_10
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+* added to enable or disable interrupts based on
+* Distributor Register base address. Normally users use
+* XScuGic instance and call XScuGic_Enable or
+* XScuGic_Disable to enable/disable interrupts. These
+* new macros are provided when user does not want to
+* use an instance pointer but still wants to enable or
+* disable interrupts.
+* Function prototypes for functions (present in newly
+* added file xscugic_hw.c) are added.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+* Zynq Ultrascale Mp
+* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
+* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef PLATFORM_ZYNQ
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
+ Shared Peripheral
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
+ b00-Use the target List
+ b01-All CPUs except requester
+ b10-To Requester
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
+ 0=separate registers,
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
+ interrupts,
+ 0= use IRQ for both,
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
+ Value Secure Non-secure
+ b000 0xFE 0xFF
+ b001 0xFC 0xFE
+ b010 0xF8 0xFC
+ b011 0xF0 0xF8
+ b100 0xE0 0xF0
+ b101 0xC0 0xE0
+ b110 0x80 0xC0
+ b111 0x00 0x80
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param Register is the register offset for the clear/enable bank.
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscutimer.h
new file mode 100644
index 0000000..5434684
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscutimer.h
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* Interrupts
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
new file mode 100644
index 0000000..d577784
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscuwdt.h
new file mode 100644
index 0000000..551eaf5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscuwdt.h
@@ -0,0 +1,379 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_H /* prevent circular inclusions */
+#define XSCUWDT_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuWdt_Config Config;/**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_RST_STS_OFFSET) & \
+ XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_ISR_OFFSET) & \
+ XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr) \
+ XScuWdt_LoadWdt((InstancePtr), \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param Value is the value to be written to the Watchdog Load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET) | \
+ (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr) \
+{ \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE1); \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE2); \
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return Contents of the watchdog control register.
+*
+* @note C-style signature:
+ u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr) \
+ XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ControlReg is the value to be written to the watchdog control
+* register.
+*
+* @return None.
+*
+* @note C-style signature:
+ void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr) \
+ XScuWdt_SetControlReg((InstancePtr), \
+ (XScuWdt_GetControlReg(InstancePtr) | \
+ XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
new file mode 100644
index 0000000..ad87a05
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
@@ -0,0 +1,178 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+* of 0x20 as the base address obtained from the tools
+* starts at 0x20.
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
+#define XSCUWDT_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
+ timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+ timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
+ value 1 */
+#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
+ value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xsdps.h
new file mode 100644
index 0000000..b81ec7c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xsdps.h
@@ -0,0 +1,274 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_6
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+* CR#956899.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */
+#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u32 CardDetect; /**< Card Detect */
+ u32 WriteProtect; /**< Write Protect */
+ u32 BusWidth; /**< Bus Width */
+ u32 BankNumber; /**< MIO Bank selection for SD */
+ u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+ u64 Address; /**< Address of current dma transfer */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XSdPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 Host_Caps; /**< Capabilities of host controller */
+ u32 Host_CapsExt; /**< Extended Capabilities */
+ u32 HCS; /**< High capacity support in card */
+ u8 CardType; /**< Type of card - SD/MMC/eMMC */
+ u8 Card_Version; /**< Card version */
+ u8 HC_Version; /**< Host controller version */
+ u8 BusWidth; /**< Current operating bus width */
+ u32 BusSpeed; /**< Current operating bus speed */
+ u8 Switch1v8; /**< 1.8V Switch support */
+ u32 CardID[4]; /**< Card ID Register */
+ u32 RelCardAddr; /**< Relative Card Address */
+ u32 CardSpecData[4]; /**< Card Specific Data Register */
+ u32 SectorCount; /**< Sector Count */
+ u32 SdCardConfig; /**< Sd Card Configuration Register */
+ u32 Mode; /**< Bus Speed Mode */
+ XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
+ /**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+ u64 Dma64BitAddr; /**< 64 Bit DMA Address */
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xsdps_hw.h
new file mode 100644
index 0000000..901fa5c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xsdps_hw.h
@@ -0,0 +1,1298 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_6
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 12/10/15 Added support for MMC cards.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
+*
+*
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
+ Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
+ /**< SDMA System Address
+ Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
+ High Register */
+#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
+ /**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
+#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
+#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
+#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
+#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
+ Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
+ Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
+ Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
+ Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
+ Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
+ Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
+ Register */
+#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
+ Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
+ Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
+ Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
+ Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
+ Register */
+#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
+ Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
+ Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
+ register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
+ Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
+ Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
+ Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
+#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT 256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
+#define XSDPS_CC_EXT_DIV_SHIFT 6U
+
+#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK 0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV 9U
+#define XSDPS_CC_DIV_SHIFT 8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * Normal and Error Interrupt Status Register
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * Normal and Error Interrupt Status Enable Register
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * Normal and Error Interrupt Signal Enable Register
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
+ Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
+ Interrupt */
+#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
+ Error */
+#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
+ Error */
+#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
+ Error */
+#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024 0x400U
+#define XSDPS_BLK_SIZE_2048 0x800U
+#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
+ Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
+ Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
+ Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
+ Select */
+#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
+ check busy after
+ response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
+ Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
+ Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
+ Set to CMD0-63,
+ AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
+ Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
+ Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
+ Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
+ select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
+ MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
+ support */
+#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
+ support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
+ support */
+#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
+ support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
+ Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
+ tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
+ support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
+ for Programmable clock
+ mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
+ pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
+ Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
+ Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
+ Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
+ Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
+ Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
+ Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
+ Error */
+#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
+ STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
+ FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
+ TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
+ Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
+ Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
+ Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
+ mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_V3 0x0002U
+#define XSDPS_HC_SPEC_V2 0x0001U
+#define XSDPS_HC_SPEC_V1 0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK 0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX 0x8000U
+#define CMD0 0x0000U
+#define CMD1 0x0100U
+#define CMD2 0x0200U
+#define CMD3 0x0300U
+#define CMD4 0x0400U
+#define CMD5 0x0500U
+#define CMD6 0x0600U
+#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7 0x0700U
+#define CMD8 0x0800U
+#define CMD9 0x0900U
+#define CMD10 0x0A00U
+#define CMD11 0x0B00U
+#define CMD12 0x0C00U
+#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16 0x1000U
+#define CMD17 0x1100U
+#define CMD18 0x1200U
+#define CMD19 0x1300U
+#define CMD21 0x1500U
+#define CMD23 0x1700U
+#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24 0x1800U
+#define CMD25 0x1900U
+#define CMD41 0x2900U
+#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52 0x3400U
+#define CMD55 0x3700U
+#define CMD58 0x3A00U
+
+#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+ (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN 0xAAU
+#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
+#define XSDPS_CIC_VOLT_LOW (1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS (1U<<31)
+#define XSDPS_OCR_CC_STS (1U<<30)
+#define XSDPS_OCR_S18 (1U<<24)
+#define XSDPS_OCR_3V5_3V6 (1U<<23)
+#define XSDPS_OCR_3V4_3V5 (1U<<22)
+#define XSDPS_OCR_3V3_3V4 (1U<<21)
+#define XSDPS_OCR_3V2_3V3 (1U<<20)
+#define XSDPS_OCR_3V1_3V2 (1U<<19)
+#define XSDPS_OCR_3V0_3V1 (1U<<18)
+#define XSDPS_OCR_2V9_3V0 (1U<<17)
+#define XSDPS_OCR_2V8_2V9 (1U<<16)
+#define XSDPS_OCR_2V7_2V8 (1U<<15)
+#define XSDPS_OCR_1V7_1V95 (1U<<7)
+#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
+#define XSDPS_OCR_LOW_VOL 0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN 8U
+#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0 0U
+#define XSDPS_SCR_SPEC_1V1 (1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE 0U
+#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
+#define XSDPS_SCR_SPEC3_MASK (1U<<12)
+#define XSDPS_SCR_SPEC3_2V0 0U
+#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
+#define XSDPS_SCR_CMD23_SUPP (1U<<1)
+#define XSDPS_SCR_CMD20_SUPP (1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
+#define XSDPS_CD_STS_WP_VIO (1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
+#define XSDPS_CD_STS_CC_ERR (1U<<20)
+#define XSDPS_CD_STS_ERR (1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
+#define XSDPS_CD_STS_ER_RST (1U<<13)
+#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
+#define XSDPS_CD_STS_APP_CMD (1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN 64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK 0U
+
+#define XSDPS_MODE_FUNC_GRP1 1U
+#define XSDPS_MODE_FUNC_GRP2 2U
+#define XSDPS_MODE_FUNC_GRP3 3U
+#define XSDPS_MODE_FUNC_GRP4 4U
+#define XSDPS_MODE_FUNC_GRP5 5U
+#define XSDPS_MODE_FUNC_GRP6 6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12 0U
+#define XSDPS_ACC_MODE_HS_SDR25 1U
+#define XSDPS_ACC_MODE_SDR50 2U
+#define XSDPS_ACC_MODE_SDR104 3U
+#define XSDPS_ACC_MODE_DDR50 4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT 4U
+#define XSDPS_CMD_SYS_DEF 0U
+#define XSDPS_CMD_SYS_eC 1U
+#define XSDPS_CMD_SYS_OTP 3U
+#define XSDPS_CMD_SYS_ASSD 4U
+#define XSDPS_CMD_SYS_VEND 5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
+#define XSDPS_DRV_TYPE_B 0U
+#define XSDPS_DRV_TYPE_A 1U
+#define XSDPS_DRV_TYPE_C 2U
+#define XSDPS_DRV_TYPE_D 3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT 12U
+#define XSDPS_CUR_LIM_200 0U
+#define XSDPS_CUR_LIM_400 1U
+#define XSDPS_CUR_LIM_600 2U
+#define XSDPS_CUR_LIM_800 3U
+
+#define CSD_SPEC_VER_MASK 0x3C0000U
+#define READ_BLK_LEN_MASK 0x00000F00U
+#define C_SIZE_MULT_MASK 0x00000380U
+#define C_SIZE_LOWER_MASK 0xFFC00000U
+#define C_SIZE_UPPER_MASK 0x00000003U
+#define CSD_STRUCT_MASK 0x00C00000U
+#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE 512U
+
+#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
+ /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
+ /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE 183U
+#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE 185U
+#define EXT_CSD_HS_TIMING_DEF 0U
+#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE 162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET 0U
+#define XSDPS_EXT_CSD_SET_BITS 1U
+#define XSDPS_EXT_CSD_CLR_BITS 2U
+#define XSDPS_EXT_CSD_WRITE_BYTE 3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+ | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY 2960U
+#define XSDPS_100CLK_DELAY 4000U
+#define XSDPS_INIT_DELAY 10000U
+
+#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR 0x1234U
+
+#define XSDPS_CARD_SD 1U
+#define XSDPS_CARD_MMC 2U
+#define XSDPS_CARD_SDIO 3U
+#define XSDPS_CARD_SDCOMBO 4U
+#define XSDPS_CHIP_EMMC 5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID (0x1U << 0)
+#define XSDPS_DESC_END (0x1U << 1)
+#define XSDPS_DESC_INT (0x1U << 2)
+#define XSDPS_DESC_TRAN (0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
+#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
+#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT 1U
+#define XSDPS_SCR_BLKSIZE 8U
+#define XSDPS_1_BIT_WIDTH 0x1U
+#define XSDPS_4_BIT_WIDTH 0x2U
+#define XSDPS_8_BIT_WIDTH 0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
+#define XSDPS_HIGH_SPEED_MODE 0x5U
+#define XSDPS_DEFAULT_SPEED_MODE 0x6U
+#define XSDPS_HS200_MODE 0x7U
+#define XSDPS_DDR52_MODE 0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT 1U
+#define XSDPS_SWITCH_CMD_BLKSIZE 64U
+#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
+#define XSDPS_TUNING_CMD_BLKCNT 1U
+#define XSDPS_TUNING_CMD_BLKSIZE 64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
+
+#define SD_DRIVER_TYPE_B 0x01U
+#define SD_DRIVER_TYPE_A 0x02U
+#define SD_DRIVER_TYPE_C 0x04U
+#define SD_DRIVER_TYPE_D 0x08U
+#define SD_SET_CURRENT_LIMIT_200 0U
+#define SD_SET_CURRENT_LIMIT_400 1U
+#define SD_SET_CURRENT_LIMIT_600 2U
+#define SD_SET_CURRENT_LIMIT_800 3U
+
+#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK 25000000U
+#define XSDPS_SD_SDR25_MAX_CLK 50000000U
+#define XSDPS_SD_SDR50_MAX_CLK 100000000U
+#define XSDPS_SD_DDR50_MAX_CLK 50000000U
+#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK 200000000U
+#define XSDPS_MMC_HSD_MAX_CLK 52000000U
+#define XSDPS_MMC_DDR_MAX_CLK 52000000U
+
+#define XSDPS_CARD_STATE_IDLE 0U
+#define XSDPS_CARD_STATE_RDY 1U
+#define XSDPS_CARD_STATE_IDEN 2U
+#define XSDPS_CARD_STATE_STBY 3U
+#define XSDPS_CARD_STATE_TRAN 4U
+#define XSDPS_CARD_STATE_DATA 5U
+#define XSDPS_CARD_STATE_RCV 6U
+#define XSDPS_CARD_STATE_PROG 7U
+#define XSDPS_CARD_STATE_DIS 8U
+#define XSDPS_CARD_STATE_BTST 9U
+#define XSDPS_CARD_STATE_SLP 10U
+
+#define XSDPS_SLOT_REM 0U
+#define XSDPS_SLOT_EMB 1U
+
+#define XSDPS_WIDTH_8 8U
+#define XSDPS_WIDTH_4 4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
+#define SD_DLL_CTRL 0x00000358U
+#define SD_ITAPDLY 0x00000314U
+#define SD_OTAPDLY 0x00000318U
+#define SD0_DLL_RST 0x00000004U
+#define SD1_DLL_RST 0x00040000U
+#define SD0_ITAPCHGWIN 0x00000200U
+#define SD0_ITAPDLYENA 0x00000100U
+#define SD0_OTAPDLYENA 0x00000040U
+#define SD1_ITAPCHGWIN 0x02000000U
+#define SD1_ITAPDLYENA 0x01000000U
+#define SD1_OTAPDLYENA 0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD0_ITAPDLYSEL_SD50 0x00000014U
+#define SD0_OTAPDLYSEL_SD50 0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
+#define SD0_ITAPDLYSEL_HSD 0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
+#define SD1_ITAPDLYSEL_SD50 0x00140000U
+#define SD1_OTAPDLYSEL_SD50 0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
+#define SD1_ITAPDLYSEL_HSD 0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+ XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+* u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+ (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+ XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+ XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xstatus.h
new file mode 100644
index 0000000..c6e18ab
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xstatus.h
@@ -0,0 +1,531 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /*!< An error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /*!< An error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /*!< The device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /*!< There was no data available */
+#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /*!< The device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
+#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /*!< Device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /*!< Used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /*!< Used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /*!< Driver defined error */
+#define XST_RECV_ERROR 27L /*!< Generic receive error */
+#define XST_SEND_ERROR 28L /*!< Generic transmit error */
+#define XST_NOT_ENABLED 29L /*!< A requested service is not
+ available because it has not
+ been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500 *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
+ * empty and full simultaneously
+ */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
+ error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
+#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
+ * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
+#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
+ device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /*!< Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /*!< Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
+ */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h
new file mode 100644
index 0000000..12004e1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#ifdef __GNUC__
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xuartps.h
new file mode 100644
index 0000000..c6c2a0a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xuartps.h
@@ -0,0 +1,517 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_5
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the parameter EffectiveAddr should be the
+* virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+*
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a drg/jz 01/12/10 First Release
+* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
+* in XUartPs_SetFlowDelay where the value was not
+* being written to the register.
+* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
+* instance structure and the driver is updated to use
+* InputClockHz parameter from the XUartPs_Config config
+* structure.
+* Added a parameter to XUartPs_Config structure which
+* specifies whether the user has selected Modem pins
+* to be connected to MIO or FMIO.
+* Added the tcl file to generate the xparameters.h
+* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+* with the correct values for CR 666724
+* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the name of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added API for uart reset and related
+* constant definitions.
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
+* Support for Zynq Ultrascale Mp added.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
+* platform variable in driver instance structure.
+* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
+* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
+* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
+*
+*
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H /* prevent circular inclusions */
+#define XUARTPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE 921600U
+#define XUARTPS_MIN_RATE 110U
+
+#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified. These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
+ * error detected */
+#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+ u32 InputClockHz;/**< Input clock frequency */
+ s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+ * to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+ u8 *NextBytePtr;
+ u32 RequestedBytes;
+ u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+ u32 BaudRate; /**< In bps, ie 1200 */
+ u32 DataBits; /**< Number of data bits */
+ u32 Parity; /**< Parity */
+ u8 StopBits; /**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the handler, and is passed back to the upper layer
+ * when the handler is called. It is used to find the device driver
+ * instance.
+ * @param Event contains one of the event constants indicating events that
+ * have occurred.
+ * @param EventData contains the number of bytes sent or received at the
+ * time of the call for send and receive events and contains the
+ * modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+ u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XUartPs_Config Config; /* Configuration data structure */
+ u32 InputClockHz; /* Input clock frequency */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 BaudRate; /* Current baud rate */
+
+ XUartPsBuffer SendBuffer;
+ XUartPsBuffer ReceiveBuffer;
+
+ XUartPs_Handler Handler;
+ void *CallBackRef; /* Callback reference for event handler */
+ u32 Platform;
+ u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+ (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if a byte can be sent
+* - FALSE if the Transmitter Fifo is not empty
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr) \
+ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xuartps_hw.h
new file mode 100644
index 0000000..8c46ecf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/include/xuartps_hw.h
@@ -0,0 +1,447 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_5
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+*
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
new file mode 100644
index 0000000..007162d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner coresightps_dcc_comp_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling coresightps_dcc"
+
+coresightps_dcc_comp_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: coresightps_dcc_includes
+
+coresightps_dcc_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
new file mode 100644
index 0000000..ec9a365
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.c
+* @addtogroup coresightps_dcc_v1_4
+* @{
+*
+* Functions in this file are the minimum required functions for the
+* XCoreSightPs driver.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.2 kvn 10/09/15 Add support for IAR Compiler.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
+
+#include
+#include
+
+#ifdef __ICCARM__
+#define INLINE
+#else
+#define INLINE __inline
+#endif
+
+/* DCC Status Bits */
+#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
+#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
+
+static INLINE u32 XCoresightPs_DccGetStatus(void);
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the DCC. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+* @param Data is the byte of data to send
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
+{
+ (void) BaseAddress;
+ while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
+ dsb();
+#ifdef __aarch64__
+ asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mcr p14, 0, %0, c0, c5, 0"
+ : : "r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Reg = Data;
+ }
+#endif
+ isb();
+
+}
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the DCC. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+*
+* @return The byte of data received.
+*
+* @note None.
+*
+******************************************************************************/
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
+{
+ u8 Data = 0U;
+ (void) BaseAddress;
+
+ while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
+ dsb();
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c5, 0"
+ : "=r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Data = Reg;
+ }
+#endif
+ isb();
+
+ return Data;
+}
+
+
+/****************************************************************************/
+/**INLINE
+*
+* This functions read the status register of the DCC.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return The contents of the Status Register.
+*
+* @note None.
+*
+******************************************************************************/
+static INLINE u32 XCoresightPs_DccGetStatus(void)
+{
+ u32 Status = 0U;
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c1, 0"
+ : "=r" (Status) : : "cc");
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c1:0");
+ Status = Reg;
+ }
+#endif
+ return Status;
+#endif
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
new file mode 100644
index 0000000..70b8aad
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_4
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/Makefile
new file mode 100644
index 0000000..7ea505c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/Makefile
@@ -0,0 +1,25 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+LIBSOURCES=*.c
+INCLUDEFILES=*.h
+
+libs:
+ echo "Compiling cpu_cortexa9"
+
+.PHONY: include
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/xcpu_cortexa9.h
new file mode 100644
index 0000000..e4a5e28
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/xcpu_cortexa9.h
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_7
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
+# extra compiler flags. Now, user can remove default flags
+# from extra compiler flags. It fixes CR#998768.
+******************************************************************************/
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
new file mode 100644
index 0000000..7b191dd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xddrps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling ddrps"
+
+xddrps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xddrps_includes
+
+xddrps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
new file mode 100644
index 0000000..b4d1f56
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
@@ -0,0 +1,62 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ *
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
new file mode 100644
index 0000000..25ff740
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdevcfg_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling devcfg"
+
+xdevcfg_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdevcfg_includes
+
+xdevcfg_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
new file mode 100644
index 0000000..74e1d59
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
@@ -0,0 +1,941 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface functions for XDcfg
+* driver. Refer to the header file xdevcfg.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Updated the XDcfg_Transfer function to use the
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+*
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize the Device Config Interface driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param ConfigPtr is the config structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note The very first APB access to the Device Configuration Interface
+* block needs to be a write to the UNLOCK register with the value
+* of 0x757BDF0D. This step is to be done once after reset, any
+* other APB access has to come after this. The APB access is
+* considered illegal if the step is not done or if it is done
+* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
+* the following additional actions would be carried out.
+* In other words, if all bits are low, the following steps are not
+* done.
+* 1. AES is disabled
+* 2. All APB writes disabled
+* 3. SoC debug fully enabled
+*
+******************************************************************************/
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Copy configuration into instance.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+ InstancePtr->IsStarted = 0;
+
+
+ /* Unlock the Device Configuration Interface */
+ XDcfg_Unlock(InstancePtr);
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* The functions enables the PCAP interface by setting the PCAP mode bit in the
+* control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note Enable FPGA programming from PCAP interface. Enabling this bit
+* disables all the external interfaces from programming of FPGA
+* except for ICAP. The user needs to ensure that the FPGA is
+* programmed through either PCAP or ICAP.
+*
+*****************************************************************************/
+void XDcfg_EnablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The functions disables the PCAP interface by clearing the PCAP mode bit in
+* the control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_DisablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit mask data to be written to the Register.
+* The mask definitions are defined in the xdevcfg_hw.h file.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function Clears the specified bit positions of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit value which holds the bit positions to be cleared.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ~Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Control
+* Register.
+* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Lock Register. These bits
+* can only be set to a 1. They will be cleared after a Power On Reset.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Lock Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Lock
+* Register.
+* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Lock Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Config
+* Register.
+* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Status
+* Register.
+* Use the XDCFG_STATUS_*_MASK constants defined in
+* xdevcfg_hw.h to interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Status Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the ROM Shadow Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note This register is can only be written and is used to control the
+* RAM shadow of 32 bit 4K page ROM pages in user mode
+*
+*****************************************************************************/
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
+ Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Software ID Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API for reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Software ID Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the bit mask for the feature in Miscellaneous Control
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the feature to be set.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
+ (RegData | Mask));
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API to reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
+}
+
+/******************************************************************************/
+/**
+*
+* This function checks if DMA command queue is full.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return XST_SUCCESS is the DMA is busy
+* XST_FAILURE if the DMA is idle
+*
+* @note The DMA queue has a depth of two.
+*
+****************************************************************************/
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
+{
+
+ u32 RegData;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the PCAP status register for DMA status */
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_STATUS_OFFSET);
+
+ if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
+ XDCFG_STATUS_DMA_CMD_Q_F_MASK){
+ return XST_SUCCESS;
+ }
+
+ return XST_FAILURE;
+}
+
+/******************************************************************************/
+/**
+*
+* This function initiates the DMA transfer.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return None.
+*
+* @note It is the responsibility of the caller function to ensure that
+* correct values are passed to this function.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+****************************************************************************/
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength)
+{
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_ADDR_OFFSET,
+ SourcePtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_ADDR_OFFSET,
+ DestPtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_LEN_OFFSET,
+ SrcWordLength);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_LEN_OFFSET,
+ DestWordLength);
+}
+
+/******************************************************************************/
+/**
+*
+* This function Implements the DMA Read Command. This command is used to
+* transfer the image data from FPGA to the external memory.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return - XST_INVALID_PARAM if source address/length is invalid.
+* - XST_SUCCESS if DMA transfer initiated properly.
+*
+* @note None.
+*
+****************************************************************************/
+static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
+ u32 SrcWordLength, u32 DestPtr,
+ u32 DestWordLength)
+{
+ u32 IntrReg;
+
+ /*
+ * Send READ Frame command to FPGA
+ */
+ XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
+ SrcWordLength, 0);
+
+ /*
+ * Store the enabled interrupts to enable before the actual read
+ * transfer is initiated and Disable all the interrupts temporarily.
+ */
+ IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
+ XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
+
+ /*
+ * Wait till you get the DMA done for the read command sent
+ */
+ while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET) &
+ XDCFG_IXR_D_P_DONE_MASK) !=
+ XDCFG_IXR_D_P_DONE_MASK);
+ /*
+ * Enable the previously stored Interrupts .
+ */
+ XDcfg_IntrEnable(InstancePtr, IntrReg);
+
+ /*
+ * Initiate the DMA write command.
+ */
+ XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
+ 0, DestWordLength);
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function starts the DMA transfer. This function only starts the
+* operation and returns before the operation may be completed.
+* If the interrupt is enabled, an interrupt will be generated when the
+* operation is completed, otherwise it is necessary to poll the Status register
+* to determine when it is completed. It is the responsibility of the caller to
+* determine when the operation is completed by handling the generated interrupt
+* or polling the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+* @param TransferType contains the type of PCAP transfer being requested.
+* The definitions can be found in the xdevcfg.h file.
+* @return
+* - XST_SUCCESS.if DMA transfer initiated successfully
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_INVALID_PARAM if invalid Source / Destination address
+* is sent or an invalid Source / Destination length is
+* sent
+*
+* @note It is the responsibility of the caller to ensure that the cache
+* is flushed and invalidated both before the DMA operation is
+* started and after the DMA operation completes if the memory
+* pointed to is cached. The caller must also ensure that the
+* pointers contain physical address rather than a virtual address
+* if address translation is being used.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+*****************************************************************************/
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType)
+{
+
+ u32 CtrlReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Check whether the fabric is in initialized state
+ */
+ if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
+ & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
+ /*
+ * We don't need to check PCFG_INIT to be high for
+ * non-encrypted loopback transfers.
+ */
+ if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ return XST_FAILURE;
+ }
+ }
+
+ if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
+ (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
+
+ /* Check for valid source pointer and length */
+ if ((!SourcePtr) || (SrcWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
+ /*
+ * AES engine handles only 8 bit data every clock cycle.
+ * Hence, Encrypted PCAP data which is 32 bit data can
+ * only be sent in every 4 clock cycles. Set the control
+ * register QUARTER_PCAP_RATE_EN bit to achieve this
+ * operation.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+
+ }
+
+ if (TransferType == XDCFG_PCAP_READBACK) {
+
+ if ((!DestPtr) || (DestWordLength == 0)) {
+
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * For PCAP readback of FPGA configuration register or memory,
+ * the read command is first sent (written) to the FPGA fabric
+ * which responds by returning the required read data. Read data
+ * from the FPGA is captured if pcap_radata_v is active.A DMA
+ * read transfer is required to obtain the readback command,
+ * which is then sent to the FPGA, followed by a DMA write
+ * transfer to support this mode of operation.
+ */
+ return XDcfg_PcapReadback(InstancePtr,
+ (u32)SourcePtr, SrcWordLength,
+ (u32)DestPtr, DestWordLength);
+ }
+
+
+ if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
+ (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
+
+ if ((!SourcePtr) || (SrcWordLength == 0) ||
+ (!DestPtr) || (DestWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ /* Enable internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg |
+ XDCFG_MCTRL_PCAP_LPBK_MASK));
+
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * Set the QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every 4 clock
+ * cycles, this is required for encrypted data.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+ }
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
new file mode 100644
index 0000000..6586370
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
@@ -0,0 +1,399 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* Interrupts
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
new file mode 100644
index 0000000..85881c6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdevcfg.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDcfg_Config XDcfg_ConfigTable[] =
+{
+ {
+ XPAR_PS7_DEV_CFG_0_DEVICE_ID,
+ XPAR_PS7_DEV_CFG_0_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
new file mode 100644
index 0000000..8a1379a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given devcfg interface by
+* configuring the appropriate control bits in the devcfg specifc registers
+* the devcfg reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status
+* Update relevant config registers with reset values
+* Disbale the looopback mode and pcap rate enable
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* devcfg controller
+******************************************************************************/
+void XDcfg_ResetHw(u32 BaseAddr)
+{
+ u32 Regval = 0;
+
+ /* Mask the interrupts */
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
+ XDCFG_IXR_ALL_MASK);
+ /* Clear the interuupt status */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
+ /* Clear the source address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
+ /* Clear the destination address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
+ /* Clear the source length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
+ /* Clear the destination length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
+ /* Clear the loopback enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
+ Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
+ /*Reset the configuration register to reset value */
+ XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
+ XDCFG_CONFIG_RESET_VALUE);
+ /*Disable the PCAP rate enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
+ Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
new file mode 100644
index 0000000..80b6678
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
@@ -0,0 +1,391 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
new file mode 100644
index 0000000..f0e5044
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
@@ -0,0 +1,306 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_intr.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains the implementation of interrupt related functions of the XDcfg
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be enabled.
+* Bit positions of 1 will be enabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be disabled.
+* Bit positions of 1 will be disabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the IMR.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Mask Register.
+ */
+ return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Interrupt
+* Status register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Status register.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be cleared.
+* Bit positions of 1 will be cleared. Bit positions of 0 will not
+* change the previous interrupt status. This mask is formed by
+* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET,
+ Mask);
+
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the Device Config Interface.
+*
+* Events are signaled to upper layer for proper handling.
+*
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XDcfg_InterruptHandler(XDcfg *InstancePtr)
+{
+ u32 IntrStatusReg;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Interrupt status register.
+ */
+ IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+
+ /*
+ * Write the status back to clear the interrupts so that no
+ * subsequent interrupts are missed while processing this interrupt.
+ * This also does the DMA acknowledgment automatically.
+ */
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET, IntrStatusReg);
+
+ /*
+ * Signal application that there are events to handle.
+ */
+ InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+ IntrStatusReg);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param InstancePtr is a pointer to the XDcfg instance
+* @param CallBackFunc is the address of the callback function.
+* @param CallBackRef is a user data item that will be passed to the
+* callback function when it is invoked.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef)
+{
+ /*
+ * Asserts validate the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallBackFunc != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
new file mode 100644
index 0000000..e8fc663
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_selftest.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains diagnostic self-test functions for the XDcfg driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm 02/27/13 Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the Device Configuration Interface. This test does a
+* control register write and reads back the same value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if fails.
+*
+* @note None.
+*
+******************************************************************************/
+int XDcfg_SelfTest(XDcfg *InstancePtr)
+{
+ u32 OldCfgReg;
+ u32 CfgReg;
+ int Status = XST_SUCCESS;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
+
+ CfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the original values of the register
+ */
+ XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
+
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
new file mode 100644
index 0000000..838db3a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdevcfg_sinit.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 3.5 ms 08/07/17 Fixed compilation warnings.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
+{
+ extern XDcfg_Config XDcfg_ConfigTable[];
+ XDcfg_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
+ if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XDcfg_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (CfgPtr);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/Makefile
new file mode 100644
index 0000000..d1240c5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdmaps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling dmaps"
+
+xdmaps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdmaps_includes
+
+xdmaps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.c
new file mode 100644
index 0000000..b30a66f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.c
@@ -0,0 +1,1978 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This file contains the implementation of the interface functions for XDmaPs
+* driver. Refer to the header file xdmaps.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/2010 First Release
+* 1.00 nm 05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
+* since it is being defined in xil_io.h
+* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include
+
+#include "xstatus.h"
+#include "xdmaps.h"
+#include "xil_io.h"
+#include "xil_cache.h"
+
+#include "xil_printf.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread);
+
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
+
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
+
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength);
+
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
+
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XDmaPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param InstPtr is a pointer to the XDmaPs instance.
+* @param Config is a reference to a structure containing information
+* about a specific XDmaPs driver.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the
+* address mapping from EffectiveAddr to the device physical base
+* address unchanged once this function is invoked. Unexpected
+* errors may occur if the address mapping changes after this
+* function is called. If address translation is not used, pass in
+* the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS on initialization completion
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr)
+{
+ int Status = XST_SUCCESS;
+ unsigned int CacheLength = 0;
+ u32 CfgReg;
+ unsigned Channel;
+ XDmaPs_ChannelData *ChanData;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Config != NULL);
+
+ /*
+ * Setup the driver instance using passed in parameters
+ */
+ InstPtr->Config.DeviceId = Config->DeviceId;
+ InstPtr->Config.BaseAddress = EffectiveAddr;
+
+ CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
+ CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
+ if (CacheLength < 2 || CacheLength > 5)
+ CacheLength = 0;
+ else
+ CacheLength = 1 << CacheLength;
+
+ InstPtr->CacheLength = CacheLength;
+
+ memset(InstPtr->Chans, 0,
+ sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV]));
+
+ for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
+ ChanData = InstPtr->Chans + Channel;
+ ChanData->ChanId = Channel;
+ ChanData->DevId = Config->DeviceId;
+ }
+
+ InstPtr->IsReady = 1;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the DMA Manager.
+*
+* @param InstPtr is the DMA instance.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetManager(XDmaPs *InstPtr)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ 0, 0);
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the specified DMA Channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel to be reset.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ Channel, 1);
+
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver fault interrupt service routine
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_FaultISR(XDmaPs *InstPtr)
+{
+
+ void *DmaProgBuf;
+ u32 Fsm; /* Fault status DMA manager register value */
+ u32 Fsc; /* Fault status DMA channel register value */
+ u32 FaultType; /* Fault type DMA manager register value */
+
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+
+ u32 Pc; /* DMA Pc or channel Pc */
+ XDmaPs_ChannelData *ChanData;
+
+ unsigned Chan;
+ unsigned DevId;
+
+ XDmaPs_Cmd *DmaCmd;
+
+ Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
+ Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
+
+
+ DevId = InstPtr->Config.DeviceId;
+
+ if (Fsm) {
+ /*
+ * if DMA manager is fault
+ */
+ FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET);
+ Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET);
+
+ xil_printf("PL330 device %d fault with type: %x at Pc %x\n",
+ DevId,
+ FaultType, Pc);
+
+ /* kill the DMA manager thread */
+ /* Should we disable interrupt?*/
+ XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0);
+ }
+
+ /*
+ * check which channel faults and kill the channel thread
+ */
+ for (Chan = 0;
+ Chan < XDMAPS_CHANNELS_PER_DEV;
+ Chan++) {
+ if (Fsc & (0x01 << Chan)) {
+ FaultType =
+ XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_FTCn_OFFSET(Chan));
+ Pc = XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CPCn_OFFSET(Chan));
+
+ /* kill the channel thread */
+ /* Should we disable interrupt? */
+ XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1);
+
+ /*
+ * get the fault type and fault Pc and invoke the
+ * fault callback.
+ */
+ ChanData = InstPtr->Chans + Chan;
+
+ DmaCmd = ChanData->DmaCmdToHw;
+
+ /* Should we check DmaCmd is not null */
+ DmaCmd->DmaStatus = -1;
+ DmaCmd->ChanFaultType = FaultType;
+ DmaCmd->ChanFaultPCAddr = Pc;
+ ChanData->DmaCmdFromHw = DmaCmd;
+ ChanData->DmaCmdToHw = NULL;
+
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ if (InstPtr->FaultHandler)
+ InstPtr->FaultHandler(Chan,
+ DmaCmd,
+ InstPtr->FaultRef);
+
+ }
+ }
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the done handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel number.
+* @param DoneHandler is the done interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef)
+{
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ if (Channel >= XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+
+ ChanData = InstPtr->Chans + Channel;
+
+ ChanData->DoneHandler = DoneHandler;
+ ChanData->DoneRef = CallbackRef;
+
+ return 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the fault handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param FaultHandler is the fault interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ InstPtr->FaultHandler = FaultHandler;
+ InstPtr->FaultRef = CallbackRef;
+
+ return XST_SUCCESS;
+}
+
+
+
+/****************************************************************************/
+/**
+* Construction function for DMAEND instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for
+* the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
+{
+ /*
+ * DMAEND encoding:
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 0 0 0
+ */
+ *DmaProg = 0x0;
+
+ return 1;
+}
+
+static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
+{
+ *Dst = *Src;
+ *(Dst + 1) = *(Src + 1);
+ *(Dst + 2) = *(Src + 2);
+ *(Dst + 3) = *(Src + 3);
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAGO instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Cn is the Channel number, 0 - 7
+* @param Imm is 32-bit immediate number written to the Channel Program
+* Counter.
+* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in
+* the Non-secure state. If Ns is 0, the execution depends on the
+* security state of the DMA manager:
+* DMA manager is in the Secure state, DMA channel operates in the
+* Secure state.
+* DMA manager is in the Non-secure state, DMAC aborts.
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns)
+{
+ /*
+ * DMAGO encoding:
+ * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+ * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ */
+ *DmaProg = 0xA0 | ((Ns << 1) & 0x02);
+
+ *(DmaProg + 1) = (u8)(Cn & 0x07);
+
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ /* success */
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALD instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for the
+* instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
+{
+ /*
+ * DMALD encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 1 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x04;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALP instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Lc is the Loop counter register, can either be 0 or 1.
+* @param LoopIterations: the number of interations, LoopInterations - 1
+* will be encoded in the DMALP instruction.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations)
+{
+ /*
+ * DMALP encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | iter[7:0] |0 0 1 0 0 0 lc 0
+ */
+ *DmaProg = (u8)(0x20 | ((Lc & 1) << 1));
+ *(DmaProg + 1) = (u8)(LoopIterations - 1);
+ return 2;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALPEND instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param BodyStart is the starting address of the loop body. It is used
+* to calculate the bytes of backward jump.
+* @param Lc is the Loop counter register, can either be 0 or 1.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
+{
+ /*
+ * DMALPEND encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | backward_jump[7:0] |0 0 1 nf 1 lc bs x
+ *
+ * lc: loop counter
+ * nf is for loop forever. The driver does not support loop forever,
+ * so nf is 1.
+ * The driver does not support conditional LPEND, so bs is 0, x is 0.
+ */
+ *DmaProg = 0x38 | ((Lc & 1) << 2);
+ *(DmaProg + 1) = (u8)(DmaProg - BodyStart);
+
+ return 2;
+}
+
+/*
+ * Register number for the DMAMOV instruction
+ */
+#define XDMAPS_MOV_SAR 0x0
+#define XDMAPS_MOV_CCR 0x1
+#define XDMAPS_MOV_DAR 0x2
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAMOV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR
+* @param Imm is the 32-bit immediate number
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
+{
+ /*
+ * DMAMOV encoding
+ * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ *
+ * rd: b000 for SAR, b001 CCR, b010 DAR
+ */
+ *DmaProg = 0xBC;
+ *(DmaProg + 1) = Rd & 0x7;
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMANOP instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
+{
+ /*
+ * DMANOP encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 1 0 0 0
+ */
+ *DmaProg = 0x18;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMARMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_Instr_DMARMB(char *DmaProg)
+{
+ /*
+ * DMARMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x12;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMASEV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param EventNumber is the Event number to signal.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
+{
+ /*
+ * DMASEV encoding
+ * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0
+ * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0
+ */
+ *DmaProg = 0x34;
+ *(DmaProg + 1) = (u8)(EventNumber << 3);
+
+ return 2;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAST instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
+{
+ /*
+ * DMAST encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 1 0 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x08;
+ return 1;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAWMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_Instr_DMAWMB(char *DmaProg)
+{
+ /*
+ * DMAWMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x13;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the endian swap size to the bit encoding of the CCR
+*
+* @param EndianSwapSize is the endian swap size, in terms of bits, it
+* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax)
+*
+* @return The endian swap size bit encoding for the CCR.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
+{
+ switch (EndianSwapSize) {
+ case 0:
+ case 8:
+ return 0;
+ case 16:
+ return 1;
+ case 32:
+ return 2;
+ case 64:
+ return 3;
+ case 128:
+ return 4;
+ default:
+ return 0;
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the burst size to the bit encoding of the CCR
+*
+* @param BurstSize is the burst size. It's the data width.
+* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128.
+* It must be no larger than the bus width.
+* (We are using DMA assembly syntax.)
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
+{
+ switch (BurstSize) {
+ case 1:
+ return 0;
+ case 2:
+ return 1;
+ case 4:
+ return 2;
+ case 8:
+ return 3;
+ case 16:
+ return 4;
+ case 32:
+ return 5;
+ case 64:
+ return 6;
+ case 128:
+ return 7;
+ default:
+ return 0;
+ }
+}
+
+
+/****************************************************************************/
+/**
+*
+* Conversion function from PL330 bus transfer descriptors to CCR value. All the
+* values passed to the functions are in terms of assembly languages, not in
+* terms of the register bit encoding.
+*
+* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl.
+*
+* @return The 32-bit CCR value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
+{
+ /*
+ * Channel Control Register encoding
+ * [31:28] - endian_swap_size
+ * [27:25] - dst_cache_ctrl
+ * [24:22] - dst_prot_ctrl
+ * [21:18] - dst_burst_len
+ * [17:15] - dst_burst_size
+ * [14] - dst_inc
+ * [13:11] - src_cache_ctrl
+ * [10:8] - src_prot_ctrl
+ * [7:4] - src_burst_len
+ * [3:1] - src_burst_size
+ * [0] - src_inc
+ */
+
+ unsigned es =
+ XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize);
+
+ unsigned dst_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
+ unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
+ unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
+ | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
+ unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
+ unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
+
+ unsigned src_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
+ unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
+ unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
+ | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
+ unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
+ unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
+
+ u32 ccr_value = (es << 28)
+ | (dst_cache_ctrl << 25)
+ | (dst_prot_ctrl << 22)
+ | (dst_burst_len << 18)
+ | (dst_burst_size << 15)
+ | (dst_inc_bit << 14)
+ | (src_cache_ctrl << 11)
+ | (src_prot_ctrl << 8)
+ | (src_burst_len << 4)
+ | (src_burst_size << 1)
+ | (src_inc_bit);
+
+ return ccr_value;
+}
+
+/****************************************************************************/
+/**
+* Construct a loop with only DMALD and DMAST as the body using loop counter 0.
+* The function also makes sure the loop body and the lpend is in the same
+* cache line.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCount The inner loop count. Loop count - 1 will be used to
+* initialize the loop counter.
+*
+* @return The number of bytes the loop has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ int LoopCount)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount);
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 3;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/****************************************************************************/
+/**
+* Construct a nested loop with only DMALD and DMAST in the inner loop body.
+* It uses loop counter 1 for the outer loop and loop counter 0 for the
+* inner loop.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCountOuter The outer loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+* @param LoopCountInner The inner loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+*
+* @return The number byes the nested loop program has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ unsigned int LoopCountOuter,
+ unsigned int LoopCountInner)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *InnerLoopStart;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter);
+ InnerLoopStart = DmaProgBuf;
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ if (CacheLength < 8) {
+ /*
+ * if the cache line is too small to fit both loops
+ * just align the inner loop
+ */
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCountInner);
+ /* outer loop end */
+ DmaProgBuf +=
+ XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart,
+ 1);
+
+ /*
+ * the nested loop is constructed for
+ * smaller cache line
+ */
+ return DmaProgBuf - DmaProgLoopStart;
+ }
+
+ /*
+ * Now let's handle the case where a cache line can
+ * fit the nested loops.
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 7;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ /* insert the inner DMALP */
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner);
+
+ /* DMALD and DMAST instructions */
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+
+ /* inner DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+ /* outer DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart, 1);
+
+ /* return the number of bytes */
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/*
+ * [31:28] endian_swap_size b0000
+ * [27:25] dst_cache_ctrl b000
+ * [24:22] dst_prot_ctrl b000
+ * [21:18] dst_burst_len b0000
+ * [17:15] dst_burst_size b000
+ * [14] dst_inc b0
+ * [27:25] src_cache_ctrl b000
+ * [24:22] src_prot_ctrl b000
+ * [21:18] src_burst_len b0000
+ * [17:15] src_burst_size b000
+ * [14] src_inc b0
+ */
+#define XDMAPS_CCR_SINGLE_BYTE (0x0)
+#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1)
+
+
+/****************************************************************************/
+/**
+*
+* Construct the DMA program based on the descriptions of the DMA transfer.
+* The function handles memory to memory DMA transfers.
+* It also handles unalgined head and small amount of residue tail.
+*
+* @param Channel DMA channel number
+* @param Cmd is the DMA command.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+*
+* @returns The number of bytes for the program.
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength)
+{
+ /*
+ * unpack arguments
+ */
+ char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg;
+ unsigned DevChan = Channel;
+ unsigned long DmaLength = Cmd->BD.Length;
+ u32 SrcAddr = Cmd->BD.SrcAddr;
+
+ unsigned SrcInc = Cmd->ChanCtrl.SrcInc;
+ u32 DstAddr = Cmd->BD.DstAddr;
+ unsigned DstInc = Cmd->ChanCtrl.DstInc;
+
+ char *DmaProgStart = DmaProgBuf;
+
+ unsigned int BurstBytes;
+ unsigned int LoopCount;
+ unsigned int LoopCount1 = 0;
+ unsigned int LoopResidue = 0;
+ unsigned int TailBytes;
+ unsigned int TailWords;
+ int DmaProgBytes;
+ u32 CCRValue;
+ unsigned int Unaligned;
+ unsigned int UnalignedCount;
+ unsigned int MemBurstSize = 1;
+ u32 MemAddr = 0;
+ unsigned int Index;
+ unsigned int SrcUnaligned = 0;
+ unsigned int DstUnaligned = 0;
+
+ XDmaPs_ChanCtrl *ChanCtrl;
+ XDmaPs_ChanCtrl WordChanCtrl;
+ static XDmaPs_ChanCtrl Mem2MemByteCC;
+
+ Mem2MemByteCC.EndianSwapSize = 0;
+ Mem2MemByteCC.DstCacheCtrl = 0;
+ Mem2MemByteCC.DstProtCtrl = 0;
+ Mem2MemByteCC.DstBurstLen = 1;
+ Mem2MemByteCC.DstBurstSize = 1;
+ Mem2MemByteCC.DstInc = 1;
+ Mem2MemByteCC.SrcCacheCtrl = 0;
+ Mem2MemByteCC.SrcProtCtrl = 0;
+ Mem2MemByteCC.SrcBurstLen = 1;
+ Mem2MemByteCC.SrcBurstSize = 1;
+ Mem2MemByteCC.SrcInc = 1;
+
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ /* insert DMAMOV for SAR and DAR */
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_SAR,
+ SrcAddr);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_DAR,
+ DstAddr);
+
+
+ if (ChanCtrl->SrcInc)
+ SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
+
+ if (ChanCtrl->DstInc)
+ DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
+
+ if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
+ ChanCtrl = &Mem2MemByteCC;
+ }
+
+ if (ChanCtrl->SrcInc) {
+ MemBurstSize = ChanCtrl->SrcBurstSize;
+ MemAddr = SrcAddr;
+
+ } else if (ChanCtrl->DstInc) {
+ MemBurstSize = ChanCtrl->DstBurstSize;
+ MemAddr = DstAddr;
+ }
+
+ /* check whether the head is aligned or not */
+ Unaligned = MemAddr % MemBurstSize;
+
+ if (Unaligned) {
+ /* if head is unaligned, transfer head in bytes */
+ UnalignedCount = MemBurstSize - Unaligned;
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ for (Index = 0; Index < UnalignedCount; Index++) {
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ }
+
+ DmaLength -= UnalignedCount;
+ }
+
+ /* now the burst transfer part */
+ CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
+
+ LoopCount = DmaLength / BurstBytes;
+ TailBytes = DmaLength % BurstBytes;
+
+ /*
+ * the loop count register is 8-bit wide, so if we need
+ * a larger loop, we need to have nested loops
+ */
+ if (LoopCount > 256) {
+ LoopCount1 = LoopCount / 256;
+ if (LoopCount1 > 256) {
+ xil_printf("DMA operation cannot fit in a 2-level "
+ "loop for channel %d, please reduce the "
+ "DMA length or increase the burst size or "
+ "length",
+ Channel);
+ return 0;
+ }
+ LoopResidue = LoopCount % 256;
+
+ if (LoopCount1 > 1)
+ DmaProgBuf +=
+ XDmaPs_ConstructNestedLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount1,
+ 256);
+ else
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ 256);
+
+ /* there will be some that cannot be covered by
+ * nested loops
+ */
+ LoopCount = LoopResidue;
+ }
+
+ if (LoopCount > 0) {
+ DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount);
+ }
+
+ if (TailBytes) {
+ /* handle the tail */
+ TailWords = TailBytes / MemBurstSize;
+ TailBytes = TailBytes % MemBurstSize;
+
+ if (TailWords) {
+ WordChanCtrl = *ChanCtrl;
+ /*
+ * if we can transfer the tail in words, we will
+ * transfer words as much as possible
+ */
+ WordChanCtrl.SrcBurstSize = MemBurstSize;
+ WordChanCtrl.SrcBurstLen = 1;
+ WordChanCtrl.DstBurstSize = MemBurstSize;
+ WordChanCtrl.DstBurstLen = 1;
+
+
+ /*
+ * the burst length is 1
+ */
+ CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailWords);
+
+ }
+
+ if (TailBytes) {
+ /*
+ * for the rest, we'll tranfer in bytes
+ */
+ /*
+ * So far just to be safe, the tail bytes
+ * are transfered in a loop. We can optimize a little
+ * to perform a burst.
+ */
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailBytes);
+
+ }
+ }
+
+ DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan);
+ DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf);
+
+ DmaProgBytes = DmaProgBuf - DmaProgStart;
+
+ Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes);
+
+ return DmaProgBytes;
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* Generate a DMA program based for the DMA command, the buffer will be pointed
+* by the GeneratedDmaProg field of the command.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+*
+* @return - XST_SUCCESS on success.
+* - XST_FAILURE if it fails
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+ void *Buf;
+ int ProgLen;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_ChanCtrl *ChanCtrl;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ ChanData = InstPtr->Chans + Channel;
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen
+ != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) {
+ return XST_FAILURE;
+ }
+
+
+ /*
+ * unaligned fixed address is not supported
+ */
+ if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) {
+ return XST_FAILURE;
+ }
+
+ if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) {
+ return XST_FAILURE;
+ }
+
+ Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool);
+ if (Buf == NULL) {
+ return XST_FAILURE;
+ }
+
+ Cmd->GeneratedDmaProg = Buf;
+ ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
+ InstPtr->CacheLength);
+ Cmd->GeneratedDmaProgLength = ProgLen;
+
+
+#ifdef XDMAPS_DEBUG
+ XDmaPs_Print_DmaProg(Cmd);
+#endif
+
+ if (ProgLen <= 0) {
+ /* something wrong, release the buffer */
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProgLength = 0;
+ Cmd->GeneratedDmaProg = NULL;
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+ * Free the DMA program buffer that is pointed by the GeneratedDmaProg field
+ * of the command.
+ *
+ * @param InstPtr is then DMA instance.
+ * @param Channel is the DMA channel number.
+ * @param Cmd is the DMA command.
+ *
+ * @return XST_SUCCESS on success.
+ * XST_FAILURE if there is any error.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+
+ void *Buf;
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ Buf = (void *)Cmd->GeneratedDmaProg;
+ ChanData = InstPtr->Chans + Channel;
+
+ if (Buf) {
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProg = 0;
+ Cmd->GeneratedDmaProgLength = 0;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Start a DMA command. The command can only be invoked when the channel
+* is idle. The driver takes the command, generates DMA program if needed,
+* then pass the program to DMAC to execute.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+* @param HoldDmaProg is tag indicating whether the driver can release
+* the allocated DMA buffer or not. If a user wants to examine the
+* generated DMA program, the flag should be set to 1. After the
+* DMA program is finished, a user needs to explicity free the
+* buffer.
+*
+* @return
+* - XST_SUCCESS on success
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_FAILURE on other failures
+*
+* @note None.
+*
+****************************************************************************/
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg)
+{
+ int Status;
+ u32 DmaProg = 0;
+ u32 Inten;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ Cmd->DmaStatus = XST_FAILURE;
+
+ if (XDmaPs_IsActive(InstPtr, Channel))
+ return XST_DEVICE_BUSY;
+
+ if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
+ Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
+ if (Status)
+ return XST_FAILURE;
+ }
+
+ InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
+
+ if (Cmd->UserDmaProg)
+ DmaProg = (u32)Cmd->UserDmaProg;
+ else if (Cmd->GeneratedDmaProg)
+ DmaProg = (u32)Cmd->GeneratedDmaProg;
+
+ if (DmaProg) {
+ /* enable the interrupt */
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+ Inten |= 0x01 << Channel; /* set the correpsonding bit */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET,
+ Inten);
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+
+ InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
+
+ if (Cmd->ChanCtrl.SrcInc) {
+ Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length);
+ }
+ if (Cmd->ChanCtrl.DstInc) {
+ Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
+ Cmd->BD.Length);
+ }
+
+ Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
+ Channel, DmaProg);
+ }
+ else {
+ InstPtr->Chans[Channel].DmaCmdToHw = NULL;
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Checks whether the DMA channel is active or idle.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel number.
+*
+* @return 0: if the channel is idle
+* 1: otherwise
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ /* Need to assert Channel is in range */
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return 0;
+
+ return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Allocate a buffer of the DMA program buffer from the pool.
+*
+* @param Pool the DMA program pool.
+*
+* @return The allocated buffer, NULL if there is any error.
+*
+* @note None.
+*
+*****************************************************************************/
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool)
+{
+ int Index;
+
+ Xil_AssertNonvoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (!Pool[Index].Allocated) {
+ Pool[Index].Allocated = 1;
+ return Pool[Index].Buf;
+ }
+ }
+
+ return NULL;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 0. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 0);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 1. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 1);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 2. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 2);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 3. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 3);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 4. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 4);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 5. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 5);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 6. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 6);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 7. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 7);
+}
+
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+
+/****************************************************************************/
+/**
+* Use the debug registers to kill the DMA thread.
+*
+* @param BaseAddr is DMA device base address.
+* @param Channel is the DMA channel number.
+* @param Thread is Debug thread encoding.
+* 0: DMA manager thread, 1: DMA channel.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread)
+{
+ u32 DbgInst0;
+ int WaitCount;
+
+ DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread);
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ /* wait time out */
+ xil_printf("PL330 device at %x debug status busy time out\n",
+ BaseAddr);
+
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0);
+
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+/****************************************************************************/
+/**
+*
+*
+* Free a buffer of the DMA program buffer.
+* @param Pool the DMA program pool.
+* @param Buf the DMA program buffer to be release.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf)
+{
+ int Index;
+ Xil_AssertVoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (Pool[Index].Buf == Buf) {
+ if (Pool[Index].Allocated) {
+ Pool[Index].Allocated = 0;
+ }
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel.
+*
+* @param BaseAddr PL330 device base address
+* @param Channel Channel number for the device
+* @param DmaProg DMA program starting address, this should be DMA address
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+****************************************************************************/
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
+{
+ char DmaGoProg[8];
+ u32 DbgInst0;
+ u32 DbgInst1;
+
+ int WaitCount;
+
+ XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0);
+
+ DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0);
+ DbgInst1 = (u32)DmaProg;
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT)) {
+
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+ /* write debug instruction 1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1);
+
+
+ /* wait while the DMA Manager is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr,
+ XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
+ != XDMAPS_DS_DMA_STATUS_STOPPED
+ && WaitCount <= XDMAPS_MAX_WAIT) {
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+
+/****************************************************************************/
+/**
+*
+* It's the generic Done ISR.
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel numer.
+*
+* @return None.*
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
+{
+
+ void *DmaProgBuf;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_Cmd *DmaCmd;
+ //u32 Value;
+
+ ChanData = InstPtr->Chans + Channel;
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+ /* clear the interrupt status */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTCLR_OFFSET,
+ 1 << ChanData->ChanId);
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+
+ DmaCmd = ChanData->DmaCmdToHw;
+ if (DmaCmd) {
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ DmaCmd->DmaStatus = 0;
+ ChanData->DmaCmdToHw = NULL;
+ ChanData->DmaCmdFromHw = DmaCmd;
+
+ if (ChanData->DoneHandler)
+ ChanData->DoneHandler(Channel, DmaCmd,
+ ChanData->DoneRef);
+ }
+
+}
+
+
+/****************************************************************************/
+/**
+* Prints the content of the buffer in bytes
+* @param Buf is the buffer.
+* @param Length is the length of the DMA program.
+*
+* @return None.
+*
+* @note None.
+****************************************************************************/
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
+{
+ int Index;
+ for (Index = 0; Index < Length; Index++)
+ xil_printf("[%x] %x\r\n", Index, Buf[Index]);
+
+}
+/****************************************************************************/
+/**
+* Print the Dma Prog Contents.
+*
+* @param Cmd is the command buffer.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+ void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
+{
+ if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
+ xil_printf("Generated DMA program (%d):\r\n",
+ Cmd->GeneratedDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
+ Cmd->GeneratedDmaProgLength);
+ }
+
+ if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
+ xil_printf("User defined DMA program (%d):\r\n",
+ Cmd->UserDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
+ Cmd->UserDmaProgLength);
+ }
+}
+
+
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.h
new file mode 100644
index 0000000..73e2b1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.h
@@ -0,0 +1,349 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_4
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
+*
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+int XDmaPs_Instr_DMARMB(char *DmaProg);
+int XDmaPs_Instr_DMAWMB(char *DmaProg);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_g.c
new file mode 100644
index 0000000..97cb370
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_DMA_NS_DEVICE_ID,
+ XPAR_PS7_DMA_NS_BASEADDR
+ },
+ {
+ XPAR_PS7_DMA_S_DEVICE_ID,
+ XPAR_PS7_DMA_S_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.c
new file mode 100644
index 0000000..5fbe4ca
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_hw.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+* for XDmaPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+/************************** Function Prototypes *****************************/
+
+/************************** Variable Definitions ****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given dmaps interface by
+* configuring the appropriate control bits in the dmaps specifc registers
+* the dmaps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the pending interrupts
+* Kill all the active channel threads
+* Kill the manager thread
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* dmaps controller
+******************************************************************************/
+void XDmaPs_ResetHw(u32 BaseAddress)
+{
+ u32 DbgInst;
+ u32 WaitCount = 0;
+ u32 ChanIndex;
+
+ /* Disable all the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
+ /* Clear the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
+ /* Kill the dma channel threads */
+ for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
+ while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+ }
+ /* Kill the manager thread */
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+}
+
+
+
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.h
new file mode 100644
index 0000000..42dfe69
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.h
@@ -0,0 +1,289 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+*
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_selftest.c
new file mode 100644
index 0000000..37e70f8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_selftest.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_selftest.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This file contains the self-test functions for the XDmaPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 hbm 03/29/2010 First Release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param InstPtr is a pointer to the XDmaPs instance
+*
+* @return
+*
+* - XST_SUCCESS if the test was successful
+* - XST_FAILURE if the test failed
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+int XDmaPs_SelfTest(XDmaPs *InstPtr)
+{
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+ int i;
+
+ if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ return XST_FAILURE;
+
+ for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
+ if (XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CSn_OFFSET(i)))
+ return XST_FAILURE;
+ }
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_sinit.c
new file mode 100644
index 0000000..e0b6fae
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_sinit.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* The implementation of the XDmaPs driver's static initialzation
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/13/10 First Release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+extern XDmaPs_Config XDmaPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return
+*
+* A pointer to the configuration structure or NULL if the specified device
+* is not in the system.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
+{
+ XDmaPs_Config *CfgPtr = NULL;
+
+ int i;
+
+ for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
+ if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XDmaPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/Makefile
new file mode 100644
index 0000000..7002e62
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xemacps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling emacps"
+
+xemacps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xemacps_includes
+
+xemacps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.c
new file mode 100644
index 0000000..b8be326
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.c
@@ -0,0 +1,488 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* The XEmacPs driver. Functions in this file are the minimum required functions
+* for this driver. See xemacps.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+* 64-bit changes.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
+* Disable extended mode. Perform all 64 bit changes under
+* check for arch64.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5 hk 08/14/17 Update cache coherency information of the interface in
+* its config structure.
+* 3.8 hk 09/17/18 Cleanup stale comments.
+* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XEmacPs_StubHandler(void); /* Default handler routine */
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* Initialize a specific XEmacPs instance/driver. The initialization entails:
+* - Initialize fields of the XEmacPs instance structure
+* - Reset hardware and apply default options
+* - Configure the DMA channels
+*
+* The PHY is setup independently from the device. Use the MII or whatever other
+* interface may be present for setup.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param CfgPtr is the device configuration structure containing required
+* hardware build data.
+* @param EffectiveAddress is the base address of the device. If address
+* translation is not utilized, this parameter can be passed in using
+* CfgPtr->Config.BaseAddress to specify the physical base address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+******************************************************************************/
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
+ UINTPTR EffectiveAddress)
+{
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ /* Set device base address and ID */
+ InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddress;
+ InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
+
+ /* Set callbacks to an initial stub routine */
+ InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
+
+ /* Reset the hardware and set default options */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ XEmacPs_Reset(InstancePtr);
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+* Start the Ethernet controller as follows:
+* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
+* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
+* - Start the SG DMA send and receive channels and enable the device
+* interrupt
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return N/A
+*
+* @note
+* Hardware is configured with scatter-gather DMA, the driver expects to start
+* the scatter-gather channels and expects that the user has previously set up
+* the buffer descriptor lists.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
+* device options while another is trying to start the device, the user is
+* required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* This function must not be preempted by an interrupt that may service the
+* device.
+*
+******************************************************************************/
+void XEmacPs_Start(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Start DMA */
+ /* When starting the DMA channels, both transmit and receive sides
+ * need an initialized BD list.
+ */
+ if (InstancePtr->Version == 2) {
+ Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+ Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ InstancePtr->RxBdRing.BaseBdAddr);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ InstancePtr->TxBdRing.BaseBdAddr);
+ }
+
+ /* clear any existed int status */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Enable transmitter if not already enabled */
+ if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
+ }
+ }
+
+ /* Enable receiver if not already enabled */
+ if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
+ }
+ }
+
+ /* Enable TX and RX interrupts */
+ XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
+ XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
+ (u32)XEMACPS_IXR_TXCOMPL_MASK));
+
+ /* Enable TX Q1 Interrupts */
+ if (InstancePtr->Version > 2)
+ XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+
+ /* Mark as started */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+ return;
+}
+
+
+/*****************************************************************************/
+/**
+* Gracefully stop the Ethernet MAC as follows:
+* - Disable all interrupts from this device
+* - Stop DMA channels
+* - Disable the tansmitter and receiver
+*
+* Device options currently in effect are not changed.
+*
+* This function will disable all interrupts. Default interrupts settings that
+* had been enabled will be restored when XEmacPs_Start() is called.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @note
+* This function makes use of internal resources that are shared between the
+* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
+* setting device options while another is trying to start the device, the user
+* is required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* Stopping the DMA channels causes this function to block until the DMA
+* operation is complete.
+*
+******************************************************************************/
+void XEmacPs_Stop(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Disable all interrupts */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Disable the receiver & transmitter */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Mark as stopped */
+ InstancePtr->IsStarted = 0U;
+}
+
+
+/*****************************************************************************/
+/**
+* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
+* transmitter, and the receiver.
+*
+* Steps to reset
+* - Stops transmit and receive channels
+* - Stops DMA
+* - Configure transmit and receive buffer size to default
+* - Clear transmit and receive status register and counters
+* - Clear all interrupt sources
+* - Clear phy (if there is any previously detected) address
+* - Clear MAC addresses (1-4) as well as Type IDs and hash value
+*
+* All options are placed in their default state. Any frames in the
+* descriptor lists will remain in the lists. The side effect of doing
+* this is that after a reset and following a restart of the device, frames
+* were in the list before the reset may be transmitted or received.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required, the driver notifies the upper layer software of
+* this need through the ErrorHandler callback and specific status codes.
+* The upper layer software is responsible for calling this Reset function
+* and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+******************************************************************************/
+void XEmacPs_Reset(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+ u8 i;
+ s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Stop the device and reset hardware */
+ XEmacPs_Stop(InstancePtr);
+ InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
+
+ InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
+
+ InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
+
+ InstancePtr->MaxMtuSize = XEMACPS_MTU;
+ InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
+ XEMACPS_TRL_SIZE;
+ InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+ XEMACPS_HDR_VLAN_SIZE;
+ InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+
+ /* Setup hardware with default values */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ (XEMACPS_NWCTRL_STATCLR_MASK |
+ XEMACPS_NWCTRL_MDEN_MASK) &
+ (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
+
+ Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
+ (u32)XEMACPS_NWCFG_FDEN_MASK |
+ (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
+ XEMACPS_NWCFG_DWIDTH_64_MASK));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET,
+ (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+ (((((u32)XEMACPS_RX_BUF_SIZE %
+ (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+ (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+ (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
+ (u32)XEMACPS_DMACR_RXSIZE_MASK |
+ (u32)XEMACPS_DMACR_TXSIZE_MASK);
+
+
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
+#if defined(__aarch64__) || defined(__arch64__)
+ (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
+#endif
+ (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, 0x0U);
+
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
+ if (InstancePtr->Version > 2)
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, 0x0U);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ Reg);
+
+ XEmacPs_ClearHash(InstancePtr);
+
+ for (i = 1U; i < 5U; i++) {
+ (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
+ (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
+ }
+
+ /* clear all counters */
+ for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
+ i++) {
+ (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
+ }
+
+ /* Disable the receiver */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Sync default options with hardware but leave receiver and
+ * transmitter disabled. They get enabled with XEmacPs_Start() if
+ * XEMACPS_TRANSMITTER_ENABLE_OPTION and
+ * XEMACPS_RECEIVER_ENABLE_OPTION are set.
+ */
+ (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
+ ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
+
+ (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
+}
+
+
+/******************************************************************************/
+/**
+ * This is a stub for the asynchronous callbacks. The stub is here in case the
+ * upper layer forgot to set the handler(s). On initialization, all handlers are
+ * set to this callback. It is considered an error for this handler to be
+ * invoked.
+ *
+ ******************************************************************************/
+void XEmacPs_StubHandler(void)
+{
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+* This function sets the start address of the transmit/receive buffer queue.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param QPtr is the address of the Queue to be written
+* @param QueueNum is the Buffer Queue Index
+* @param Direction indicates Transmit/Recive
+*
+* @note
+* The buffer queue addresses has to be set before starting the transfer, so
+* this function has to be called in prior to XEmacPs_Start()
+*
+******************************************************************************/
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction)
+{
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* If already started, then there is nothing to do */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ return;
+ }
+
+ if (QueueNum == 0x00U) {
+ if (Direction == XEMACPS_SEND) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ } else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+ }
+ else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQ1BASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+#ifdef __aarch64__
+ if (Direction == XEMACPS_SEND) {
+ /* Set the MSB of TX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_TXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ } else {
+ /* Set the MSB of RX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_RXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ }
+#endif
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.h
new file mode 100644
index 0000000..c22354f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.h
@@ -0,0 +1,807 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_8
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * Driver Description
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * Initialization & Configuration
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * Interrupts and Asynchronous Callbacks
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * Virtual Memory
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * DMA
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * Alignment & Data Cache Restrictions
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * Buffer Copying
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * Checksum Offloading
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * PHY Interfaces
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * Asserts
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
+ * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bd.h
new file mode 100644
index 0000000..2b22223
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bd.h
@@ -0,0 +1,784 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_8
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * Buffer Descriptors
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * Performance
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
+ * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+ *
+ *
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param InstancePtr is the pointer to XEmacps instance
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.c
new file mode 100644
index 0000000..208deb9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.c
@@ -0,0 +1,1098 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* This file implements buffer descriptor ring related functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+* Earlier it used to search in "BdLimit" number of BDs to
+* know which BDs are processed. Now one more check is
+* added. It looks for BDs till the current BD pointer
+* reaches HwTail. By doing this processing time is saved.
+* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+* xemacps_bdring.c is modified. Now start of packet is
+* searched for returning the number of BDs processed.
+* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+* removed. It is expected that all BDs are allocated in
+* from uncached area. Fix for CR #663885.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* pointers
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_cache.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************
+ * Compute the virtual address of a descriptor from its physical address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Virtual address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
+ ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Compute the physical address of a descriptor from its virtual address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Physical address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
+ ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
+ * to the beginning of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is greater than
+ * the high address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr += ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
+ { \
+ Addr -= (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
+ }
+
+/****************************************************************************
+ * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
+ * around to the end of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is less than
+ * the base address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr -= ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
+ { \
+ Addr += (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
+ }
+
+
+/************************** Function Prototypes ******************************/
+
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * Using a memory segment allocated by the caller, create and setup the BD list
+ * for the given DMA channel.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param PhysAddr is the physical base address of user memory region.
+ * @param VirtAddr is the virtual base address of the user memory region. If
+ * address translation is not being utilized, then VirtAddr should be
+ * equivalent to PhysAddr.
+ * @param Alignment governs the byte alignment of individual BDs. This function
+ * will enforce a minimum alignment of 4 bytes with no maximum as long
+ * as it is specified as a power of 2.
+ * @param BdCount is the number of BDs to setup in the user memory region. It
+ * is assumed the region is large enough to contain the BDs.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if initialization was successful
+ * - XST_NO_FEATURE if the provided instance is a non DMA type
+ * channel.
+ * - XST_INVALID_PARAM under any of the following conditions:
+ * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
+ * parameter.
+ * 2) Alignment parameter does not meet minimum requirements or is not a
+ * power of 2 value.
+ * 3) BdCount is 0.
+ * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
+ * over address 0x00000000 in virtual address space.
+ *
+ * @note
+ * Make sure to pass in the right alignment value.
+ *****************************************************************************/
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
+{
+ u32 i;
+ UINTPTR BdVirtAddr;
+ UINTPTR BdPhyAddr;
+ UINTPTR VirtAddrLoc = VirtAddr;
+
+ /* In case there is a failure prior to creating list, make sure the
+ * following attributes are 0 to prevent calls to other functions
+ * from doing anything.
+ */
+ RingPtr->AllCnt = 0U;
+ RingPtr->FreeCnt = 0U;
+ RingPtr->HwCnt = 0U;
+ RingPtr->PreCnt = 0U;
+ RingPtr->PostCnt = 0U;
+
+ /* Make sure Alignment parameter meets minimum requirements */
+ if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure Alignment is a power of 2 */
+ if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure PhysAddr and VirtAddr are on same Alignment */
+ if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is BdCount reasonable? */
+ if (BdCount == 0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Figure out how many bytes will be between the start of adjacent BDs */
+ RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
+
+ /* Must make sure the ring doesn't span address 0x00000000. If it does,
+ * then the next/prev BD traversal macros will fail.
+ */
+ if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Initial ring setup:
+ * - Clear the entire space
+ * - Setup each BD's BDA field with the physical address of the next BD
+ */
+ (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
+
+ BdVirtAddr = VirtAddrLoc;
+ BdPhyAddr = PhysAddr + RingPtr->Separation;
+ for (i = 1U; i < BdCount; i++) {
+ BdVirtAddr += RingPtr->Separation;
+ BdPhyAddr += RingPtr->Separation;
+ }
+
+ /* Setup and initialize pointers and counters */
+ RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
+ RingPtr->BaseBdAddr = VirtAddrLoc;
+ RingPtr->PhysBaseAddr = PhysAddr;
+ RingPtr->HighBdAddr = BdVirtAddr;
+ RingPtr->Length =
+ ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
+ RingPtr->AllCnt = (u32)BdCount;
+ RingPtr->FreeCnt = (u32)BdCount;
+ RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
+ RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clone the given BD into every BD in the list.
+ * every field of the source BD is replicated in every BD of the list.
+ *
+ * This function can be called only when all BDs are in the free group such as
+ * they are immediately after initialization with XEmacPs_BdRingCreate().
+ * This prevents modification of BDs while they are in use by hardware or the
+ * user.
+ *
+ * @param RingPtr is the pointer of BD ring instance to be worked on.
+ * @param SrcBdPtr is the source BD template to be cloned into the list. This
+ * BD will be modified.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the list was modified.
+ * - XST_DMA_SG_NO_LIST if a list has not been created.
+ * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
+ * hardware or user control.
+ * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction)
+{
+ u32 i;
+ UINTPTR CurBd;
+
+ /* Can't do this function if there isn't a ring */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't do this function with the channel running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_DEVICE_IS_STARTED);
+ }
+
+ /* Can't do this function with some of the BDs in use */
+ if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Starting from the top of the ring, save BD.Next, overwrite the entire
+ * BD with the template, then restore BD.Next
+ */
+ CurBd = RingPtr->BaseBdAddr;
+ for (i = 0U; i < RingPtr->AllCnt; i++) {
+ memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+ CurBd += RingPtr->Separation;
+ }
+
+ CurBd -= RingPtr->Separation;
+
+ if (Direction == XEMACPS_RECV) {
+ XEmacPs_BdSetRxWrap(CurBd);
+ }
+ else {
+ XEmacPs_BdSetTxWrap(CurBd);
+ }
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Reserve locations in the BD list. The set of returned BDs may be modified
+ * in preparation for future DMA transaction(s). Once the BDs are ready to be
+ * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
+ * order which they were allocated here. Example:
+ *
+ *
+ * NumBd = 2,
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ * if (Status != XST_SUCCESS)
+ * {
+ * *Not enough BDs available for the request*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ *
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ * parameter.
+ * - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ * parameter. Doing so will lead to data corruption and system
+ * instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ LONG Status;
+ /* Enough free BDs available for the request? */
+ if (RingPtr->FreeCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead forward */
+ *BdSetPtr = RingPtr->FreeHead;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+ RingPtr->FreeCnt -= NumBd;
+ RingPtr->PreCnt += NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ *
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ * ...
+ * if (Error)
+ * {
+ * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ * }
+ *
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ *
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the BDs were unallocated.
+ * - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ * the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ (void) BdSetPtr;
+ Xil_AssertNonvoid(RingPtr != NULL);
+ Xil_AssertNonvoid(BdSetPtr != NULL);
+
+ /* Enough BDs in the free state for the request? */
+ if (RingPtr->PreCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead backward */
+ XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PreCnt -= NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ * - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ * did not have its "last" bit set.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 i;
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+ if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ CurBdPtr = BdSetPtr;
+ for (i = 0U; i < NumBd; i++) {
+ CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+ }
+ /* Adjust ring pointers & counters */
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+ RingPtr->PreCnt -= NumBd;
+ RingPtr->HwTail = CurBdPtr;
+ RingPtr->HwCnt += NumBd;
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ *
+ * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ * if (NumBd == 0)
+ * {
+ * * hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ *
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Sop = 0U;
+ u32 Status;
+ u32 BdLimitLoc = BdLimit;
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ if (BdLimitLoc > RingPtr->HwCnt){
+ BdLimitLoc = RingPtr->HwCnt;
+ }
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has not completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimitLoc) {
+ /* Read the status */
+ if(CurBdPtr != NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+
+ if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+ Sop = 1U;
+ }
+ if (Sop == 0x00000001U) {
+ BdCount++;
+ BdPartialCount++;
+ }
+
+ /* hardware has processed this BD so check the "last" bit.
+ * If it is clear, then there are more BDs for the current
+ * packet. Keep a count of these partial packet BDs.
+ */
+ if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+ Sop = 0U;
+ BdPartialCount = 0U;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ } else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ *
+ * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ * if (NumBd == 0)
+ * {
+ * *hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ *
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Status;
+
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimit) {
+
+ /* Read the status */
+ if(CurBdPtr!=NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+ if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+ break;
+ }
+
+ BdCount++;
+
+ /* hardware has processed this BD so check the "last" bit. If
+ * it is clear, then there are more BDs for the current packet.
+ * Keep a count of these partial packet BDs.
+ */
+ if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+ BdPartialCount = 0U;
+ } else {
+ BdPartialCount++;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ }
+ else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+}
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0x00000000U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+ if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ /* Update pointers and counters */
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PostCnt -= NumBd;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ * - Is the BD ring linked correctly in physical address space.
+ * - Do the internal pointers point to BDs in the ring.
+ * - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_NO_LIST if the list has not been created.
+ * - XST_IS_STARTED if the channel is not stopped.
+ * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ * structures. If this value is returned, the channel should be reset to
+ * avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+ UINTPTR AddrV, AddrP;
+ u32 i;
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is the list created */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't check if channel is running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_IS_STARTED);
+ }
+
+ /* RunState doesn't make sense */
+ if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal pointers point to correct memory space */
+ AddrV = (UINTPTR) RingPtr->FreeHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PreHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwTail;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PostHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal counters add up */
+ if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+ RingPtr->PostCnt) != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify BDs are linked correctly */
+ AddrV = RingPtr->BaseBdAddr;
+ AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+ for (i = 1U; i < RingPtr->AllCnt; i++) {
+ /* Check BDA for this BD. It should point to next physical addr */
+ if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Move on to next BD */
+ AddrV += RingPtr->Separation;
+ AddrP += RingPtr->Separation;
+ }
+
+ /* Last BD should have wrap bit set */
+ if (XEMACPS_SEND == Direction) {
+ if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+ else { /* XEMACPS_RECV */
+ if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+
+ /* No problems found */
+ return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueRx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueRx = *TempPtr;
+ DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+ *TempPtr = DataValueRx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueTx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueTx = *TempPtr;
+ DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+ *TempPtr = DataValueTx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Reset BD ring head and tail pointers.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param virtaddrloc is the virtual base address of the user memory region.
+ *
+ * @note
+ * Should be called after XEmacPs_Stop()
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+ *
+ *****************************************************************************/
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+{
+ RingPtr->FreeHead = virtaddrloc;
+ RingPtr->PreHead = virtaddrloc;
+ RingPtr->HwHead = virtaddrloc;
+ RingPtr->HwTail = virtaddrloc;
+ RingPtr->PostHead = virtaddrloc;
+}
+
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.h
new file mode 100644
index 0000000..ed8ce2a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.h
@@ -0,0 +1,237 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_control.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_control.c
new file mode 100644
index 0000000..38dbabb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_control.c
@@ -0,0 +1,1155 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_8
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * register. Added a new API for setting the BURST length
+ * in DMACR register.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ *
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device. The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Aptr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ }
+ else{
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ /* Set the MAC bits [31:0] in BOT */
+ MacAddr = *(Aptr);
+ MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+ MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+ MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ /* There are reserved bits in TOP so don't affect them */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+ MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+ /* Set MAC bits [47:32] in TOP */
+ MacAddr |= (u32)(*(Aptr+4));
+ MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ * which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Aptr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *Aptr = (u8) MacAddr;
+ *(Aptr+1) = (u8) (MacAddr >> 8U);
+ *(Aptr+2) = (u8) (MacAddr >> 16U);
+ *(Aptr+3) = (u8) (MacAddr >> 24U);
+
+ /* Read MAC bits [47:32] in TOP */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *(Aptr+4) = (u8) MacAddr;
+ *(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ *
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ *
+ * 000 : divide pclk by 8 (pclk up to 20 MHz)
+ * 001 : divide pclk by 16 (pclk up to 40 MHz)
+ * 010 : divide pclk by 32 (pclk up to 80 MHz)
+ * 011 : divide pclk by 48 (pclk up to 120 MHz)
+ * 100 : divide pclk by 64 (pclk up to 160 MHz)
+ * 101 : divide pclk by 96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+ u32 Reg;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ /* clear these three bits, could be done with mask */
+ Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+ Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+* which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpReadTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpReadTemp = Ipisr;
+ } while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ /* Read data */
+ *PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY. Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+* status from the MAC on a write, the user should read the PHY to verify the
+* write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpWriteTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpWriteTemp = Ipisr;
+ } while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+ u32 Reg;
+ u32 RegUpdateVal = 0;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+ (BLength == XEMACPS_4BYTE_BURST) ||
+ (BLength == XEMACPS_8BYTE_BURST) ||
+ (BLength == XEMACPS_16BYTE_BURST));
+
+ switch (BLength) {
+ case XEMACPS_SINGLE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+ break;
+
+ case XEMACPS_4BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+ break;
+
+ case XEMACPS_8BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+ break;
+
+ case XEMACPS_16BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+ break;
+ }
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+
+ Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+ Reg |= RegUpdateVal;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ Reg);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_g.c
new file mode 100644
index 0000000..d7a5a6d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_g.c
@@ -0,0 +1,52 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_ETHERNET_0_DEVICE_ID,
+ XPAR_PS7_ETHERNET_0_BASEADDR,
+ XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.c
new file mode 100644
index 0000000..aa8aa51
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.c
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc 28/06/13 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status registers
+* Disable Rx and Tx engines
+* Update the Tx and Rx descriptor queue registers with reset values
+* Update the other relevant control registers with reset value
+*
+* @param BaseAddr of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+ u32 RegVal;
+
+ /* Disable the interrupts */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+ /* Stop transmission,disable loopback and Stop tx and Rx engines */
+ RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+ RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+ (u32)XEMACPS_NWCTRL_RXEN_MASK|
+ (u32)XEMACPS_NWCTRL_HALTTX_MASK|
+ (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+ /* Clear the statistic registers, flush the packets in DPRAM*/
+ RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+ XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+ /* Clear the interrupt status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+ /* Clear the tx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+ (u32)XEMACPS_TXSR_TXCOMPL_MASK|
+ (u32)XEMACPS_TXSR_TXGO_MASK));
+ /* Clear the rx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+ XEMACPS_RXSR_FRAMERX_MASK);
+ /* Clear the tx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+ /* Clear the rx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+ /* Update the network config register with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+ /* Update the hash address registers with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.h
new file mode 100644
index 0000000..4a01aea
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.h
@@ -0,0 +1,653 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 3.8 hk 09/17/18 Fix PTP interrupt masks.
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
+
+#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
+
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_intr.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_intr.c
new file mode 100644
index 0000000..acb0a50
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_intr.c
@@ -0,0 +1,264 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
+* Rx errors. Under heavy Rx traffic, there will be a large
+* number of errors related to receive buffer not available.
+* Because of a HW bug (SI #692601), under such heavy errors,
+* the Rx data path can become unresponsive. To reduce the
+* probabilities for hitting this HW bug, the SW writes to
+* bit 18 to flush a packet from Rx DPRAM immediately. The
+* changes for it are done in the function
+* XEmacPs_IntrHandler.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+* and 64-bit changes.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+* there is no error. CR# 869403
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ * XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ * when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef)
+{
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FuncPointer != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ switch (HandlerType) {
+ case XEMACPS_HANDLER_DMASEND:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->SendRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_DMARECV:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->RecvRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_ERROR:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+ InstancePtr->ErrorRef = CallBackRef;
+ break;
+ default:
+ Status = (LONG)(XST_INVALID_PARAM);
+ break;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+* interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+ u32 RegISR;
+ u32 RegSR;
+ u32 RegCtrl;
+ u32 RegQ1ISR = 0U;
+ XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* This ISR will try to handle as many interrupts as it can in a single
+ * call. However, in most of the places where the user's error handler
+ * is called, this ISR exits because it is expected that the user will
+ * reset the device in nearly all instances.
+ */
+ RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+
+ /* Read Transmit Q1 ISR */
+
+ if (InstancePtr->Version > 2)
+ RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET);
+
+ /* Clear the interrupt status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ RegISR);
+
+ /* Receive complete interrupt */
+ if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+ /* Clear RX status register RX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET,
+ ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+ (u32)XEMACPS_RXSR_BUFFNA_MASK));
+ InstancePtr->RecvHandler(InstancePtr->RecvRef);
+ }
+
+ /* Transmit Q1 complete interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET,
+ XEMACPS_INTQ1SR_TXCOMPL_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Transmit complete interrupt */
+ if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Receive error conditions interrupt */
+ if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+ /* Clear RX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, RegSR);
+
+ /* Fix for CR # 692702. Write to bit 18 of net_ctrl
+ * register to flush a packet out of Rx SRAM upon
+ * an error for receive buffer not available. */
+ if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+ RegCtrl =
+ XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, RegCtrl);
+ }
+
+ if(RegSR != 0) {
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+ XEMACPS_RECV, RegSR);
+ }
+ }
+
+ /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+ * will be asserted the same time.
+ * Have to distinguish this bit to handle the real error condition.
+ */
+ /* Transmit Q1 error conditions interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear Interrupt Q1 status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegQ1ISR);
+ }
+
+ /* Transmit error conditions interrupt */
+ if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+ (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, RegSR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegSR);
+ }
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_sinit.c
new file mode 100644
index 0000000..123e6e5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_sinit.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 New
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+ XEmacPs_Config *CfgPtr = NULL;
+ u32 i;
+
+ for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+ if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XEmacPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/Makefile
new file mode 100644
index 0000000..8601ce4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.c
new file mode 100644
index 0000000..c781335
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.c
@@ -0,0 +1,626 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device. The interrupts are disabled
+* for output pins on all banks during initialization.
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1 aru 07/13/18 Resolved doxygen reported warnings. CR# 1006331.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param ConfigPtr points to the XGpioPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address should be passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return XST_SUCCESS always.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status = XST_SUCCESS;
+ u8 i;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+ /*
+ * Set some default values for instance data, don't indicate the device
+ * is ready to use until everything has been initialized successfully.
+ */
+ InstancePtr->IsReady = 0U;
+ InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+ InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
+ InstancePtr->Platform = XGetPlatform_Info();
+
+ /* Initialize the Bank data based on platform */
+ if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * Max pins in the ZynqMP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+ InstancePtr->MaxPinNum = (u32)174;
+ InstancePtr->MaxBanks = (u8)6;
+ } else {
+ /*
+ * Max pins in the GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+ InstancePtr->MaxPinNum = (u32)118;
+ InstancePtr->MaxBanks = (u8)4;
+ }
+
+ /*
+ * By default, interrupts are not masked in GPIO. Disable
+ * interrupts for all pins in all the 4 banks.
+ */
+ for (i=0;iMaxBanks;i++) {
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+ }
+
+ /* Indicate the component is now ready to use. */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Current value of the Data register.
+*
+* @note This function is used for reading the state of all the GPIO pins
+* of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the data has to be read.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return Current value of the Pin (0 or 1).
+*
+* @note This function is used for reading the state of the specified
+* GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Data is the value to be written to the Data register.
+*
+* @return None.
+*
+* @note This function is used for writing to all the GPIO pins of
+* the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Data is the data to be written to the specified pin (0 or 1).
+*
+* @return None.
+*
+* @note This function does a masked write to the specified pin of
+* the specified GPIO bank. The previous state of other pins
+* is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+ u32 RegOffset;
+ u32 Value;
+ u8 Bank;
+ u8 PinNumber;
+ u32 DataVar = Data;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ if (PinNumber > 15U) {
+ /* There are only 16 data bits in bit maskable register. */
+ PinNumber -= (u8)16;
+ RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+ } else {
+ RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+ }
+
+ /*
+ * Get the 32 bit value to be written to the Mask/Data register where
+ * the upper 16 bits is the mask and lower 16 bits is the data.
+ */
+ DataVar &= (u32)0x01;
+ Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+ RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Direction is the 32 bit mask of the Pin direction to be set for
+* all the pins in the Bank. Bits with 0 are set to Input mode,
+* bits with 1 are set to Output Mode.
+*
+* @return None.
+*
+* @note This function is used for setting the direction of all the pins
+* in the specified bank. The previous state of the pins is
+* not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Direction is the direction to be set for the specified pin.
+* Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 DirModeReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(Direction <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+
+ if (Direction!=(u32)0) { /* Output Direction */
+ DirModeReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Input Direction */
+ DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Returns a 32 bit mask of the Direction register. Bits with 0 are
+* in Input mode, bits with 1 are in Output Mode.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Direction is to be
+* retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Direction of the specified pin.
+* - 0 for Input Direction
+* - 1 for Output Direction
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param OpEnable is the 32 bit mask of the Output Enables to be set for
+* all the pins in the Bank. The Output Enable of bits with 0 are
+* disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return None.
+*
+* @note This function is used for setting the Output Enables of all the
+* pins in the specified bank. The previous state of the Output
+* Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param OpEnable specifies whether the Output Enable for the specified
+* pin should be enabled.
+* Valid values are 0 for Disabling Output Enable,
+* 1 for Enabling Output Enable.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 OpEnableReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(OpEnable <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+
+ if (OpEnable != (u32)0) { /* Enable Output Enable */
+ OpEnableReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Disable Output Enable */
+ OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Returns a a 32 bit mask of the Output Enable register.
+* Bits with 0 are in Disabled state, bits with 1 are in
+* Enabled State.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Output Enable status is to
+* be retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Output Enable of the specified pin.
+* - 0 if Output Enable is disabled for this pin
+* - 1 if Output Enable is enabled for this pin
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param PinNumber is the Pin number in the GPIO device.
+* @param BankNumber returns the Bank in which this GPIO pin is present.
+* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+ u32 XGpioPsPinTable[6] = {0};
+ u32 Platform = XGetPlatform_Info();
+
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * This structure defines the mapping of the pin numbers to the banks when
+ * the driver APIs are used for working on the individual pins.
+ */
+
+ XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+ XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+ XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+ XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+ XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+ XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < 6U) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ } else {
+ XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+ XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+ XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+ XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < 4U) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ }
+ if (*BankNumber == (u8)0) {
+ *PinNumberInBank = PinNumber;
+ } else {
+ *PinNumberInBank = (u8)((u32)PinNumber %
+ (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+ }
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.h
new file mode 100644
index 0000000..3ab40b9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.h
@@ -0,0 +1,274 @@
+
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_4
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_g.c
new file mode 100644
index 0000000..c4e9e85
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_GPIO_0_DEVICE_ID,
+ XPAR_PS7_GPIO_0_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.c
new file mode 100644
index 0000000..6c53b8d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains low level GPIO functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk 08/22/13 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param Base address of GPIO module
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+ u32 BankCount;
+ u32 Platform,MaxBanks;
+
+ Platform = XGetPlatform_Info();
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ MaxBanks = (u32)6;
+ } else {
+ MaxBanks = (u32)4;
+ }
+ /* Write reset values to all mask data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+ }
+ /* Write reset values to all output data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET), 0x0U);
+ }
+
+ /* Reset all registers of all GPIO banks */
+ for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET), 0x0U);
+ }
+
+ /* Bank 0 Int type */
+ XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+ XGPIOPS_INTTYPE_BANK0_RESET);
+ /* Bank 1 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK1_RESET);
+ /* Bank 2 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK2_RESET);
+ /* Bank 3 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK3_RESET);
+
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /* Bank 4 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK4_RESET);
+ /* Bank 5 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK5_RESET);
+ }
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.h
new file mode 100644
index 0000000..59ec921
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.h
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_intr.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_intr.c
new file mode 100644
index 0000000..1bcc84b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_intr.c
@@ -0,0 +1,730 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to API's. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1 aru 07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
+* 3.4 aru 08/09/18 Ressolved cppcheck warnings.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are to
+* be enabled. Bit positions of 1 will be enabled. Bit positions
+* of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be enabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are
+* to be disabled. Bit positions of 1 will be disabled. Bit
+* positions of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be disabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+* indicate that the interrupt for that pin is enabled, bit
+* positions with 0 indicate that the interrupt for that pin is
+* disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+ u32 IntrMask;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+ return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt is enabled.
+* - FALSE if the interrupt is disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return The value read from Interrupt Status Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt has occurred.
+* - FALSE if the interrupt has not occurred.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the mask of the interrupts to be cleared. Bit positions
+* of 1 will be cleared. Bit positions of 0 will not change the
+* previous interrupt status.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ /* Clear the currently pending interrupts. */
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt status is to be
+* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ /* Clear the specified pending interrupts. */
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ IntrReg &= ((u32)1 << PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType is the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
+* 0 means Active Low or Falling Edge and 1 means Active High or
+* Rising Edge.
+* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note This function is used for setting the interrupt related
+* properties of all the pins in the specified bank. The previous
+* state of the pins is not maintained.
+* To change the Interrupt properties of a single GPIO pin, use the
+* function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType returns the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity returns the 32 bit mask of the interrupt
+* polarity. 0 means Active Low or Falling Edge and 1 means
+* Active High or Rising Edge.
+* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be set.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+* defined in xgpiops.h to specify the IRQ type.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+ u32 IntrTypeReg;
+ u32 IntrPolReg;
+ u32 IntrOnAnyReg;
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+
+ switch (IrqType) {
+ case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ default:
+ /**< Default statement is added for MISRA C compliance. */
+ break;
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be obtained.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+* returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u32 IntrType;
+ u32 IntrPol;
+ u32 IntrOnAny;
+ u8 Bank;
+ u8 PinNumber;
+ u8 IrqType;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrType == ((u32)1 << PinNumber)) {
+
+ IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+ if (IntrOnAny == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+ } else if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+ }
+ } else {
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+ }
+ }
+
+ return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FuncPointer is the pointer to the callback function.
+*
+*
+* @return None.
+*
+* @note The handler is called within interrupt context, so it should do
+* its work quickly and queue potentially time-consuming work to a
+* task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPointer != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Handler = (XGpioPs_Handler)FuncPointer;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return None.
+*
+* @note This function does not save and restore the processor context
+* such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+ u8 Bank;
+ u32 IntrStatus;
+ u32 IntrEnabled;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+ IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+ if (IntrStatus != (u32)0) {
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+ Bank);
+ XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+ (IntrStatus & IntrEnabled));
+ InstancePtr->Handler(InstancePtr->
+ CallBackRef, Bank,
+ (IntrStatus & IntrEnabled));
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param Bank is the GPIO Bank in which an interrupt occurred.
+* @param Status is the Interrupt status of the GPIO bank.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+ (void) CallBackRef;
+ (void) Bank;
+ (void) Status;
+
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_selftest.c
new file mode 100644
index 0000000..0fe83aa
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_selftest.c
@@ -0,0 +1,129 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+* - XST_SUCCESS if the self-test passed.
+* - XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+ s32 Status = XST_SUCCESS;
+ u32 IntrEnabled;
+ u32 CurrentIntrType = 0U;
+ u32 CurrentIntrPolarity = 0U;
+ u32 CurrentIntrOnAny = 0U;
+ u32 IntrType = 0U;
+ u32 IntrPolarity = 0U;
+ u32 IntrOnAny = 0U;
+ u32 IntrTestValue = 0x22U;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable the Interrupts for Bank 0 . */
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+ XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ /*
+ * Get the Current Interrupt properties for Bank 0.
+ * Set them to a known value, read it back and compare.
+ */
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+ &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+ IntrTestValue, IntrTestValue);
+
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+ &IntrPolarity, &IntrOnAny);
+
+ if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+ (IntrOnAny != IntrTestValue)) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the contents of all the interrupt registers modified in this
+ * test.
+ */
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+ CurrentIntrPolarity, CurrentIntrOnAny);
+
+ XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_sinit.c
new file mode 100644
index 0000000..5cd560a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+ XGpioPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+ if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XGpioPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/Makefile
new file mode 100644
index 0000000..3600928
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspips_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling qspips"
+
+xqspips_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspips_includes
+
+xqspips_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips.c
new file mode 100644
index 0000000..94f9098
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips.c
@@ -0,0 +1,1568 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.c
+* @addtogroup qspips_v3_5
+* @{
+*
+* Contains implements the interface functions of the XQspiPs driver.
+* See xqspips.h for a detailed description of the device and driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added logic to XQspiPs_GetReadData to handle data
+* shift for normal data reads and instruction/status
+* reads differently based on the ShiftReadData flag.
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* This version of the driver fixes CRs 670197/663787.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+*
+* 2.02a hk 05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
+* function
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141
+*
+* 2.03a hk 09/05/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* 3.5 tjs 13/08/18 Fixed compilation warnings for ARMCC.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines qspi flash instruction format
+ */
+typedef struct {
+ u8 OpCode; /**< Operational code of the instruction */
+ u8 InstSize; /**< Size of the instruction including address bytes */
+ u8 TxOffset; /**< Register address where instruction has to be
+ written */
+} XQspiPsInstFormat;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ARRAY_SIZE(Array) (sizeof(Array) / sizeof((Array)[0]))
+
+/************************** Function Prototypes ******************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * List of all the QSPI instructions and its format
+ */
+static XQspiPsInstFormat FlashInst[] = {
+ { XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
+ { XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
+ /* Add all the instructions supported by the flash device */
+};
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+* - Master mode
+* - Active high clock polarity
+* - Clock phase 0
+* - Baud rate divisor 2
+* - Transfer width 32
+* - Master reference clock = pclk
+* - No chip select active
+* - Manual CS and Manual Start disabled
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific QSPI device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_DEVICE_IS_STARTED if the device is already started.
+* It must be stopped to re-initialize.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is busy, disallow the initialize and return a status
+ * indicating it is already started. This allows the user to stop the
+ * device and re-initialize, but prevents a user from inadvertently
+ * initializing. This assumes the busy flag is cleared at startup.
+ */
+ if (InstancePtr->IsBusy == TRUE) {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Set some default values.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->StatusHandler = StubStatusHandler;
+
+ InstancePtr->SendBufferPtr = NULL;
+ InstancePtr->RecvBufferPtr = NULL;
+ InstancePtr->RequestedBytes = 0;
+ InstancePtr->RemainingBytes = 0;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+
+ /*
+ * Reset the QSPI device to get it into its initial state. It is
+ * expected that device configuration will take place after this
+ * initialization is done, but before the device is started.
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPI device. Reset must only be called after the driver has been
+* initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPI device after the reset.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_Reset(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Abort any transfer that is in progress
+ */
+ XQspiPs_Abort(InstancePtr);
+
+ /*
+ * Write default value to configuration register.
+ * Do not modify reserved bits.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+ ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+ ConfigReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
+* The byte counts are cleared, the busy flag is cleared.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note
+*
+* This function does a read/modify/write of the config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XQspiPs_Abort(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+ u32 IsLock;
+
+ XQspiPs_Disable(InstancePtr);
+
+ /*
+ * De-assert slave select lines.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * QSPI Software Reset
+ */
+ IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
+ if (IsLock) {
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
+ SLCR_UNLOCK_MASK);
+ }
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
+ LQSPI_RST_CTRL_MASK);
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
+ if (IsLock) {
+ XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
+ SLCR_LOCK_MASK);
+ }
+
+ /*
+ * Set the RX and TX FIFO threshold to reset value (one)
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
+
+ InstancePtr->RemainingBytes = 0;
+ InstancePtr->RequestedBytes = 0;
+ InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the QSPI bus. Initiates bus communication and
+* sends/receives data to/from the selected QSPI slave. For every byte sent,
+* a byte is received.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+* The caller wishes to send and receive, and provides two different
+* buffers for send and receive.
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+* The caller wishes only to send and does not care about the received
+* data. The driver ignores the received data in this case.
+*
+* XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+* The caller wishes to send and receive, but provides the same buffer
+* for doing both. The driver sends the data and overwrites the send
+* buffer with received data as it transfers the data.
+*
+* XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+* The caller wishes to only receive and does not care about sending
+* data. In this case, the caller must still provide a send buffer, but
+* it can be the same as the receive buffer if the caller does not care
+* what it sends. The device must send N bytes of data if it wishes to
+* receive N bytes of data.
+*
+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. The SetSlaveSelect function must be called
+* prior to this function.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param SendBufPtr is a pointer to a data buffer that needs to be
+* transmitted. This buffer must not be NULL.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* This argument can be NULL if do not care about receiving.
+* @param ByteCount contains the number of bytes to send/receive.
+* The number of bytes received always equals the number of bytes
+* sent.
+*
+* @return
+* - XST_SUCCESS if the buffers are successfully handed off to the
+* device for transfer.
+* - XST_DEVICE_BUSY indicates that a data transfer is already in
+* progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe. The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount)
+{
+ u32 StatusReg;
+ u32 ConfigReg;
+ u8 Instruction;
+ u32 Data;
+ unsigned int Index;
+ u8 TransCount = 0;
+ XQspiPsInstFormat *CurrInst;
+ XQspiPsInstFormat NewInst[2];
+ u8 SwitchFlag = 0;
+
+ CurrInst = &NewInst[0];
+
+ /*
+ * The RecvBufPtr argument can be null
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SendBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check whether there is another transfer in progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Set the busy flag, which will be cleared in the ISR when the
+ * transfer is entirely done.
+ */
+ InstancePtr->IsBusy = TRUE;
+
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
+
+ /*
+ * The first byte with every chip-select assertion is always
+ * expected to be an instruction for flash interface mode
+ */
+ Instruction = *InstancePtr->SendBufferPtr;
+
+ for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+ if (Instruction == FlashInst[Index].OpCode) {
+ break;
+ }
+ }
+
+ /*
+ * Set the RX FIFO threshold
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+ /*
+ * If the slave select is "Forced" or under manual control,
+ * set the slave select now, before beginning the transfer.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Enable the device.
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ /*
+ * Clear all the interrrupts.
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+ XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+ if (Index < ARRAY_SIZE(FlashInst)) {
+ CurrInst = &FlashInst[Index];
+ /*
+ * Check for WRSR instruction which has different size for
+ * Spansion (3 bytes) and Micron (2 bytes)
+ */
+ if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+ (ByteCount == 3)) {
+ CurrInst->InstSize = 3;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ }
+ }
+
+ /*
+ * If instruction not present in table
+ */
+ if (Index == ARRAY_SIZE(FlashInst)) {
+ /*
+ * Assign current instruction, size and TXD register to be used
+ * The InstSize mentioned in case of instructions greater than
+ * 4 bytes is not the actual size, but is indicative of
+ * the TXD register used.
+ * The remaining bytes of the instruction will be transmitted
+ * through TXD0 below.
+ */
+ switch (ByteCount%4) {
+ case XQSPIPS_SIZE_ONE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+ CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_TWO:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+ CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_THREE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ default:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+ CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+ break;
+ }
+ }
+
+ /*
+ * If the instruction size in not 4 bytes then the data received needs
+ * to be shifted
+ */
+ if (CurrInst->InstSize != 4) {
+ InstancePtr->ShiftReadData = 1;
+ } else {
+ InstancePtr->ShiftReadData = 0;
+ }
+
+ /* Get the complete command (flash inst + address/data) */
+ Data = *((u32 *)InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += CurrInst->InstSize;
+ InstancePtr->RemainingBytes -= CurrInst->InstSize;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+
+ /* Write the command to the FIFO */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ CurrInst->TxOffset, Data);
+ TransCount++;
+
+ /*
+ * If switching from TXD1/2/3 to TXD0, then start transfer and
+ * check for FIFO empty
+ */
+ if (SwitchFlag == 1) {
+ SwitchFlag = 0;
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ /*
+ * Wait for the transfer to finish by polling Tx fifo status.
+ */
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+ }
+
+ /*
+ * Fill the Tx FIFO with as many bytes as it takes (or as many as
+ * we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_FIFO_DEPTH)) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ TransCount++;
+ }
+
+ /*
+ * Enable QSPI interrupts (connecting to the interrupt controller and
+ * enabling interrupts should have been done by the caller).
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+
+ /*
+ * If, in Manual Start mode, Start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the QSPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+* The caller wishes to send and receive, and provides two different
+* buffers for send and receive.
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+* The caller wishes only to send and does not care about the received
+* data. The driver ignores the received data in this case.
+*
+* XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+* The caller wishes to send and receive, but provides the same buffer
+* for doing both. The driver sends the data and overwrites the send
+* buffer with received data as it transfers the data.
+*
+* XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+* The caller wishes to only receive and does not care about sending
+* data. In this case, the caller must still provide a send buffer, but
+* it can be the same as the receive buffer if the caller does not care
+* what it sends. The device must send N bytes of data if it wishes to
+* receive N bytes of data.
+*
+*
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param SendBufPtr is a pointer to a data buffer that needs to be
+* transmitted. This buffer must not be NULL.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* This argument can be NULL if do not care about receiving.
+* @param ByteCount contains the number of bytes to send/receive.
+* The number of bytes received always equals the number of bytes
+* sent.
+* @return
+* - XST_SUCCESS if the buffers are successfully handed off to the
+* device for transfer.
+* - XST_DEVICE_BUSY indicates that a data transfer is already in
+* progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe. The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount)
+{
+ u32 StatusReg;
+ u32 ConfigReg;
+ u8 Instruction;
+ u32 Data;
+ u8 TransCount;
+ unsigned int Index;
+ XQspiPsInstFormat *CurrInst;
+ XQspiPsInstFormat NewInst[2];
+ u8 SwitchFlag = 0;
+ u8 IsManualStart = FALSE;
+ u32 RxCount = 0;
+
+ CurrInst = &NewInst[0];
+ /*
+ * The RecvBufPtr argument can be NULL.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(SendBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check whether there is another transfer in progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Set the busy flag, which will be cleared when the transfer is
+ * entirely done.
+ */
+ InstancePtr->IsBusy = TRUE;
+
+ /*
+ * Set up buffer pointers.
+ */
+ InstancePtr->SendBufferPtr = SendBufPtr;
+ InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+ InstancePtr->RequestedBytes = ByteCount;
+ InstancePtr->RemainingBytes = ByteCount;
+
+ /*
+ * The first byte with every chip-select assertion is always
+ * expected to be an instruction for flash interface mode
+ */
+ Instruction = *InstancePtr->SendBufferPtr;
+
+ for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+ if (Instruction == FlashInst[Index].OpCode) {
+ break;
+ }
+ }
+
+ /*
+ * Set the RX FIFO threshold
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+ /*
+ * If the slave select is "Forced" or under manual control,
+ * set the slave select now, before beginning the transfer.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Enable the device.
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ if (Index < ARRAY_SIZE(FlashInst)) {
+
+ CurrInst = &FlashInst[Index];
+ /*
+ * Check for WRSR instruction which has different size for
+ * Spansion (3 bytes) and Micron (2 bytes)
+ */
+ if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+ (ByteCount == 3)) {
+ CurrInst->InstSize = 3;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ }
+ }
+
+ /*
+ * If instruction not present in table
+ */
+ if (Index == ARRAY_SIZE(FlashInst)) {
+ /*
+ * Assign current instruction, size and TXD register to be used.
+ * The InstSize mentioned in case of instructions greater than 4 bytes
+ * is not the actual size, but is indicative of the TXD register used.
+ * The remaining bytes of the instruction will be transmitted
+ * through TXD0 below.
+ */
+ switch (ByteCount % 4) {
+ case XQSPIPS_SIZE_ONE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+ CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_TWO:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+ CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ case XQSPIPS_SIZE_THREE:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+ CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+ if (ByteCount > 4) {
+ SwitchFlag = 1;
+ }
+ break;
+ default:
+ CurrInst->OpCode = Instruction;
+ CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+ CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+ break;
+ }
+ }
+
+ /*
+ * If the instruction size in not 4 bytes then the data received needs
+ * to be shifted
+ */
+ if (CurrInst->InstSize != 4) {
+ InstancePtr->ShiftReadData = 1;
+ } else {
+ InstancePtr->ShiftReadData = 0;
+ }
+ TransCount = 0;
+ /* Get the complete command (flash inst + address/data) */
+ Data = *((u32 *)InstancePtr->SendBufferPtr);
+ InstancePtr->SendBufferPtr += CurrInst->InstSize;
+ InstancePtr->RemainingBytes -= CurrInst->InstSize;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+
+ /* Write the command to the FIFO */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ CurrInst->TxOffset, Data);
+ ++TransCount;
+
+ /*
+ * If switching from TXD1/2/3 to TXD0, then start transfer and
+ * check for FIFO empty
+ */
+ if (SwitchFlag == 1) {
+ SwitchFlag = 0;
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ /*
+ * Wait for the transfer to finish by polling Tx fifo status.
+ */
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+ }
+
+ /*
+ * Check if manual start is selected and store it in a
+ * local varibale for reference. This is to avoid reading
+ * the config register everytime.
+ */
+ IsManualStart = XQspiPs_IsManualStart(InstancePtr);
+
+ /*
+ * Fill the DTR/FIFO with as many bytes as it will take (or as
+ * many as we have to send).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_FIFO_DEPTH)) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ ++TransCount;
+ }
+
+ while ((InstancePtr->RemainingBytes > 0) ||
+ (InstancePtr->RequestedBytes > 0)) {
+
+ /*
+ * Fill the TX FIFO with RX threshold no. of entries (or as
+ * many as we have to send, in case that's less).
+ */
+ while ((InstancePtr->RemainingBytes > 0) &&
+ (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)InstancePtr->SendBufferPtr));
+ InstancePtr->SendBufferPtr += 4;
+ InstancePtr->RemainingBytes -= 4;
+ if (InstancePtr->RemainingBytes < 0) {
+ InstancePtr->RemainingBytes = 0;
+ }
+ ++TransCount;
+ }
+
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (IsManualStart == TRUE) {
+ ConfigReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Reset TransCount - this is only used to fill TX FIFO
+ * in the above loop;
+ * RxCount is used to keep track of data received
+ */
+ TransCount = 0;
+
+ /*
+ * Wait for RX FIFO to reach threshold (or)
+ * TX FIFO to become empty.
+ * The latter check is required for
+ * small transfers (<32 words) and
+ * when the last chunk in a large data transfer is < 32 words.
+ */
+
+ do {
+ StatusReg = XQspiPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ } while (((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
+ ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0));
+
+ /*
+ * A transmit has just completed. Process received data
+ * and check for more data to transmit.
+ * First get the data received as a result of the
+ * transmit that just completed. Receive data based on the
+ * count obtained while filling tx fifo. Always get
+ * the received data, but only fill the receive
+ * buffer if it points to something (the upper layer
+ * software may not care to receive data).
+ */
+ while ((InstancePtr->RequestedBytes > 0) &&
+ (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ u32 Data;
+
+ RxCount++;
+
+ if (InstancePtr->RecvBufferPtr != NULL) {
+ if (InstancePtr->RequestedBytes < 4) {
+ Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ XQspiPs_GetReadData(InstancePtr, Data,
+ InstancePtr->RequestedBytes);
+ } else {
+ (*(u32 *)InstancePtr->RecvBufferPtr) =
+ XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ InstancePtr->RecvBufferPtr += 4;
+ InstancePtr->RequestedBytes -= 4;
+ if (InstancePtr->RequestedBytes < 0) {
+ InstancePtr->RequestedBytes = 0;
+ }
+ }
+ } else {
+ Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ InstancePtr->RequestedBytes -= 4;
+ }
+ }
+ RxCount = 0;
+ }
+
+ /*
+ * If the Slave select lines are being manually controlled, disable
+ * them because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Clear the busy flag.
+ */
+ InstancePtr->IsBusy = FALSE;
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(InstancePtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the flash in Linear QSPI mode.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RecvBufPtr is a pointer to a buffer for received data.
+* @param Address is the starting address within the flash from
+* from where data needs to be read.
+* @param ByteCount contains the number of bytes to receive.
+*
+* @return
+* - XST_SUCCESS if read is performed
+* - XST_FAILURE if Linear mode is not set
+*
+* @note None.
+*
+*
+******************************************************************************/
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount)
+{
+ int Status = (int)XST_SUCCESS;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(RecvBufPtr != NULL);
+ Xil_AssertNonvoid(ByteCount > 0);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#endif
+ /*
+ * Enable the controller
+ */
+ XQspiPs_Enable(InstancePtr);
+
+ if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
+ XQSPIPS_LQSPI_CR_LINEAR_MASK) {
+ memcpy((void *)RecvBufPtr,
+ (const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
+ Address),
+ (size_t)ByteCount);
+ Status = (int)XST_SUCCESS;
+ } else {
+ Status = (int)XST_FAILURE;
+ }
+
+ /*
+ * Disable the controller
+ */
+ XQspiPs_Disable(InstancePtr);
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects the slave with which the master communicates.
+*
+* The user is not allowed to select the slave while a transfer is in progress.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - XST_SUCCESS if the slave is selected or deselected
+* successfully.
+* - XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+* changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the QSPI is idle.
+*
+******************************************************************************/
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow the slave select to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Select the slave
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+*
+*
+* XST_SPI_TRANSFER_DONE The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data
+* but there were none available in the transmit
+* register/FIFO. This typically means the slave
+* application did not issue a transfer request
+* fast enough, or the processor/driver could not
+* fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received
+* but the receive data register/FIFO was full.
+*
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = FuncPtr;
+ InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param StatusEvent is the event that just occurred.
+* @param ByteCount is the number of bytes transferred up until the event
+* occurred.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount)
+{
+ (void) CallBackRef;
+ (void) StatusEvent;
+ (void) ByteCount;
+
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for QSPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+* transmit register or FIFO is empty. The driver uses this interrupt during a
+* transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+* the QSPI device, when configured as a slave, attempts to read an empty
+* DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the
+* device data in a timely manner. No action is taken by the driver other than
+* to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+* QSPI device attempts to write a received byte to an already full DRR/FIFO.
+* A full DRR/FIFO usually means software is not emptying the data in a timely
+* manner. No action is taken by the driver other than to inform the upper
+* layer software of the error.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.
+*
+******************************************************************************/
+void XQspiPs_InterruptHandler(void *InstancePtr)
+{
+ XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
+ u32 IntrStatus;
+ u32 ConfigReg;
+ u32 Data;
+ u32 TransCount;
+ u32 Count = 0;
+ unsigned BytesDone; /* Number of bytes done so far. */
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Immediately clear the interrupts in case the ISR causes another
+ * interrupt to be generated. If we clear at the end of the ISR,
+ * we may miss newly generated interrupts. This occurs because we
+ * transmit from within the ISR, which could potentially cause another
+ * TX_EMPTY interrupt.
+ */
+ IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_SR_OFFSET);
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+ (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
+
+ if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
+ (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
+
+ /*
+ * Rx FIFO has just reached threshold no. of entries.
+ * Read threshold no. of entries from RX FIFO
+ * Another possiblity of entering this loop is when
+ * the last byte has been transmitted and TX FIFO is empty,
+ * in which case, read all the data from RX FIFO.
+ * Always get the received data, but only fill the
+ * receive buffer if it is not null (it can be null when
+ * the device does not care to receive data).
+ */
+ TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+ if (TransCount % 4) {
+ TransCount = TransCount/4 + 1;
+ } else {
+ TransCount = TransCount/4;
+ }
+
+ while ((Count < TransCount) &&
+ (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+
+ if (QspiPtr->RecvBufferPtr != NULL) {
+ if (QspiPtr->RequestedBytes < 4) {
+ Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ XQspiPs_GetReadData(QspiPtr, Data,
+ QspiPtr->RequestedBytes);
+ } else {
+ (*(u32 *)QspiPtr->RecvBufferPtr) =
+ XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ QspiPtr->RecvBufferPtr += 4;
+ QspiPtr->RequestedBytes -= 4;
+ if (QspiPtr->RequestedBytes < 0) {
+ QspiPtr->RequestedBytes = 0;
+ }
+ }
+ } else {
+ XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXD_OFFSET);
+ QspiPtr->RequestedBytes -= 4;
+ if (QspiPtr->RequestedBytes < 0) {
+ QspiPtr->RequestedBytes = 0;
+ }
+
+ }
+ Count++;
+ }
+ Count = 0;
+ /*
+ * Interrupt asserted as TX_OW got asserted
+ * See if there is more data to send.
+ * Fill TX FIFO with RX threshold no. of entries or
+ * remaining entries (in case that is less than threshold)
+ */
+ while ((QspiPtr->RemainingBytes > 0) &&
+ (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+ /*
+ * Send more data.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_TXD_00_OFFSET,
+ *((u32 *)QspiPtr->SendBufferPtr));
+ QspiPtr->SendBufferPtr += 4;
+ QspiPtr->RemainingBytes -= 4;
+ if (QspiPtr->RemainingBytes < 0) {
+ QspiPtr->RemainingBytes = 0;
+ }
+
+ Count++;
+ }
+
+ if ((QspiPtr->RemainingBytes == 0) &&
+ (QspiPtr->RequestedBytes == 0)) {
+ /*
+ * No more data to send. Disable the interrupt
+ * and inform the upper layer software that the
+ * transfer is done. The interrupt will be re-enabled
+ * when another transfer is initiated.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK |
+ XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+
+ /*
+ * If the Slave select is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+ }
+
+ /*
+ * Clear the busy flag.
+ */
+ QspiPtr->IsBusy = FALSE;
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_TRANSFER_DONE,
+ QspiPtr->RequestedBytes);
+ } else {
+ /*
+ * Enable the TXOW interrupt.
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_IER_OFFSET,
+ XQSPIPS_IXR_RXNEMPTY_MASK |
+ XQSPIPS_IXR_TXOW_MASK |
+ XQSPIPS_IXR_RXOVR_MASK |
+ XQSPIPS_IXR_TXUF_MASK);
+ /*
+ * If, in Manual Start mode, start the transfer.
+ */
+ if (XQspiPs_IsManualStart(QspiPtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+ XQspiPs_WriteReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+ }
+ }
+
+ /*
+ * Check for overflow and underflow errors.
+ */
+ if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
+ BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+ QspiPtr->IsBusy = FALSE;
+
+ /*
+ * If the Slave select lines is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_RECEIVE_OVERRUN, BytesDone);
+ }
+
+ if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
+ BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+
+ QspiPtr->IsBusy = FALSE;
+ /*
+ * If the Slave select lines is being manually controlled,
+ * disable it because the transfer is complete.
+ */
+ if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+ ConfigReg = XQspiPs_ReadReg(
+ QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET, ConfigReg);
+ }
+
+ /*
+ * Disable the device.
+ */
+ XQspiPs_Disable(QspiPtr);
+
+ /*
+ * Reset the RX FIFO threshold to one
+ */
+ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+ XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+ QspiPtr->StatusHandler(QspiPtr->StatusRef,
+ XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+ }
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Copies data from Data to the Receive buffer.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Data is the data which needs to be copied to the Rx buffer.
+* @param Size is the number of bytes to be copied to the Receive buffer.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
+{
+ u8 DataByte3;
+
+ if (InstancePtr->RecvBufferPtr) {
+ switch (Size) {
+ case 1:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u8 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0xFF000000) >> 24);
+ } else {
+ *((u8 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFF);
+ }
+ InstancePtr->RecvBufferPtr += 1;
+ break;
+ case 2:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0xFFFF0000) >> 16);
+ } else {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFFFF);
+ }
+ InstancePtr->RecvBufferPtr += 2;
+ break;
+ case 3:
+ if (InstancePtr->ShiftReadData == 1) {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ ((Data & 0x00FFFF00) >> 8);
+ InstancePtr->RecvBufferPtr += 2;
+ DataByte3 = ((Data & 0xFF000000) >> 24);
+ *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+ } else {
+ *((u16 *)InstancePtr->RecvBufferPtr) =
+ (Data & 0xFFFF);
+ InstancePtr->RecvBufferPtr += 2;
+ DataByte3 = ((Data & 0x00FF0000) >> 16);
+ *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+ }
+ InstancePtr->RecvBufferPtr += 1;
+ break;
+ default:
+ /* This will never execute */
+ break;
+ }
+ }
+ InstancePtr->ShiftReadData = 0;
+ InstancePtr->RequestedBytes -= Size;
+ if (InstancePtr->RequestedBytes < 0) {
+ InstancePtr->RequestedBytes = 0;
+ }
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips.h
new file mode 100644
index 0000000..302c870
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips.h
@@ -0,0 +1,797 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_5
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* Linear Mode
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device. The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+* static configuration structure defined in xqspips_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+* is written into the TXFIFO and de asserted when the TXFIFO becomes
+* empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+* TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+* the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+* TXFIFO write otherwise there could be a race condition where the TXFIFO
+* becomes empty before the new word is written. In that case the
+* transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+* This results in a single transaction to be split into multiple pieces each
+* with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data. The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+* in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* Removed code related to mode fault for CR 671468
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added a flag ShiftReadData to the instance structure
+*. and is used in the XQspiPs_GetReadData API.
+* The ShiftReadData Flag indicates whether the data
+* read from the Rx FIFO needs to be shifted
+* in cases where the data is less than 4 bytes
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* This version of the driver fixes CRs 670197/663787/
+* 670297/671468.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Added macros for Set/Get Rx Watermark. Changed QSPI
+* Enable/Disable macro argument from BaseAddress to
+* Instance Pointer. Added DelayNss argument to SetDelays
+* and GetDelays API's.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+* SetDelays and GetDelays API's include DelayNss parameter.
+* Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register. Renamed Fixed burst error to
+* data FSM error in LQSPI Status register.
+*
+* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
+* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+* Added enable and disable to the XQspiPs_LqspiRead() function
+* Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set.
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added prefix to constant definitions for ConnectionMode
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added API's for QSPI reset and
+* linear mode initialization for boot.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* Updated linear init API for parallel and stacked modes.
+* CR#737760.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
+* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_H /* prevent circular inclusions */
+#define XQSPIPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device. Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats. A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver. These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+ * RX FIFO full
+ */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
+#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
+#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
+#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
+#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
+#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
+#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
+#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
+#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
+#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
+#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
+#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
+#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 1
+#define XQSPIPS_SIZE_TWO 2
+#define XQSPIPS_SIZE_THREE 3
+#define XQSPIPS_SIZE_FOUR 4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE 0
+#define XQSPIPS_CONNECTION_MODE_STACKED 1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param CallBackRef is the callback reference passed in by the upper
+ * layer when setting the callback functions, and passed back to
+ * the upper layer when the callback is invoked. Its type is
+ * not important to the driver, so it is a void pointer.
+ * @param StatusEvent holds one or more status events that have occurred.
+ * See the XQspiPs_SetStatusHandler() for details on the status
+ * events that can be passed in the callback.
+ * @param ByteCount indicates how many bytes of data were successfully
+ * transferred. This may be less than the number of bytes
+ * requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XQspiPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ u8 *SendBufferPtr; /**< Buffer to send (state) */
+ u8 *RecvBufferPtr; /**< Buffer to receive (state) */
+ int RequestedBytes; /**< Number of bytes to transfer (state) */
+ int RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 IsBusy; /**< A transfer is in progress (state) */
+ XQspiPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+ u32 ShiftReadData; /**< Flag to indicate whether the data
+ * read from the Rx FIFO needs to be shifted
+ * in cases where the data is less than 4
+ * bytes
+ */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are
+* 0-255.
+*
+* @return None
+*
+* @note C-Style signature:
+* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return An 8-bit value representing Slave Idle Count.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr) \
+ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Tx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Rx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+ XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written to the Linear QSPI
+* configuration register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 32-bit value representing the contents of the LQSPI Config
+* register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
+ u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_g.c
new file mode 100644
index 0000000..b3c4be1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_g.c
@@ -0,0 +1,53 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_QSPI_0_DEVICE_ID,
+ XPAR_PS7_QSPI_0_BASEADDR,
+ XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
+ XPAR_PS7_QSPI_0_QSPI_MODE
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_hw.c
new file mode 100644
index 0000000..e7910af
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_hw.c
@@ -0,0 +1,220 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.c
+* @addtogroup qspips_v3_5
+* @{
+*
+* Contains low level functions, primarily reset related.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 2.03a hk 09/17/13 First release
+* 3.1 hk 06/19/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Pre-scaler value for divided by 4
+ *
+ * Pre-scaler value for divided by 4
+ *
+ * @{
+ */
+#define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets QSPI by disabling the device and bringing it to reset state through
+* register writes.
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_ResetHw(u32 BaseAddress)
+{
+ u32 ConfigReg;
+
+ /*
+ * Disable interrupts
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
+ XQSPIPS_IXR_DISABLE_ALL);
+
+ /*
+ * Disable device
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+ 0);
+
+ /*
+ * De-assert slave select lines.
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Write default value to RX and TX threshold registers
+ * RX threshold should be set to 1 here because the corresponding
+ * status bit is used next to clear the RXFIFO
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
+ (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
+ (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
+
+ /*
+ * Clear RXFIFO
+ */
+ while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
+ XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+ XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
+ }
+
+ /*
+ * Clear status register by reading register and
+ * writing 1 to clear the write to clear bits
+ */
+ XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
+ XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+ /*
+ * Write default value to configuration register
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+ ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * De-select linear mode
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+ 0x0);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes QSPI to Linear mode with default QSPI boot settings.
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_LinearInit(u32 BaseAddress)
+{
+ u32 BaudRateDiv;
+ u32 LinearCfg;
+ u32 ConfigReg;
+
+ /*
+ * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
+ * should be set to 0x001; hence shift the value and use the mask.
+ */
+ BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
+ XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
+ /*
+ * Write configuration register with default values, slave selected &
+ * pre-scaler value for divide by 4
+ */
+ ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+ ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
+ ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+ /*
+ * Write linear configuration register with default value -
+ * enable linear mode and use fast read.
+ */
+
+ if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
+
+ }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+ XQSPIPS_CONNECTION_MODE_STACKED){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
+
+ }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+ XQSPIPS_CONNECTION_MODE_PARALLEL){
+
+ LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+ XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
+ XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
+
+ }
+
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+ LinearCfg);
+
+ /*
+ * Enable device
+ */
+ XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+ XQSPIPS_ER_ENABLE_MASK);
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_hw.h
new file mode 100644
index 0000000..9a47979
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_hw.h
@@ -0,0 +1,419 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a ka 07/25/12 Added a few register defines for CR 670297
+* and removed some defines of reserved fields for
+* CR 671468
+* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+* bit in Configuration register.
+* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register.
+* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
+* linear mode initialization for boot. Added related
+* constant definitions.
+* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
+#define XQSPIPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+ Enable */
+#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
+ transferred */
+#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
+ XQSPIPS_CR_SSCTRL_MASK | \
+ XQSPIPS_CR_DATA_SZ_MASK | \
+ XQSPIPS_CR_MSTREN_MASK | \
+ XQSPIPS_CR_SSFORCE_MASK | \
+ XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
+ XQSPIPS_CR_CPHA_MASK | \
+ XQSPIPS_CR_PRESC_MASK | \
+ XQSPIPS_CR_MANSTRTEN_MASK | \
+ XQSPIPS_CR_MANSTRT_MASK | \
+ XQSPIPS_CR_ENDIAN_MASK | \
+ XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Disable Register
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
+ mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
+ need write to clear */
+#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
+ between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
+ between two words shift */
+#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
+ mask */
+#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
+ or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
+ between addr and return
+ read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
+ received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
+ received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+ XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_options.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_options.c
new file mode 100644
index 0000000..6765001
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_options.c
@@ -0,0 +1,426 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_options.c
+* @addtogroup qspips_v3_5
+* @{
+*
+* Contains functions for the configuration of the XQspiPs driver component.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode. The driver doesnot support
+* Slave mode or the legacy mode.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* 2.01a sg 02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
+*
+* 2.02a hk 26/03/13 Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+ u32 Option;
+ u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+ {XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
+ {XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
+ {XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
+ {XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
+ {XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
+};
+
+#define XQSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPI device driver. The options control
+* how the device behaves relative to the QSPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Options contains the specified options to be set. This is a bit
+* mask where a 1 means to turn the option on, and a 0 means to
+* turn the option off. One or more bit values may be contained in
+* the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
+* the file xqspips.h.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
+{
+ u32 ConfigReg;
+ unsigned int Index;
+ u32 QspiOptions;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow to modify the Control Register while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
+ Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
+
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ /*
+ * Loop through the options table, turning the option on or off
+ * depending on whether the bit is set in the incoming options flag.
+ */
+ for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+ if (Options & OptionsTable[Index].Option) {
+ /* Turn it on */
+ ConfigReg |= OptionsTable[Index].Mask;
+ } else {
+ /* Turn it off */
+ ConfigReg &= ~(OptionsTable[Index].Mask);
+ }
+ }
+
+ /*
+ * Now write the control register. Leave it to the upper layers
+ * to restart the device.
+ */
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+ ConfigReg);
+
+ /*
+ * Check for the LQSPI configuration options.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET);
+
+
+ if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET,
+ XQSPIPS_LQSPI_CR_RST_STATE);
+ XQspiPs_SetSlaveSelect(InstancePtr);
+ } else {
+ ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPI device. The options control how
+* the device behaves relative to the QSPI bus.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
+*
+* @note None.
+*
+******************************************************************************/
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
+{
+ u32 OptionsFlag = 0;
+ u32 ConfigReg;
+ unsigned int Index;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the current options from QSPI configuration register.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ /*
+ * Loop through the options table to grab options
+ */
+ for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+ if (ConfigReg & OptionsTable[Index].Mask) {
+ OptionsFlag |= OptionsTable[Index].Option;
+ }
+ }
+
+ /*
+ * Check for the LQSPI configuration options.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_LQSPI_CR_OFFSET);
+
+ if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
+ OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
+ }
+
+ return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an QSPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param Prescaler is the value that determine how much the clock should
+* be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
+* in xqspips.h for this setting.
+*
+* @return
+* - XST_SUCCESS if options are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
+
+ /*
+ * Do not allow the slave select to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Read the configuration register, mask out the interesting bits, and set
+ * them with the shifted value passed into the function. Write the
+ * results back to the configuration register.
+ */
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
+ ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
+ XQSPIPS_CR_PRESC_SHIFT;
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET,
+ ConfigReg);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an QSPI device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return The prescaler value.
+*
+* @note None.
+*
+*
+******************************************************************************/
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
+{
+ u32 ConfigReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_CR_OFFSET);
+
+ ConfigReg &= XQSPIPS_CR_PRESC_MASK;
+
+ return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the QSPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param DelayNss is the delay to de-assert slave select between
+* two word transfers.
+* @param DelayBtwn is the delay between one Slave Select being
+* de-activated and the activation of another slave. The delay is
+* the number of master clock periods given by DelayBtwn + 2.
+* @param DelayAfter define the delay between the last bit of the current
+* byte transfer and the first bit of the next byte transfer.
+* The delay in number of master clock periods is given as:
+* CHPA=0:DelayInit+DelayAfter+3
+* CHPA=1:DelayAfter+1
+* @param DelayInit is the delay between asserting the slave select signal
+* and the first bit transfer. The delay int number of master clock
+* periods is DelayInit+1.
+*
+* @return
+* - XST_SUCCESS if delays are successfully set.
+* - XST_DEVICE_BUSY if the device is currently transferring data.
+* The transfer must complete or be aborted before setting options.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit)
+{
+ u32 DelayRegister;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Do not allow the delays to change while a transfer is in
+ * progress. Not thread-safe.
+ */
+ if (InstancePtr->IsBusy) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /* Shift, Mask and OR the values to build the register settings */
+ DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
+ DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
+ DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
+ DelayRegister |= (u32) DelayInit;
+
+ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_DR_OFFSET, DelayRegister);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an QSPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param DelayNss is a pointer to the Delay to de-assert slave select
+* between two word transfers.
+* @param DelayBtwn is a pointer to the Delay Between transfers value.
+* This is a return parameter.
+* @param DelayAfter is a pointer to the Delay After transfer value.
+* This is a return parameter.
+* @param DelayInit is a pointer to the Delay Initially value. This is
+* a return parameter.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit)
+{
+ u32 DelayRegister;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XQSPIPS_DR_OFFSET);
+
+ *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
+
+ *DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
+ XQSPIPS_DR_AFTER_SHIFT);
+
+ *DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
+ XQSPIPS_DR_BTWN_SHIFT);
+
+ *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
+ XQSPIPS_DR_NSS_SHIFT);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_selftest.c
new file mode 100644
index 0000000..aa23fce
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_selftest.c
@@ -0,0 +1,135 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_selftest.c
+* @addtogroup qspips_v3_5
+* @{
+*
+* This file contains the implementation of selftest function for the QSPI
+* device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter.
+* 3.1 hk 06/19/14 Remove checks for CR and ISR register values as they are
+* reset in the previous step.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - XST_SUCCESS if successful
+* - XST_REGISTER_ERROR indicates a register did not read or write
+* correctly.
+*
+* @note None.
+*
+******************************************************************************/
+int XQspiPs_SelfTest(XQspiPs *InstancePtr)
+{
+ int Status;
+ u8 DelayTestNss;
+ u8 DelayTestBtwn;
+ u8 DelayTestAfter;
+ u8 DelayTestInit;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Reset the QSPI device to leave it in a known good state
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ DelayTestNss = 0x5A;
+ DelayTestBtwn = 0xA5;
+ DelayTestAfter = 0xAA;
+ DelayTestInit = 0x55;
+
+ /*
+ * Write and read the delay register, just to be sure there is some
+ * hardware out there.
+ */
+ Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+ DelayTestAfter, DelayTestInit);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+ &DelayTestAfter, &DelayTestInit);
+ if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
+ (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
+ return XST_REGISTER_ERROR;
+ }
+
+ Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ /*
+ * Reset the QSPI device to leave it in a known good state
+ */
+ XQspiPs_Reset(InstancePtr);
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_sinit.c
new file mode 100644
index 0000000..a5686c2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/qspips_v3_5/src/xqspips_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_sinit.c
+* @addtogroup qspips_v3_5
+* @{
+*
+* The implementation of the XQspiPs component's static initialization
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPs_Config XQspiPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device to look up the
+* configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspips.h for the definition of XQspiPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
+{
+ XQspiPs_Config *CfgPtr = NULL;
+ int Index;
+
+ for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
+ if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XQspiPs_ConfigTable[Index];
+ break;
+ }
+ }
+ return CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/Makefile
new file mode 100644
index 0000000..04867a4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic.c
new file mode 100644
index 0000000..c142c27
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic.c
@@ -0,0 +1,1033 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v3_10
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize
+* Since entry is now made as pointer in the XScuGic
+* structure, necessary changes are made.
+* The HandlerTable can now be populated through the low
+* level routine XScuGic_RegisterHandler added in this
+* release. Hence necessary checks are added not to
+* overwrite the HandlerTable entriesin function
+* XScuGic_CfgInitialize.
+* 1.03a srt 02/27/13 Added APIs
+* -XScuGic_SetPriTrigTypeByDistAddr()
+* -XScuGic_GetPriTrigTypeByDistAddr()
+* Removed Offset calculation macros, defined in _hw.h
+* (CR 702687)
+* added support to direct interrupts to the appropriate
+* CPU Earlier interrupts were directed to CPU1
+* (hard coded).Now depending upon the CPU selected by the
+* user(xparameters.h), interrupts will be directed to
+* the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove
+* warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+* in function XScuGic_CfgInitialize is removed as it was
+* a bug.
+* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+* target CPU mapping
+* 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add
+* the current cpu to interrupt processor targets registers
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is
+* assumed that the distributor will be initialized by
+* Linux master. However for CortexR5 case, the earlier code
+* is left unchanged where the the interrupt processor target
+* registers in the distributor is initialized with the
+* corresponding CPU ID on which the application built over
+* the scugic driver runs. These changes fix CR#937243.
+* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+* to interrupt target register to fix CR#951848
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to
+* simplify the flow and avoid code duplication. Changes are
+* made for USE_AMP use case for R5. In a scenario
+* (in R5 split mode) when one R5 is operating with A53 in
+* open amp config and other R5 running baremetal app, the
+* existing code had the potential to stop the whole AMP
+* solution to work(if for some reason the R5 running the
+* baremetal app tasked to initialize the Distributor hangs
+* or crashes before initializing).Changes are made so that
+* the R5 under AMP first checks if the distributor is
+* enabled or not and if not, it does the standard
+* Distributor initialization.This fixes the CR#952962.
+* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+* for single core zynq-7000s
+* 3.5 mus 10/05/16 Modified DistributorInit function to avoid
+* re-initialization of distributor, If it is already
+* initialized by other CPU.
+* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id
+* value and properly mask interrupt target processor value
+* to modify interrupt target processor register for a given
+* interrupt ID and cpu ID
+* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and
+* interrupts in case they are being used only by current
+* cpu. It also removes current cpu from interrupt target
+* registers for all interrupts.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU. It fixes CR#992490.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* It fixes CR#1007753.
+* 3.10 mus 09/19/18 Fix cppcheck warnings
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DoDistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param CpuID is the Cpu ID to be initialized.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+ u32 Int_Id;
+ u32 LocalCpuID = CpuID;
+
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+ /*
+ * Set the security domains in the int_security registers for
+ * non-secure interrupts
+ * All are secure, so leave at the default. Set to 1 for non-secure
+ * interrupts.
+ */
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+16U) {
+ /*
+ * Each INT_ID uses two bits, or 16 INT_ID per register
+ * Set them all to be level sensitive, active HIGH.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ 0U);
+ }
+
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+ /*
+ * 2. The priority using int the priority_level register
+ * The priority_level and spi_target registers use one byte per
+ * INT_ID.
+ * Write a default value that can be changed elsewhere.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+ /*
+ * 3. The CPU interface in the spi_target register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ LocalCpuID);
+ }
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+32U) {
+ /*
+ * 4. Enable the SPI using the enable_set register.
+ * Leave all disabled for now.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
+ 0xFFFFFFFFU);
+
+ }
+
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
+ XSCUGIC_EN_INT_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* DistributorInit initializes the distributor of the GIC. It calls
+* DoDistributorInit to finish the initialization.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param CpuID is the Cpu ID to be initialized.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+ u32 Int_Id;
+ u32 LocalCpuID = CpuID;
+ u32 RegValue;
+
+#if USE_AMP == 1 && (defined(ARMA9) || defined(__aarch64__))
+#warning "Building GIC for AMP"
+ /*
+ * GIC initialization is taken care by master CPU in
+ * openamp configuration, so do nothing and return.
+ */
+ return;
+#endif
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+ if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
+ DoDistributorInit(InstancePtr, CpuID);
+ return;
+ }
+
+ /*
+ * The overall distributor should not be initialized in AMP case where
+ * another CPU is taking care of it.
+ */
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ RegValue |= LocalCpuID;
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInitialize initializes the CPU Interface of the GIC. The initialization
+* entails:
+*
+* - Set the priority of the CPU
+* - Enable the CPU interface
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void CPUInitialize(XScuGic *InstancePtr)
+{
+ /*
+ * Program the priority mask of the CPU using the Priority mask register
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
+
+
+ /*
+ * If the CPU operates in both security domains, set parameters in the
+ * control_s register.
+ * 1. Set FIQen=1 to use FIQ for secure interrupts,
+ * 2. Program the AckCtl bit
+ * 3. Program the SBPR bit to select the binary pointer behavior
+ * 4. Set EnableS = 1 to enable secure interrupts
+ * 5. Set EnbleNS = 1 to enable non secure interrupts
+ */
+
+ /*
+ * If the CPU operates only in the secure domain, setup the
+ * control_s register.
+ * 1. Set FIQen=1,
+ * 2. Set EnableS=1, to enable the CPU interface to signal secure
+ * interrupts. Only enable the IRQ output unless secure interrupts
+ * are needed.
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param ConfigPtr is a pointer to a config table for the particular
+* device this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* Config->BaseAddress for this parameters, passing the physical
+* address instead.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
+ XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ u32 Int_Id;
+ u32 Cpu_Id = CpuId + (u32)1;
+ (void) EffectiveAddr;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ /*
+ * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+ * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+ */
+#ifdef ARMA9
+ if (XPAR_CPU_ID == 0x01) {
+ Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR
+ + EFUSE_STATUS_OFFSET) & EFUSE_STATUS_CPU_MASK) == 0);
+ }
+#endif
+
+ if (InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+ InstancePtr->IsReady = 0U;
+ InstancePtr->Config = ConfigPtr;
+
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id++) {
+ /*
+ * Initalize the handler to point to a stub to handle an
+ * interrupt which has not been connected to a handler
+ * Only initialize it if the handler is 0 which means it
+ * was not initialized statically by the tools/user. Set
+ * the callback reference to this instance so that
+ * unhandled interrupts can be tracked.
+ */
+ if ((InstancePtr->Config->HandlerTable[Int_Id].Handler
+ == (Xil_InterruptHandler)NULL)) {
+ InstancePtr->Config->HandlerTable[Int_Id].Handler
+ = (Xil_InterruptHandler)StubHandler;
+ }
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+ InstancePtr;
+ }
+ XScuGic_Stop(InstancePtr);
+ DistributorInit(InstancePtr, Cpu_Id);
+ CPUInitialize(InstancePtr);
+
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param Handler to the handler for that interrupt.
+* @param CallBackRef is the callback reference, usually the instance
+* pointer of the connecting driver.
+*
+* @return
+*
+* - XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef)
+{
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertNonvoid(Handler != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used as an index into the table to select the proper
+ * handler
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)Handler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param Int_Id contains the ID of the interrupt source and should
+* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the interrupt such that it won't occur while disconnecting
+ * the handler, only disable the specified interrupt id without
+ * modifying the other interrupt ids
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+
+ /*
+ * Disconnect the handler and connect a stub, the callback reference
+ * must be set to this instance to allow unhandled interrupts to be
+ * tracked
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)StubHandler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Enable the selected interrupt source by setting the
+ * corresponding bit in the Enable Set register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id contains the ID of the interrupt source and should be
+* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the selected interrupt source by setting the
+ * corresponding bit in the IDR.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+ ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller. This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode. A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param Int_Id is the software interrupt ID to simulate an interrupt.
+* @param Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Int_Id <= 15U);
+ Xil_AssertNonvoid(Cpu_Id <= 255U);
+
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired interrupt. Int_Id currently limited to 0 - 15
+ * Use the target list for the Cpu ID.
+ */
+ Mask = ((Cpu_Id << 16U) | Int_Id) &
+ (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+ /*
+ * Write to the Software interrupt trigger register. Use the appropriate
+ * CPU Int_Id.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+ /* Indicate the interrupt was successfully simulated */
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef)
+{
+ /*
+ * verify that the inputs are valid
+ */
+ Xil_AssertVoid(CallBackRef != NULL);
+
+ /*
+ * Indicate another unhandled interrupt for stats
+ */
+ ((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is the new priority for the IRQ source. 0 is highest
+* priority, 0xF8(248) is lowest. There are 32 priority levels
+* supported with a step of 8. Hence the supported priorities are
+* 0, 8, 16, 32, 40 ..., 248.
+* @param Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI Read Only b10 always
+* PPI Read Only depending on how the PPIs are configured.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive
+* SPI LSB is read only.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive/
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+ u8 LocalPriority;
+ LocalPriority = Priority;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+ RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is a pointer to the value of the priority of the IRQ
+* source. This is a return value.
+* @param Trigger is pointer to the value of the trigger of the IRQ
+* source. This is a return value.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%4U)*8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+ u32 Offset;
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ Offset = (Int_Id & 0x3U);
+ Cpu_Id = (0x1U << Cpu_Id);
+
+ RegValue = (RegValue & (~(0xFFU << (Offset*8U))));
+ RegValue |= ((Cpu_Id) << (Offset*8U));
+
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+ u8 BitPos;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ /*
+ * Identify bit position corresponding to Int_Id and Cpu_Id,
+ * in interrupt target register and clear it
+ */
+ BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+ RegValue &= (~(1U << BitPos));
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+
+ Target_Cpu = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ /* Remove LocalCpuID from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+}
+/****************************************************************************/
+/**
+* It checks if the interrupt target register contains all interrupts to be
+* targeted for current CPU. If they are programmed to be forwarded to current
+* cpu, this API disable all interrupts and disable GIC distributor.
+* This API also removes current CPU from interrupt target registers for all
+* interrupt.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_Stop(XScuGic *InstancePtr)
+{
+ u32 Int_Id;
+ u32 RegValue;
+ u32 Target_Cpu;
+ u32 DistDisable = 1; /* Track distributor status*/
+ u32 LocalCpuID = ((u32)0x1 << CpuId);
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /* If distributor is already disabled, no need to do anything */
+ RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+ if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
+ return;
+ }
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ /*
+ * Check if the interrupt are targeted to current cpu only or not.
+ * Also remove current cpu from interrupt target register for all
+ * interrupts.
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+
+ Target_Cpu = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ if ((Target_Cpu != LocalCpuID) && (Target_Cpu != 0)) {
+ /*
+ * If any other CPU is also programmed to target
+ * register, GIC distributor can not be disabled.
+ */
+ DistDisable = 0;
+ }
+
+ /* Remove current CPU from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+
+ /*
+ * If GIC distributor is safe to be disabled, disable all the interrupt
+ * and then disable distributor.
+ */
+ if (DistDisable == 1) {
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+32U) {
+ /*
+ * Disable all the interrupts
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+ Int_Id),
+ 0xFFFFFFFFU);
+ }
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+ }
+}
+
+/****************************************************************************/
+/**
+* This updates the CpuId global variable.
+*
+* @param CpuCoreId is the CPU core number.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_SetCpuID(u32 CpuCoreId)
+{
+ Xil_AssertVoid(CpuCoreId <= 1U);
+
+ CpuId = CpuCoreId;
+}
+
+/****************************************************************************/
+/**
+* This function returns the CpuId variable.
+*
+* @return The CPU core number.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XScuGic_GetCpuID(void)
+{
+ return CpuId;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic.h
new file mode 100644
index 0000000..befa209
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic.h
@@ -0,0 +1,369 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_10
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+* - specific individual interrupt enabling/disabling
+* - specific individual interrupt acknowledging
+* - attaching specific callback function to handle interrupt source
+* - assigning desired priority to interrupt source if default is not
+* acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* Interrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs. The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/00 First release
+* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+* The HandlerTable (of type XScuGic_VectorTableEntry) is
+* moved to XScuGic_Config structure from XScuGic structure.
+*
+* The "Config" entry in XScuGic structure is made as
+* pointer for better efficiency.
+*
+* A new file named as xscugic_hw.c is now added. It is
+* to implement low level driver routines without using
+* any xscugic instance pointer. They are useful when the
+* user wants to use xscugic through device id or
+* base address. The driver routines provided are explained
+* below.
+* XScuGic_DeviceInitialize that takes device id as
+* argument and initializes the device (without calling
+* XScuGic_CfgInitialize).
+* XScuGic_DeviceInterruptHandler that takes device id
+* as argument and calls appropriate handlers from the
+* HandlerTable.
+* XScuGic_RegisterHandler that registers a new handler
+* by taking xscugic hardware base address as argument.
+* LookupConfigByBaseAddress is used to return the
+* corresponding config structure from XScuGic_ConfigTable
+* based on the scugic base address passed.
+* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+* structure.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+* *_hw.h
+* Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+* xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET 0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config *Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32 XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_g.c
new file mode 100644
index 0000000..84dff68
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_g.c
@@ -0,0 +1,53 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUGIC_0_DEVICE_ID,
+ XPAR_PS7_SCUGIC_0_BASEADDR,
+ XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
+ {{0}} /**< Initialize the HandlerTable to 0 */
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_hw.c
new file mode 100644
index 0000000..9ef7f86
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_hw.c
@@ -0,0 +1,652 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v3_10
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device. The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm 07/18/11 First release
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* Added support to direct interrupts to the appropriate
+* CPU. Earlier interrupts were directed to CPU1
+* (hard coded). Now depending upon the CPU selected by
+* the user (xparameters.h), interrupts will be directed
+* to the relevant CPU.This fixes CR 699688.
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* 3.9 mus 02/21/18 Added new API's
+* XScuGic_InterruptUnmapFromCpuByDistAddr and
+* XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap
+* specific/all interrupts from target CPU. It fixes
+* CR#992490.
+* 3.10 mus 07/17/18 Updated XScuGic_DeviceInterruptHandler to fix array
+* overrun reported by coverity tool. It fixes
+* CR#1006344.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+* It fixes CR#1007753
+* 3.10 mus 09/19/18 Update documentation for XScuGic_RegisterHandler to
+* fix doxygen warnings.
+*
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+extern u32 CpuId;
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+* @param CpuID is the Cpu ID to be initialized.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+ u32 Int_Id;
+ u32 LocalCpuID = CpuID;
+
+#if USE_AMP == 1
+ #warning "Building GIC for AMP"
+
+ /*
+ * The distrubutor should not be initialized by FreeRTOS in the case of
+ * AMP -- it is assumed that Linux is the master of this device in that
+ * case.
+ */
+ return;
+#endif
+
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+ /*
+ * Set the security domains in the int_security registers for non-secure
+ * interrupts. All are secure, so leave at the default. Set to 1 for
+ * non-secure interrupts.
+ */
+
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+16U) {
+ /*
+ * Each INT_ID uses two bits, or 16 INT_ID per register
+ * Set them all to be level sensitive, active HIGH.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+ }
+
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+ /*
+ * 2. The priority using int the priority_level register
+ * The priority_level and spi_target registers use one byte per
+ * INT_ID.
+ * Write a default value that can be changed elsewhere.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+ /*
+ * 3. The CPU interface in the spi_target register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+ }
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+32U) {
+ /*
+ * 4. Enable the SPI using the enable_set register.
+ * Leave all disabled for now.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+ Int_Id),
+ 0xFFFFFFFFU);
+
+ }
+
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+ XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param ConfigPtr is a pointer to a config table for the particular
+* device this driver is associated with.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+ /*
+ * Program the priority mask of the CPU using the Priority mask
+ * register
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+ 0xF0U);
+
+ /*
+ * If the CPU operates in both security domains, set parameters in the
+ * control_s register.
+ * 1. Set FIQen=1 to use FIQ for secure interrupts,
+ * 2. Program the AckCtl bit
+ * 3. Program the SBPR bit to select the binary pointer behavior
+ * 4. Set EnableS = 1 to enable secure interrupts
+ * 5. Set EnbleNS = 1 to enable non secure interrupts
+ */
+
+ /*
+ * If the CPU operates only in the secure domain, setup the
+ * control_s register.
+ * 1. Set FIQen=1,
+ * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+ * interrupts Only enable the IRQ output unless secure interrupts
+ * are needed.
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize the GIC based on the device id. The
+* initialization entails:
+*
+* - Initialize distributor interface
+* - Initialize cpu interface
+*
+* @param DeviceId is device id to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+ XScuGic_Config *Config;
+ u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1;
+
+ Config = &XScuGic_ConfigTable[(u32)DeviceId];
+
+ DistInit(Config, Cpu_Id);
+
+ CPUInit(Config);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver. It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized. It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param DeviceId is the unique identifier for the ScuGic device.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+ u32 InterruptID;
+ u32 IntIDFull;
+ XScuGic_VectorTableEntry *TablePtr;
+ XScuGic_Config *CfgPtr;
+
+ CfgPtr = &XScuGic_ConfigTable[(INTPTR)DeviceId];
+
+ /*
+ * Read the int_ack register to identify the highest priority
+ * interrupt ID and make sure it is valid. Reading Int_Ack will
+ * clear the interrupt in the GIC.
+ */
+ IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress,
+ XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+ if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if there are
+ * multiple processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine based on
+ * the IRQSource. A software trigger is cleared by the ACK.
+ */
+ TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+ if (TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+ XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+ /*
+ * Return from the interrupt. Change security domains could happen
+ * here.
+ */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID. The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param BaseAddress is the CPU Interface Register base address of the
+* interrupt controller whose vector table will be modified.
+* @param InterruptID is the interrupt ID to be associated with the input
+* handler.
+* @param IntrHandler is the function pointer that will be added to
+* the vector table for the given interrupt ID.
+* @param CallBackRef is the argument that will be passed to the new
+* handler function when it is called. This is user-specific.
+*
+* @return None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+ XScuGic_Config *CfgPtr;
+ CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+ if (CfgPtr != NULL) {
+ if (IntrHandler != NULL) {
+ CfgPtr->HandlerTable[InterruptID].Handler =
+ (Xil_InterruptHandler)IntrHandler;
+ }
+ if (CallBackRef != NULL) {
+ CfgPtr->HandlerTable[InterruptID].CallBackRef =
+ CallBackRef;
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return A pointer to the configuration structure for the specified
+* device, or NULL if the device was not found.
+*
+* @note None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+ XScuGic_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+ CpuBaseAddress) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param DistBaseAddress is the distributor base address
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is the new priority for the IRQ source. 0 is highest
+* priority, 0xF8(248) is lowest. There are 32 priority
+* levels supported with a step of 8. Hence the supported
+* priorities are 0, 8, 16, 32, 40 ..., 248.
+* @param Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI Read Only b10 always
+* PPI Read Only depending on how the PPIs are configured.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive
+* SPI LSB is read only.
+* b01 Active HIGH level sensitive
+* b11 Rising edge sensitive/
+*
+* @return None.
+*
+* @note This API has the similar functionality of XScuGic_SetPriority
+* TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+ u8 LocalPriority = Priority;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+ RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param DistBaseAddress is the distributor base address
+* @param Int_Id is the IRQ source number to modify
+* @param Priority is a pointer to the value of the priority of the IRQ
+* source. This is a return value.
+* @param Trigger is pointer to the value of the trigger of the IRQ
+* source. This is a return value.
+*
+* @return None.
+*
+* @note This API has the similar functionality of XScuGic_GetPriority
+* TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%4U)*8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupt has to be
+* unmapped
+* @param Int_Id is the IRQ source number to modify
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue;
+ u8 BitPos;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ /*
+ * Identify bit position corresponding to Int_Id and Cpu_Id,
+ * in interrupt target register and clear it
+ */
+ BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+ RegValue &= (~(1U << BitPos));
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
+}
+
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param DistBaseAddress is the device base address
+* @param Cpu_Id is a CPU number from which the interrupts has to be
+* unmapped
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id)
+{
+ u32 Int_Id;
+ u32 Target_Cpu;
+ u32 LocalCpuID = (1U << Cpu_Id);
+
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
+ Int_Id = Int_Id+4U) {
+
+ Target_Cpu = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+ /* Remove LocalCpuID from interrupt target register */
+ Target_Cpu &= (~LocalCpuID);
+ XScuGic_WriteReg(DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+ }
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_hw.h
new file mode 100644
index 0000000..54f1035
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_hw.h
@@ -0,0 +1,648 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_10
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+* added to enable or disable interrupts based on
+* Distributor Register base address. Normally users use
+* XScuGic instance and call XScuGic_Enable or
+* XScuGic_Disable to enable/disable interrupts. These
+* new macros are provided when user does not want to
+* use an instance pointer but still wants to enable or
+* disable interrupts.
+* Function prototypes for functions (present in newly
+* added file xscugic_hw.c) are added.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+* Zynq Ultrascale Mp
+* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
+* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef PLATFORM_ZYNQ
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
+ Shared Peripheral
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
+ b00-Use the target List
+ b01-All CPUs except requester
+ b10-To Requester
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
+ 0=separate registers,
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
+ interrupts,
+ 0= use IRQ for both,
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
+ Value Secure Non-secure
+ b000 0xFE 0xFF
+ b001 0xFC 0xFE
+ b010 0xF8 0xFC
+ b011 0xF0 0xF8
+ b100 0xE0 0xF0
+ b101 0xC0 0xE0
+ b110 0x80 0xC0
+ b111 0x00 0x80
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param Register is the register offset for the clear/enable bank.
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_intr.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_intr.c
new file mode 100644
index 0000000..14beb6e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_intr.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v3_10
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller. The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing. This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported. This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system. The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
+* since the HandlerTable has now moved to XScuGic_Config.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.10 mus 07/17/18 Updated XScuGic_InterruptHandler to fix array overrun
+* reported by coverity tool. It fixes CR#1006344.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+*
+*
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver. It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized. It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+ u32 InterruptID;
+ u32 IntIDFull;
+ XScuGic_VectorTableEntry *TablePtr;
+
+ /* Assert that the pointer to the instance is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Read the int_ack register to identify the highest priority
+ * interrupt ID and make sure it is valid. Reading Int_Ack will
+ * clear the interrupt in the GIC.
+ */
+ IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+ if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if
+ * there are multiple processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC
+ * instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine
+ * based on the IRQSource. A software trigger is cleared by
+ *.the ACK.
+ */
+ TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+ if (TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+ /*
+ * Return from the interrupt. Change security domains
+ * could happen here.
+ */
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_selftest.c
new file mode 100644
index 0000000..7cb02fb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_selftest.c
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v3_10
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUGIC_PCELL_ID 0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* -XST_SUCCESS if self-test is successful.
+* -XST_FAILURE if the self-test is not successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+ u32 RegValue1 = 0U;
+ u32 Index;
+ s32 Status;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the ID registers.
+ */
+ for (Index = 0U; Index <= 3U; Index++) {
+ RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+ ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) <<
+ (Index * 8U);
+ }
+
+ if (XSCUGIC_PCELL_ID != RegValue1) {
+ Status = XST_FAILURE;
+ } else {
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_sinit.c
new file mode 100644
index 0000000..2abfa8b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scugic_v3_10/src/xscugic_sinit.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_10
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
+* reported by checkpatch. It fixes CR#1006344.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique identifier for a device.
+*
+* @return A pointer to the XScuGic configuration structure for the
+* specified device, or NULL if the device was not found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+ XScuGic_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
new file mode 100644
index 0000000..7c673d4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scutimer_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling scutimer"
+
+scutimer_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scutimer_includes
+
+scutimer_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
new file mode 100644
index 0000000..d7f6348
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
@@ -0,0 +1,282 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function must be called
+* before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param ConfigPtr points to the XScuTimer configuration structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+ /*
+ * Copy configuration into the instance structure.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+ InstancePtr->IsStarted = (u32)0;
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ Status =(s32)XST_SUCCESS;
+ }
+ else {
+ Status = (s32)XST_DEVICE_IS_STARTED;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Set the 'timer enable' bit in the register.
+ */
+ Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is started.
+ */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear the 'timer enable' bit in the register.
+ */
+ Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is stopped.
+ */
+ InstancePtr->IsStarted = (u32)0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear all of the prescaler control bits in the register.
+ */
+ ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
+
+ /*
+ * Set the prescaler value.
+ */
+ ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+ /*
+ * Write the register with the new values.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return The prescaler value.
+*
+* @note None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+ return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
new file mode 100644
index 0000000..5434684
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* Interrupts
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
new file mode 100644
index 0000000..c6bf324
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+ XPAR_PS7_SCUTIMER_0_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
new file mode 100644
index 0000000..d577784
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
new file mode 100644
index 0000000..b3464b6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
@@ -0,0 +1,135 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if self test was not successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+ u32 Register;
+ u32 CtrlOrig;
+ u32 LoadOrig;
+ s32 Status;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Save the contents of the Control Register and stop the timer.
+ */
+ CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Save the contents of the Load Register.
+ * Load a new test value in the Load Register, read it back and
+ * compare it with the written value.
+ */
+ LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+ XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+ Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+
+ /*
+ * Restore the contents of the Load Register and Control Register.
+ */
+ XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+ /*
+ * Return a Failure if the contents of the Load Register do not
+ * match with the value written to it.
+ */
+ if (Register != XSCUTIMER_SELFTEST_VALUE) {
+ Status = (s32)XST_FAILURE;
+ }
+ else {
+ Status = (s32)XST_SUCCESS;
+ }
+
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
new file mode 100644
index 0000000..0c5f671
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions ****************************/
+extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+ XScuTimer_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+ if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuTimer_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuTimer_Config *)CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
new file mode 100644
index 0000000..493ad9a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scuwdt_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling scuwdt"
+
+scuwdt_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scuwdt_includes
+
+scuwdt_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
new file mode 100644
index 0000000..85f0507
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
@@ -0,0 +1,213 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the XScuWdt driver.
+* See xscuwdt.h for a description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ConfigPtr is the config structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note This function enables the watchdog mode.
+*
+******************************************************************************/
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ s32 CfgStatus;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddress != 0x00U);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+ CfgStatus = (s32)XST_DEVICE_IS_STARTED;
+ }
+ else {
+ /*
+ * Copy configuration into instance.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+ InstancePtr->IsStarted = 0U;
+
+ /*
+ * Put the watchdog timer in Watchdog mode.
+ */
+ XScuWdt_SetWdMode(InstancePtr);
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ CfgStatus =(s32)XST_SUCCESS;
+ }
+ return CfgStatus;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog counter of the device.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note User needs to select the appropriate mode (watchdog/timer)
+* before using this API.
+* See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
+* xscuwdt.h.
+*
+******************************************************************************/
+void XScuWdt_Start(XScuWdt *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET);
+
+ /*
+ * Set the 'watchdog enable' bit in the register.
+ */
+ Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is started.
+ */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the watchdog timer.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuWdt_Stop(XScuWdt *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET);
+
+ /*
+ * Clear the 'watchdog enable' bit in the register.
+ */
+ Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUWDT_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is stopped.
+ */
+ InstancePtr->IsStarted = 0U;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
new file mode 100644
index 0000000..551eaf5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
@@ -0,0 +1,379 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_H /* prevent circular inclusions */
+#define XSCUWDT_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuWdt_Config Config;/**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_RST_STS_OFFSET) & \
+ XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_ISR_OFFSET) & \
+ XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr) \
+ XScuWdt_LoadWdt((InstancePtr), \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param Value is the value to be written to the Watchdog Load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET) | \
+ (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr) \
+{ \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE1); \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE2); \
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return Contents of the watchdog control register.
+*
+* @note C-style signature:
+ u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr) \
+ XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ControlReg is the value to be written to the watchdog control
+* register.
+*
+* @return None.
+*
+* @note C-style signature:
+ void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr) \
+ XScuWdt_SetControlReg((InstancePtr), \
+ (XScuWdt_GetControlReg(InstancePtr) | \
+ XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
new file mode 100644
index 0000000..b8f47a4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscuwdt.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SCUWDT_0_DEVICE_ID,
+ XPAR_PS7_SCUWDT_0_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
new file mode 100644
index 0000000..ad87a05
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
@@ -0,0 +1,178 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+* of 0x20 as the base address obtained from the tools
+* starts at 0x20.
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
+#define XSCUWDT_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
+ timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+ timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
+ value 1 */
+#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
+ value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
new file mode 100644
index 0000000..aa0cd39
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_selftest.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuWdt driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the WDT. This test stops the watchdog, writes a value to
+* the watchdog load register, starts the watchdog and verifies that the value
+* read from the counter register is less that the value written to the load
+* register. It then restores the control register and the watchdog load
+* register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if the WDT is not decrementing.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
+{
+ s32 SelfTestStatus;
+ u32 Register;
+ u32 CtrlOrig;
+ u32 LoadOrig;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Stop the watchdog timer.
+ */
+ CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
+ XScuWdt_SetControlReg(InstancePtr,
+ CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
+
+ LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUWDT_LOAD_OFFSET);
+ XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
+
+ /*
+ * Start the watchdog timer and check if the watchdog counter is
+ * decrementing.
+ */
+ XScuWdt_SetControlReg(InstancePtr,
+ CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+ Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUWDT_COUNTER_OFFSET);
+
+ XScuWdt_LoadWdt(InstancePtr, LoadOrig);
+ XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
+
+ if (Register == 0xFFFFFFFFU) {
+ SelfTestStatus = (s32)XST_FAILURE;
+ }
+ else {
+ SelfTestStatus = (s32)XST_SUCCESS;
+ }
+
+ return SelfTestStatus;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
new file mode 100644
index 0000000..e311a04
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscuwdt_sinit.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
+{
+ XScuWdt_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
+ if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuWdt_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuWdt_Config *)CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/Makefile
new file mode 100644
index 0000000..f57081a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps.c
new file mode 100644
index 0000000..d2ba055
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps.c
@@ -0,0 +1,1857 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v3_6
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 07/17/17 Add support for running SD at 200MHz
+* mn 07/26/17 Fixed compilation warnings
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
+* 3.4 mn 10/17/17 Use different commands for single and multi block
+* transfers
+* mn 03/02/18 Move UHS macro check to SD card initialization routine
+* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
+* 3.6 mn 07/06/18 Fix Cppcheck and Doxygen warnings for sdps driver
+* mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+* mn 08/01/18 Add cache invalidation call before returning from
+* ReadPolled API
+* mn 08/14/18 Resolve compilation warnings for ARMCC toolchain
+* mn 10/01/18 Change Expected Response for CMD3 to R1 for MMC
+ * 3.6 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN 0x1AAU
+#define XSDPS_RESPOCR_READY 0x80000000U
+#define XSDPS_ACMD41_HCS 0x40000000U
+#define XSDPS_ACMD41_3V3 0x00300000U
+#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
+#define HIGH_SPEED_SUPPORT 0x2U
+#define UHS_SDR50_SUPPORT 0x4U
+#define WIDTH_4_BIT_SUPPORT 0x4U
+#define SD_CLK_25_MHZ 25000000U
+#define SD_CLK_19_MHZ 19000000U
+#define SD_CLK_26_MHZ 26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE 196U
+#define EXT_CSD_SEC_COUNT_BYTE1 212U
+#define EXT_CSD_SEC_COUNT_BYTE2 213U
+#define EXT_CSD_SEC_COUNT_BYTE3 214U
+#define EXT_CSD_SEC_COUNT_BYTE4 215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
+#define CSD_SPEC_VER_3 0x3U
+#define SCR_SPEC_VER_3 0x80U
+#define ADDRESS_BEYOND_32BIT 0x100000000U
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+
+u16 TransferMode;
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ConfigPtr is a reference to a structure containing information
+* about a specific SD device. This function initializes an
+* InstancePtr object for a specific device specified by the
+* contents of Config.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, use
+* ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_DEVICE_IS_STARTED if the device is already started.
+* It must be stopped to re-initialize.
+*
+* @note This function initializes the host controller.
+* Initial clock of 400KHz is set.
+* Voltage of 3.3V is selected as that is supported by host.
+* Interrupts status is enabled and signal disabled by default.
+* Default data direction is card to host and
+* 32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status;
+ u8 PowerLevel;
+ u8 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /* Set some default values. */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
+ InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
+ InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+ InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+ InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+ InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
+ InstancePtr->SectorCount = 0;
+ InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+ InstancePtr->Config_TapDelay = NULL;
+ InstancePtr->Dma64BitAddr = 0U;
+
+ /* Disable bus power and issue emmc hw reset */
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+ XSDPS_HC_SPEC_V3)
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+ else
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET, 0x0);
+
+ /* Delay to poweroff card */
+ (void)usleep(1000U);
+
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_ALL_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+ /* Host Controller version is read. */
+ InstancePtr->HC_Version =
+ (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+ /*
+ * Read capabilities register and update it in Instance pointer.
+ * It is sufficient to read this once on power on.
+ */
+ InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_CAPS_OFFSET);
+
+ /* Select voltage and enable bus power. */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+ ~XSDPS_PC_EMMC_HW_RST_MASK);
+ else
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+ /* Delay before issuing the command after emmc reset */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+ XSDPS_CAPS_EMB_SLOT)
+ usleep(200);
+
+ /* Change the clock frequency to 400 KHz */
+ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH ;
+ }
+
+ if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+ } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+ } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+ PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+ } else {
+ PowerLevel = 0U;
+ }
+
+ /* Select voltage based on capability and enable bus power. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_POWER_CTRL_OFFSET,
+ PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ /* Enable ADMA2 in 64bit mode. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ XSDPS_HC_DMA_ADMA2_64_MASK);
+ } else {
+ /* Enable ADMA2 in 32bit mode. */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ XSDPS_HC_DMA_ADMA2_32_MASK);
+ }
+
+ /* Enable all interrupt status except card interrupt initially */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_EN_OFFSET,
+ XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_EN_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+
+ /* Disable all interrupt signals by default. */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+ /*
+ * Transfer mode register - default value
+ * DMA enabled, block count enabled, data direction card to host(read)
+ */
+ TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK;
+
+ /* Set block size to 512 by default */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) SD is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the
+ initialization cycle failed
+*
+* @note This function initializes the SD card by following its
+* initialization and identification state diagram.
+* CMD0 is sent to reset card.
+* CMD8 and ACDM41 are sent to identify voltage and
+* high capacity support
+* CMD2 and CMD3 are sent to obtain Card ID and
+* Relative card address respectively.
+* CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+ u32 PresentStateReg;
+ s32 Status;
+ u32 RespOCR;
+ u32 CSD[4];
+ u32 Arg;
+ u8 ReadReg;
+ u32 BlkLen, DeviceSize, Mult;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef UHS_MODE_ENABLE
+ InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
+#endif
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /*
+ * Check the present state register to make sure
+ * card is inserted and detected by host controller
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * CMD8; response expected
+ * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+ */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+ XSDPS_CMD8_VOL_PATTERN, 0U);
+ if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (Status == XSDPS_CT_ERROR) {
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_CMD_LINE_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+ }
+
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+ InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+ }
+ else {
+ InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+ }
+
+ RespOCR = 0U;
+ /* Send ACMD41 while card is still busy with power up */
+ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+ /*
+ * There is no support to switch to 1.8V and use UHS mode on
+ * 1.0 silicon
+ */
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ Arg |= XSDPS_OCR_S18;
+ }
+
+ /* 0x40300000 - Host High Capacity support & 3.3V window */
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+ Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Response with card capacity */
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ }
+
+ /* Update HCS support flag based on card capacity response */
+ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+ InstancePtr->HCS = 1U;
+ }
+
+ if ((RespOCR & XSDPS_OCR_S18) != 0U) {
+ InstancePtr->Switch1v8 = 1U;
+ Status = XSdPs_Switch_Voltage(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* CMD2 for Card ID */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->CardID[0] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ InstancePtr->CardID[1] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ InstancePtr->CardID[2] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ InstancePtr->CardID[3] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+ do {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Relative card address is stored as the upper 16 bits
+ * This is to avoid shifting when sending commands
+ */
+ InstancePtr->RelCardAddr =
+ XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+ } while (InstancePtr->RelCardAddr == 0U);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Card specific data is read.
+ * Currently not used for any operation.
+ */
+ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+ BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+ Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+ DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+ DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+ DeviceSize = (DeviceSize + 1U) * Mult;
+ DeviceSize = DeviceSize * BlkLen;
+ InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+ } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+ InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+ 1U) * 1024U;
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) SD is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the
+* initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ static u8 ExtCsd[512];
+ u8 SCR[8] = { 0U };
+#pragma data_alignment = 4
+#else
+ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+ static u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
+#endif
+ u8 ReadBuff[64] = { 0U };
+ s32 Status;
+ u32 Arg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Default settings */
+ InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+ InstancePtr->CardType = XSDPS_CARD_SD;
+ InstancePtr->Switch1v8 = 0U;
+ InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ == XSDPS_CAPS_EMB_SLOT)) {
+ InstancePtr->CardType = XSDPS_CHIP_EMMC;
+ } else {
+ Status = XSdPs_IdentifyCard(InstancePtr);
+ if (Status == XST_FAILURE) {
+ goto RETURN_PATH;
+ }
+ }
+
+ if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+ (InstancePtr->CardType != XSDPS_CARD_MMC) &&
+ (InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ Status = XSdPs_SdCardInitialize(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Change clock to default clock 25MHz */
+ /*
+ * SD default speed mode timing should be closed at 19 MHz.
+ * The reason for this is SD requires a voltage level shifter.
+ * This limitation applies to ZynqMPSoC.
+ */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+ else
+ InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ } else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+ || (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+ Status = XSdPs_MmcCardInitialize(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ /* Change clock to default clock 26MHz */
+ InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Select_Card(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ /* Pull-up disconnected during data transfer */
+ Status = XSdPs_Pullup(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Get speed supported by device */
+ Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+ if (Status != XST_SUCCESS) {
+ goto RETURN_PATH;
+ }
+
+ if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
+ (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ (XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+ (InstancePtr->Switch1v8 == 0U)) {
+ u16 CtrlReg, ClockReg;
+
+ /* Stop the clock */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ CtrlReg);
+
+ /* Enabling 1.8V in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+ CtrlReg);
+
+ /* Wait minimum 5mSec */
+ (void)usleep(5000U);
+
+ /* Check for 1.8V signal enable bit is cleared by Host */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ /* Wait for 1mSec */
+ (void)usleep(1000U);
+
+ InstancePtr->Switch1v8 = 1U;
+ }
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ if (InstancePtr->Switch1v8 != 0U) {
+
+ /* Identify the UHS mode supported by card */
+ XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
+ /* Set UHS-I SDR104 mode */
+ Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
+ if (Status != XST_SUCCESS) {
+ goto RETURN_PATH;
+ }
+
+ } else {
+#endif
+ /*
+ * card supports CMD6 when SD_SPEC field in SCR register
+ * indicates that the Physical Layer Specification Version
+ * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+ */
+ if (SCR[0] != 0U) {
+ /* Check for high speed support */
+ if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ }
+#endif
+
+ } else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+ (InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+ (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+ if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+ /* Change bus width to 8-bit */
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Get Extended CSD */
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+ InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+ /* Check for card supported speed */
+ if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+ EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+#endif
+ } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
+ EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_DDR52_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+#endif
+ } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+ EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+ (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+ InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+ } else
+ InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+
+ if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
+ Status = XSdPs_Change_BusSpeed(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
+ InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Status = XSdPs_Change_BusWidth(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+ }
+
+ /* Enable Rst_n_Fun bit if it is disabled */
+ if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+ Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+ Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+ if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
+ (InstancePtr->CardType == XSDPS_CARD_SD)) {
+ Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u8 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* 74 CLK delay after card is powered up, before the first command. */
+ usleep(XSDPS_INIT_DELAY);
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Host High Capacity support & High voltage window */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+ XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+ if (Status != XST_SUCCESS) {
+ InstancePtr->CardType = XSDPS_CARD_SD;
+ } else {
+ InstancePtr->CardType = XSDPS_CARD_MMC;
+ }
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+ /* "Software reset for all" is initiated */
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+ XSDPS_SWRST_CMD_LINE_MASK);
+
+ /* Proceed with initialization only after reset is complete */
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_SW_RST_OFFSET);
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u16 CtrlReg;
+ u32 ReadReg, ClockReg;
+
+ /* Send switch voltage command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ }
+
+ /* Wait for CMD and DATA line to go low */
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+ XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ }
+
+ /* Stop the clock */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ CtrlReg);
+
+ /* Enabling 1.8V in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+ CtrlReg);
+
+ /* Wait minimum 5mSec */
+ (void)usleep(5000U);
+
+ /* Check for 1.8V signal enable bit is cleared by Host */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ /* Wait for 1mSec */
+ (void)usleep(1000U);
+
+ /* Wait for CMD and DATA line to go high */
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+ != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ }
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cmd is the command to be sent.
+* @param Arg is the argument to be sent along with the command.
+* This could be address or any other information
+* @param BlkCnt - Block count passed by the user.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+ u32 PresentStateReg;
+ u32 CommandReg;
+ u32 StatusReg;
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Check the command inhibit to make sure no other
+ * command transfer is in progress
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Write block count register */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+ /* Write argument register */
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XSDPS_ARGMT_OFFSET, Arg);
+
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+ /* Command register is set to trigger transfer of command */
+ CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+ /*
+ * Mask to avoid writing to reserved bits 31-30
+ * This is necessary because 0x80000000 is used by this software to
+ * distinguish between ACMD and CMD of same number
+ */
+ CommandReg = CommandReg & 0x3FFFU;
+
+ /*
+ * Check for data inhibit in case of command using DAT lines.
+ * For Tuning Commands DAT lines check can be ignored.
+ */
+ if ((Cmd != CMD21) && (Cmd != CMD19)) {
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+ XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+ ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+ (CommandReg << 16) | TransferMode);
+
+ /* Polling for response for now */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((Cmd == CMD21) || (Cmd == CMD19)) {
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+ break;
+ }
+ }
+
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET);
+ if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
+ Status = XSDPS_CT_ERROR;
+ }
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET,
+ XSDPS_INTR_CC_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Cmd is the Command to be sent.
+*
+* @return Command register value complete with response type and
+* data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+ u32 RetVal;
+
+ RetVal = Cmd;
+
+ switch(Cmd) {
+ case CMD0:
+ RetVal |= RESP_NONE;
+ break;
+ case CMD1:
+ RetVal |= RESP_R3;
+ break;
+ case CMD2:
+ RetVal |= RESP_R2;
+ break;
+ case CMD3:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R6;
+ } else {
+ RetVal |= RESP_R1;
+ }
+ break;
+ case CMD4:
+ RetVal |= RESP_NONE;
+ break;
+ case CMD5:
+ RetVal |= RESP_R1B;
+ break;
+ case CMD6:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ } else {
+ RetVal |= RESP_R1B;
+ }
+ break;
+ case ACMD6:
+ RetVal |= RESP_R1;
+ break;
+ case CMD7:
+ RetVal |= RESP_R1;
+ break;
+ case CMD8:
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ RetVal |= RESP_R1;
+ } else {
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ }
+ break;
+ case CMD9:
+ RetVal |= RESP_R2;
+ break;
+ case CMD11:
+ case CMD10:
+ case CMD12:
+ case ACMD13:
+ case CMD16:
+ RetVal |= RESP_R1;
+ break;
+ case CMD17:
+ case CMD18:
+ case CMD19:
+ case CMD21:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case CMD23:
+ case ACMD23:
+ case CMD24:
+ case CMD25:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case ACMD41:
+ RetVal |= RESP_R3;
+ break;
+ case ACMD42:
+ RetVal |= RESP_R1;
+ break;
+ case ACMD51:
+ RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+ break;
+ case CMD52:
+ case CMD55:
+ RetVal |= RESP_R1;
+ break;
+ case CMD58:
+ break;
+ default :
+ RetVal |= Cmd;
+ break;
+ }
+
+ return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Arg is the address passed by the user that is to be sent as
+* argument along with the command.
+* @param BlkCnt - Block count passed by the user.
+* @param Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+ s32 Status;
+ u32 PresentStateReg;
+ u32 StatusReg;
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /* Check status to ensure card is initialized */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* Set block size to 512 if not already set */
+ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+ Status = XSdPs_SetBlkSize(InstancePtr,
+ XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
+ XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
+ } else {
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+ }
+
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send single block read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+ XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+ XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
+
+ /* Send multiple blocks read command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Check for transfer complete */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Arg is the address passed by the user that is to be sent as
+* argument along with the command.
+* @param BlkCnt - Block count passed by the user.
+* @param Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because another transfer
+* is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+ s32 Status;
+ u32 PresentStateReg;
+ u32 StatusReg;
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /* Check status to ensure card is initialized */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* Set block size to 512 if not already set */
+ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+ Status = XSdPs_SetBlkSize(InstancePtr,
+ XSDPS_BLK_SIZE_512_MASK);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ }
+
+ if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
+ XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
+ } else {
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)Buff,
+ BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+ }
+ }
+
+ if (BlkCnt == 1U) {
+ TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send single block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+ XSDPS_TM_BLK_CNT_EN_MASK |
+ XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send multiple blocks write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+ s32 Status;
+
+ /* Send CMD7 - Select card */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table for 64 Bit DMA
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param BlkCnt - block count.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt)
+{
+ u32 TotalDescLines;
+ u32 DescNum;
+ u32 BlkSize;
+
+ /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+ BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) &
+ XSDPS_BLK_SIZE_MASK;
+
+ if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+ TotalDescLines = 1U;
+
+ } else {
+
+ TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+ if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+ TotalDescLines += 1U;
+ }
+
+ }
+
+ for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+ InstancePtr->Adma2_DescrTbl[DescNum].Address =
+ InstancePtr->Dma64BitAddr +
+ (DescNum*XSDPS_DESC_MAX_LENGTH);
+ InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+ /* This will write '0' to length field which indicates 65536 */
+ InstancePtr->Adma2_DescrTbl[DescNum].Length =
+ (u16)XSDPS_DESC_MAX_LENGTH;
+ }
+
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+ InstancePtr->Dma64BitAddr +
+ (DescNum*XSDPS_DESC_MAX_LENGTH);
+
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+ (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+ (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+ sizeof(XSdPs_Adma2Descriptor) * 32U);
+ }
+
+ /* Clear the 64-Bit Address variable */
+ InstancePtr->Dma64BitAddr = 0U;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param BlkCnt - block count.
+* @param Buff pointer to data buffer.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+ u32 TotalDescLines;
+ u32 DescNum;
+ u32 BlkSize;
+
+ /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+ BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET) &
+ XSDPS_BLK_SIZE_MASK;
+
+ if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+ TotalDescLines = 1U;
+
+ }else {
+
+ TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+ if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+ TotalDescLines += 1U;
+ }
+
+ }
+
+ for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+#if defined(__aarch64__) || defined(__arch64__)
+ InstancePtr->Adma2_DescrTbl[DescNum].Address =
+ (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+ InstancePtr->Adma2_DescrTbl[DescNum].Address =
+ (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+ InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+ /* This will write '0' to length field which indicates 65536 */
+ InstancePtr->Adma2_DescrTbl[DescNum].Length =
+ (u16)XSDPS_DESC_MAX_LENGTH;
+ }
+
+#if defined(__aarch64__) || defined(__arch64__)
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+ (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+ (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+ XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+ InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+ (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+#if defined(__aarch64__) || defined(__arch64__)
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
+ (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
+#endif
+
+ XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+ (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+ sizeof(XSdPs_Adma2Descriptor) * 32U);
+ }
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+* - XST_FAILURE if failure - could be because
+* a) MMC is already initialized
+* b) There is no card inserted
+* c) One of the steps (commands) in the initialization
+* cycle failed
+* @note This function initializes the SD card by following its
+* initialization and identification state diagram.
+* CMD0 is sent to reset card.
+* CMD1 sent to identify voltage and high capacity support
+* CMD2 and CMD3 are sent to obtain Card ID and
+* Relative card address respectively.
+* CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+ u32 PresentStateReg;
+ s32 Status;
+ u32 RespOCR;
+ u32 CSD[4];
+ u32 BlkLen, DeviceSize, Mult;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+ ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+ != XSDPS_CAPS_EMB_SLOT)) {
+ if(InstancePtr->Config.CardDetect != 0U) {
+ /*
+ * Check the present state register to make sure
+ * card is inserted and detected by host controller
+ */
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+ if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ /* CMD0 no response expected */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ RespOCR = 0U;
+ /* Send CMD1 while card is still busy with power up */
+ while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+ /* Host High Capacity support & High volage window */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+ XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Response with card capacity */
+ RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+
+ }
+
+ /* Update HCS support flag based on card capacity response */
+ if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+ InstancePtr->HCS = 1U;
+ }
+
+ /* CMD2 for Card ID */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->CardID[0] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ InstancePtr->CardID[1] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ InstancePtr->CardID[2] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ InstancePtr->CardID[3] =
+ XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ /* Set relative card address */
+ InstancePtr->RelCardAddr = 0x12340000U;
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Card specific data is read.
+ * Currently not used for any operation.
+ */
+ CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP0_OFFSET);
+ CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP1_OFFSET);
+ CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP2_OFFSET);
+ CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_RESP3_OFFSET);
+
+ InstancePtr->Card_Version = (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
+
+ /* Calculating the memory capacity */
+ BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+ Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+ DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+ DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+ DeviceSize = (DeviceSize + 1U) * Mult;
+ DeviceSize = DeviceSize * BlkLen;
+
+ InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps.h
new file mode 100644
index 0000000..b81ec7c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps.h
@@ -0,0 +1,274 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_6
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+* CR#956899.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */
+#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u32 CardDetect; /**< Card Detect */
+ u32 WriteProtect; /**< Write Protect */
+ u32 BusWidth; /**< Bus Width */
+ u32 BankNumber; /**< MIO Bank selection for SD */
+ u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+ u64 Address; /**< Address of current dma transfer */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XSdPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 Host_Caps; /**< Capabilities of host controller */
+ u32 Host_CapsExt; /**< Extended Capabilities */
+ u32 HCS; /**< High capacity support in card */
+ u8 CardType; /**< Type of card - SD/MMC/eMMC */
+ u8 Card_Version; /**< Card version */
+ u8 HC_Version; /**< Host controller version */
+ u8 BusWidth; /**< Current operating bus width */
+ u32 BusSpeed; /**< Current operating bus speed */
+ u8 Switch1v8; /**< 1.8V Switch support */
+ u32 CardID[4]; /**< Card ID Register */
+ u32 RelCardAddr; /**< Relative Card Address */
+ u32 CardSpecData[4]; /**< Card Specific Data Register */
+ u32 SectorCount; /**< Sector Count */
+ u32 SdCardConfig; /**< Sd Card Configuration Register */
+ u32 Mode; /**< Bus Speed Mode */
+ XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
+ /**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+ u64 Dma64BitAddr; /**< 64 Bit DMA Address */
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_g.c
new file mode 100644
index 0000000..68cd76e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_g.c
@@ -0,0 +1,58 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_SD_0_DEVICE_ID,
+ XPAR_PS7_SD_0_BASEADDR,
+ XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
+ XPAR_PS7_SD_0_HAS_CD,
+ XPAR_PS7_SD_0_HAS_WP,
+ XPAR_PS7_SD_0_BUS_WIDTH,
+ XPAR_PS7_SD_0_MIO_BANK,
+ XPAR_PS7_SD_0_HAS_EMIO,
+ XPAR_PS7_SD_0_IS_CACHE_COHERENT
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_hw.h
new file mode 100644
index 0000000..901fa5c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_hw.h
@@ -0,0 +1,1298 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_6
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 12/10/15 Added support for MMC cards.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
+*
+*
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
+ Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
+ /**< SDMA System Address
+ Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
+ High Register */
+#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
+ /**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
+#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
+#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
+#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
+#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
+ Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
+ Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
+ Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
+ Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
+ Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
+ Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
+ Register */
+#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
+ Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
+ Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
+ Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
+ Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
+ Register */
+#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
+ Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
+ Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
+ register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
+ Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
+ Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
+ Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
+#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT 256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
+#define XSDPS_CC_EXT_DIV_SHIFT 6U
+
+#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK 0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV 9U
+#define XSDPS_CC_DIV_SHIFT 8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * Normal and Error Interrupt Status Register
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * Normal and Error Interrupt Status Enable Register
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * Normal and Error Interrupt Signal Enable Register
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
+ Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
+ Interrupt */
+#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
+ Error */
+#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
+ Error */
+#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
+ Error */
+#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024 0x400U
+#define XSDPS_BLK_SIZE_2048 0x800U
+#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
+ Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
+ Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
+ Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
+ Select */
+#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
+ check busy after
+ response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
+ Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
+ Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
+ Set to CMD0-63,
+ AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
+ Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
+ Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
+ Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
+ select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
+ MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
+ support */
+#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
+ support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
+ support */
+#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
+ support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
+ Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
+ tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
+ support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
+ for Programmable clock
+ mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
+ pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
+ Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
+ Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
+ Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
+ Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
+ Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
+ Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
+ Error */
+#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
+ STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
+ FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
+ TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
+ Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
+ Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
+ Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
+ mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_V3 0x0002U
+#define XSDPS_HC_SPEC_V2 0x0001U
+#define XSDPS_HC_SPEC_V1 0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK 0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX 0x8000U
+#define CMD0 0x0000U
+#define CMD1 0x0100U
+#define CMD2 0x0200U
+#define CMD3 0x0300U
+#define CMD4 0x0400U
+#define CMD5 0x0500U
+#define CMD6 0x0600U
+#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7 0x0700U
+#define CMD8 0x0800U
+#define CMD9 0x0900U
+#define CMD10 0x0A00U
+#define CMD11 0x0B00U
+#define CMD12 0x0C00U
+#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16 0x1000U
+#define CMD17 0x1100U
+#define CMD18 0x1200U
+#define CMD19 0x1300U
+#define CMD21 0x1500U
+#define CMD23 0x1700U
+#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24 0x1800U
+#define CMD25 0x1900U
+#define CMD41 0x2900U
+#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52 0x3400U
+#define CMD55 0x3700U
+#define CMD58 0x3A00U
+
+#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+ (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN 0xAAU
+#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
+#define XSDPS_CIC_VOLT_LOW (1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS (1U<<31)
+#define XSDPS_OCR_CC_STS (1U<<30)
+#define XSDPS_OCR_S18 (1U<<24)
+#define XSDPS_OCR_3V5_3V6 (1U<<23)
+#define XSDPS_OCR_3V4_3V5 (1U<<22)
+#define XSDPS_OCR_3V3_3V4 (1U<<21)
+#define XSDPS_OCR_3V2_3V3 (1U<<20)
+#define XSDPS_OCR_3V1_3V2 (1U<<19)
+#define XSDPS_OCR_3V0_3V1 (1U<<18)
+#define XSDPS_OCR_2V9_3V0 (1U<<17)
+#define XSDPS_OCR_2V8_2V9 (1U<<16)
+#define XSDPS_OCR_2V7_2V8 (1U<<15)
+#define XSDPS_OCR_1V7_1V95 (1U<<7)
+#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
+#define XSDPS_OCR_LOW_VOL 0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN 8U
+#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0 0U
+#define XSDPS_SCR_SPEC_1V1 (1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE 0U
+#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
+#define XSDPS_SCR_SPEC3_MASK (1U<<12)
+#define XSDPS_SCR_SPEC3_2V0 0U
+#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
+#define XSDPS_SCR_CMD23_SUPP (1U<<1)
+#define XSDPS_SCR_CMD20_SUPP (1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
+#define XSDPS_CD_STS_WP_VIO (1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
+#define XSDPS_CD_STS_CC_ERR (1U<<20)
+#define XSDPS_CD_STS_ERR (1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
+#define XSDPS_CD_STS_ER_RST (1U<<13)
+#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
+#define XSDPS_CD_STS_APP_CMD (1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN 64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK 0U
+
+#define XSDPS_MODE_FUNC_GRP1 1U
+#define XSDPS_MODE_FUNC_GRP2 2U
+#define XSDPS_MODE_FUNC_GRP3 3U
+#define XSDPS_MODE_FUNC_GRP4 4U
+#define XSDPS_MODE_FUNC_GRP5 5U
+#define XSDPS_MODE_FUNC_GRP6 6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12 0U
+#define XSDPS_ACC_MODE_HS_SDR25 1U
+#define XSDPS_ACC_MODE_SDR50 2U
+#define XSDPS_ACC_MODE_SDR104 3U
+#define XSDPS_ACC_MODE_DDR50 4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT 4U
+#define XSDPS_CMD_SYS_DEF 0U
+#define XSDPS_CMD_SYS_eC 1U
+#define XSDPS_CMD_SYS_OTP 3U
+#define XSDPS_CMD_SYS_ASSD 4U
+#define XSDPS_CMD_SYS_VEND 5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
+#define XSDPS_DRV_TYPE_B 0U
+#define XSDPS_DRV_TYPE_A 1U
+#define XSDPS_DRV_TYPE_C 2U
+#define XSDPS_DRV_TYPE_D 3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT 12U
+#define XSDPS_CUR_LIM_200 0U
+#define XSDPS_CUR_LIM_400 1U
+#define XSDPS_CUR_LIM_600 2U
+#define XSDPS_CUR_LIM_800 3U
+
+#define CSD_SPEC_VER_MASK 0x3C0000U
+#define READ_BLK_LEN_MASK 0x00000F00U
+#define C_SIZE_MULT_MASK 0x00000380U
+#define C_SIZE_LOWER_MASK 0xFFC00000U
+#define C_SIZE_UPPER_MASK 0x00000003U
+#define CSD_STRUCT_MASK 0x00C00000U
+#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE 512U
+
+#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
+ /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
+ /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE 183U
+#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE 185U
+#define EXT_CSD_HS_TIMING_DEF 0U
+#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE 162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET 0U
+#define XSDPS_EXT_CSD_SET_BITS 1U
+#define XSDPS_EXT_CSD_CLR_BITS 2U
+#define XSDPS_EXT_CSD_WRITE_BYTE 3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+ | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY 2960U
+#define XSDPS_100CLK_DELAY 4000U
+#define XSDPS_INIT_DELAY 10000U
+
+#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR 0x1234U
+
+#define XSDPS_CARD_SD 1U
+#define XSDPS_CARD_MMC 2U
+#define XSDPS_CARD_SDIO 3U
+#define XSDPS_CARD_SDCOMBO 4U
+#define XSDPS_CHIP_EMMC 5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID (0x1U << 0)
+#define XSDPS_DESC_END (0x1U << 1)
+#define XSDPS_DESC_INT (0x1U << 2)
+#define XSDPS_DESC_TRAN (0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
+#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
+#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT 1U
+#define XSDPS_SCR_BLKSIZE 8U
+#define XSDPS_1_BIT_WIDTH 0x1U
+#define XSDPS_4_BIT_WIDTH 0x2U
+#define XSDPS_8_BIT_WIDTH 0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
+#define XSDPS_HIGH_SPEED_MODE 0x5U
+#define XSDPS_DEFAULT_SPEED_MODE 0x6U
+#define XSDPS_HS200_MODE 0x7U
+#define XSDPS_DDR52_MODE 0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT 1U
+#define XSDPS_SWITCH_CMD_BLKSIZE 64U
+#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
+#define XSDPS_TUNING_CMD_BLKCNT 1U
+#define XSDPS_TUNING_CMD_BLKSIZE 64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
+
+#define SD_DRIVER_TYPE_B 0x01U
+#define SD_DRIVER_TYPE_A 0x02U
+#define SD_DRIVER_TYPE_C 0x04U
+#define SD_DRIVER_TYPE_D 0x08U
+#define SD_SET_CURRENT_LIMIT_200 0U
+#define SD_SET_CURRENT_LIMIT_400 1U
+#define SD_SET_CURRENT_LIMIT_600 2U
+#define SD_SET_CURRENT_LIMIT_800 3U
+
+#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK 25000000U
+#define XSDPS_SD_SDR25_MAX_CLK 50000000U
+#define XSDPS_SD_SDR50_MAX_CLK 100000000U
+#define XSDPS_SD_DDR50_MAX_CLK 50000000U
+#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK 200000000U
+#define XSDPS_MMC_HSD_MAX_CLK 52000000U
+#define XSDPS_MMC_DDR_MAX_CLK 52000000U
+
+#define XSDPS_CARD_STATE_IDLE 0U
+#define XSDPS_CARD_STATE_RDY 1U
+#define XSDPS_CARD_STATE_IDEN 2U
+#define XSDPS_CARD_STATE_STBY 3U
+#define XSDPS_CARD_STATE_TRAN 4U
+#define XSDPS_CARD_STATE_DATA 5U
+#define XSDPS_CARD_STATE_RCV 6U
+#define XSDPS_CARD_STATE_PROG 7U
+#define XSDPS_CARD_STATE_DIS 8U
+#define XSDPS_CARD_STATE_BTST 9U
+#define XSDPS_CARD_STATE_SLP 10U
+
+#define XSDPS_SLOT_REM 0U
+#define XSDPS_SLOT_EMB 1U
+
+#define XSDPS_WIDTH_8 8U
+#define XSDPS_WIDTH_4 4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
+#define SD_DLL_CTRL 0x00000358U
+#define SD_ITAPDLY 0x00000314U
+#define SD_OTAPDLY 0x00000318U
+#define SD0_DLL_RST 0x00000004U
+#define SD1_DLL_RST 0x00040000U
+#define SD0_ITAPCHGWIN 0x00000200U
+#define SD0_ITAPDLYENA 0x00000100U
+#define SD0_OTAPDLYENA 0x00000040U
+#define SD1_ITAPCHGWIN 0x02000000U
+#define SD1_ITAPDLYENA 0x01000000U
+#define SD1_OTAPDLYENA 0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD0_ITAPDLYSEL_SD50 0x00000014U
+#define SD0_OTAPDLYSEL_SD50 0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
+#define SD0_ITAPDLYSEL_HSD 0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
+#define SD1_ITAPDLYSEL_SD50 0x00140000U
+#define SD1_OTAPDLYSEL_SD50 0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
+#define SD1_ITAPDLYSEL_HSD 0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+ XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+* u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+ (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+ XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+ XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_options.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_options.c
new file mode 100644
index 0000000..420bded
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_options.c
@@ -0,0 +1,1735 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v3_6
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* vns 03/13/17 Fixed MISRAC mandatory violation
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
+* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit
+* settings
+* mn 08/17/17 Added CCI support for A53 and disabled data cache
+* operations when it is enabled.
+* mn 08/22/17 Updated for Word Access System support
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6 mn 07/06/18 Fix Cppcheck warnings for sdps driver
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+#if defined (__aarch64__)
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+#define UHS_SDR12_SUPPORT 0x1U
+#define UHS_SDR25_SUPPORT 0x2U
+#define UHS_SDR50_SUPPORT 0x4U
+#define UHS_SDR104_SUPPORT 0x8U
+#define UHS_DDR50_SUPPORT 0x10U
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+static void XSdPs_DllReset(XSdPs *InstancePtr);
+#endif
+
+extern u16 TransferMode;
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param BlkSize - Block size passed by the user.
+*
+* @return None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+ s32 Status;
+ u32 PresentStateReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XSDPS_PRES_STATE_OFFSET);
+
+ if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+ (u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+ (u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+
+ /* Send block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Set block size to the value passed */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize & XSDPS_BLK_SIZE_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param SCR - buffer to store SCR register returned by card.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+ s32 Status;
+ u32 StatusReg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+ SCR[LoopCnt] = 0U;
+ }
+
+ /* Send block write command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ BlkCnt = XSDPS_SCR_BLKCNT;
+ BlkSize = XSDPS_SCR_BLKSIZE;
+
+ /* Set block size to the value passed */
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * check for bus width for 3.0 controller and return if
+ * bus width is <4
+ */
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+ (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
+ Status = XST_SUCCESS;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+ 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+ Arg = ((u32)InstancePtr->BusWidth);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+
+ if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+ && (InstancePtr->CardType == XSDPS_CHIP_EMMC) &&
+ (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+ /* in case of eMMC data width 8-bit */
+ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+ } else {
+ InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+ }
+
+ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+ Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+ else
+ Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+ } else {
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+ Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+ else
+ Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Check for transfer complete */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+ }
+
+ usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+ StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET);
+
+ /* Width setting in controller */
+ if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+ StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+ } else {
+ StatusReg |= XSDPS_HC_WIDTH_MASK;
+ }
+
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET,
+ (u8)StatusReg);
+
+ if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+ StatusReg |= InstancePtr->Mode;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, StatusReg);
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff - buffer to store function group support data
+* returned by card.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+ ReadBuff[LoopCnt] = 0U;
+ }
+
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ u8 ReadBuff[64] = {0U};
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ /* Change the clock frequency to 50 MHz */
+ InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ } else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /*
+ * Write to clear bit
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ /* Change the clock frequency to 52 MHz */
+ InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ Arg = XSDPS_MMC_HS200_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+ } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
+ } else {
+ Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+ InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /*
+ * Write to clear bit
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+ Status = XSdPs_Execute_Tuning(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+ }
+
+ usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+ StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET);
+ StatusReg |= XSDPS_HC_SPEED_MASK;
+ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param SelFreq - Clock frequency in Hz.
+*
+* @return None
+*
+* @note This API will change clock frequency to the value less than
+* or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+ u16 ClockReg;
+ u16 DivCnt;
+ u16 Divisor = 0U;
+ u16 ExtDivisor;
+ s32 Status;
+ u16 ReadReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+ (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
+ /* Program the Tap delays */
+ XSdPs_SetTapDelay(InstancePtr);
+#endif
+ /* Calculate divisor */
+ for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+ if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+ Divisor = DivCnt >> 1;
+ break;
+ }
+ }
+
+ if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+ /* No valid divisor found for given frequency */
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } else {
+ /* Calculate divisor */
+ DivCnt = 0x1U;
+ while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+ if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+ Divisor = DivCnt / 2U;
+ break;
+ }
+ DivCnt = DivCnt << 1U;
+ }
+
+ if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+ /* No valid divisor found for given frequency */
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ /* Set clock divisor */
+ if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+ XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+ ExtDivisor = Divisor >> 8;
+ ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+ ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+ Divisor <<= XSDPS_CC_DIV_SHIFT;
+ Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+ ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ ClockReg);
+ } else {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+ Divisor <<= XSDPS_CC_DIV_SHIFT;
+ Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+ ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+ ClockReg);
+ }
+
+ /* Wait for internal clock to stabilize */
+ ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);;
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+ Status = XST_SUCCESS;
+
+RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+ s32 Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+ InstancePtr->RelCardAddr, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff - buffer to store EXT_CSD
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+ s32 Status;
+ u32 StatusReg;
+ u32 Arg = 0U;
+ u16 BlkCnt;
+ u16 BlkSize;
+ s32 LoopCnt;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+ ReadBuff[LoopCnt] = 0U;
+ }
+
+ BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+ BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ /* Send SEND_EXT_CSD command */
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param Arg is the argument to be sent along with the command
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+ s32 Status;
+ u32 StatusReg;
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /*
+ * Write to clear error bits
+ */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET,
+ XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param ReadBuff contains the response for CMD6
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+ InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+ }
+ else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+ InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
+ }
+ else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+ InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+ }
+ else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+ (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+ InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+ }
+ else
+ InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+}
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+* @param Mode UHS-I mode
+*
+* @return
+* - XST_SUCCESS if successful.
+* - XST_FAILURE if fail.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+ s32 Status;
+ u16 StatusReg;
+ u16 CtrlReg;
+ u32 Arg;
+ u16 BlkCnt;
+ u16 BlkSize;
+ u8 ReadBuff[64] = {0U};
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Drive strength */
+
+ /* Bus speed mode selection */
+ BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+ BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize);
+
+ XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+ }
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+ switch (Mode) {
+ case 0U:
+ Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+ break;
+ case 1U:
+ Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+ break;
+ case 2U:
+ Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+ break;
+ case 3U:
+ Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+ break;
+ case 4U:
+ Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+ InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+ break;
+ default:
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ break;
+ }
+
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /*
+ * Check for transfer complete
+ * Polling for response for now
+ */
+ do {
+ StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET);
+ if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+ /* Write to clear error bits */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+ /* Write to clear bit */
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+ /* Current limit */
+
+ /* Set UHS mode in controller */
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+ CtrlReg |= Mode;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+ /* Change the clock frequency */
+ Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+ (Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+ /* Send tuning pattern */
+ Status = XSdPs_Execute_Tuning(InstancePtr);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+ }
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH:
+ return Status;
+}
+#endif
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+ s32 Status;
+ u16 BlkSize;
+ u16 CtrlReg;
+ u8 TuningCount;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+ if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+ {
+ BlkSize = BlkSize*2U;
+ }
+ BlkSize &= XSDPS_BLK_SIZE_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+ BlkSize);
+
+ TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK;
+
+ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET);
+ CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+ /*
+ * workaround which can work for 1.0/2.0 silicon for auto tuning.
+ * This can be revisited for 3.0 silicon if necessary.
+ */
+ /* Wait for ~60 clock cycles to reset the tap values */
+ (void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+
+ for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+ if (InstancePtr->CardType == XSDPS_CARD_SD) {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+ } else {
+ Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+ }
+
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+ break;
+ }
+
+ if (TuningCount == 31) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+ }
+ }
+
+ if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+ Status = XST_FAILURE;
+ goto RETURN_PATH;
+ }
+
+ /* Wait for ~12 clock cycles to synchronize the new tap values */
+ (void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+ /* Issue DLL Reset to load new SDHC tuned tap values */
+ XSdPs_DllReset(InstancePtr);
+#endif
+
+ Status = XST_SUCCESS;
+
+ RETURN_PATH: return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR104 and HS200 modes
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ if (Bank == 2)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ if (Bank == 2)
+ TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
+ else
+ TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ if (Bank == 2)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ if (Bank == 2)
+ TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
+ else
+ TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR50 mode
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) Bank;
+ (void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+ ((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50,
+ 0, 0, 0, 0, 0);
+#else
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ TapDelay |= SD0_OTAPDLYSEL_SD50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+ ((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50,
+ 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ TapDelay |= SD1_OTAPDLYSEL_SD50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for DDR50 mode
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ if (CardType== XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+ (u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+ (u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD0_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ if (CardType== XSDPS_CARD_SD)
+ TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ if (CardType== XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+ (u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+ (u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD1_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
+ else
+ TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for HSD and SDR25 mode
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+ u32 TapDelay;
+ (void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+ (u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD0_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay |= SD0_ITAPDLYSEL_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD0_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
+ else
+ TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+ } else {
+#endif
+ (void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)TapDelay;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD,
+ 0, 0, 0, 0, 0);
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+ ((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+ if (CardType == XSDPS_CARD_SD)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+ else
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+ (u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+ TapDelay |= SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the ITAPDLY */
+ TapDelay |= SD1_ITAPDLYENA;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay |= SD1_ITAPDLYSEL_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ TapDelay &= ~SD1_ITAPCHGWIN;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+ /* Program the OTAPDLY */
+ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+ TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+ if (CardType == XSDPS_CARD_SD)
+ TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
+ else
+ TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+ u32 DllCtrl, BankNum, DeviceId, CardType;
+
+ BankNum = InstancePtr->Config.BankNumber;
+ DeviceId = InstancePtr->Config.DeviceId ;
+ CardType = InstancePtr->CardType ;
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ DllCtrl |= SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ } else {
+#endif
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ DllCtrl |= SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+ }
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param InstancePtr is a pointer to the XSdPs instance.
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+ u32 ClockReg, DllCtrl;
+
+ /* Disable clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+ /* Issue DLL Reset to load zero tap values */
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl |= SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ } else {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+ DllCtrl |= SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ }
+
+ /* Wait for 2 micro seconds */
+ (void)usleep(2U);
+
+ /* Release the DLL out of reset */
+ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+ if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD0_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ } else {
+#if EL1_NONSECURE && defined (__aarch64__)
+ (void)DllCtrl;
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+ SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+ (u64)0x0, 0, 0, 0, 0, 0);
+#else
+ DllCtrl &= ~SD1_DLL_RST;
+ XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+ }
+
+ /* Wait for internal clock to stabilize */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ }
+
+ /* Enable SD clock */
+ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET);
+ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+ XSDPS_CLK_CTRL_OFFSET,
+ ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+}
+#endif
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_sinit.c
new file mode 100644
index 0000000..349ecae
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6/src/xsdps_sinit.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v3_6
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device to look up the
+* configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+ XSdPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+ if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XSdPs_ConfigTable[Index];
+ break;
+ }
+ }
+ return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/Makefile
new file mode 100644
index 0000000..9711412
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/Makefile
@@ -0,0 +1,83 @@
+###############################################################################
+#
+# Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+include config.make
+
+CC=$(COMPILER)
+AR=$(ARCHIVER)
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc)
+ECC_FLAGS += -nostartfiles\
+ -march=armv7-a \
+ -mfloat-abi=soft \
+ -mfpu=neon
+endif
+
+ifeq (($(notdir $(CC))) , arm-none-eabi-gcc)
+ECC_FLAGS += -nostartfiles
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S)))
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+ echo "Compiling standalone"
+ $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+ $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+profile_libs:
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs
+
+.PHONY: include
+include: standalone_includes profile_includes
+
+standalone_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+profile_includes:
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include
+
+clean:
+ rm -rf ${OBJECTS}
+ rm -rf ${ASSEMBLY_OBJECTS}
+ $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_exit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_exit.c
new file mode 100644
index 0000000..87271ae
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_exit.c
@@ -0,0 +1,40 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+ (void)status;
+ while (1) {
+ ;
+ }
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_open.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_open.c
new file mode 100644
index 0000000..4ef7441
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_open.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ * we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+ (void)buf;
+ (void)flags;
+ (void)mode;
+ errno = EIO;
+ return (-1);
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_sbrk.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_sbrk.c
new file mode 100644
index 0000000..6d8af62
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/_sbrk.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+ static u8 *heap = NULL;
+ u8 *prev_heap;
+ static u8 *HeapEndPtr = (u8 *)&_heap_end;
+ caddr_t Status;
+
+ if (heap == NULL) {
+ heap = (u8 *)&_heap_start;
+ }
+ prev_heap = heap;
+
+ if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
+ heap += incr;
+ Status = (caddr_t) ((void *)prev_heap);
+ } else {
+ Status = (caddr_t) -1;
+ }
+
+ return Status;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/abort.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/abort.c
new file mode 100644
index 0000000..78d3839
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/abort.c
@@ -0,0 +1,38 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+ _exit(1);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/asm_vectors.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/asm_vectors.S
new file mode 100644
index 0000000..4fbfa2d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/asm_vectors.S
@@ -0,0 +1,199 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex A9 processor
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm 02/02/12 Save lr when profiling is enabled
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 4.00a pkp 22/01/14 Modified return addresses for interrupt
+* handlers (DataAbortHandler and SVCHandler)
+* to fix CR#767251
+* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
+* abort and prefetch abort into DataAbortAddr and
+* PrefetchAbortAddr for further use to fix CR#854523
+* 5.4 pkp 12/03/15 Added handler for undefined exception
+* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now,
+* saving/restoring of of HW floating point register
+* would be done through newly introduced flag
+* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
+* configured based on the -mfpu-abi option in extra
+* compiler flags.
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "xil_errata.h"
+#include "bspconfig.h"
+
+.org 0
+.text
+
+.globl _vector_table
+
+.section .vectors
+_vector_table:
+ B _boot
+ B Undefined
+ B SVCHandler
+ B PrefetchAbortHandler
+ B DataAbortHandler
+ NOP /* Placeholder for address exception vector*/
+ B IRQHandler
+ B FIQHandler
+
+
+IRQHandler: /* IRQ vector handler */
+
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ vpush {d0-d7}
+ vpush {d16-d31}
+ vmrs r1, FPSCR
+ push {r1}
+ vmrs r1, FPEXC
+ push {r1}
+#endif
+
+#ifdef PROFILING
+ ldr r2, =prof_pc
+ subs r3, lr, #0
+ str r3, [r2]
+#endif
+
+ bl IRQInterrupt /* IRQ vector */
+
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ pop {r1}
+ vmsr FPEXC, r1
+ pop {r1}
+ vmsr FPSCR, r1
+ vpop {d16-d31}
+ vpop {d0-d7}
+#endif
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+
+ subs pc, lr, #4 /* adjust return */
+
+
+FIQHandler: /* FIQ vector handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ vpush {d0-d7}
+ vpush {d16-d31}
+ vmrs r1, FPSCR
+ push {r1}
+ vmrs r1, FPEXC
+ push {r1}
+#endif
+
+FIQLoop:
+ bl FIQInterrupt /* FIQ vector */
+
+#if FPU_HARD_FLOAT_ABI_ENABLED
+ pop {r1}
+ vmsr FPEXC, r1
+ pop {r1}
+ vmsr FPSCR, r1
+ vpop {d16-d31}
+ vpop {d0-d7}
+#endif
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ subs pc, lr, #4 /* adjust return */
+
+
+Undefined: /* Undefined handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ ldr r0, =UndefinedExceptionAddr
+ sub r1, lr, #4
+ str r1, [r0] /* Store address of instruction causing undefined exception */
+
+ bl UndefinedException /* UndefinedException: call C function here */
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+ movs pc, lr
+
+SVCHandler: /* SWI handler */
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+
+ tst r0, #0x20 /* check the T bit */
+ ldrneh r0, [lr,#-2] /* Thumb mode */
+ bicne r0, r0, #0xff00 /* Thumb mode */
+ ldreq r0, [lr,#-4] /* ARM mode */
+ biceq r0, r0, #0xff000000 /* ARM mode */
+
+ bl SWInterrupt /* SWInterrupt: call C function here */
+
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+ movs pc, lr /*return to the next instruction after the SWI instruction */
+
+
+DataAbortHandler: /* Data Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+ dsb
+#endif
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ ldr r0, =DataAbortAddr
+ sub r1, lr, #8
+ str r1, [r0] /* Stores instruction causing data abort */
+
+ bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
+
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+ subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
+
+PrefetchAbortHandler: /* Prefetch Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+ dsb
+#endif
+ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
+ ldr r0, =PrefetchAbortAddr
+ sub r1, lr, #4
+ str r1, [r0] /* Stores instruction causing prefetch abort */
+
+ bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
+
+ ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
+
+ subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
+
+.end
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/boot.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/boot.S
new file mode 100644
index 0000000..c8ebfd1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/boot.S
@@ -0,0 +1,492 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
+* @{
+*
boot.S
+* The boot code performs minimum configuration which is required for an
+* application to run starting from processor's reset state. Below is a
+* sequence illustrating what all configuration is performed before control
+* reaches to main function.
+*
+* 1. Program vector table base for exception handling
+* 2. Invalidate instruction cache, data cache and TLBs
+* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
+* abort, system)
+* 4. Configure MMU with short descriptor translation table format and program
+* base address of translation table
+* 5. Enable data cache, instruction cache and MMU
+* 6. Enable Floating point unit
+* 7. Transfer control to _start which clears BSS sections, initializes
+* global timer and runs global constructor before jumping to main
+* application
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+* register settings.
+* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+* register settings.
+* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
+* performance. Changed the property of the ".boot"
+* section.
+* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
+* Register settings
+* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
+* value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
+* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
+* MMU is enabled
+* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
+* caches and TLB, enable MMU and caches, then enable SMP
+* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+* is done later.
+* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
+* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
+* attempt to enable dual core behavior on single cpu zynq-7000s
+* devices is prevented from corrupting system behavior.
+* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
+* zynq-7000s devices
+*
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_errata.h"
+
+.globl MMUTable
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+.set PSS_L2CC_BASE_ADDR, 0xF8F02000
+.set PSS_SLCR_BASE_ADDR, 0xF8000000
+
+.set RESERVED, 0x0fffff00
+.set TblBase , MMUTable
+.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
+.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
+.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
+.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
+.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
+.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
+.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
+.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
+.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
+
+.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
+.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
+.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
+.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
+.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
+
+/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
+.if SIM_MODE == 1
+.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
+.else
+.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
+.endif
+
+.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
+
+.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
+ Event monitor bus enable and Way Size (64 KB) */
+.set L2CCControl, 0x01 /* Enable L2CC */
+.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
+.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
+
+.set SLCRlockKey, 0x767B /* SLCR lock key */
+.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
+.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack, __undef_stack
+.set FIQ_stack, __fiq_stack
+.set Abort_stack, __abort_stack
+.set SPV_stack, __supervisor_stack
+.set IRQ_stack, __irq_stack
+.set SYS_stack, __stack
+
+.set vector_base, _vector_table
+
+.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+#if XPAR_CPU_ID==0
+ /* only allow cpu0 through */
+ mrc p15,0,r1,c0,c0,5
+ and r1, r1, #0xf
+ cmp r1, #0
+ beq CheckEFUSE
+ EndlessLoop0:
+ wfe
+ b EndlessLoop0
+
+CheckEFUSE:
+ ldr r0,=EFUSEStaus
+ ldr r1,[r0] /* Read eFuse setting */
+ ands r1,r1,#0x80 /* Check whether device is having single core */
+ beq OKToRun
+
+ /* single core device, reset cpu1 */
+ ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
+ ldr r1,=SLCRUnlockKey /* set unlock key */
+ str r1, [r0] /* Unlock SLCR */
+
+ ldr r0,=SLCRCPURSTReg
+ ldr r1,[r0] /* Read CPU Software Reset Control register */
+ orr r1,r1,#0x22
+ str r1,[r0] /* Reset CPU1 */
+
+ ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
+ ldr r1,=SLCRlockKey /* set lock key */
+ str r1, [r0] /* lock SLCR */
+
+#elif XPAR_CPU_ID==1
+ /* only allow cpu1 through */
+ mrc p15,0,r1,c0,c0,5
+ and r1, r1, #0xf
+ cmp r1, #1
+ beq CheckEFUSE1
+ b EndlessLoop1
+
+CheckEFUSE1:
+ ldr r0,=EFUSEStaus
+ ldr r1,[r0] /* Read eFuse setting */
+ ands r1,r1,#0x80 /* Check whether device is having single core */
+ beq OKToRun
+ EndlessLoop1:
+ wfe
+ b EndlessLoop1
+#endif
+
+OKToRun:
+ mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
+ and r5, r0, #0x00f00000
+ and r6, r0, #0x0000000f
+ orr r6, r6, r5, lsr #20-4
+
+#ifdef CONFIG_ARM_ERRATA_742230
+ cmp r6, #0x22 /* only present up to r2p2 */
+ mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
+ orrle r10, r10, #1 << 4 /* set bit #4 */
+ mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+ teq r5, #0x00200000 /* only present in r2p* */
+ mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
+ orreq r10, r10, #1 << 6 /* set bit #6 */
+ mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
+#endif
+
+ /* set VBAR to the _vector_table address in linker script */
+ ldr r0, =vector_base
+ mcr p15, 0, r0, c12, c0, 0
+
+ /*invalidate scu*/
+ ldr r7, =0xf8f0000c
+ ldr r6, =0xffff
+ str r6, [r7]
+
+ /* Invalidate caches and TLBs */
+ mov r0,#0 /* r0 = 0 */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
+ mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
+ bl invalidate_dcache /* invalidate dcache */
+
+ /* Disable MMU, if enabled */
+ mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
+ bic r0, r0, #0x1 /* clear bit 0 */
+ mcr p15, 0, r0, c1, c0, 0 /* write value back */
+
+#ifdef SHAREABLE_DDR
+ /* Mark the entire DDR memory as shareable */
+ ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
+ ldr r0, =TblBase /* MMU Table address in memory */
+ ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+shareable_loop:
+ str r2, [r0] /* write the entry to MMU table */
+ add r0, r0, #0x4 /* next entry in the table */
+ add r2, r2, #0x100000 /* next section */
+ subs r3, r3, #1
+ bge shareable_loop /* loop till 1G is covered */
+#endif
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the irq stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x12 /* IRQ mode */
+ msr cpsr, r2
+ ldr r13,=IRQ_stack /* IRQ stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the supervisor stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x13 /* supervisor mode */
+ msr cpsr, r2
+ ldr r13,=SPV_stack /* Supervisor stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the Abort stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x17 /* Abort mode */
+ msr cpsr, r2
+ ldr r13,=Abort_stack /* Abort stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the FIQ stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x11 /* FIQ mode */
+ msr cpsr, r2
+ ldr r13,=FIQ_stack /* FIQ stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the Undefine stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x1b /* Undefine mode */
+ msr cpsr, r2
+ ldr r13,=Undef_stack /* Undefine stack pointer */
+ bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
+ msr spsr_fsxc,r2
+
+ mrs r0, cpsr /* get the current PSR */
+ mvn r1, #0x1f /* set up the system stack pointer */
+ and r2, r1, r0
+ orr r2, r2, #0x1F /* SYS mode */
+ msr cpsr, r2
+ ldr r13,=SYS_stack /* SYS stack pointer */
+
+ /*set scu enable bit in scu*/
+ ldr r7, =0xf8f00000
+ ldr r0, [r7]
+ orr r0, r0, #0x1
+ str r0, [r7]
+
+ /* enable MMU and cache */
+
+ ldr r0,=TblBase /* Load MMU translation table base */
+ orr r0, r0, #0x5B /* Outer-cacheable, WB */
+ mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
+
+ mvn r0,#0 /* Load MMU domains -- all ones=manager */
+ mcr p15,0,r0,c3,c0,0
+
+ /* Enable mmu, icahce and dcache */
+ ldr r0,=CRValMmuCac
+ mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
+ dsb /* dsb allow the MMU to start up */
+ isb /* isb flush prefetch buffer */
+
+ /* Write to ACTLR */
+ mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
+ orr r0, r0, #(0x01 << 6) /* set SMP bit */
+ orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
+ mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
+
+/* Invalidate L2 Cache and enable L2 Cache*/
+/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
+#if USE_AMP!=1
+ ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
+ mov r1, #0 /* force the disable bit */
+ str r1, [r0] /* disable the L2 Caches */
+
+ ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
+ ldr r1,[r0] /* read the register */
+ ldr r2,=L2CCAuxControl /* set the default bits */
+ orr r1,r1,r2
+ str r1, [r0] /* store the Aux Control Register */
+
+ ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
+ ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
+ str r1, [r0] /* store the TAG Latency register Register */
+
+ ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
+ ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
+ str r1, [r0] /* store the Data Latency register Register */
+
+ ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
+ ldr r2, =0xFFFF
+ str r2, [r0] /* force invalidate */
+
+ ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
+ /* Load L2CC base address base + sync register*/
+ /* poll for completion */
+Sync: ldr r1, [r0]
+ cmp r1, #0
+ bne Sync
+
+ ldr r0,=L2CCIntRaw /* clear pending interrupts */
+ ldr r1,[r0]
+ ldr r0,=L2CCIntClear
+ str r1,[r0]
+
+ ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
+ ldr r1,=SLCRUnlockKey /* set unlock key */
+ str r1, [r0] /* Unlock SLCR */
+
+ ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
+ ldr r1,=SLCRL2cRamConfig /* set the configuration value */
+ str r1, [r0] /* store the L2c Ram Control Register */
+
+ ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
+ ldr r1,=SLCRlockKey /* set lock key */
+ str r1, [r0] /* lock SLCR */
+
+ ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
+ ldr r1,[r0] /* read the register */
+ mov r2, #L2CCControl /* set the enable bit */
+ orr r1,r1,r2
+ str r1, [r0] /* enable the L2 Caches */
+#endif
+
+ mov r0, r0
+ mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
+ orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
+ mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
+
+ /* enable vfp */
+ fmrx r1, FPEXC /* read the exception register */
+ orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
+ fmxr FPEXC, r1 /* write back the exception register */
+
+ mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
+ orr r0, r0, #(0x01 << 11) /* #0x8000 */
+ mcr p15,0,r0,c1,c0,0
+
+ mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
+ orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
+ orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
+ mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
+
+ mrs r0, cpsr /* get the current PSR */
+ bic r0, r0, #0x100 /* enable asynchronous abort exception */
+ msr cpsr_xsf, r0
+
+
+ b _start /* jump to C startup code */
+ and r0, r0, r0 /* no op */
+
+.Ldone: b .Ldone /* Paranoia: we should never get here */
+
+
+/*
+ *************************************************************************
+ *
+ * invalidate_dcache - invalidate the entire d-cache by set/way
+ *
+ * Note: for Cortex-A9, there is no cp instruction for invalidating
+ * the whole D-cache. Need to invalidate each line.
+ *
+ *************************************************************************
+ */
+invalidate_dcache:
+ mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
+ ands r3, r0, #0x7000000
+ mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
+ beq finished
+ mov r10, #0 /* start with level 0 */
+loop1:
+ add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
+ mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
+ and r1, r1, #7 /* get those 3 bits alone */
+ cmp r1, #2
+ blt skip /* no cache or only instruction cache at this level */
+ mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
+ isb /* isb to sync the change to the CacheSizeID reg */
+ mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
+ and r2, r1, #7 /* extract the line length field */
+ add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
+ clz r5, r4 /* r5 is the bit position of the way size increment */
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
+loop2:
+ mov r9, r4 /* r9 working copy of the max way size (right aligned) */
+loop3:
+ orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
+ orr r11, r11, r7, lsl r2 /* factor in the index number */
+ mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
+ subs r9, r9, #1 /* decrement the way number */
+ bge loop3
+ subs r7, r7, #1 /* decrement the index */
+ bge loop2
+skip:
+ add r10, r10, #2 /* increment the cache number */
+ cmp r3, r10
+ bgt loop1
+
+finished:
+ mov r10, #0 /* swith back to cache level 0 */
+ mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
+ dsb
+ isb
+
+ bx lr
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/bspconfig.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/bspconfig.h
new file mode 100644
index 0000000..69c1dc8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/bspconfig.h
@@ -0,0 +1,44 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+/* Definition for hard-float ABI */
+#define FPU_HARD_FLOAT_ABI_ENABLED 1
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/changelog.txt b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/changelog.txt
new file mode 100644
index 0000000..01711e4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/changelog.txt
@@ -0,0 +1,574 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ---------------------------------------------------
+ * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ * cacheable regions
+ * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ * generated by the cpu driver, for enabling caches
+ * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
+ * write-thru caches
+ * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
+ * Updated the MMU table to mark OCM in high address space
+ * as inner cacheable and reserved space as Invalid
+ * 3.03a sdm 08/20/11 Changes to support FreeRTOS
+ * Updated the MMU table to mark upper half of the DDR as
+ * non-cacheable
+ * Setup supervisor and abort mode stacks
+ * Do not initialize/enable L2CC in case of AMP
+ * Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ * in case of AMP
+ * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
+ * counters
+ * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
+ * xparameters.h file for CR630532 - Xil_DCacheFlush()/
+ * Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ * for MicroBlaze will invalidate data in the cache instead
+ * of flushing it for writeback caches
+ * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
+ * Remove redundant dsb/dmb instructions in cache maintenance
+ * APIs
+ * Remove redundant dsb in mcr instruction
+ * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
+ * driver tcl in xparameters.h. Update the gcc/translationtable.s
+ * for the QSPI complete address range - DT644567
+ * Removed profile directory for armcc compiler and changed
+ * profiling setting to false in standalone_v2_1_0.tcl file
+ * Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ * invalidate the caches before enabling back the MMU and
+ * D cache.
+ * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
+ * xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ * array, flush the D-cache before changing the attributes
+ * in translation table. The user need not call Xil_DisableMMU
+ * before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ * sgd initialization is present. Changes for this were done in
+ * uart.c and xil-crt0.s.
+ * Made changes in xil_io.c to use volatile pointers.
+ * Made changes in xil_mmu.c to correct the function
+ * Xil_SetTlbAttributes.
+ * Changes are made xil-crt0.s to initialize the static
+ * C++ constructors.
+ * Changes are made in boot.s, to fix the TTBR settings,
+ * correct the L2 Cache Auxiliary register settings, L2 cache
+ * latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ * sgd usleep.c to use global timer intstead of CP15.
+ * Made changes in cortexa9/gcc/translation_table.s to map
+ * the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/boot.S to initialize
+ * the global timer.
+ * Made changes in cortexa9/armcc/translation_table.s to
+ * map the peripheral devices as shareable device memory.
+ * Made changes in cortexa9/gcc/boot.S to optimize the
+ * L2 cache settings. Changes the section properties for
+ * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ * and cortexa9/gcc/translation_table.S.
+ * Made changes in cortexa9/xil_cache.c to change the
+ * cache invalidation order.
+ * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
+ * compilation/linking issues for C++ compiler.
+ * Made changes in mb_interface.h to remove compilation/
+ * linking issues for C++ compiler.
+ * Added macros for swapb and swaph microblaze instructions
+ * mb_interface.h
+ * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ * for CortexA9.
+ * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa 08/31/12 Added xil_printf.h include
+ * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
+ * Corrected L2 cache sequence disable sequence
+ * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
+ * irq/fiq handling.
+ * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ * fixes the CR #692094.
+ * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt 04/18/13 Implemented ARM Erratas.
+ * Cortex A9 Errata - 742230, 743622, 775420, 794073
+ * L2Cache PL310 Errata - 588369, 727915, 759370
+ * Please refer to file 'xil_errata.h' for errata
+ * description.
+ * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ * cache APIs were corresponding to only Layer 1 cache
+ * memories. New APIs were now added and the existing cache
+ * related APIs were changed to provide a uniform interface
+ * to flush/invalidate/enable/disable the complete cache
+ * system which includes both L1 and L2 caches. The changes
+ * for these were done in:
+ * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ * files.
+ * Four new files were added for supporting L2 cache. They are:
+ * microblaze_flush_cache_ext.S-> Flushes L2 cache
+ * microblaze_flush_cache_ext_range.S -> Flushes a range of
+ * memory in L2 cache.
+ * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ * microblaze_invalidate_cache_ext_range -> Invalidates a
+ * range of memory in L2 cache.
+ * These changes are done to implement PR #697214.
+ * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ * fix the CR #706464. L2 cache disabling happens independent
+ * of L1 data cache disable operation. Changes are done in the
+ * same file in cache handling APIs to do a L2 cache sync
+ * (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
+ * interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ * sync operation. This fixes the CR# 716781.
+ * 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
+ * for armcc toolchain.
+ * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ * fix issues related to NEON context saving. The assembly
+ * routines for IRQ and FIQ handling are modified.
+ * Deprecated the older BSP (3.10a).
+ * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ * various potential issues. Made changes in the function
+ * Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ * in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ * L2 cache sync operation and to fix issues around complete
+ * L2 cache flush/invalidation by ways.
+ * 3.12a asa 10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ * to fix linking issues with armcc/DS-5. Modified the armcc
+ * makefile to fix issues.
+ * 3.12a asa 11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0 hk 12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 pkp 22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ * and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ * src\cortexa9\armcc\) to fix CR#767251
+ * 4.0 pkp 24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ * Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ * Few cache lines were missed to invalidate when unaligned address
+ * invalidation was accommodated in Xil_DCacheInvalidateRange.
+ * In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ * stack memory (which contains return address) was invalidated. So
+ * stack memory is flushed first and then L1D cache is invalidated.
+ * This is done to fix CR #763829
+ * 4.0 adk 22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ * mblaze_nt_types.h file and replace uint32_t with u32 in the
+ * profile_hist.c to fix the above CR.
+ * 4.1 bss 04/14/14 Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * instead of libxil.a and added prototypes for
+ * microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ * mb_interface.h
+ * 4.1 hk 04/18/14 Add sleep function.
+ * 4.1 asa 04/21/14 Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ * some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa 04/28/14 Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss 04/29/14 Modified driver tcl to use libxil.a if libgloss.a does not exist
+ * CR#794205
+ * 4.1 asa 05/09/14 Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ * common/xil_testcache.c
+ * Fix for CR#764881.
+ * 4.1 srt 06/27/14 Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ * output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp 06/27/14 Added support for IAR compiler in src/cortexa9/iccarm.
+ * Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp 06/19/14 Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ * cortexa9/armcc/boot.s. Added default exception handlers for data
+ * abort and prefetch abort using handlers called
+ * DataAbortHandler and PrefetchAbortHandler respectively in
+ * cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp 06/30/14 MakeFile for cortexa9/armcc has been changed to fixes the
+ * issue of improper linking of translation_table.s
+ * 4.2 pkp 07/04/14 added weak attribute for the function in BSP which are also present
+ * in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp 07/21/14 Corrected reset value of event counter in function
+ * Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp 07/21/14 Included xil_types.h file in xil_mmu.h which had contained a function
+ * containing type def u32 defined in xil_types.g to resolve issue of
+ * CR#805869
+ * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ * it is not possible to generate timer in nanosecond due to limited
+ * cpu frequency
+ * 4.2 pkp 08/04/14 Removed PEEP board related code which contained initialization of
+ * uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ * and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ * removed function definition of XSmc_NorInit and XSmc_NorInit from
+ * cortexa9/smc.h
+ * 4.2 bss 08/11/14 Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ * cache_ext_range declarations in mb_interface.h CR#783821.
+ * Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp 08/21/14 modified makefile of iccarm for proper linking of objectfiles in
+ * cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp 09/02/14 modified translation table entries in cortexa9/gcc/translation_table.s,
+ * armcc/translation_table.s and iccarm/translation_table.s
+ * to properly defined reserved entries according to address map for
+ * fixing CR#820146
+ * 4.2 pkp 09/11/14 modified translation table entries in cortexa9/iccarm/translation_table.s
+ * and cortexa9/armcc/translation_table.s to resolve compilation
+ * error for solving CR#822897
+ * 5.0 kvn 12/9/14 Support for Zync Ultrascale Mp.Also modified code for
+ * MISRA-C:2012 compliance.
+ * 5.0 pkp 12/15/14 Added APIs to get information about the platforms running the code by
+ * adding src/common/xplatform_info.*s
+ * 5.0 pkp 16/12/14 Modified boot code to enable scu after MMU is enabled and
+ * removed incorrect initialization of TLB lockdown register to fix
+ * CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ * and iccarm/boot.s
+ * 5.0 pkp 25/02/15 Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ * for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp 05/13/15 Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ * and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ * caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ * of L2Cache is done later.
+ * 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ * Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ * taking long time to fix CR#853097. L2CacheSync is added into
+ * Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ * Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ * instead of just System Stack
+ * 5.1 pkp 14/05/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS and also take the compiler and archiver as specified
+ * in settings instead of hardcoding it.
+ * 5.2 pkp 06/08/15 Modified cortexa9/gcc/translation_table.S to put a check for
+ * XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ * accordingly generate the translation table
+ * 5.2 pkp 23/07/15 Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ * to update ECC_FLAGS to fix a bug introduced during new version creation
+ * of BSP.
+ * 5.3 pkp 10/07/15 Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ * functionalities are avoided for the OpenAMP slave application(when
+ * USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ * cache for its operation. Also file operations such as read, write,
+ * close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ * defined for BSP) because XilOpenAMP library contains own file operation.
+ * The xil-crt0.S file is modified for not initializing global timer for
+ * OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp 10/09/15 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ * definition for dsb, isb and dmb to fix the compilation error when used
+ * kvn 16/10/15 Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp 09/11/15 Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ * R5 deadlock for errata 780125
+ * 5.4 pkp 09/11/15 Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ * 32 bit BSP in the initialization
+ * 5.4 pkp 09/11/15 Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * 5.4 pkp 16/11/15 Modified microblaze/xil_misc_psreset_api.c file to change the description
+ * for XOcm_Remap function
+ * kvn 21/11/15 Added volatile keyword for ADDR varibles in Xil_Out API
+ * kvn 21/11/15 Changed ADDR variable type from u32 to UINTPTR. This is
+ * required for MISRA-C:2012 Compliance.
+ * 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ * in cortexa9/xil_mmu.h
+ * 5.4 pkp 23/11/15 Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp 11/12/15 Modified common/xplatform_info.h to add #defines for silicon for
+ * checking the current executing platform
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ * to initialize global constructor for C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ * C++ applications
+ * 5.4 pkp 18/12/15 Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ * translation_table.S to update the translation table according to proper
+ * address map
+ * 5.4 pkp 18/12/15 Modified cortexar5/mpu.c to initialize the MPU according to proper
+ * address map
+ * 5.4 pkp 05/01/16 Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ * equivalent to vector table base address
+ * 5.4 pkp 08/01/16 Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ * as per the toolchain update
+ * 5.4 pkp 12/01/16 Changed common/xplatform_info.* to add platform information support
+ * for Cortex-A53 32bit mode
+ * 5.4 pkp 28/01/16 Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ * and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ * instead take it from xparameters.h to properly configure the timestamp
+ * clock frequency
+ * 5.4 asa 29/01/16 Modified microblaze/mb_interface.h to add macros that support the
+ * new instructions for MB address extension feature
+ * 5.4 kvn 30/01/16 Modified xparameters_ps.h file to add interrupt ID number for
+ * system monitor.
+ * 5.4 pkp 04/02/16 Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp 19/02/16 Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ * cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ * cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ * use set of assembly instructions to provide required delay to fix
+ * CR#913249.
+ * 5.4 asa 25/02/16 Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ * _exit with exit. We should not be directly calling _exit and should
+ * always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp 25/02/16 Made change to cortexr5/gcc/boot.S to initialize the floating point
+ * registers, banked registers for various modes and enabled
+ * the cache ECC check before enabling the fault log for lock step mode
+ * Also modified the cortexr5/gcc/Makefile to support floating point
+ * registers initialization in boot code.
+ * 5.4 pkp 03/01/16 Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ * logic in case of lock-step mode when fault log is enabled to fix
+ * CR#938281
+ * 5.4 pkp 03/02/16 Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ * header file instrinsics.h which contains assembly instructions
+ * definitions which can be used by C
+ * 5.4 asa 03/02/16 Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ * proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp 03/09/16 Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ * interrupts when sleep/usleep is being executed using assembly
+ * instructions to fix CR#913249.
+ * 5.4 pkp 03/11/16 Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ * instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ * value and compare it with previous value to detect the overflow
+ * to fix CR#940209.
+ * 5.4 pkp 03/24/16 Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ * the fault log to avoid intervention for lock-step mode and cortexr5/
+ * _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ * to fix CR#947335
+ * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ * in lock-step to avoid resetting the debug logic which restricts the
+ * access for debugger and removed enabling back of debug modules in
+ * cortexr5/_exit.c
+ * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ * to return correct number of bytes when read buffer is filled and
+ * removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when
+ * read buffer is filled and removed the redundant NULL checking for
+ * buffer to simplify the code
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ * instruction macros to disable certain optimizations which may move
+ * code out of loops if optimizers believe that the code will always
+ * return the same result or discard asm statements if optimizers
+ * determine there is no need for the output variables
+ * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ * starts the timer if it is disabled and modified XTime_GetTime to
+ * enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ * disabled and read the counter value directly from register instead
+ * of using XTime_GetTime for optimization
+ * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * Xil_DCacheInvalidateRange functions description for proper
+ * explaination to fix CR#949801
+ * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP
+ * file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache
+ * memory is not included for MicroBlaze.
+ * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros
+ * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ * the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+ * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ * section since it is part of boot process to fix CR#949555
+ * hk 07/12/16 Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53
+ * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the
+ * the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs.
+ * Source code directories specific to ARM processor's are moved to src/arm
+ * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ * into common file each and consolidated files are kept at src/arm/common directory.
+ * GCC source files related to file operations are consolidated and kept
+ * at src/arm/common/gcc directory.
+ * All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ * are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ * xil_io.h must be included as a header file to access io interfacing functions.
+ * Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ * TTC counter value register is read only.
+ * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes
+ * the CR#956899.
+ * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ * in cortexr5/xparameters_ps.h
+ * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices
+ * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ * these APIs and modifications are done on top of it to handle stdout/stdin
+ * parameters for design which doesnt have UART.It fixes CR#953681
+ * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy
+ * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
+ * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
+ * and rest of the memory in that 32GB region is marked as reserved to avoid
+ * any speculative access
+ * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified
+ * asm_vectors.S to implement lazy floating point context saving i.e. floating point
+ * access is enabled if there is any floating point operation, it is disabled by
+ * default. Also FPU is initally disabled for IRQ and none of the floating point
+ * registers are saved during normal context saving. If IRQ handler does not require
+ * floating point operation, the floating point registers are untouched and no need
+ * for saving/restoring. If IRQ handler uses any floating point operation, then floating
+ * point registers are saved and FPU is enabled for IRQ handler. Then floating point
+ * registers are restored back after servicing IRQ during normal context restoring.
+ * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
+ * target.It fixes the CR#966900
+ * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
+ * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
+ * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
+ * as false i.e. default bsp is EL3.
+ * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
+ * contains initial status of FPU i.e. disabled. In case of a warm restart execution
+ * when bss sections are not cleared, it may contain previously updated value which
+ * does not hold true once processor resumes. This fixes CR#966826.
+ * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
+ * D caches and then disables it. The problem with that is,
+ * potentially there will be a small window after the cache
+ * flush operation and before the we disable D caches where
+ * we might have valid data in cache lines. In such a
+ * scenario disabling the D cache can lead to unknown behavior.
+ * The ideal solution to this is to use assembly code for
+ * the complete API and avoid any memory accesses. But with
+ * that we will end up having a huge amount on assembly code
+ * which is not maintainable. Changes are done to use a mix
+ * of assembly and C code. All local variables are put in
+ * registers. Also function calls are avoided in the API to
+ * avoid using stack memory.
+ * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
+ * scenarios when an invalidated cache line can get pre fetched to cache.
+ * If that happens, the coherency between cache and memory is lost
+ * resulting in lost data. To avoid this kind of issue either
+ * user has to use dsb() or disable pre-fetching for L1 cache
+ * or else reduce maximum number of outstanding data prefetches allowed.
+ * Using dsb() while comparing data costing more performance compared to
+ * disabling pre-fetching/reducing maximum number of outstanding data
+ * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
+ * to disable pre-fetching/configure maximum number of outstanding data
+ * prefetches allowed in L1 cache system.This fixes CR#967864.
+ * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
+ * used by cortex-A53 64bit EL1 Non-secure application.
+ * 6.2 kvn 03/03/17 Added support thumb mode
+ * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
+ * It fixes CR#970543
+ * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
+ * profiling we see a crash. That is because the the tcl uses invalid
+ * HSI command. This change fixes it.
+ * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
+ * any FPD peripheral is configured to use CCI.It fixes CR#972638
+ * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
+ * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
+ * the HW coherency enablement. It fixes the CR#973287
+ * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
+ * L2CTLR_EL1 register. It fixes the CR#974698
+ * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
+ * of ARM 32 bit processor's.
+ * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code
+ * snippet, which checks for the FPEN bit of CPACR_EL1 register.
+ * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
+ * XGetPSVersion_Info function for PMUFW.
+ * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
+ * function for PMUFW.
+ * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
+ * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
+ * operations.Now,VFP is being enabled in FPEXC register, through boot code
+ * and FPU registers are being saved/restored when irq/fiq vector is invoked.
+ * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
+ * if h/w design configured with HPC port.
+ * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for
+ * EL1 NS execution. This change has been done to support CCI enabled IP's.
+ * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
+ * CR#982209.
+ * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
+ * make RPU MPU handling user-friendly. This also fixes the CR-981028.
+ * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
+ * version register through SMC call, over EL1 NS mode. This change has been done to
+ * support these APIs over EL1 NS mode.
+ * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
+ * it fixes CR#987464.
+ * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
+ * It fixes CR#989132.
+ * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
+ * will use the timer specified by the user to provide delay. A9 and A53 can use
+ * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
+ * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
+ * to support the sleep configuration Added new API's for the Axi timer in
+ * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
+ * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
+ * xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
+ * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor.
+ * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache
+ * or L2 cache only when the respective caches are enabled. This fixes CR-922023.
+ * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
+ * after writing to cpacr_el1/cptr_el3 registers. It would ensure
+ * disabling/enabling of floating-point unit, before any subsequent
+ * instruction.
+ * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
+ * support. Now, xil_printf would use PV console instead of UART in case of
+ * hypervisor enabled BSP.
+ * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port
+ * configured with smart interconnect.It fixes CR#990318.
+ * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
+ * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932.
+ * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
+ * CR#995014.
+ * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
+ * non-JTAG boot mode, when processor is in lockstep configuration.
+ * This behavior is restricting application debugging in non-JTAG boot
+ * mode. To get rid of this restriction, added new mld parameter
+ * "lockstep_mode_debug", to enable/disable debug logic from BSP
+ * settings. Now, debug logic can be enabled through BSP settings,
+ * by modifying value of parameter "lockstep_mode_debug" as "true".
+ * It fixes CR#993896.
+ * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and
+ * Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug
+ * in handling upper DDR addresses.It fixes CR#995581.
+ * 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
+ * in the list of include paths. This change allows applications/BSP
+ * files to include .h files in include_ps directory.
+ * 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it
+ * results into abort if accessed from EL1 non secure privilege
+ * level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
+ * to avoid CPUACTLR_EL1 access from privile levels other than EL3.
+ * 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the
+ * XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
+ * use UART console, PV console can be enabled by appending
+ * "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
+ * 6.7 asa 04/26/18 Added API Xil_GetExceptionRegisterHandler for obtaining information
+ * on an already registered exception vector.
+ * 6.7 asa 05/18/18 Fixed bugss in the API Xil_GetExceptionRegisterHandler.
+ * 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now, saving/restoring of of HW
+ * floating point register would be done through newly introduced flag
+ * FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be configured based on
+ * the -mfpu-abi option in extra compiler flags.. This change has
+ * been done to avoid saving/restoring of HW floating point registers,
+ * when BSP is not compiled with HW floating point configuration.
+ * 6.8 aru 06/15/18 Removed unused variable in xil_cache.c for A53-32. It
+ * fixes CR1005118.
+ * 6.8 aru 07/02/18 Returned the pointer instead of address of that pointer in xil_mpu.c
+ * for R5 processor.It Fixes CR#1005119.
+ * 6.8 mus 07/12/18 Updated Cortexa9 translation table to mark DDR memory as inner cacheable,
+ * if BSP is built with the USE_AMP flag. It fixes CR#1006745.
+ *
+ * 6.8 aru 07/04/18 Optimized the code to use a loop and to remove redundant code
+ * in Xil_DCacheFlush() and Xil_DCacheInvalidate()
+ * of xil_cache.c for A53-32.
+ * 6.8 aru 07/26/18 added support in xil_printf.c to print u64 variabbles
+ * correctly in 32 bit processor.It fixes CR#1007207.
+ * 6.8 aru 09/03/18 Optimized the code to use a single function and removed
+ * code redundancy in xil_printf.c . It Fixes CR#1009654.
+ * 6.8 aru 09/06/18 Removed the compiler warnings for ARMCC toolchain.
+ * It fixes CR#1008309.
+ * 6.8 mus 09/20/18 Updated CortexR5 boot code to initialize CortexR5 core with LOVEC
+ * on reset. It fixes CR#1010656.
+ * 6.8 mus 10/04/18 Updated microblaze sleep functinality to execute default method of
+ * sleep implementation, incase of FreeRTOS BSP.
+ * 6.8 mus 10/25/18 Updated assembly code for cache APIs and inline assemby macros to
+ * to support 64 bit addresses.
+ * 6.8 asa 10/11/18 Updated the A53 32 bit cache APIs for Xil_DCacheFlush and
+ * Xil_DCacheInvalidate to fix various issues. These issues were not
+ * present in the previous releases but got introduced as part of
+ * optimization patches that got applied for 6.8 BSP version. These
+ * changes fix the CR#1016012.
+ *****************************************************************************************/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/close.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/close.c
new file mode 100644
index 0000000..64f7f49
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/close.c
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+ (void)fd;
+ return (0);
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/config.make b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/config.make
new file mode 100644
index 0000000..7ca8d6d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/config.make
@@ -0,0 +1,3 @@
+LIBSOURCES = *.c *.S
+PROFILE_ARCH_OBJS = profile_mcount_arm.o
+LIBS = standalone_libs
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/cpu_init.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/cpu_init.S
new file mode 100644
index 0000000..5b597be
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/cpu_init.S
@@ -0,0 +1,76 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
+* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
+* register to fix CR#830580
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+ .text
+ .global __cpu_init
+ .align 2
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+ mov r0, #0x0
+ mcr p15, 0, r0, c5, c0, 0 /* DFSR */
+ mcr p15, 0, r0, c5, c0, 1 /* IFSR */
+ mcr p15, 0, r0, c6, c0, 0 /* DFAR */
+ mcr p15, 0, r0, c6, c0, 2 /* IFAR */
+ mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
+ mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
+ mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
+
+/* Reset and start Cycle Counter */
+ mov r2, #0x80000000 /* clear overflow */
+ mcr p15, 0, r2, c9, c12, 3
+ mov r2, #0xd /* D, C, E */
+ mcr p15, 0, r2, c9, c12, 0
+ mov r2, #0x80000000 /* enable cycle counter */
+ mcr p15, 0, r2, c9, c12, 1
+
+ bx lr
+
+.end
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/errno.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/errno.c
new file mode 100644
index 0000000..3cdb751
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/errno.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure. This
+ function returns its address for use by the macro errno defined in
+ errno.h. */
+
+#include
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+ return &_REENT->_errno;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/fcntl.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/fcntl.c
new file mode 100644
index 0000000..42c2bff
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/fcntl.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ * We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
+{
+ (void)fd;
+ (void)cmd;
+ (void)arg;
+ return 0;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/fstat.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/fstat.c
new file mode 100644
index 0000000..92a3ebf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/fstat.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+ (void)fd;
+ buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+ return (0);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/getpid.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/getpid.c
new file mode 100644
index 0000000..36c8769
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/getpid.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+ return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+ return 1;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/inbyte.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/inbyte.c
new file mode 100644
index 0000000..a5a6448
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif
+
+char inbyte(void) {
+ return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/isatty.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/isatty.c
new file mode 100644
index 0000000..d1ef081
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/isatty.c
@@ -0,0 +1,52 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ * returns 0 if not. Since we're hooked up to a
+ * serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+ (void)fd;
+ return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+ (void)fd;
+ return (1);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/kill.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/kill.c
new file mode 100644
index 0000000..22b66a2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/kill.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) int _kill(pid_t pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) int kill(pid_t pid, int sig)
+{
+ if(pid == 1) {
+ _exit(sig);
+ }
+ return 0;
+}
+
+__attribute__((weak)) int _kill(pid_t pid, int sig)
+{
+ if(pid == 1) {
+ _exit(sig);
+ }
+ return 0;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/lseek.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/lseek.c
new file mode 100644
index 0000000..400d4cc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/lseek.c
@@ -0,0 +1,57 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek -- Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+ (void)fd;
+ (void)offset;
+ (void)whence;
+ errno = ESPIPE;
+ return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+ (void)fd;
+ (void)offset;
+ (void)whence;
+ errno = ESPIPE;
+ return ((off_t)-1);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/open.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/open.c
new file mode 100644
index 0000000..4c46b67
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/open.c
@@ -0,0 +1,49 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ * we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+ (void)buf;
+ (void)flags;
+ (void)mode;
+ errno = EIO;
+ return (-1);
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/outbyte.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/outbyte.c
new file mode 100644
index 0000000..3c64308
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c);
+
+#ifdef __cplusplus
+}
+#endif
+
+void outbyte(char c) {
+ XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/print.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/print.c
new file mode 100644
index 0000000..da7e768
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/print.c
@@ -0,0 +1,36 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ XPVXenConsole_Write(ptr);
+#else
+#ifdef STDOUT_BASEADDRESS
+ while (*ptr != (char8)0) {
+ outbyte (*ptr);
+ ptr++;
+ }
+#else
+(void)ptr;
+#endif
+#endif
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/Makefile
new file mode 100644
index 0000000..53a288e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/Makefile
@@ -0,0 +1,74 @@
+###############################################################################
+#
+# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# Makefile for profiler
+#
+#######################################################################
+
+# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
+include ../config.make
+
+AS=mb-as
+COMPILER = mb-gcc
+ARCHIVER = mb-ar
+CP = cp
+COMPILER_FLAGS=-O2
+EXTRA_COMPILER_FLAGS=
+LIB = libxil.a
+DUMMYLIB = libxilprofile.a
+
+CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
+
+RELEASEDIR = ../../../../lib
+INCLUDEDIR = ../../../../include
+INCLUDES = -I./. -I${INCLUDEDIR}
+
+OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
+DUMMYOBJ = dummy.o
+INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
+
+libs : reallibs dummylibs
+
+reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
+ $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
+
+dummylibs : $(DUMMYOBJ)
+ $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
+
+%.o:%.c
+ $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+%.o:%.S
+ $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+include:
+ $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_clean.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_clean.c
new file mode 100644
index 0000000..b1c61f8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_clean.c
@@ -0,0 +1,43 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+void _profile_clean( void );
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+ Xil_ExceptionDisable();
+ disable_timer();
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_init.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_init.c
new file mode 100644
index 0000000..050b0a7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_init.c
@@ -0,0 +1,86 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_init.c:
+* Initialize the Profiling Structures.
+*
+******************************************************************************/
+
+#include "profile.h"
+
+/* XMD Initializes the following Global Variables Value during Program
+ * Download with appropriate values. */
+
+#ifdef PROC_MICROBLAZE
+
+extern s32 microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern s32 powerpc405_init(void);
+
+#else
+
+extern s32 cortexa9_init(void);
+
+#endif
+
+s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
+
+u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
+u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
+u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
+u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
+
+/* Structure for Storing the Profiling Data */
+struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
+s32 n_gmon_sections = 1;
+
+/* This is the initialization code, which is called from the crtinit. */
+
+void _profile_init( void )
+{
+/* print("Gmon Init called....\r\n") */
+/* putnum(n_gmon_sections) , print("\r\n") */
+/* if( _gmonparam == 0xffffffff ) */
+/* printf("Gmonparam is NULL !!\r\n") */
+/* for( i = 0, i < n_gmon_sections, i++ )[ */
+/* putnum( _gmonparam[i].lowpc) , print("\t") */
+/* putnum( _gmonparam[i].highpc) , print("\r\n") */
+/* putnum( _gmonparam[i].textsize ), print("\r\n") */
+/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
+/* ] */
+
+#ifdef PROC_MICROBLAZE
+ (void)microblaze_init();
+#elif defined PROC_PPC
+ powerpc405_init();
+#else
+ (void)cortexa9_init();
+#endif
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_timer_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_timer_hw.c
new file mode 100644
index 0000000..c8243e5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_timer_hw.c
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.c:
+* Timer related functions
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+/* extern u32 timer_clk_ticks, */
+
+#ifdef PROC_PPC405
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_pit_init( void );
+#endif
+s32 powerpc405_init()
+#endif /* PROC_CORTEXA9 */
+
+#ifdef PROC_PPC440
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void );
+#endif
+s32 powerpc405_init(void);
+#endif /* PROC_PPC440 */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void );
+#endif
+
+#ifdef PROC_MICROBLAZE
+s32 microblaze_init(void);
+#endif /* PROC_MICROBLAZE */
+
+#ifdef PROC_CORTEXA9
+s32 scu_timer_init( void );
+s32 cortexa9_init(void);
+#endif /* PROC_CORTEXA9 */
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC405
+
+
+/*--------------------------------------------------------------------
+* PowerPC PIT Timer Init.
+* Defined only if PIT Timer is used for Profiling
+*
+*-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set PIT Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_PITSetInterval( timer_clk_ticks ) ;
+ XTime_PITEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------
+* PowerPC Timer Initialization functions.
+* For PowerPC, PIT and opb_timer can be used for Profiling. This
+* is selected by the user in standalone BSP
+*
+*-------------------------------------------------------------------- */
+s32 powerpc405_init()
+{
+ Xil_ExceptionInit() ;
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+ * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC */
+
+
+
+/*--------------------------------------------------------------------
+ * PowerPC440 Target - Timer related functions
+ * -------------------------------------------------------------------- */
+#ifdef PROC_PPC440
+
+
+/*--------------------------------------------------------------------
+ * PowerPC DEC Timer Init.
+ * Defined only if DEC Timer is used for Profiling
+ *
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void )
+{
+ /* 1. Register Profile_intr_handler as Interrupt handler */
+ /* 2. Set DEC Timer Interrupt and Enable it. */
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ XTime_DECSetInterval( timer_clk_ticks ) ;
+ XTime_DECEnableAutoReload() ;
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Timer Initialization functions.
+ * For PowerPC, DEC and opb_timer can be used for Profiling. This
+ * is selected by the user in standalone BSP
+ *
+ *-------------------------------------------------------------------- */
+s32 powerpc405_init(void)
+{
+ Xil_ExceptionInit();
+ Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+ /* Initialize the Timer.
+ * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+ * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+ ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+ Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+ /* Initialize the timer with Timer Ticks */
+ opb_timer_init() ;
+#endif
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+ XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+ XIntc_MasterEnable( INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+ Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+ return 0;
+}
+
+#endif /* PROC_PPC440 */
+
+/* --------------------------------------------------------------------
+ * opb_timer Initialization for PowerPC and MicroBlaze. This function
+ * is not needed if DEC timer is used in PowerPC
+ *
+ *-------------------------------------------------------------------- */
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting */
+ XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
+
+ /* reset the timers, and clear interrupts */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
+ (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
+
+ /* start the timers */
+ XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
+ | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
+ return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for MicroBlaze Target.
+ * For MicroBlaze, opb_timer is used. The opb_timer can be directly
+ * connected to MicroBlaze or connected through Interrupt Controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 microblaze_init(void)
+{
+ /* Register profile_intr_handler
+ * 1. If timer is connected to Interrupt Controller, register the handler
+ * to Interrupt Controllers vector table.
+ * 2. If timer is directly connected to MicroBlaze, register the handler
+ * as Interrupt handler */
+ Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+ XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+ (XInterruptHandler)profile_intr_handler,NULL);
+#else
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL) ;
+#endif
+
+ /* Initialize the timer with Timer Ticks */
+ (void)opb_timer_init() ;
+
+ /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+ * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+ XIntc_MasterEnable((u32)INTC_BASEADDR );
+ XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+ XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+#endif
+
+#endif
+
+ Xil_ExceptionEnable();
+
+ return 0;
+
+}
+
+#endif /* PROC_MICROBLAZE */
+
+
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for Cortex A9 Target.
+ * The scu private timer is connected to the Scu GIC controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 scu_timer_init( void )
+{
+ /* set the number of cycles the timer counts before interrupting
+ * scu timer runs at half the cpu clock */
+ XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
+
+ /* clear any pending interrupts */
+ XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
+
+ /* enable interrupts, auto-reload mode and start the timer */
+ XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ return 0;
+}
+
+s32 cortexa9_init(void)
+{
+
+ Xil_ExceptionInit();
+
+ XScuGic_DeviceInitialize(0);
+
+ /*
+ * Connect the interrupt controller interrupt handler to the hardware
+ * interrupt handling logic in the processor.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+ NULL);
+
+ /*
+ * Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device.
+ */
+ XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+ PROFILE_TIMER_INTR_ID,
+ (Xil_ExceptionHandler)profile_intr_handler,
+ NULL);
+
+ /*
+ * Enable the interrupt for scu timer.
+ */
+ XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+ /*
+ * Enable interrupts in the Processor.
+ */
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+ /*
+ * Initialize the timer with Timer Ticks
+ */
+ (void)scu_timer_init() ;
+
+ Xil_ExceptionEnable();
+
+ return 0;
+}
+
+#endif /* PROC_CORTEXA9 */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_timer_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_timer_hw.h
new file mode 100644
index 0000000..1647600
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/_profile_timer_hw.h
@@ -0,0 +1,308 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+* Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+# define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+# define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+ ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
+ (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
+ ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+ (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
+ ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ * 1. XTime_PITDisableInterrupt() ;
+ * 2. Store the remaining timer clk tick
+ * 3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
+ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
+ mtspr(XREG_SPR_PIT, 0); \
+ }
+#else
+#define disable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ * 1. Load the remaining timer clk ticks
+ * 2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
+ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+ }
+#else
+#define enable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 1. Load the timer clk ticks
+ * 2. Enable AutoReload and Interrupt
+ * 3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack() \
+ { \
+ u32 val; \
+ mtspr(XREG_SPR_PIT, timer_clk_ticks); \
+ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+ }
+#else
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
+ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
+ }
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(Addr); \
+ tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+ u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+ OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ OutAddr += (u32)XTC_TCSR_OFFSET; \
+ ProfIo_Out32(OutAddr, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = (u32)ProfIo_In32(Addr); \
+ tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
+ ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
+ }
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+{ \
+ Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+ (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/dummy.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/dummy.S
new file mode 100644
index 0000000..f4ff406
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/dummy.S
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+ .globl dummy_f
+
+#ifdef PROC_MICROBLAZE
+ .text
+ .align 2
+ .ent dummy_f
+
+dummy_f:
+ nop
+
+ .end dummy_f
+#endif
+
+#ifdef PROC_PPC
+ .section .text
+ .align 2
+ .type dummy_f@function
+
+dummy_f:
+ b dummy_f
+
+#endif
+
+#ifdef PROC_CORTEXA9
+ .section .text
+ .align 2
+ .type dummy_f, %function
+
+dummy_f:
+ b dummy_f
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/mblaze_nt_types.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/mblaze_nt_types.h
new file mode 100644
index 0000000..807dda3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/mblaze_nt_types.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char byte;
+typedef short half;
+typedef int word;
+typedef unsigned char ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int uword;
+typedef ubyte boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile.h
new file mode 100644
index 0000000..63f503a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile.h
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef PROFILE_H
+#define PROFILE_H 1
+
+#include
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define HISTCOUNTER u16
+
+struct tostruct {
+ u32 selfpc;
+ s32 count;
+ s16 link;
+ u16 pad;
+};
+
+struct fromstruct {
+ u32 frompc ;
+ s16 link ;
+ u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y) (((x)/(y))*(y))
+#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+ s32 state;
+
+ /* Histogram Information */
+ u16 *kcount; /* No. of bins in histogram */
+ u32 kcountsize; /* Histogram samples */
+
+ /* Call-graph Information */
+ struct fromstruct *froms;
+ u32 fromssize;
+ struct tostruct *tos;
+ u32 tossize;
+
+ /* Initialization I/Ps */
+ u32 lowpc;
+ u32 highpc;
+ u32 textsize;
+ /* u32 cg_froms, */
+ /* u32 cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define GMON_PROF_ON 0
+#define GMON_PROF_BUSY 1
+#define GMON_PROF_ERROR 2
+#define GMON_PROF_OFF 3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define GPROF_STATE 0 /* int: profiling enabling variable */
+#define GPROF_COUNT 1 /* struct: profile tick count buffer */
+#define GPROF_FROMS 2 /* struct: from location hash bucket */
+#define GPROF_TOS 3 /* struct: destination/count structure */
+#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PROFILE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_cg.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_cg.c
new file mode 100644
index 0000000..328e6fc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_cg.c
@@ -0,0 +1,167 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount fucntion is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include
+#include
+#include
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
+#endif
+
+/*extern struct gmonparam *_gmonparam, */
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
+{
+ s32 index = 0 ;
+
+ while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == cgtable_size ) {
+ return -1 ;
+ } else {
+ return index ;
+ }
+}
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
+{
+ s32 index = 0 ;
+ s32 Status;
+
+ while( (index < fromssize) && (froms[index].frompc != frompc) ){
+ index++ ;
+ }
+ if( index == fromssize ) {
+ Status = -1 ;
+ } else {
+ Status = index ;
+ }
+ return Status;
+}
+#endif /* PROFILE_NO_FUNCPTR */
+
+
+void mcount( u32 frompc, u32 selfpc )
+{
+ register struct gmonparam *p = NULL;
+ register s32 toindex, fromindex;
+ s32 j;
+
+ disable_timer();
+
+ /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
+ * check that frompcindex is a reasonable pc value.
+ * for example: signal catchers get called from the stack,
+ * not from text space. too bad.
+ */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+ p = &_gmonparam[j];
+ break;
+ }
+ }
+ if( j == n_gmon_sections ) {
+ goto done;
+ }
+
+#ifdef PROFILE_NO_FUNCPTR
+ fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = p->cgtable_size ;
+ p->cgtable_size++ ;
+ p->cgtable[fromindex].frompc = frompc ;
+ p->cgtable[fromindex].selfpc = selfpc ;
+ p->cgtable[fromindex].count = 1 ;
+ goto done ;
+ }
+ p->cgtable[fromindex].count++ ;
+#else
+ fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
+ if( fromindex == -1 ) {
+ fromindex = (s32)p->fromssize ;
+ p->fromssize++ ;
+ /*if( fromindex >= N_FROMS ) {
+ * print("Error : From PC table overflow\r\n")
+ * goto overflow
+ *}*/
+ p->froms[fromindex].frompc = frompc ;
+ p->froms[fromindex].link = -1 ;
+ }else {
+ toindex = ((s32)(p->froms[fromindex].link));
+ while(toindex != -1) {
+ toindex = (((s32)p->tossize) - toindex)-1 ;
+ if( p->tos[toindex].selfpc == selfpc ) {
+ p->tos[toindex].count++ ;
+ goto done ;
+ }
+ toindex = ((s32)(p->tos[toindex].link)) ;
+ }
+ }
+
+ /*if( toindex == -1 ) { */
+ p->tos-- ;
+ p->tossize++ ;
+ /* if( toindex >= N_TOS ) {
+ * print("Error : To PC table overflow\r\n")
+ * goto overflow
+ *} */
+ p->tos[0].selfpc = selfpc ;
+ p->tos[0].count = 1 ;
+ p->tos[0].link = p->froms[fromindex].link ;
+ p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
+#endif
+
+ done:
+ p->state = GMON_PROF_ON;
+ goto enable_timer_label ;
+ /* overflow: */
+ /*p->state = GMON_PROF_ERROR */
+ enable_timer_label:
+ enable_timer();
+ return ;
+}
+
+
+#endif /* PROFILE_NO_GRAPH */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_config.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_config.h
new file mode 100644
index 0000000..0f6a526
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_config.h
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#define BINSIZE 4U
+#define SAMPLE_FREQ_HZ 100000U
+#define TIMER_CLK_TICKS 1000U
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000U
+#define PROFILE_TIMER_INTR_ID 0U
+
+#define TIMER_CONNECT_INTC
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_hist.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_hist.c
new file mode 100644
index 0000000..b3e237b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_hist.c
@@ -0,0 +1,67 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h"
+
+extern u32 binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+ s32 j;
+
+#ifdef PROC_MICROBLAZE
+ asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+ prof_pc = mfspr(SPR_SRR0);
+#else
+ /* for cortexa9, lr is saved in asm interrupt handler */
+#endif
+ /* print("PC: "), putnum(prof_pc), print("\r\n"), */
+ for(j = 0; j < n_gmon_sections; j++ ){
+ if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
+ _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
+ break;
+ }
+ }
+ /* Ack the Timer Interrupt */
+ timer_ack();
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_arm.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_arm.S
new file mode 100644
index 0000000..9a84363
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_arm.S
@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
+
+.globl __gnu_mcount_nc
+.type __gnu_mcount_nc, %function
+
+__gnu_mcount_nc:
+ push {r0, r1, r2, r3, lr}
+ subs r1, lr, #0 /* callee - current lr */
+ ldr r0, [sp, #20] /* caller - at the top of the stack */
+ bl mcount /* when __gnu_mcount_nc is called */
+ pop {r0, r1, r2, r3, ip, lr}
+ bx ip
+
+ .end __gnu_mcount_nc
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_mb.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_mb.S
new file mode 100644
index 0000000..21ab5b4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_mb.S
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+ .globl _mcount
+ .text
+ .align 2
+ .ent _mcount
+
+ #ifndef PROFILE_NO_GRAPH
+
+_mcount:
+ addi r1, r1, -48
+ swi r11, r1, 44
+ swi r12, r1, 40
+ swi r5, r1, 36
+ swi r6, r1, 32
+ swi r7, r1, 28
+ swi r8, r1, 24
+ swi r9, r1, 20
+ swi r10, r1, 16
+ swi r15, r1, 12
+ add r5, r0, r15
+ brlid r15, mcount
+ add r6, r0, r16
+
+ lwi r11, r1, 44
+ lwi r12, r1, 40
+ lwi r5, r1, 36
+ lwi r6, r1, 32
+ lwi r7, r1, 28
+ lwi r8, r1, 24
+ lwi r9, r1, 20
+ lwi r10, r1, 16
+ lwi r15, r1, 12
+ rtsd r15, 4
+ addi r1, r1, 48
+
+ #endif /* PROFILE_NO_GRAPH */
+
+ .end _mcount
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_ppc.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_ppc.S
new file mode 100644
index 0000000..230df08
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/profile/profile_mcount_ppc.S
@@ -0,0 +1,67 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+ .globl _mcount
+
+ #define _MCOUNT_STACK_FRAME 48
+ .section .text
+ .align 2
+ .type _mcount@function
+
+
+_mcount:
+ stwu 1, -_MCOUNT_STACK_FRAME(1)
+ stw 3, 8(1)
+ stw 4, 12(1)
+ stw 5, 16(1)
+ stw 6, 20(1)
+ stw 7, 24(1)
+ stw 8, 28(1)
+ stw 9, 32(1)
+ stw 10, 36(1)
+ stw 11, 40(1)
+ stw 12, 44(1)
+ mflr 4
+ stw 4, (_MCOUNT_STACK_FRAME+4)(1)
+ lwz 3, (_MCOUNT_STACK_FRAME)(1)
+ lwz 3, 4(3)
+ bl mcount
+ lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
+ mtlr 4
+ lwz 12, 44(1)
+ lwz 11, 40(1)
+ lwz 10, 36(1)
+ lwz 9, 32(1)
+ lwz 8, 28(1)
+ lwz 7, 24(1)
+ lwz 6, 20(1)
+ lwz 5, 16(1)
+ lwz 4, 12(1)
+ lwz 3, 8(1)
+ addi 1,1, _MCOUNT_STACK_FRAME
+ blr
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/putnum.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/putnum.c
new file mode 100644
index 0000000..aaf9ede
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+ char8 buf[9];
+ s32 cnt;
+ s32 i;
+ char8 *ptr;
+ u32 digit;
+ for(i = 0; i<9; i++) {
+ buf[i] = '0';
+ }
+
+ ptr = buf;
+ for (cnt = 7 ; cnt >= 0 ; cnt--) {
+ digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+ if ((digit <= 9U) && (ptr != NULL)) {
+ digit += (u32)'0';
+ *ptr = ((char8) digit);
+ ptr += 1;
+ } else if (ptr != NULL) {
+ digit += ((u32)'a' - (u32)10);
+ *ptr = ((char8)digit);
+ ptr += 1;
+ } else {
+ /*Made for MisraC Compliance*/;
+ }
+ }
+
+ if(ptr != NULL) {
+ *ptr = (char8) 0;
+ }
+ print (buf);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/read.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/read.c
new file mode 100644
index 0000000..9900842
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/read.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read -- read bytes from the serial port. Ignore fd, since
+ * we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+ s32 i;
+ s32 numbytes = 0;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
+ }
+ }
+ }
+
+ return numbytes;
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+ s32 i;
+ s32 numbytes = 0;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ if(LocalBuf != NULL) {
+ for (i = 0; i < nbytes; i++) {
+ numbytes++;
+ *(LocalBuf + i) = inbyte();
+ if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+ break;
+ }
+ }
+ }
+
+ return numbytes;
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sbrk.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sbrk.c
new file mode 100644
index 0000000..7f91b9c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sbrk.c
@@ -0,0 +1,57 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+ char8 *base;
+ static char8 *heap_ptr = HeapBase;
+
+ base = heap_ptr;
+ if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
+ heap_ptr += nbytes;
+ return base;
+ } else {
+ errno = ENOMEM;
+ return ((char8 *)-1);
+ }
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sleep.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sleep.c
new file mode 100644
index 0000000..659c21b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sleep.c
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 11/11/09 First release
+* 3.07a sgd 07/05/12 Updated sleep function to make use Global
+* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
+*
+*
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param seconds requested
+*
+* @return 0 always
+*
+* @note None.
+*
+****************************************************************************/
+unsigned sleep_A9(unsigned int seconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
+#else
+ XTime tEnd, tCur;
+
+ XTime_GetTime(&tCur);
+ tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+ do
+ {
+ XTime_GetTime(&tCur);
+ } while (tCur < tEnd);
+#endif
+
+ return 0;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sleep.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sleep.h
new file mode 100644
index 0000000..f3a632b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/sleep.h
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep rountines
+* function prototypes.
+*
+*
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/smc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/smc.h
new file mode 100644
index 0000000..f7cc91c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/smc.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 11/03/09 Initial release.
+* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+* as smc.c is removed
+*
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET 0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/translation_table.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/translation_table.S
new file mode 100644
index 0000000..154517f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/translation_table.S
@@ -0,0 +1,226 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file translation_table.s
+*
+* @addtogroup a9_boot_code
+* @{
+*
translation_table.S
+* translation_table.S contains a static page table required by MMU for
+* cortex-A9. This translation table is flat mapped (input address = output
+* address) with default memory attributes defined for zynq architecture. It
+* utilizes short descriptor translation table format with each section defining
+* 1MB of memory.
+*
+* The overview of translation table memory attributes is described below.
+*
+*| | Memory Range | Definition in Translation Table |
+*|-----------------------|-------------------------|-----------------------------------|
+*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
+*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
+*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
+*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
+*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
+*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
+*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
+*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
+*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
+*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
+*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
+*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
+*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
+*
+* @note
+*
+* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
+* region after DDR and before PL is marked as undefined/reserved in translation
+* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
+* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
+* of 1MB, it is not possible to define separate regions for them. For region
+* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
+* granual size, it is not possible to define separate region for it
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/09 Initial version
+* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
+* instead of strongly-ordered.
+* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+* and 0xe0000000 - 0xe1ffffff is broken down into
+* 0xe0000000 - 0xe02fffff (memory mapped devides)
+* 0xe0300000 - 0xe0ffffff (reserved) and
+* 0xe1000000 - 0xe1ffffff (NAND)
+* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
+* if DDR is present or not and accordingly generate the
+* translation table
+* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
+* 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
+* with the USE_AMP flag.
+*
+*
+*
+******************************************************************************/
+#include "xparameters.h"
+ .globl MMUTable
+
+ .section .mmu_tbl,"a"
+
+MMUTable:
+ /* Each table entry occupies one 32-bit word and there are
+ * 4096 entries, so the entire table takes up 16KB.
+ * Each entry covers a 1MB section.
+ */
+.set SECT, 0
+
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
+.set DDR_SIZE, (DDR_END - DDR_START)+1
+.set DDR_REG, DDR_SIZE/0x100000
+#else
+.set DDR_REG, 0
+#endif
+
+.set UNDEF_REG, 0x3FF - DDR_REG
+
+#ifndef USE_AMP
+ /*0x00000000 - 0x00100000 (inner and outer cacheable )*/
+.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+#else
+ /*0x00000000 - 0x00100000 (inner cacheable )*/
+.word SECT + 0x14de6 /* S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b1 */
+#endif
+.set SECT, SECT+0x100000
+
+.rept DDR_REG /* (DDR Cacheable) */
+.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept UNDEF_REG /* (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+
+.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
+.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
+.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
+ * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
+.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
+ 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
+ 1MB, it is not possible to define separate regions for them */
+
+.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
+
+.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
+.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
+ * Generates a translation fault if accessed */
+.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set SECT, SECT+0x100000
+.endr
+
+/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
+ 1MB, it is not possible to define separate region for it
+
+ 0xfff00000 - 0xffffffff
+ 256K OCM when mapped to high address space
+ inner-cacheable */
+.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
+.set SECT, SECT+0x100000
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/unlink.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/unlink.c
new file mode 100644
index 0000000..abd0d87
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/unlink.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ * we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+ (void) path;
+ errno = EIO;
+ return (-1);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/usleep.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/usleep.c
new file mode 100644
index 0000000..0965233
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/usleep.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 11/11/09 First release
+* 3.07a sgd 07/05/12 Upadted micro sleep function to make use Global Timer
+* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
+* possible to generate timer in nanosecond due to
+* limited cpu frequency
+* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
+* implementation. Now sleep routines will use Timer
+* specified by the user (i.e. Global timer/TTC timer)
+*
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/**************************** Constant Definitions ************************/
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param useconds requested
+*
+* @return 0 if the delay can be achieved, -1 if the requested delay
+* is out of range
+*
+* @note None.
+*
+****************************************************************************/
+int usleep_A9(unsigned long useconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+ Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
+#else
+ XTime tEnd, tCur;
+
+ XTime_GetTime(&tCur);
+ tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+ do
+ {
+ XTime_GetTime(&tCur);
+ } while (tCur < tEnd);
+#endif
+
+ return 0;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/vectors.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/vectors.c
new file mode 100644
index 0000000..2e23fc9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/vectors.c
@@ -0,0 +1,227 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
+* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
+* and added UndefinedException for a53 32 bit and r5
+* processor
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+ XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+ XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/vectors.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/vectors.h
new file mode 100644
index 0000000..56bacbc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/vectors.h
@@ -0,0 +1,84 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/write.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/write.c
new file mode 100644
index 0000000..dc10ed7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/write.c
@@ -0,0 +1,117 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+ __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ * stdout and stderr are the same. Since we have no filesystem,
+ * open will only return an error.
+ */
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+ s32 i;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ for (i = 0; i < nbytes; i++) {
+ if(LocalBuf != NULL) {
+ LocalBuf += i;
+ }
+ if(LocalBuf != NULL) {
+ if (*LocalBuf == '\n') {
+ outbyte ('\r');
+ }
+ outbyte (*LocalBuf);
+ }
+ if(LocalBuf != NULL) {
+ LocalBuf -= i;
+ }
+ }
+ return (nbytes);
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+}
+
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+ sint32 length;
+
+ (void)fd;
+ (void)nbytes;
+ length = XPVXenConsole_Write(buf);
+ return length;
+#else
+#ifdef STDOUT_BASEADDRESS
+ s32 i;
+ char8* LocalBuf = buf;
+
+ (void)fd;
+ for (i = 0; i < nbytes; i++) {
+ if(LocalBuf != NULL) {
+ LocalBuf += i;
+ }
+ if(LocalBuf != NULL) {
+ if (*LocalBuf == '\n') {
+ outbyte ('\r');
+ }
+ outbyte (*LocalBuf);
+ }
+ if(LocalBuf != NULL) {
+ LocalBuf -= i;
+ }
+ }
+ return (nbytes);
+#else
+ (void)fd;
+ (void)buf;
+ (void)nbytes;
+ return 0;
+#endif
+#endif
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xbasic_types.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xbasic_types.h
new file mode 100644
index 0000000..ea7c8aa
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xbasic_types.h
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note Dummy File for backwards compatibility
+*
+
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+*
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xdebug.h
new file mode 100644
index 0000000..650946b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xenv.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xenv.h
new file mode 100644
index 0000000..9c7c4c3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xenv.h
@@ -0,0 +1,183 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+*
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xenv_standalone.h
new file mode 100644
index 0000000..ef905af
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xenv_standalone.h
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implemention MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil-crt0.S b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil-crt0.S
new file mode 100644
index 0000000..8ea3a09
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil-crt0.S
@@ -0,0 +1,155 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/09 Initial version
+* 3.05a sdm 02/02/12 Added code for profiling
+* 3.06a sgd 05/16/12 Added global constructors and cleanup code
+* Uart initialization based on compiler flag
+* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
+* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
+* initialization of uart smc nor and sram
+* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
+* timer when USE_AMP flag is defined
+* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
+* Now the TTC instance as specified by the user will be
+* started.
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "bspconfig.h"
+
+ .file "xil-crt0.S"
+ .section ".got2","aw"
+ .align 2
+
+ .text
+.Lsbss_start:
+ .long __sbss_start
+
+.Lsbss_end:
+ .long __sbss_end
+
+.Lbss_start:
+ .long __bss_start
+
+.Lbss_end:
+ .long __bss_end
+
+.Lstack:
+ .long __stack
+
+
+ .globl _start
+_start:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this) */
+
+ mov r0, #0
+
+ /* clear sbss */
+ ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
+ ldr r2,.Lsbss_end /* calculate end of the SBSS */
+
+.Lloop_sbss:
+ cmp r1,r2
+ bge .Lenclsbss /* If no SBSS, no clearing required */
+ str r0, [r1], #4
+ b .Lloop_sbss
+
+.Lenclsbss:
+ /* clear bss */
+ ldr r1,.Lbss_start /* calculate beginning of the BSS */
+ ldr r2,.Lbss_end /* calculate end of the BSS */
+
+.Lloop_bss:
+ cmp r1,r2
+ bge .Lenclbss /* If no BSS, no clearing required */
+ str r0, [r1], #4
+ b .Lloop_bss
+
+.Lenclbss:
+
+ /* set stack pointer */
+ ldr r13,.Lstack /* stack address */
+
+ /* Reset and start Global Timer */
+ mov r0, #0x0
+ mov r1, #0x0
+
+ /* Reset and start Triple Timer Counter */
+ #if defined SLEEP_TIMER_BASEADDR
+ bl XTime_StartTTCTimer
+ #endif
+
+#if USE_AMP != 1
+ bl XTime_SetTime
+#endif
+
+#ifdef PROFILING /* defined in Makefile */
+ /* Setup profiling stuff */
+ bl _profile_init
+#endif /* PROFILING */
+
+ /* run global constructors */
+ bl __libc_init_array
+
+ /* make sure argc and argv are valid */
+ mov r0, #0
+ mov r1, #0
+
+ /* Let her rip */
+ bl main
+
+ /* Cleanup global constructors */
+ bl __libc_fini_array
+
+#ifdef PROFILING
+ /* Cleanup profiling stuff */
+ bl _profile_clean
+#endif /* PROFILING */
+
+ /* All done */
+ bl exit
+
+.Lexit: /* should never get here */
+ b .Lexit
+
+.Lstart:
+ .size _start,.Lstart-_start
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_assert.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_assert.c
new file mode 100644
index 0000000..f6ec066
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_assert.c
@@ -0,0 +1,143 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 Initial release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+s32 Xil_AssertWait = 1;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief Implement assert. Currently, it calls a user-defined callback
+* function if one has been set. Then, it potentially enters an
+* infinite loop depending on the value of the Xil_AssertWait
+* variable.
+*
+* @param file: filename of the source
+* @param line: linenumber within File
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+ /* if the callback has been set then invoke it */
+ if (Xil_AssertCallbackRoutine != 0) {
+ (*Xil_AssertCallbackRoutine)(File, Line);
+ }
+
+ /* if specified, wait indefinitely such that the assert will show up
+ * in testing
+ */
+ while (Xil_AssertWait != 0) {
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Set up a callback function to be invoked when an assert occurs.
+* If a callback is already installed, then it will be replaced.
+*
+* @param routine: callback to be invoked when an assert is taken
+*
+* @return None.
+*
+* @note This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+ Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Null handler function. This follows the XInterruptHandler
+* signature for interrupt handlers. It can be used to assign a null
+* handler (a stub) to an interrupt controller vector table.
+*
+* @param NullParameter: arbitrary void pointer and not used.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void) NullParameter;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_assert.h
new file mode 100644
index 0000000..917de31
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_assert.h
@@ -0,0 +1,191 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+*
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accomodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache.c
new file mode 100644
index 0000000..536800f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache.c
@@ -0,0 +1,1637 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+* to xil_cache_mach.h to give access to sophisticated users
+* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+* L1 and L2 caches in a single loop and used dsb, L2 sync
+* at the end of the loop.
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+* operation was being done with L1 Data cache disabled. This is
+* fixed so that L2 cache disable operation happens independent of
+* L1 cache disable operation. This fixes CR #706464.
+* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+* This is done to fix the CR #700542.
+* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+* relevant cache APIs to disable and enable back the interrupts.
+* This fixes CR #663885.
+* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
+* out that for L2 cache flush/clean/invalidation by cache lines
+* does not need a cache sync as these are atomic nature. Similarly
+* figured out that for complete L2 cache flush/invalidation by way
+* we need to wait for some more time in a loop till the status
+* shows that the cache operation is completed.
+* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+* cache lines were missed to invalidate when unaligned address
+* invalidation was accommodated. That fixes CR #766768.
+* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+* stack memory which contains return address was invalidated. So
+* stack memory was flushed first and then L1D cache is invalidated.
+* This is done to fix CR #763829
+* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+* explanation of CR#785243
+* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+* has stack memory which has return address. Before invalidating
+* cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+* to remove unnecessary dsb in the APIs. Instead of using dsb
+* for L2 Cache, L2CacheSync has been used for each L2 cache line
+* and single dsb has been used for L1 cache. Also L2CacheSync is
+* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+* and Xil_L2CacheInvalidate APIs are modified to flush the complete
+* stack instead of just System Stack
+* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+* application(when USE_AMP flag is defined for BSP) as master CPU
+* would be utilizing L2 cache for its operation
+* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+* version r0p2, which is present in zynq. So,removed the handling
+* related to same.It fixes CR#989132.
+* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+* routines to ensure the stack data flushed only when the respective
+* caches are enabled. This fixes CR-992023.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+ extern s32 _stack_end;
+ extern s32 __undef_stack;
+#endif
+
+#ifndef USE_AMP
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param Value, value to be written to Debug Control Register.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+ (void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
+}
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+ Xil_L1DCacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1DCacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a Data cache line. If the byte specified by the address
+* (adr) is cached by the Data cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* modified contents are lost and are NOT written to the system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1DCacheInvalidateLine(adr);
+
+ mtcpsr(currmask);
+}
+
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If
+* the cachelines are modified (dirty), the modified contents are lost
+* and NOT written to the system memory before the lines are
+* invalidated.
+*
+* In this function, if start address or end address is not aligned to
+* cache-line, particular cache-line containing unaligned start or end
+* address is flush first and then invalidated the others as
+* invalidating the same unaligned cache line may result into loss of
+* data. This issue raises few possibilities.
+*
+* If the address to be invalidated is not cache-line aligned, the
+* following choices are available:
+* 1. Invalidate the cache line when required and do not bother much
+* for the side effects. Though it sounds good, it can result in
+* hard-to-debug issues. The problem is, if some other variable are
+* allocated in the same cache line and had been recently updated
+* (in cache), the invalidation would result in loss of data.
+* 2. Flush the cache line first. This will ensure that if any other
+* variable present in the same cache line and updated recently are
+* flushed out to memory. Then it can safely be invalidated. Again it
+* sounds good, but this can result in issues. For example, when the
+* invalidation happens in a typical ISR (after a DMA transfer has
+* updated the memory), then flushing the cache line means, loosing
+* data that were updated recently before the ISR got invoked.
+*
+* Linux prefers the second one. To have uniform implementation
+* (across standalone and Linux), the second option is implemented.
+* This being the case, follwoing needs to be taken care of:
+* 1. Whenever possible, the addresses must be cache line aligned.
+* Please nore that, not just start address, even the end address must
+* be cache line aligned. If that is taken care of, this will always
+* work.
+* 2. Avoid situations where invalidation has to be done after the
+* data is updated by peripheral/DMA directly into the memory. It is
+* not tough to achieve (may be a bit risky). The common use case to
+* do invalidation is when a DMA happens. Generally for such use
+* cases, buffers can be allocated first and then start the DMA. The
+* practice that needs to be followed here is, immediately after
+* buffer allocation and before starting the DMA, do the invalidation.
+* With this approach, invalidation need not to be done after the DMA
+* transfer is over.
+*
+* This is going to always work if done carefully.
+* However, the concern is, there is no guarantee that invalidate has
+* not needed to be done after DMA is complete. For example, because
+* of some reasons if the first cache line or last cache line
+* (assuming the buffer in question comprises of multiple cache lines)
+* are brought into cache (between the time it is invalidated and DMA
+* completes) because of some speculative prefetching or reading data
+* for a variable present in the same cache line, then we will have to
+* invalidate the cache after DMA is complete.
+*
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 tempadr = adr;
+ u32 tempend;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ end = tempadr + len;
+ tempend = end;
+ /* Select L1 Data cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ if ((tempadr & (cacheline-1U)) != 0U) {
+ tempadr &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempadr);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ tempadr += cacheline;
+ }
+ if ((tempend & (cacheline-1U)) != 0U) {
+ tempend &= (~(cacheline - 1U));
+
+ Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+ Xil_L2CacheFlushLine(tempend);
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ }
+
+ while (tempadr < tempend) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = tempadr;
+ Xil_L2CacheSync();
+#endif
+
+ /* Invalidate L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(tempadr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = tempadr; }
+#endif
+ tempadr += cacheline;
+ }
+ }
+
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlush();
+#ifndef USE_AMP
+ Xil_L2CacheFlush();
+#endif
+ mtcpsr(currmask);
+}
+
+
+/****************************************************************************/
+/**
+* @brief Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ Xil_L1DCacheFlushLine(adr);
+#ifndef USE_AMP
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_L2CacheFlushLine(adr);
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ Xil_L2CacheSync();
+#endif
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the Data cache for the given address range.
+* If the bytes specified by the address range are cached by the
+* data cache, the cachelines containing those bytes are invalidated.
+* If the cachelines are modified (dirty), they are written to the
+* system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr &= ~(cacheline - 1U);
+
+ while (LocalAddr < end) {
+
+ /* Flush L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+#ifndef USE_AMP
+ /* Flush L2 cache line */
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+ dsb();
+ mtcpsr(currmask);
+}
+/****************************************************************************/
+/**
+* @brief Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param adr: 32bit address of the data to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
+ Xil_L2CacheStoreLine(adr);
+#endif
+ mtcpsr(currmask);
+}
+
+/***************************************************************************/
+/**
+* @brief Enable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+ Xil_L1ICacheEnable();
+#ifndef USE_AMP
+ Xil_L2CacheEnable();
+#endif
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+#ifndef USE_AMP
+ Xil_L2CacheDisable();
+#endif
+ Xil_L1ICacheDisable();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidate();
+#endif
+ Xil_L1ICacheInvalidate();
+
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate an instruction cache line. If the instruction specified
+* by the address is cached by the instruction cache, the cacheline
+* containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(u32 adr)
+{
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+ Xil_L2CacheInvalidateLine(adr);
+#endif
+ Xil_L1ICacheInvalidateLine(adr);
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the instruction cache for the given address range.
+* If the instructions specified by the address range are cached by
+* the instrunction cache, the cachelines containing those
+* instructions are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+#ifndef USE_AMP
+ /* Invalidate L2 cache line */
+ *L2CCOffset = LocalAddr;
+ dsb();
+#endif
+
+ /* Invalidate L1 I-cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 and L2 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ return;
+ }
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheInvalidate();
+
+ /* enable the Data cache */
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/***************************************************************************/
+/**
+* @brief Disable the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ /* clean and invalidate the Data cache */
+ Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+ /* disable the Data cache */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for invalidating
+* the whole D-cache. This function invalidates each line by
+* set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way, WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+#ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 CtrlReg;
+#endif
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+#ifdef __GNUC__
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * dont flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ * */
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+#endif
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+ /* Determine Cache Size */
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+
+ /* Invalidate by Set/Way */
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_sw(C7Reg);
+#else
+ /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set=0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 Data cache line. If the byte specified by the
+* address (Addr) is cached by the Data cache, the cacheline
+* containing that byte is invalidated. If the cacheline is modified
+* (dirty), the modified contents are lost and are NOT written to
+* system memory before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cachelines containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* NOT written to the system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note In Cortex A9, there is no cp instruction for flushing
+* the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+ register u32 CsidReg, C7Reg;
+ u32 CacheSize, LineSize, NumWays;
+ u32 Way;
+ u32 WayIndex, Set, SetIndex, NumSet;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ /* Select cache level 0 and D cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+ CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+ CsidReg = Reg; }
+#endif
+
+ /* Determine Cache Size */
+
+ CacheSize = (CsidReg >> 13U) & 0x1FFU;
+ CacheSize +=1U;
+ CacheSize *=128U; /* to get number of bytes */
+
+ /* Number of Ways */
+ NumWays = (CsidReg & 0x3ffU) >> 3U;
+ NumWays += 1U;
+
+ /* Get the cacheline size, way size, index size from csidr */
+ LineSize = (CsidReg & 0x07U) + 4U;
+
+ NumSet = CacheSize/NumWays;
+ NumSet /= (0x00000001U << LineSize);
+
+ Way = 0U;
+ Set = 0U;
+
+ /* Invalidate all the cachelines */
+ for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+ for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+ C7Reg = Way | Set;
+ /* Flush by Set/Way */
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_sw(C7Reg);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+ Reg = C7Reg; }
+#endif
+ Set += (0x00000001U << LineSize);
+ }
+ Set = 0U;
+ Way += 0x40000000U;
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data to be flushed.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 flush to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 1 Data cache for the given address range.
+* If the bytes specified by the address range are cached by the Data
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to system memory
+* before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 D-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 flush to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 1 Data cache line. If the byte specified by the
+* address (adr) is cached by the Data cache and the cacheline is
+* modified (dirty), the entire contents of the cacheline are written
+* to system memory. After the store completes, the cacheline is
+* marked as unmodified (not dirty).
+*
+* @param Address to be stored.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+ mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+ /* Wait for L1 store to complete */
+ dsb();
+}
+
+
+/****************************************************************************/
+/**
+* @brief Enable the level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+ register u32 CtrlReg;
+
+ /* enable caches only if they are disabled */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
+ return;
+ }
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* enable the instruction cache */
+ CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Disable level 1 the instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+ register u32 CtrlReg;
+
+ dsb();
+
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* disable the instruction cache */
+#ifdef __GNUC__
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+ { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+ CtrlReg = Reg; }
+#endif
+ CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the entire level 1 instruction cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ /* invalidate the instruction cache */
+ mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate a level 1 instruction cache line. If the instruction
+* specified by the address is cached by the instruction cache, the
+* cacheline containing that instruction is invalidated.
+*
+* @param adr: 32bit address of the instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(u32 adr)
+{
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+ mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 1 instruction cache for the given address
+* range. If the instrucions specified by the address range are cached
+* by the instruction cache, the cacheline containing those bytes are
+* invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Select cache L0 I-cache in CSSR */
+ mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+ while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+ asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+ { volatile register u32 Reg
+ __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+ Reg = LocalAddr; }
+#endif
+ LocalAddr += cacheline;
+ }
+ }
+
+ /* Wait for L1 invalidate to complete */
+ dsb();
+ mtcpsr(currmask);
+}
+
+#ifndef USE_AMP
+/****************************************************************************/
+/**
+* @brief Enable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ /* only enable if L2CC is currently disabled */
+ if ((L2CCReg & 0x01U) == 0U) {
+ /* set up the way size and latencies */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_AUX_CNTRL_OFFSET);
+ L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+ L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+ L2CCReg);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+ XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+ XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+ /* Clear the pending interrupts */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_ISR_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+ Xil_L2CacheInvalidate();
+ /* Enable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg | (0x01U)));
+
+ Xil_L2CacheSync();
+ /* synchronize the processor */
+ dsb();
+
+ }
+}
+
+/****************************************************************************/
+/**
+* @brief Disable the L2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+ register u32 L2CCReg;
+
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+ if((L2CCReg & 0x1U) != 0U) {
+
+ /* Clean and Invalidate L2 Cache */
+ Xil_L2CacheFlush();
+
+ /* Disable the L2CC */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+ (L2CCReg & (~0x01U)));
+ /* Wait for the cache operations to complete */
+
+ dsb();
+ }
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+ #ifdef __GNUC__
+ u32 stack_start,stack_end,stack_size;
+ register u32 L2CCReg;
+ stack_end = (u32)&_stack_end;
+ stack_start = (u32)&__undef_stack;
+ stack_size=stack_start-stack_end;
+
+ /* Check for the cache status. If cache is enabled, then only
+ * flush stack memory to save return address. If cache is disabled,
+ * dont flush anything as it might result in flushing stale date into
+ * memory which is undesirable.
+ */
+ L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+ if ((L2CCReg & 0x01U) != 0U) {
+ /*Flush stack memory to save return address*/
+ Xil_DCacheFlushRange(stack_end, stack_size);
+ }
+
+ #endif
+ u32 ResultDCache;
+ /* Invalidate the caches */
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ while(ResultDCache != (u32)0U) {
+ ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ /* Wait for the invalidate to complete */
+ Xil_L2CacheSync();
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Invalidate a level 2 cache line. If the byte specified by the
+* address (adr) is cached by the Data cache, the cacheline containing
+* that byte is invalidated. If the cacheline is modified (dirty),
+* the modified contents are lost and are NOT written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be invalidated.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Invalidate the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), the modified contents are lost and
+* are NOT written to system memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be invalidated.
+* @param len: Length of the range to be invalidated in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the entire level 2 cache.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+ u32 ResultL2Cache;
+
+ /* Flush the caches */
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+ 0x0000FFFFU);
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+
+ while(ResultL2Cache != (u32)0U) {
+ ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+ & 0x0000FFFFU;
+ }
+
+ Xil_L2CacheSync();
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache, the cacheline containing that
+* byte is invalidated. If the cacheline is modified (dirty), the
+* entire contents of the cacheline are written to system memory
+* before the line is invalidated.
+*
+* @param adr: 32bit address of the data/instruction to be flushed.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(u32 adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+ /* synchronize the processor */
+ dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief Flush the level 2 cache for the given address range.
+* If the bytes specified by the address range are cached by the L2
+* cache, the cacheline containing those bytes are invalidated. If the
+* cachelines are modified (dirty), they are written to the system
+* memory before the lines are invalidated.
+*
+* @param adr: 32bit start address of the range to be flushed.
+* @param len: Length of the range to be flushed in bytes.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(u32 adr, u32 len)
+{
+ u32 LocalAddr = adr;
+ const u32 cacheline = 32U;
+ u32 end;
+ volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+ XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+ u32 currmask;
+
+ currmask = mfcpsr();
+ mtcpsr(currmask | IRQ_FIQ_MASK);
+ if (len != 0U) {
+ /* Back the starting address up to the start of a cache line
+ * perform cache operations until adr+len
+ */
+ end = LocalAddr + len;
+ LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+ /* Disable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x3U);
+
+ while (LocalAddr < end) {
+ *L2CCOffset = LocalAddr;
+ Xil_L2CacheSync();
+ LocalAddr += cacheline;
+ }
+
+ /* Enable Write-back and line fills */
+ Xil_L2WriteDebugCtrl(0x0U);
+ }
+ /* synchronize the processor */
+ dsb();
+ mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief Store a level 2 cache line. If the byte specified by the address
+* (adr) is cached by the L2 cache and the cacheline is modified
+* (dirty), the entire contents of the cacheline are written to
+* system memory. After the store completes, the cacheline is marked
+* as unmodified (not dirty).
+*
+* @param adr: 32bit address of the data/instruction to be stored.
+*
+* @return None.
+*
+* @note The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(u32 adr)
+{
+ Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+ /* synchronize the processor */
+ dsb();
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache.h
new file mode 100644
index 0000000..ce6fcf4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache.h
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache_l.h
new file mode 100644
index 0000000..b6ff809
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache_l.h
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache_vxworks.h
new file mode 100644
index 0000000..7e2a7d9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_cache_vxworks.h
@@ -0,0 +1,89 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_errata.h
new file mode 100644
index 0000000..8ac0795
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_errata.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+*
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_exception.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_exception.c
new file mode 100644
index 0000000..26d9acc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_exception.c
@@ -0,0 +1,359 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
+* Handler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
+* processors and added Xil_UndefinedExceptionHandler
+* for a53 32 bit and r5 as well.
+* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
+* fix the warnings.
+* 6.7 mna 26/04/18 Add an API to obtain a corresponding
+* Xil_ExceptionHandler entry from XExc_VectorTable.
+* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+ Xil_ExceptionHandler Handler;
+ void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SyncAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_UndefinedExceptionHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_PrefetchAbortHandler, NULL},
+ {Xil_DataAbortHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+ {Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr; /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
+ exception */
+#endif
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param Data is unused by this function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+ (void) Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* @brief The function is a common API used to initialize exception handlers
+* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
+* and Cortex-A9, the exception handlers are being initialized
+* statically and this function does not do anything.
+* However, it is still present to take care of backward compatibility
+* issues (in earlier versions of BSPs, this API was being used to
+* initialize exception handlers).
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+ return;
+}
+
+/*****************************************************************************/
+/**
+* @brief Register a handler for a specific exception. This handler is being
+* called when the processor encounters the specified exception.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data)
+{
+ XExc_VectorTable[Exception_id].Handler = Handler;
+ XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+* @brief Get a handler for a specific exception. This handler is being
+* called when the processor encounters the specified exception.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+* @param Handler to the Handler for that exception.
+* @param Data is a reference to Data that will be passed to the
+* Handler when it gets called.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler,
+ void **Data)
+{
+ *Handler = XExc_VectorTable[Exception_id].Handler;
+ *Data = XExc_VectorTable[Exception_id].Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Removes the Handler for a specific exception Id. The stub Handler
+* is then registered for this exception Id.
+*
+* @param exception_id contains the ID of the exception source and should
+* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+* See xil_exception.h for further information.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+ Xil_ExceptionRegisterHandler(Exception_id,
+ Xil_ExceptionNullHandler,
+ NULL);
+}
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+ while(1) {
+ ;
+ }
+}
+#else
+/*****************************************************************************/
+/*
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+
+/*****************************************************************************/
+/*
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+ (void) CallBackRef;
+#ifdef DEBUG
+ u32 FaultStatus;
+
+ xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+ #ifdef __GNUC__
+ FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+ #elif defined (__ICCARM__)
+ mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+ #else
+ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+ FaultStatus = Reg; }
+ #endif
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
+#endif
+ while(1) {
+ ;
+ }
+}
+/*****************************************************************************/
+/*
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param None
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+ (void) CallBackRef;
+ xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
+ while(1) {
+ ;
+ }
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_exception.h
new file mode 100644
index 0000000..4da1b73
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_exception.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_hal.h
new file mode 100644
index 0000000..720adf9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_hal.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_io.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_io.c
new file mode 100644
index 0000000..6ed1559
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_io.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 16-bit endian converion.
+*
+* @param Data: 16 bit value to be converted
+*
+* @return 16 bit Data with converted endianess
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a 32-bit endian converion.
+*
+* @param Data: 32 bit value to be converted
+*
+* @return 32 bit data with converted endianess
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16) (Data & 0x0000FFFFU);
+ HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+ /* swap the half words before returning the value */
+
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_io.h
new file mode 100644
index 0000000..00207cf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_io.h
@@ -0,0 +1,341 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+*
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_macroback.h
new file mode 100644
index 0000000..cdc2fe2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_macroback.h
@@ -0,0 +1,1048 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mem.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mem.c
new file mode 100644
index 0000000..a869b0a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mem.c
@@ -0,0 +1,79 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief This function copies memory from once location to other.
+*
+* @param dst: pointer pointing to destination memory
+*
+* @param src: pointer pointing to source memory
+*
+* @param cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+ char *d = (char*)(void *)dst;
+ const char *s = src;
+
+ while (cnt >= sizeof (int)) {
+ *(int*)d = *(int*)s;
+ d += sizeof (int);
+ s += sizeof (int);
+ cnt -= sizeof (int);
+ }
+ while ((cnt) > 0U){
+ *d = *s;
+ d += 1U;
+ s += 1U;
+ cnt -= 1U;
+ }
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mem.h
new file mode 100644
index 0000000..afc0f8b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mem.h
@@ -0,0 +1,55 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+*
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_misc_psreset_api.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_misc_psreset_api.c
new file mode 100644
index 0000000..77d6fc1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_misc_psreset_api.c
@@ -0,0 +1,520 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in
+* slcr reset functional blcok.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release
+* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
+*
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XDdr_ResetHw(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert and deassert the ddr softreset bit */
+ RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
+ RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+ RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
+ Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* to postbootrom state.
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XOcm_Remap(void)
+{
+ u32 RegVal;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Map the ocm region to postbootrom state */
+ RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+ RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
+ Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+*
+* @param BaseAddress of the interface
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+ u32 RegVal;
+
+ /* Clear the interuupts */
+ RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+ RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
+ Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+ /* Clear the idle counter registers */
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
+ Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
+ /* Update the ecc registers with reset values */
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
+ XSMC_ECC_MEMCFG1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+ XSMC_ECC_MEMCMD1_RESET_VAL);
+ Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
+ XSMC_ECC_MEMCMD2_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues(void)
+{
+ u32 i;
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Update all the MIO registers with reset values */
+ for (i=0U; i<=1U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+ for (; i<=8U;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_02_RESET_VAL);
+ }
+ for (; i<=53U ;i++)
+ {
+ Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+ XSLCR_MIO_PIN_00_RESET_VAL);
+ }
+
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers
+* with reset values
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues(void)
+{
+
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+
+ /* update the pll control registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
+ /* update the pll config registers with reset values */
+ Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
+ /* update the clock control registers with reset values */
+ Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
+ Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Disable the level shifters */
+ RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
+ Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from
+* the slcr
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr
+* registers
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from
+* the slcr
+*
+* @param N/A.
+*
+* @return N/A.
+*
+* @note None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+ u32 RegVal;
+ /* Unlock the slcr register access lock */
+ Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+ /* Assert the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+ /* Release the reset */
+ RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+ RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
+ Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_misc_psreset_api.h
new file mode 100644
index 0000000..3a26175
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_misc_psreset_api.h
@@ -0,0 +1,273 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mmu.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mmu.c
new file mode 100644
index 0000000..ef5bbfe
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mmu.c
@@ -0,0 +1,227 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+* before enabling back.
+* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
+* translation table and branch predictor arrays are
+* invalidated, D-cache flushed before the attribute
+* change is applied. This is done so that the user
+* need not call Xil_DisableMMU before calling
+* Xil_SetTlbAttributes.
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+* D cache after the translation table update. Removed the
+* redundant TLB invalidation in the same API at the beginning.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+* It fixes CR#1008309.
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
+#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
+/************************** Variable Definitions *****************************/
+
+extern u32 MMUTable;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* @brief This function sets the memory attributes for a section covering 1MB
+* of memory in the translation table.
+*
+* @param Addr: 32-bit address for which memory attributes need to be set.
+* @param attrib: Attribute for the given memory region. xil_mmu.h contains
+* definitions of commonly used memory attributes which can be
+* utilized for this function.
+*
+*
+* @return None.
+*
+* @note The MMU or D-cache does not need to be disabled before changing a
+* translation table entry.
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
+{
+ u32 *ptr;
+ u32 section;
+
+ section = Addr / 0x100000U;
+ ptr = &MMUTable;
+ ptr += section;
+ if(ptr != NULL) {
+ *ptr = (Addr & 0xFFF00000U) | attrib;
+ }
+
+ Xil_DCacheFlush();
+
+ mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+ /* Invalidate all branch predictors */
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+
+ dsb(); /* ensure completion of the BP and TLB invalidation */
+ isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************/
+/**
+* @brief Enable MMU for cortex A9 processor. This function invalidates the
+* instruction and data caches, and then enables MMU.
+*
+* @param None.
+* @return None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+ u32 Reg;
+ Xil_DCacheInvalidate();
+ Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg |= (u32)0x05U;
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+ dsb();
+ isb();
+}
+
+/*****************************************************************************/
+/**
+* @brief Disable MMU for Cortex A9 processors. This function invalidates
+* the TLBs, Branch Predictor Array and flushed the D Caches before
+* disabling the MMU.
+*
+* @param None.
+*
+* @return None.
+*
+* @note When the MMU is disabled, all the memory accesses are treated as
+* strongly ordered.
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+ u32 Reg;
+
+ mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+ mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+ Xil_DCacheFlush();
+
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+ { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+ Reg = Cp15Reg; }
+#endif
+ Reg &= (u32)(~0x05U);
+#ifdef CONFIG_ARM_ERRATA_794073
+ /* Disable Branch Prediction */
+ Reg &= (u32)(~0x800U);
+#endif
+ mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
+
+/*****************************************************************************/
+/**
+* @brief Memory mapping for Cortex A9 processor.
+*
+* @param PhysAddr is physical address.
+* @param size is size of region.
+* @param flags is flags used to set translation table.
+*
+* @return Pointer to virtual address.
+*
+* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
+* functionality is specific to A9 processor.
+*
+******************************************************************************/
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags)
+{
+ u32 Sectionoffset;
+ u32 Ttbaddr;
+
+ if (!flags)
+ return (void*)PhysAddr;
+
+ /* Ensure alignement on a section boundary */
+ PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
+
+ /* Loop through entire region of memory (one MMU section at a time).
+ Each section requires a TTB entry. */
+ for (Sectionoffset = 0; Sectionoffset < size;
+ Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) {
+ /* Calculate translation table entry for this memory section */
+ Ttbaddr = (PhysAddr + Sectionoffset);
+
+ /* Write translation table entry value to entry address */
+ Xil_SetTlbAttributes(Ttbaddr, flags);
+ }
+ return (void*)PhysAddr;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mmu.h
new file mode 100644
index 0000000..3b63c0b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_mmu.h
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_printf.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_printf.c
new file mode 100644
index 0000000..0e6c8a7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_printf.c
@@ -0,0 +1,443 @@
+/*---------------------------------------------------*/
+/* Modified from : */
+/* Public Domain version of printf */
+/* Rud Merriam, Compsult, Inc. Houston, Tx. */
+/* For Embedded Systems Programming, 1991 */
+/* */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include
+#include
+#include
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+ s32 len;
+ s32 num1;
+ s32 num2;
+ char8 pad_character;
+ s32 do_padding;
+ s32 left_flag;
+ s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/* */
+/* This routine puts pad characters into the output */
+/* buffer. */
+/* */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+ s32 i;
+
+ if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+ i=(par->len);
+ for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( par->pad_character);
+#endif
+ }
+ }
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a string to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+static void outs(const charptr lp, struct params_s *par)
+{
+ charptr LocalPtr;
+ LocalPtr = lp;
+ /* pad on left if needed */
+ if(LocalPtr != NULL) {
+ par->len = (s32)strlen( LocalPtr);
+ }
+ padding( !(par->left_flag), par);
+
+ /* Move string to the buffer */
+ while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+ (par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*LocalPtr);
+#endif
+ LocalPtr += 1;
+}
+
+ /* Pad on right if needed */
+ /* CR 439175 - elided next stmt. Seemed bogus. */
+ /* par->len = strlen( lp) */
+ padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a number to the output buffer */
+/* as directed by the padding and positioning flags. */
+/* */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+ s32 negative;
+ s32 i;
+ char8 outbuf[32];
+ const char8 digits[] = "0123456789ABCDEF";
+ u32 num;
+ for(i = 0; i<32; i++) {
+ outbuf[i] = '0';
+ }
+
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = n;
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = 0;
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+ outbyte( outbuf[i] );
+#endif
+ i--;
+}
+ padding( par->left_flag, par);
+}
+/*---------------------------------------------------*/
+/* */
+/* This routine moves a 64-bit number to the output */
+/* buffer as directed by the padding and positioning */
+/* flags. */
+/* */
+#if defined (__aarch64__) || defined (__arch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+ s32 negative;
+ s32 i;
+ char8 outbuf[64];
+ const char8 digits[] = "0123456789ABCDEF";
+ u64 num;
+ for(i = 0; i<64; i++) {
+ outbuf[i] = '0';
+ }
+
+ /* Check if number is negative */
+ if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+ negative = 1;
+ num =(-(n));
+ }
+ else{
+ num = (n);
+ negative = 0;
+ }
+
+ /* Build number (backwards) in outbuf */
+ i = 0;
+ do {
+ outbuf[i] = digits[(num % base)];
+ i++;
+ num /= base;
+ } while (num > 0);
+
+ if (negative != 0) {
+ outbuf[i] = '-';
+ i++;
+ }
+
+ outbuf[i] = 0;
+ i--;
+
+ /* Move the converted number to the buffer and */
+ /* add in the padding where needed. */
+ par->len = (s32)strlen(outbuf);
+ padding( !(par->left_flag), par);
+ while (&outbuf[i] >= outbuf) {
+ outbyte( outbuf[i] );
+ i--;
+}
+ padding( par->left_flag, par);
+}
+#endif
+/*---------------------------------------------------*/
+/* */
+/* This routine gets a number from the format */
+/* string. */
+/* */
+static s32 getnum( charptr* linep)
+{
+ s32 n;
+ s32 ResultIsDigit = 0;
+ charptr cptr;
+ n = 0;
+ cptr = *linep;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ while (ResultIsDigit != 0) {
+ if(cptr != NULL){
+ n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+ cptr += 1;
+ if(cptr != NULL){
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ }
+ ResultIsDigit = isdigit(((s32)*cptr));
+ }
+ *linep = ((charptr )(cptr));
+ return(n);
+}
+
+/*---------------------------------------------------*/
+/* */
+/* This routine operates just like a printf/sprintf */
+/* routine. It outputs a set of data under the */
+/* control of a formatting string. Not all of the */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded */
+/* systems work. Primarily the floating point */
+/* routines are omitted. Other formats could be */
+/* added easily by following the examples shown for */
+/* the supported formats. */
+/* */
+
+/* void esp_printf( const func_ptr f_ptr,
+ const charptr ctrl1, ...) */
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+void xil_printf( const char8 *ctrl1, ...){
+ XPVXenConsole_Printf(ctrl1);
+}
+#else
+void xil_printf( const char8 *ctrl1, ...)
+{
+ s32 Check;
+#if defined (__aarch64__) || defined (__arch64__)
+ s32 long_flag;
+#endif
+ s32 dot_flag;
+
+ params_t par;
+
+ char8 ch;
+ va_list argp;
+ char8 *ctrl = (char8 *)ctrl1;
+
+ va_start( argp, ctrl1);
+
+ while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+ /* move format string chars to buffer until a */
+ /* format control is found. */
+ if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+ outbyte(*ctrl);
+#endif
+ ctrl += 1;
+ continue;
+ }
+
+ /* initialize all the flags for this format. */
+ dot_flag = 0;
+#if defined (__aarch64__) || defined (__arch64__)
+ long_flag = 0;
+#endif
+ par.unsigned_flag = 0;
+ par.left_flag = 0;
+ par.do_padding = 0;
+ par.pad_character = ' ';
+ par.num2=32767;
+ par.num1=0;
+ par.len=0;
+
+ try_next:
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ if(ctrl != NULL) {
+ ch = *ctrl;
+ }
+ else {
+ ch = *ctrl;
+ }
+
+ if (isdigit((s32)ch) != 0) {
+ if (dot_flag != 0) {
+ par.num2 = getnum(&ctrl);
+ }
+ else {
+ if (ch == '0') {
+ par.pad_character = '0';
+ }
+ if(ctrl != NULL) {
+ par.num1 = getnum(&ctrl);
+ }
+ par.do_padding = 1;
+ }
+ if(ctrl != NULL) {
+ ctrl -= 1;
+ }
+ goto try_next;
+ }
+
+ switch (tolower((s32)ch)) {
+ case '%':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( '%');
+#endif
+ Check = 1;
+ break;
+
+ case '-':
+ par.left_flag = 1;
+ Check = 0;
+ break;
+
+ case '.':
+ dot_flag = 1;
+ Check = 0;
+ break;
+
+ case 'l':
+ #if defined (__aarch64__) || defined (__arch64__)
+ long_flag = 1;
+ #endif
+ Check = 0;
+ break;
+
+ case 'u':
+ par.unsigned_flag = 1;
+ /* fall through */
+ case 'i':
+ case 'd':
+ #if defined (__aarch64__) || defined (__arch64__)
+ if (long_flag != 0){
+ outnum1((s64)va_arg(argp, s64), 10L, &par);
+ }
+ else {
+ outnum( va_arg(argp, s32), 10L, &par);
+ }
+ #else
+ outnum( va_arg(argp, s32), 10L, &par);
+ #endif
+ Check = 1;
+ break;
+ case 'p':
+ #if defined (__aarch64__) || defined (__arch64__)
+ par.unsigned_flag = 1;
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ Check = 1;
+ break;
+ #endif
+ case 'X':
+ case 'x':
+ par.unsigned_flag = 1;
+ #if defined (__aarch64__) || defined (__arch64__)
+ if (long_flag != 0) {
+ outnum1((s64)va_arg(argp, s64), 16L, &par);
+ }
+ else {
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ }
+ #else
+ outnum((s32)va_arg(argp, s32), 16L, &par);
+ #endif
+ Check = 1;
+ break;
+
+ case 's':
+ outs( va_arg( argp, char *), &par);
+ Check = 1;
+ break;
+
+ case 'c':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( va_arg( argp, s32));
+#endif
+ Check = 1;
+ break;
+
+ case '\\':
+ switch (*ctrl) {
+ case 'a':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x07));
+#endif
+ break;
+ case 'h':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x08));
+#endif
+ break;
+ case 'r':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+#endif
+ break;
+ case 'n':
+#ifdef STDOUT_BASEADDRESS
+ outbyte( ((char8)0x0D));
+ outbyte( ((char8)0x0A));
+#endif
+ break;
+ default:
+#ifdef STDOUT_BASEADDRESS
+ outbyte( *ctrl);
+#endif
+ break;
+ }
+ ctrl += 1;
+ Check = 0;
+ break;
+
+ default:
+ Check = 1;
+ break;
+ }
+ if(Check == 1) {
+ if(ctrl != NULL) {
+ ctrl += 1;
+ }
+ continue;
+ }
+ goto try_next;
+ }
+ va_end( argp);
+}
+#endif
+/*---------------------------------------------------*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_printf.h
new file mode 100644
index 0000000..016ae3b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+#include
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleepcommon.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleepcommon.c
new file mode 100644
index 0000000..cb28204
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleepcommon.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+*@file xil_sleepcommon.c
+*
+* This file contains the sleep API's
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 srm 11/02/17 First release
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "sleep.h"
+
+/**************************** Constant Definitions *************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This API gives delay in sec
+*
+* @param seconds - delay time in seconds
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+ void sleep(unsigned int seconds)
+ {
+#if defined (ARMR5)
+ sleep_R5(seconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ sleep_A53(seconds);
+#elif defined (__MICROBLAZE__)
+ sleep_MB(seconds);
+#else
+ sleep_A9(seconds);
+#endif
+
+ }
+
+/****************************************************************************/
+/**
+*
+* This API gives delay in usec
+*
+* @param useconds - delay time in useconds
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+ void usleep(unsigned long useconds)
+ {
+#if defined (ARMR5)
+ usleep_R5(useconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+ usleep_A53(useconds);
+#elif defined (__MICROBLAZE__)
+ usleep_MB(useconds);
+#else
+ usleep_A9(useconds);
+#endif
+
+ }
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleeptimer.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleeptimer.c
new file mode 100644
index 0000000..8fb7f6b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleeptimer.c
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.c
+*
+* This file provides the common helper routines for the sleep API's
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
+*
+*
+*****************************************************************************/
+
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xil_sleeptimer.h"
+#include "xtime_l.h"
+
+/**************************** Constant Definitions *************************/
+
+
+/* Function definitions are applicable only when TTC3 is present*/
+#if defined (SLEEP_TIMER_BASEADDR)
+/****************************************************************************/
+/**
+*
+* This is a helper function used by sleep/usleep APIs to
+* have delay in sec/usec
+*
+* @param delay - delay time in seconds/micro seconds
+*
+* @param frequency - Number of counts per second/micro second
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void Xil_SleepTTCCommon(u32 delay, u64 frequency)
+{
+ u64 tEnd = 0U;
+ u64 tCur = 0U;
+ XCntrVal TimeHighVal = 0U;
+ XCntrVal TimeLowVal1 = 0U;
+ XCntrVal TimeLowVal2 = 0U;
+
+ TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
+ do
+ {
+ TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+ if (TimeLowVal2 < TimeLowVal1) {
+ TimeHighVal++;
+ }
+ TimeLowVal1 = TimeLowVal2;
+ tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
+ (u64)TimeLowVal2;
+ }while (tCur < tEnd);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This API starts the Triple Timer Counter
+*
+* @param none
+*
+* @return none
+*
+* @note none
+*
+*****************************************************************************/
+void XTime_StartTTCTimer()
+{
+ u32 TimerPrescalar;
+ u32 TimerCntrl;
+
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+ u32 LpdRst;
+
+ LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2);
+
+ /* check if the timer is reset */
+ if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+ XSLEEP_TTC_INSTANCE)) != 0 )) {
+ LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+ XSLEEP_TTC_INSTANCE));
+ Xil_Out32(RST_LPD_IOU2, LpdRst);
+ } else {
+#endif
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ /* check if Timer is disabled */
+ if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ /* check if Timer is configured with proper functionalty for sleep */
+ if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
+ return;
+ }
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+ }
+#endif
+ /* Disable the timer to configure */
+ TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+ TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+ /* Disable the prescalar */
+ TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+ XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+ TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
+ TimerPrescalar);
+ /* Enable the Timer */
+ TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
+ Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+ TimerCntrl);
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleeptimer.h
new file mode 100644
index 0000000..4449ba6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_sleeptimer.h
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+*
+*
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testcache.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testcache.c
new file mode 100644
index 0000000..6ea52a8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testcache.c
@@ -0,0 +1,367 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
+* cache line.
+*
+*
+* @note
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
+* and Xil_DCacheInvalidateRange. This test function writes a constant
+* value to the Data array, flushes the range, writes a new value, then
+* invalidates the corresponding range.
+* @param None
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestDCacheRange(void)
+{
+ s32 Index;
+ s32 Status = 0;
+ u32 CtrlReg;
+ INTPTR Value;
+
+ xil_printf("-- Cache Range Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A00505;
+
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" flush range done\r\n");
+
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A00505) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush worked\r\n");
+ }
+ else {
+ xil_printf("Error: flush dcache range not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0C505;
+
+
+
+ Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+ xil_printf(" invalidate dcache range done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0xA0A0A05;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0xA0A0A05) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+
+ if (!Status) {
+ xil_printf(" Invalidate worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache range not working\r\n");
+ }
+ xil_printf("-- Cache Range Test Complete --\r\n");
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value,
+* then invalidates the DCache.
+*
+* @return
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*****************************************************************************/
+s32 Xil_TestDCacheAll(void)
+{
+ s32 Index;
+ s32 Status;
+ INTPTR Value;
+ u32 CtrlReg;
+
+ xil_printf("-- Cache All Test --\n\r");
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50500A0A;
+ xil_printf(" initialize Data done:\r\n");
+
+ Xil_DCacheFlush();
+ xil_printf(" flush all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+
+ if (Value != 0x50500A0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Flush all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Flush dcache all not working\r\n");
+ }
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x505FFA0A;
+
+ Xil_DCacheFlush();
+
+
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = Index + 3;
+
+ Xil_DCacheInvalidate();
+
+ xil_printf(" invalidate all done\r\n");
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ for (Index = 0; Index < DATA_LENGTH; Index++)
+ Data[Index] = 0x50CFA0A;
+ dsb();
+ #ifdef __aarch64__
+ CtrlReg = mfcp(SCTLR_EL3);
+ CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+ mtcp(SCTLR_EL3,CtrlReg);
+ #else
+ CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+ CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+ mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+ #endif
+ dsb();
+ Status = 0;
+
+ for (Index = 0; Index < DATA_LENGTH; Index++) {
+ Value = Data[Index];
+ if (Value != 0x50CFA0A) {
+ Status = -1;
+ xil_printf("Data[%d] = %x\r\n", Index, Value);
+ break;
+ }
+ }
+
+ if (!Status) {
+ xil_printf(" Invalidate all worked\r\n");
+ }
+ else {
+ xil_printf("Error: Invalidate dcache all not working\r\n");
+ }
+
+ xil_printf("-- DCache all Test Complete --\n\r");
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+* - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheRange(void)
+{
+
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+ Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+ xil_printf("-- Invalidate icache range done --\r\n");
+
+ return 0;
+}
+
+/*****************************************************************************/
+/**
+* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
+*
+* @return
+* - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheAll(void)
+{
+ Xil_ICacheInvalidate();
+ xil_printf("-- Invalidate icache all done --\r\n");
+ return 0;
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testcache.h
new file mode 100644
index 0000000..8289ca9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testcache.h
@@ -0,0 +1,67 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+*
Cache test
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testio.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testio.c
new file mode 100644
index 0000000..9a13a64
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testio.c
@@ -0,0 +1,295 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.c
+*
+* Contains the memory test utility functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param Data is the 16-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+ return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param Data is the 32-bit word to be swapped.
+ * @return The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+ u16 Lo16;
+ u16 Hi16;
+
+ u16 Swap16Lo;
+ u16 Swap16Hi;
+
+ Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+ Lo16 = (u16)(Data & 0x0000FFFFU);
+
+ Swap16Lo = Swap16(Lo16);
+ Swap16Hi = Swap16(Hi16);
+
+ return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 8-bit wide register IO test where the
+* register is accessed using Xil_Out8 and Xil_In8, and comparing
+* the written values by reading them back.
+*
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writting the memory.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+ u8 ValueIn;
+ s32 Index;
+ s32 Status = 0;
+
+ for (Index = 0; Index < Length; Index++) {
+ Xil_Out8((INTPTR)Addr, Value);
+
+ ValueIn = Xil_In8((INTPTR)Addr);
+
+ if ((Value != ValueIn) && (Status == 0)) {
+ Status = -1;
+ break;
+ }
+ }
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 16-bit wide register IO test. Each location
+* is tested by sequentially writing a 16-bit wide register, reading
+* the register, and comparing value. This function tests three kinds
+* of register IO functions, normal register IO, little-endian register
+* IO, and big-endian register IO. When testing little/big-endian IO,
+* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+* Compare In-Out values. Whether to swap the read-in value before
+* comparing is controlled by the 5th argument.
+*
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writting the memory.
+* @param Kind: Type of test. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+ u16 *TempAddr16;
+ u16 ValueIn = 0U;
+ s32 Index;
+ TempAddr16 = Addr;
+ Xil_AssertNonvoid(TempAddr16 != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out16LE((INTPTR)TempAddr16, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out16BE((INTPTR)TempAddr16, Value);
+ break;
+ default:
+ Xil_Out16((INTPTR)TempAddr16, Value);
+ break;
+ }
+
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out16((INTPTR)TempAddr16, Value);
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+ break;
+ default:
+ ValueIn = Xil_In16((INTPTR)TempAddr16);
+ break;
+ }
+
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap16(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr16 += sizeof(u16);
+ }
+ return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 32-bit wide register IO test. Each location
+* is tested by sequentially writing a 32-bit wide regsiter, reading
+* the register, and comparing value. This function tests three kinds
+* of register IO functions, normal register IO, little-endian register IO,
+* and big-endian register IO. When testing little/big-endian IO,
+* the function perform the following sequence, Xil_Out32LE/
+* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+* Whether to swap the read-in value *before comparing is controlled
+* by the 5th argument.
+* @param Addr: a pointer to the region of memory to be tested.
+* @param Length: Length of the block.
+* @param Value: constant used for writting the memory.
+* @param Kind: type of test. Acceptable values are:
+* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+ u32 *TempAddr;
+ u32 ValueIn = 0U;
+ s32 Index;
+ TempAddr = Addr;
+ Xil_AssertNonvoid(TempAddr != NULL);
+
+ for (Index = 0; Index < Length; Index++) {
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ Xil_Out32LE((INTPTR)TempAddr, Value);
+ break;
+ case XIL_TESTIO_BE:
+ Xil_Out32BE((INTPTR)TempAddr, Value);
+ break;
+ default:
+ Xil_Out32((INTPTR)TempAddr, Value);
+ break;
+ }
+
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+
+ /* second round */
+ Xil_Out32((INTPTR)TempAddr, Value);
+
+
+ switch (Kind) {
+ case XIL_TESTIO_LE:
+ ValueIn = Xil_In32LE((INTPTR)TempAddr);
+ break;
+ case XIL_TESTIO_BE:
+ ValueIn = Xil_In32BE((INTPTR)TempAddr);
+ break;
+ default:
+ ValueIn = Xil_In32((INTPTR)TempAddr);
+ break;
+ }
+
+ if ((Kind != 0) && (Swap != 0)) {
+ ValueIn = Swap32(ValueIn);
+ }
+
+ if (Value != ValueIn) {
+ return -1;
+ }
+ TempAddr += sizeof(u32);
+ }
+ return 0;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testio.h
new file mode 100644
index 0000000..6f0fc1c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testio.h
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+*
I/O test
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testmem.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testmem.c
new file mode 100644
index 0000000..b7eb68b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testmem.c
@@ -0,0 +1,864 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 32-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: test type selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+* - 0 is returned for a pass
+* - 1 is returned for a failure
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u32 Val;
+ u32 FirtVal;
+ u32 WordMem32;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ *(Addr+I) = Val;
+ Val++;
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (1U << j);
+
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u32) RotateLeft(Val, 32U);
+ }
+
+ /*
+ * Restore the reference 'val' to the
+ * initial value
+ */
+ Val = 1U << j;
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = (u32)RotateLeft(Val, 32U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible
+ * initial test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)32; j++) {
+
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = ~(1U << j);
+
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)32; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+
+ Val = ~(1U << j);
+
+ /* Read the values from each location that was
+ * written */
+ for (I = 0U; I < (u32)32; I++) {
+ /* read memory location */
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u32)RotateLeft(~Val, 32U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* Read the location */
+ WordMem32 = *(Addr+I);
+ Val = (u32) (~((INTPTR) (&Addr[I])));
+
+ if ((WordMem32 ^ Val) != 0x00000000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u32)0) {
+ Val = 0xDEADBEEFU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+
+ /* read memory location */
+
+ WordMem32 = *(Addr+I);
+ if (WordMem32 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 16-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant Pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: type of test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u16 Val;
+ u16 FirtVal;
+ u16 WordMem16;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * selectthe proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+
+ Val = (u16)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u16)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u16)RotateLeft(Val, 16U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)16; j++) {
+ /*
+ * Generate an initial value for walking ones
+ * test to test for bad
+ * data bits
+ */
+
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+
+ for (I = 0U; I < (u32)16; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)16; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = ~((u16)RotateLeft(~Val, 16U));
+ }
+
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u16) (~((INTPTR)(&Addr[I])));
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ Val = (u16) (~((INTPTR) (&Addr[I])));
+ if ((WordMem16 ^ Val) != 0x0000U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+ if (Pattern == (u16)0) {
+ Val = 0xDEADU;
+ }
+ else {
+ Val = Pattern;
+ }
+
+ /*
+ * Fill the memory with fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem16 = *(Addr+I);
+ if (WordMem16 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Perform a destructive 8-bit wide memory test.
+*
+* @param Addr: pointer to the region of memory to be tested.
+* @param Words: length of the block.
+* @param Pattern: constant used for the constant pattern test, if 0,
+* 0xDEADBEEF is used.
+* @param Subtest: type of test selected. See xil_testmem.h for possible
+* values.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+ u32 I;
+ u32 j;
+ u8 Val;
+ u8 FirtVal;
+ u8 WordMem8;
+ s32 Status = 0;
+
+ Xil_AssertNonvoid(Words != (u32)0);
+ Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+ Xil_AssertNonvoid(Addr != NULL);
+
+ /*
+ * variable initialization
+ */
+ Val = XIL_TESTMEM_INIT_VALUE;
+ FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+ /*
+ * select the proper Subtest(s)
+ */
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+ /*
+ * Fill the memory with incrementing
+ * values starting from 'FirtVal'
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val++;
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = FirtVal;
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the incrementing reference
+ * Val
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val++;
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+ /*
+ * set up to cycle through all possible initial
+ * test Patterns for walking ones test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test
+ * to test for bad data bits
+ */
+ Val = (u8)((u32)1 << j);
+ /*
+ * START walking ones test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = (u8)((u32)1 << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ Val = (u8)RotateLeft(Val, 8U);
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+ /*
+ * set up to cycle through all possible initial test
+ * Patterns for walking zeros test
+ */
+
+ for (j = 0U; j < (u32)8; j++) {
+ /*
+ * Generate an initial value for walking ones test to test
+ * for bad data bits
+ */
+ Val = ~(1U << j);
+ /*
+ * START walking zeros test
+ * Write a one to each data bit indifferent locations
+ */
+ for (I = 0U; I < (u32)8; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ /*
+ * Restore the reference 'Val' to the
+ * initial value
+ */
+ Val = ~(1U << j);
+ /* Read the values from each location that was written */
+ for (I = 0U; I < (u32)8; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+
+ Val = ~((u8)RotateLeft(~Val, 8U));
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+ /* Fill the memory with inverse of address */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ *(Addr+I) = Val;
+ }
+
+ /*
+ * Check every word within the words
+ * of tested memory
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ Val = (u8) (~((INTPTR) (&Addr[I])));
+ if ((WordMem8 ^ Val) != 0x00U) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+ if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+ /*
+ * Generate an initial value for
+ * memory testing
+ */
+
+ if (Pattern == (u8)0) {
+ Val = 0xA5U;
+ }
+ else {
+ Val = Pattern;
+ }
+ /*
+ * Fill the memory with fixed Pattern
+ */
+ for (I = 0U; I < Words; I++) {
+ /* write memory location */
+ *(Addr+I) = Val;
+ }
+ /*
+ * Check every word within the words
+ * of tested memory and compare it
+ * with the fixed Pattern
+ */
+
+ for (I = 0U; I < Words; I++) {
+ /* read memory location */
+ WordMem8 = *(Addr+I);
+ if (WordMem8 != Val) {
+ Status = -1;
+ goto End_Label;
+ }
+ }
+ }
+
+End_Label:
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief Rotates the provided value to the left one bit position
+*
+* @param Input is value to be rotated to the left
+* @param Width is the number of bits in the input data
+*
+* @return
+* The resulting unsigned long value of the rotate left
+*
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+ u32 Msb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+ /*
+ * set the Width of the Input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ Msb = LocalInput & MsbMask;
+
+ ReturnVal = LocalInput << 1U;
+
+ if (Msb != 0x00000000U) {
+ ReturnVal = ReturnVal | (u32)0x00000001;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* @brief Rotates the provided value to the right one bit position
+*
+* @param Input: value to be rotated to the right
+* @param Width: number of bits in the input data
+*
+* @return
+* The resulting u32 value of the rotate right
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+ u32 Lsb;
+ u32 ReturnVal;
+ u32 WidthMask;
+ u32 MsbMask;
+ u32 LocalInput = Input;
+ /*
+ * set up the WidthMask and the MsbMask
+ */
+
+ MsbMask = 1U << (Width - 1U);
+
+ WidthMask = (MsbMask << 1U) - 1U;
+
+ /*
+ * set the width of the input to the correct width
+ */
+
+ LocalInput = LocalInput & WidthMask;
+
+ ReturnVal = LocalInput >> 1U;
+
+ Lsb = LocalInput & 0x00000001U;
+
+ if (Lsb != 0x00000000U) {
+ ReturnVal = ReturnVal | MsbMask;
+ }
+
+ ReturnVal = ReturnVal & WidthMask;
+
+ return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testmem.h
new file mode 100644
index 0000000..ecce6b7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_testmem.h
@@ -0,0 +1,154 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+*
Memory test
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+* - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+* @endcode
+*
+* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*@endcode
+*
+* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_types.h
new file mode 100644
index 0000000..8adaf1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xil_types.h
@@ -0,0 +1,205 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#include
+#include
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc.h
new file mode 100644
index 0000000..22373c1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc.h
@@ -0,0 +1,168 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc_counter.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc_counter.c
new file mode 100644
index 0000000..465be05
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc_counter.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.c
+*
+* This file contains APIs for configuring and controlling the event counters
+* in PL310 L2 cache controller. For more information about the event counters,
+* see xl2cc_counter.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xparameters_ps.h"
+#include "xl2cc_counter.h"
+#include "xl2cc.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XL2cc_EventCtrReset(void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief This function initializes the event counters in L2 Cache controller
+* with a set of event codes specified by the user.
+*
+* @param Event0: Event code for counter 0.
+* @param Event1: Event code for counter 1.
+*
+* @return None.
+*
+* @note The definitions for event codes XL2CC_* can be found in
+* xl2cc_counter.h.
+*
+*****************************************************************************/
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
+{
+
+ /* Write event code into cnt1 cfg reg */
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
+
+ /* Write event code into cnt0 cfg reg */
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
+
+ /* Reset counters */
+ XL2cc_EventCtrReset();
+}
+
+
+/****************************************************************************/
+/**
+*
+* @brief This function starts the event counters in L2 Cache controller.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStart(void)
+{
+ u32 *LocalPtr;
+ LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
+ XL2cc_EventCtrReset();
+
+ /* Enable counter */
+ /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
+ *LocalPtr = (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the event counters in L2 Cache controller,
+* saves the counter values and resets the counters.
+*
+* @param EveCtr0: Output parameter which is used to return the value
+* in event counter 0.
+* EveCtr1: Output parameter which is used to return the value
+* in event counter 1.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
+{
+ /* Disable counter */
+ *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
+
+ /* Save counter values */
+ *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
+ *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
+
+ XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function resets the event counters in L2 Cache controller.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrReset(void)
+{
+ *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc_counter.h
new file mode 100644
index 0000000..b8d768f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xl2cc_counter.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO 0x1
+#define XL2CC_DRHIT 0x2
+#define XL2CC_DRREQ 0x3
+#define XL2CC_DWHIT 0x4
+#define XL2CC_DWREQ 0x5
+#define XL2CC_DWTREQ 0x6
+#define XL2CC_IRHIT 0x7
+#define XL2CC_IRREQ 0x8
+#define XL2CC_WA 0x9
+#define XL2CC_IPFALLOC 0xa
+#define XL2CC_EPFHIT 0xb
+#define XL2CC_EPFALLOC 0xc
+#define XL2CC_SRRCVD 0xd
+#define XL2CC_SRCONF 0xe
+#define XL2CC_EPFRCVD 0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xparameters_ps.h
new file mode 100644
index 0000000..2a6a0e0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xparameters_ps.h
@@ -0,0 +1,334 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xplatform_info.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xplatform_info.c
new file mode 100644
index 0000000..53459c2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xplatform_info.c
@@ -0,0 +1,157 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00 pkp 12/15/14 Initial release
+* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
+* mode
+* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+* ms 06/13/17 Added PSU_PMU macro to provide support of
+* XGetPlatform_Info function for PMUFW.
+* mus 08/17/17 Add EL1 NS mode support for
+* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+* APIs.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xplatform_info.h"
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about platform
+*
+* @param None.
+*
+* @return The information about platform defined in xplatform_info.h
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+ return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+ return XPLAT_MICROBLAZE;
+#else
+ return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about zynq ultrascale MP platform
+*
+* @param None.
+*
+* @return The information about zynq ultrascale MP platform defined in
+* xplatform_info.h
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+#if EL1_NONSECURE
+ XSmc_OutVar reg;
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
+ u32 reg;
+ reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+ return reg;
+#endif
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief This API is used to provide information about PS Silicon version
+*
+* @param None.
+*
+* @return The information about PS Silicon version.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info()
+{
+#if EL1_NONSECURE
+ /*
+ * This SMC call will return,
+ * idcode - upper 32 bits of reg.Arg0
+ * version - lower 32 bits of reg.Arg1
+ */
+ XSmc_OutVar reg;
+ reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+ return (u32)(reg.Arg1 & XPS_VERSION_INFO_MASK);
+#else
+ u32 reg;
+ reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+ & XPS_VERSION_INFO_MASK);
+ return reg;
+#endif
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xplatform_info.h
new file mode 100644
index 0000000..771d4ba
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xplatform_info.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+*
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info(void);
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpm_counter.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpm_counter.c
new file mode 100644
index 0000000..482671e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpm_counter.c
@@ -0,0 +1,293 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
+* Xpm_ResetEventCounters to fix CR#796275
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+ /* Disable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function enables the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+ /* Enable the event counters */
+ mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function resets the Cortex A9 event counters.
+*
+* @param None.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+ u32 Reg;
+#ifdef __GNUC__
+ Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+#else
+ { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+ Reg = C15Reg; }
+#endif
+ Reg |= (1U << 1U); /* reset event counters */
+ mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+
+}
+
+/****************************************************************************/
+/**
+* @brief This function configures the Cortex A9 event counters controller,
+* with the event codes, in a configuration selected by the user and
+* enables the counters.
+*
+* @param PmcrCfg: Configuration value based on which the event counters
+* are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
+* be utilized for setting configuration.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+ u32 Counter;
+ static PmcrEventCfg32 PmcrEvents[] = {
+ {
+ XPM_EVENT_SOFTINCR,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+ {
+ XPM_EVENT_DATA_READS,
+ XPM_EVENT_DATA_WRITE,
+ XPM_EVENT_EXCEPTION,
+ XPM_EVENT_EXCEPRETURN,
+ XPM_EVENT_CHANGECONTEXT,
+ XPM_EVENT_SW_CHANGEPC
+ },
+ {
+ XPM_EVENT_IMMEDBRANCH,
+ XPM_EVENT_UNALIGNEDACCESS,
+ XPM_EVENT_BRANCHMISS,
+ XPM_EVENT_CLOCKCYCLES,
+ XPM_EVENT_BRANCHPREDICT,
+ XPM_EVENT_JAVABYTECODE
+ },
+ {
+ XPM_EVENT_SWJAVABYTECODE,
+ XPM_EVENT_JAVABACKBRANCH,
+ XPM_EVENT_COHERLINEMISS,
+ XPM_EVENT_COHERLINEHIT,
+ XPM_EVENT_INSTRSTALL,
+ XPM_EVENT_DATASTALL
+ },
+ {
+ XPM_EVENT_MAINTLBSTALL,
+ XPM_EVENT_STREXPASS,
+ XPM_EVENT_STREXFAIL,
+ XPM_EVENT_DATAEVICT,
+ XPM_EVENT_NODISPATCH,
+ XPM_EVENT_ISSUEEMPTY
+ },
+ {
+ XPM_EVENT_INSTRRENAME,
+ XPM_EVENT_PREDICTFUNCRET,
+ XPM_EVENT_MAINEXEC,
+ XPM_EVENT_SECEXEC,
+ XPM_EVENT_LDRSTR,
+ XPM_EVENT_FLOATRENAME
+ },
+ {
+ XPM_EVENT_NEONRENAME,
+ XPM_EVENT_PLDSTALL,
+ XPM_EVENT_WRITESTALL,
+ XPM_EVENT_INSTRTLBSTALL,
+ XPM_EVENT_DATATLBSTALL,
+ XPM_EVENT_INSTR_uTLBSTALL
+ },
+ {
+ XPM_EVENT_DATA_uTLBSTALL,
+ XPM_EVENT_DMB_STALL,
+ XPM_EVENT_INT_CLKEN,
+ XPM_EVENT_DE_CLKEN,
+ XPM_EVENT_INSTRISB,
+ XPM_EVENT_INSTRDSB
+ },
+ {
+ XPM_EVENT_INSTRDMB,
+ XPM_EVENT_EXTINT,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_PLE_OVFL,
+ XPM_EVENT_PLE_PROG,
+ XPM_EVENT_PLE_LRC,
+ XPM_EVENT_PLE_LRS,
+ XPM_EVENT_PLE_FLUSH,
+ XPM_EVENT_PLE_CMPL
+ },
+ {
+ XPM_EVENT_DATASTALL,
+ XPM_EVENT_INSRFETCH_CACHEREFILL,
+ XPM_EVENT_INSTRFECT_TLBREFILL,
+ XPM_EVENT_DATA_CACHEREFILL,
+ XPM_EVENT_DATA_CACHEACCESS,
+ XPM_EVENT_DATA_TLBREFILL
+ },
+ };
+ const u32 *ptr = PmcrEvents[PmcrCfg];
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+ /* Selecet event counter */
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+ /* Set the event */
+ mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+ }
+
+ Xpm_ResetEventCounters();
+ Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief This function disables the event counters and returns the counter
+* values.
+*
+* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
+* It is an output parameter which is used to return the PM
+* counter values.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+ u32 Counter;
+
+ Xpm_DisableEventCounters();
+
+ for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+ mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+ PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#elif defined (__ICCARM__)
+ mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
+#else
+ { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+ PmCtrValue[Counter] = Cp15Reg; }
+#endif
+ }
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpm_counter.h
new file mode 100644
index 0000000..39db7d8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpm_counter.h
@@ -0,0 +1,572 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpseudo_asm.h
new file mode 100644
index 0000000..8000a68
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpseudo_asm.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..85b067d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xpseudo_asm_gcc.h
@@ -0,0 +1,252 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+*
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xreg_cortexa9.h
new file mode 100644
index 0000000..ad93665
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xreg_cortexa9.h
@@ -0,0 +1,587 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+*
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xstatus.h
new file mode 100644
index 0000000..c6e18ab
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xstatus.h
@@ -0,0 +1,531 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /*!< An error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /*!< An error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /*!< The device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /*!< There was no data available */
+#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /*!< The device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
+#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /*!< Device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /*!< Used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /*!< Used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /*!< Driver defined error */
+#define XST_RECV_ERROR 27L /*!< Generic receive error */
+#define XST_SEND_ERROR 28L /*!< Generic transmit error */
+#define XST_NOT_ENABLED 29L /*!< A requested service is not
+ available because it has not
+ been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500 *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
+ * empty and full simultaneously
+ */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
+ error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
+#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
+ * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
+#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
+ device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /*!< Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /*!< Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
+ */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xtime_l.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xtime_l.c
new file mode 100644
index 0000000..a687473
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xtime_l.c
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A9 MP core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+*
+*
+* @note None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+* @brief Set the time in the Global Timer Counter Register.
+*
+* @param Xtime_Global: 64-bit Value to be written to the Global Timer
+* Counter Register.
+*
+* @return None.
+*
+* @note When this function is called by any one processor in a multi-
+* processor environment, reference time will reset/lost for all
+* processors.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+ /* Disable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
+
+ /* Updating Global Timer Counter Register */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
+ (u32)((u32)(Xtime_Global>>32U)));
+
+ /* Enable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
+}
+
+/****************************************************************************/
+/**
+* @brief Get the time from the Global Timer Counter Register.
+*
+* @param Xtime_Global: Pointer to the 64-bit location which will be
+* updated with the current timer value.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+ u32 low;
+ u32 high;
+
+ /* Reading Global Timer Counter Register */
+ do
+ {
+ high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+ low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+ } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+ *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xtime_l.h
new file mode 100644
index 0000000..12004e1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/standalone_v6_8/src/xtime_l.h
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#ifdef __GNUC__
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/Makefile
new file mode 100644
index 0000000..88b1e62
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps.c
new file mode 100644
index 0000000..944afa1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps.c
@@ -0,0 +1,642 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue.
+* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+ u32 ByteCount);
+
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param Config is a reference to a structure containing information
+* about a specific XUartPs driver.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the address
+* mapping from EffectiveAddr to the device physical base address
+* unchanged once this function is invoked. Unexpected errors may
+* occur if the address mapping changes after this function is
+* called. If address translation is not used, pass in the physical
+* address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+* - XST_UART_BAUD_ERROR if the baud rate is not possible because
+* the inputclock frequency is not divisible with an acceptable
+* amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr)
+{
+ s32 Status;
+ u32 ModeRegister;
+ u32 BaudRate;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Config != NULL);
+
+ /* Setup the driver instance using passed in parameters */
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+ InstancePtr->Config.InputClockHz = Config->InputClockHz;
+ InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+ /* Initialize other instance data to default values */
+ InstancePtr->Handler = (XUartPs_Handler)XUartPs_StubHandler;
+
+ InstancePtr->SendBuffer.NextBytePtr = NULL;
+ InstancePtr->SendBuffer.RemainingBytes = 0U;
+ InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+ InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+ InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+ InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+ /* Initialize the platform data */
+ InstancePtr->Platform = XGetPlatform_Info();
+
+ InstancePtr->is_rxbs_error = 0U;
+
+ /* Flag that the driver instance is ready to use */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ /*
+ * Set the default baud rate here, can be changed prior to
+ * starting the device
+ */
+ BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+ Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+ if (Status != (s32)XST_SUCCESS) {
+ InstancePtr->IsReady = 0U;
+ } else {
+
+ /*
+ * Set up the default data format: 8 bit data, 1 stop bit, no
+ * parity
+ */
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Mask off what's already there */
+ ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+ (u32)XUARTPS_MR_STOPMODE_MASK |
+ (u32)XUARTPS_MR_PARITY_MASK));
+
+ /* Set the register value to the desired data format */
+ ModeRegister |= ((u32)XUARTPS_MR_CHARLEN_8_BIT |
+ (u32)XUARTPS_MR_STOPMODE_1_BIT |
+ (u32)XUARTPS_MR_PARITY_NONE);
+
+ /* Write the mode register out */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ /* Set the RX FIFO trigger at 8 data bytes. */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET, 0x08U);
+
+ /* Set the RX timeout to 1, which will be 4 character time */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+ /* Disable all interrupts, polled mode is the default */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ Status = XST_SUCCESS;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param BufferPtr is pointer to a buffer of data to be sent.
+* @param NumBytes contains the number of bytes to be sent. A value of
+* zero will stop a previous send operation that is in progress
+* in interrupt mode. Any data that was already put into the
+* transmit FIFO will be sent.
+*
+* @return The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+*
+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+ u32 NumBytes)
+{
+ u32 BytesSent;
+
+ /* Asserts validate the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the UART transmit interrupts to allow this call to stop a
+ * previous operation that may be interrupt driven.
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+ /* Setup the buffer parameters */
+ InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+ InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+ InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+ /*
+ * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+ * filling the TX FIFO.
+ */
+ BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+ return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param BufferPtr is pointer to buffer for data to be received into
+* @param NumBytes is the number of bytes to be received. A value of zero
+* will stop a previous receive operation that is in progress in
+* interrupt mode.
+*
+* @return The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+ u8 *BufferPtr, u32 NumBytes)
+{
+ u32 ReceivedCount;
+ u32 ImrRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(BufferPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable all the interrupts.
+ * This stops a previous operation that may be interrupt driven
+ */
+ ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ /* Setup the buffer parameters */
+ InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+ InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+ /* Receive the data from the device */
+ ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+ /* Restore the interrupt state */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+ ImrRegister);
+
+ return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return The number of bytes actually sent
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+ u32 SentCount = 0U;
+ u32 ImrRegister;
+
+ /*
+ * If the TX FIFO is full, send nothing.
+ * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+ * data has been put into the FIFO.
+ */
+ while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+ (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+ /* Fill the FIFO from the buffer */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FIFO_OFFSET,
+ ((u32)InstancePtr->SendBuffer.
+ NextBytePtr[SentCount]));
+
+ /* Increment the send count. */
+ SentCount++;
+ }
+
+ /* Update the buffer to reflect the bytes that were sent from it */
+ InstancePtr->SendBuffer.NextBytePtr += SentCount;
+ InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+ /*
+ * If interrupts are enabled as indicated by the receive interrupt, then
+ * enable the TX FIFO empty interrupt, so further action can be taken
+ * for this sending.
+ */
+ ImrRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+ ((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+ ((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IER_OFFSET,
+ ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+ }
+
+ return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return The number of bytes received.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+ u32 CsrRegister;
+ u32 ReceivedCount = 0U;
+ u32 ByteStatusValue, EventData;
+ u32 Event;
+
+ /*
+ * Read the Channel Status Register to determine if there is any data in
+ * the RX FIFO
+ */
+ CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+
+ /*
+ * Loop until there is no more data in RX FIFO or the specified
+ * number of bytes has been received
+ */
+ while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
+ (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+ if (InstancePtr->is_rxbs_error) {
+ ByteStatusValue = XUartPs_ReadReg(
+ InstancePtr->Config.BaseAddress,
+ XUARTPS_RXBS_OFFSET);
+ if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+ EventData = ByteStatusValue;
+ Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+ /*
+ * Call the application handler to indicate that there is a receive
+ * error or a break interrupt, if the application cares about the
+ * error it call a function to get the last errors.
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ Event, EventData);
+ }
+ }
+
+ InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+ XUartPs_ReadReg(InstancePtr->Config.
+ BaseAddress,
+ XUARTPS_FIFO_OFFSET);
+
+ ReceivedCount++;
+
+ CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+ }
+ InstancePtr->is_rxbs_error = 0;
+ /*
+ * Update the receive buffer to reflect the number of bytes just
+ * received
+ */
+ if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+ InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+ }
+ InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+ return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param BaudRate to be set
+*
+* @return
+* - XST_SUCCESS if everything configured as expected
+* - XST_UART_BAUD_ERROR if the requested rate is not available
+* because there was too much error
+*
+* @note None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+ u32 IterBAUDDIV; /* Iterator for available baud divisor values */
+ u32 BRGR_Value; /* Calculated value for baud rate generator */
+ u32 CalcBaudRate; /* Calculated baud rate */
+ u32 BaudError; /* Diff between calculated and requested baud rate */
+ u32 Best_BRGR = 0U; /* Best value for baud rate generator */
+ u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
+ u32 Best_Error = 0xFFFFFFFFU;
+ u32 PercentError;
+ u32 ModeReg;
+ u32 InputClk;
+
+ /* Asserts validate the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+ Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+ /*
+ * Make sure the baud rate is not impossilby large.
+ * Fastest possible baud rate is Input Clock / 2.
+ */
+ if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+ return XST_UART_BAUD_ERROR;
+ }
+ /* Check whether the input clock is divided by 8 */
+ ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ InputClk = InstancePtr->Config.InputClockHz;
+ if(ModeReg & XUARTPS_MR_CLKSEL) {
+ InputClk = InstancePtr->Config.InputClockHz / 8;
+ }
+
+ /*
+ * Determine the Baud divider. It can be 4to 254.
+ * Loop through all possible combinations
+ */
+ for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+ /* Calculate the value for BRGR register */
+ BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+ /* Calculate the baud rate from the BRGR value */
+ CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+ /* Avoid unsigned integer underflow */
+ if (BaudRate > CalcBaudRate) {
+ BaudError = BaudRate - CalcBaudRate;
+ }
+ else {
+ BaudError = CalcBaudRate - BaudRate;
+ }
+
+ /* Find the calculated baud rate closest to requested baud rate. */
+ if (Best_Error > BaudError) {
+
+ Best_BRGR = BRGR_Value;
+ Best_BAUDDIV = IterBAUDDIV;
+ Best_Error = BaudError;
+ }
+ }
+
+ /* Make sure the best error is not too large. */
+ PercentError = (Best_Error * 100) / BaudRate;
+ if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+ return XST_UART_BAUD_ERROR;
+ }
+
+ /* Disable TX and RX to avoid glitches when setting the baud rate. */
+ XUartPs_DisableUart(InstancePtr);
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+ /* RX and TX SW reset */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+ XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+ /* Enable device */
+ XUartPs_EnableUart(InstancePtr);
+
+ InstancePtr->BaudRate = BaudRate;
+
+ return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param CallBackRef is unused by this function.
+* @param Event is unused by this function.
+* @param ByteCount is unused by this function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+ u32 ByteCount)
+{
+ (void) CallBackRef;
+ (void) Event;
+ (void) ByteCount;
+ /* Assert occurs always since this is a stub and should never be called */
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps.h
new file mode 100644
index 0000000..c6c2a0a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps.h
@@ -0,0 +1,517 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_5
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the parameter EffectiveAddr should be the
+* virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+*
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a drg/jz 01/12/10 First Release
+* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
+* in XUartPs_SetFlowDelay where the value was not
+* being written to the register.
+* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
+* instance structure and the driver is updated to use
+* InputClockHz parameter from the XUartPs_Config config
+* structure.
+* Added a parameter to XUartPs_Config structure which
+* specifies whether the user has selected Modem pins
+* to be connected to MIO or FMIO.
+* Added the tcl file to generate the xparameters.h
+* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+* with the correct values for CR 666724
+* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the name of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added API for uart reset and related
+* constant definitions.
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
+* Support for Zynq Ultrascale Mp added.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
+* platform variable in driver instance structure.
+* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
+* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
+* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
+*
+*
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H /* prevent circular inclusions */
+#define XUARTPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE 921600U
+#define XUARTPS_MIN_RATE 110U
+
+#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified. These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
+ * error detected */
+#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+ u32 InputClockHz;/**< Input clock frequency */
+ s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+ * to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+ u8 *NextBytePtr;
+ u32 RequestedBytes;
+ u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+ u32 BaudRate; /**< In bps, ie 1200 */
+ u32 DataBits; /**< Number of data bits */
+ u32 Parity; /**< Parity */
+ u8 StopBits; /**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the handler, and is passed back to the upper layer
+ * when the handler is called. It is used to find the device driver
+ * instance.
+ * @param Event contains one of the event constants indicating events that
+ * have occurred.
+ * @param EventData contains the number of bytes sent or received at the
+ * time of the call for send and receive events and contains the
+ * modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+ u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XUartPs_Config Config; /* Configuration data structure */
+ u32 InputClockHz; /* Input clock frequency */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 BaudRate; /* Current baud rate */
+
+ XUartPsBuffer SendBuffer;
+ XUartPsBuffer ReceiveBuffer;
+
+ XUartPs_Handler Handler;
+ void *CallBackRef; /* Callback reference for event handler */
+ u32 Platform;
+ u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+ (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if a byte can be sent
+* - FALSE if the Transmitter Fifo is not empty
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr) \
+ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_g.c
new file mode 100644
index 0000000..113abc8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_g.c
@@ -0,0 +1,53 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_UART_1_DEVICE_ID,
+ XPAR_PS7_UART_1_BASEADDR,
+ XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+ XPAR_PS7_UART_1_HAS_MODEM
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_hw.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_hw.c
new file mode 100644
index 0000000..11462ba
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_hw.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_5
+* @{
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.05a hk 08/22/13 Added reset function
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param Data contains the byte to be sent.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+ /* Wait until there is space in TX FIFO */
+ while (XUartPs_IsTransmitFull(BaseAddress)) {
+ ;
+ }
+
+ /* Write the byte into the TX FIFO */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return The data byte received.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+ u32 RecievedByte;
+ /* Wait until there is data */
+ while (!XUartPs_IsReceiveData(BaseAddress)) {
+ ;
+ }
+ RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+ /* Return the byte received */
+ return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+ /* Disable interrupts */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+ /* Disable receive and transmit */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+ /*
+ * Software reset of receive and transmit
+ * This clears the FIFO.
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+ /* Clear status flags - SW reset wont clear sticky flags. */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+ /*
+ * Mode register reset value : All zeroes
+ * Normal mode, even parity, 1 stop bit
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+ XUARTPS_MR_CHMODE_NORM);
+
+ /* Rx and TX trigger register reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+ XUARTPS_RXWM_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+ XUARTPS_TXWM_RESET_VAL);
+
+ /* Rx timeout disabled by default */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+ XUARTPS_RXTOUT_DISABLE);
+
+ /* Baud rate generator and dividor reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+ XUARTPS_BAUDGEN_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+ XUARTPS_BAUDDIV_RESET_VAL);
+
+ /*
+ * Control register reset value -
+ * RX and TX are disable by default
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+ (u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_hw.h
new file mode 100644
index 0000000..8c46ecf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_hw.h
@@ -0,0 +1,447 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_5
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+*
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_intr.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_intr.c
new file mode 100644
index 0000000..88eed1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_intr.c
@@ -0,0 +1,447 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* The current interrupt mask. The mask indicates which interupts
+* are enabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+ /* Assert validates the input argument */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Read the Interrupt Mask register */
+ return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param Mask contains the interrupts to be enabled or disabled.
+* A '1' enables an interupt, and a '0' disables.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+ u32 TempMask = Mask;
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ TempMask &= (u32)XUARTPS_IXR_MASK;
+
+ /* Write the mask to the IER Register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IER_OFFSET, TempMask);
+
+ /* Write the inverse of the Mask to the IDR register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param FuncPtr is the pointer to the callback function.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+*
+* @return None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef)
+{
+ /*
+ * Asserts validate the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Handler = (XUartPs_Handler)FuncPtr;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param InstancePtr contains a pointer to the driver instance
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+ u32 IsrStatus;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the interrupt ID register to determine which
+ * interrupt is active
+ */
+ IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+
+ IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_ISR_OFFSET);
+
+ /* Dispatch an appropriate handler. */
+ if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+ (u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+ /* Received data interrupt */
+ ReceiveDataHandler(InstancePtr);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+ != (u32)0) {
+ /* Transmit data interrupt */
+ SendDataHandler(InstancePtr, IsrStatus);
+ }
+
+ /* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+ if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+ (u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+ /* Received Error Status interrupt */
+ ReceiveErrorHandler(InstancePtr, IsrStatus);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+ /* Received Timeout interrupt */
+ ReceiveTimeoutHandler(InstancePtr);
+ }
+
+ if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+ /* Modem status interrupt */
+ ModemHandler(InstancePtr);
+ }
+
+ /* Clear the interrupt status. */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+ IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+ u32 EventData;
+ u32 Event;
+
+ InstancePtr->is_rxbs_error = 0;
+
+ if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+ (IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+ | (u32)XUARTPS_IXR_FRAMING))) {
+ InstancePtr->is_rxbs_error = 1;
+ }
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+
+ if (!(InstancePtr->is_rxbs_error)) {
+ Event = XUARTPS_EVENT_RECV_ERROR;
+ EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes;
+
+ /*
+ * Call the application handler to indicate that there is a receive
+ * error or a break interrupt, if the application cares about the
+ * error it call a function to get the last errors.
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ Event,
+ EventData);
+ }
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+ u32 Event;
+
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+ }
+
+ /*
+ * If there are no more bytes to receive then indicate that this is
+ * not a receive timeout but the end of the buffer reached, a timeout
+ * normally occurs if # of bytes is not divisible by FIFO threshold,
+ * don't rely on previous test of remaining bytes since receive
+ * function updates it
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ Event = XUARTPS_EVENT_RECV_TOUT;
+ } else {
+ Event = XUARTPS_EVENT_RECV_DATA;
+ }
+
+ /*
+ * Call the application handler to indicate that there is a receive
+ * timeout or data event
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+ InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+ /*
+ * If there are bytes still to be received in the specified buffer
+ * go ahead and receive them. Removing bytes from the RX FIFO will
+ * clear the interrupt.
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+ (void)XUartPs_ReceiveBuffer(InstancePtr);
+ }
+
+ /* If the last byte of a message was received then call the application
+ * handler, this code should not use an else from the previous check of
+ * the number of bytes to receive because the call to receive the buffer
+ * updates the bytes ramained
+ */
+ if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_RECV_DATA,
+ (InstancePtr->ReceiveBuffer.RequestedBytes -
+ InstancePtr->ReceiveBuffer.RemainingBytes));
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+* @param IsrStatus is the register value for channel status register
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+ /*
+ * If there are not bytes to be sent from the specified buffer then disable
+ * the transmit interrupt so it will stop interrupting as it interrupts
+ * any time the FIFO is empty
+ */
+ if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IDR_OFFSET,
+ ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+ /* Call the application handler to indicate the sending is done */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_SENT_DATA,
+ InstancePtr->SendBuffer.RequestedBytes -
+ InstancePtr->SendBuffer.RemainingBytes);
+ }
+
+ /* If TX FIFO is empty, send more. */
+ else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+ (void)XUartPs_SendBuffer(InstancePtr);
+ }
+ else {
+ /* Else with dummy entry for MISRA-C Compliance.*/
+ ;
+ }
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts. It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+ u32 MsrRegister;
+
+ /*
+ * Read the modem status register so that the interrupt is acknowledged
+ * and it can be passed to the callback handler with the event
+ */
+ MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MODEMSR_OFFSET);
+
+ /*
+ * Call the application handler to indicate the modem status changed,
+ * passing the modem status and the event data in the call
+ */
+ InstancePtr->Handler(InstancePtr->CallBackRef,
+ XUARTPS_EVENT_MODEM,
+ MsrRegister);
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_options.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_options.c
new file mode 100644
index 0000000..ee0db5f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_options.c
@@ -0,0 +1,760 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+* value was not being written to the register.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+ u16 Option;
+ u16 RegisterOffset;
+ u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+ {XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+ {XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+ {XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+ {XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+ {XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+ {XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+ XUARTPS_MODEMCR_RTS},
+ {XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+ XUARTPS_MODEMCR_DTR},
+ {XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+ u16 Options = 0U;
+ u32 Register;
+ u32 Index;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Loop thru the options table to map the physical options in the
+ * registers of the UART to the logical options to be returned
+ */
+ for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+ Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].
+ RegisterOffset);
+
+ /*
+ * If the bit in the register which correlates to the option
+ * is set, then set the corresponding bit in the options,
+ * ignoring any bits which are zero since the options variable
+ * is initialized to zero
+ */
+ if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+ Options |= OptionsTable[Index].Option;
+ }
+ }
+
+ return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param Options contains the options to be set which are bit masks
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+ u32 Index;
+ u32 Register;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Loop thru the options table to map the logical options to the
+ * physical options in the registers of the UART.
+ */
+ for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+ /*
+ * Read the register which contains option so that the register
+ * can be changed without destoying any other bits of the
+ * register.
+ */
+ Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].
+ RegisterOffset);
+
+ /*
+ * If the option is set in the input, then set the corresponding
+ * bit in the specified register, otherwise clear the bit in
+ * the register.
+ */
+ if ((Options & OptionsTable[Index].Option) != (u16)0) {
+ if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+ Register &= ~XUARTPS_CR_STOPBRK;
+ Register |= OptionsTable[Index].Mask;
+ }
+ else {
+ Register &= ~OptionsTable[Index].Mask;
+ }
+
+ /* Write the new value to the register to set the option */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ OptionsTable[Index].RegisterOffset,
+ Register);
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The current receive FIFO trigger level. This is a value
+* from 0-31.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+ u8 RtrigRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the value of the FIFO control register so that the threshold
+ * can be retrieved, this read takes special register processing
+ */
+ RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET);
+
+ /* Return only the trigger level from the register value */
+
+ RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+ return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param TriggerLevel contains the trigger level to set.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+ u32 RtrigRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+ /*
+ * Write the new value for the FIFO control register to it such that the
+ * threshold is changed
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+ u32 ModemStatusRegister;
+ u16 TmpRegister;
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the modem status register to return
+ */
+ ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MODEMSR_OFFSET);
+ TmpRegister = (u16)ModemStatusRegister;
+ return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if the UART is sending data
+* - FALSE if UART is not sending data
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+ u32 ChanStatRegister;
+ u32 ChanTmpSRegister;
+ u32 ActiveResult;
+ u32 EmptyResult;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel status register to determine if the transmitter is
+ * active
+ */
+ ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_SR_OFFSET);
+
+ /*
+ * If the transmitter is active, or the TX FIFO is not empty, then indicate
+ * that the UART is still sending some data
+ */
+ ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+ EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+ ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+ (((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+ return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+ u32 ModeRegister;
+ u8 OperMode;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Mode register. */
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+ /* Return the constant */
+ switch (ModeRegister) {
+ case XUARTPS_MR_CHMODE_NORM:
+ OperMode = XUARTPS_OPER_MODE_NORMAL;
+ break;
+ case XUARTPS_MR_CHMODE_ECHO:
+ OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+ break;
+ case XUARTPS_MR_CHMODE_L_LOOP:
+ OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+ break;
+ case XUARTPS_MR_CHMODE_R_LOOP:
+ OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+ break;
+ default:
+ OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+ XUARTPS_MR_CHMODE_SHIFT);
+ break;
+ }
+
+ return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param OperationMode is the mode of the UART.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+ u32 ModeRegister;
+
+ /* Assert validates the input arguments. */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+ /* Read the Mode register. */
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Set the correct value by masking the bits, then ORing the const. */
+ ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+ switch (OperationMode) {
+ case XUARTPS_OPER_MODE_NORMAL:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+ break;
+ case XUARTPS_OPER_MODE_AUTO_ECHO:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+ break;
+ case XUARTPS_OPER_MODE_LOCAL_LOOP:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+ break;
+ case XUARTPS_OPER_MODE_REMOTE_LOOP:
+ ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+ break;
+ default:
+ /* Default case made for MISRA-C Compliance. */
+ break;
+ }
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+ u32 FdelTmpRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Mode register. */
+ FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FLOWDEL_OFFSET);
+
+ /* Return the contents of the flow delay register */
+ FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+ return FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FlowDelayValue is the Setting for the flow delay.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+ u32 FdelRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Set the correct value by shifting the input constant, then masking
+ * the bits
+ */
+ FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The current setting for receive time out.
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+ u32 RtoRegister;
+ u8 RtoRTmpRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the Receive Timeout register. */
+ RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET);
+
+ /* Return the contents of the mode register shifted appropriately */
+ RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+ return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RecvTimeout setting allows the UART to detect an idle connection
+* on the reciever data line.
+* Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+* timeout function.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+ u32 RtoRegister;
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Set the correct value by masking the bits */
+ RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+ /* Configure CR to restart the receiver timeout counter */
+ RtoRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_CR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+ (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FormatPtr is a pointer to a format structure containing the data
+* format to be set.
+*
+* @return
+* - XST_SUCCESS if the data format was successfully set.
+* - XST_UART_BAUD_ERROR indicates the baud rate could not be
+* set because of the amount of error with the baud rate and
+* the input clock frequency.
+* - XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+*
+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+ XUartPsFormat * FormatPtr)
+{
+ s32 Status;
+ u32 ModeRegister;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FormatPtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Verify the inputs specified are valid */
+ if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+ (FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+ (FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+ Status = XST_INVALID_PARAM;
+ } else {
+
+ /*
+ * Try to set the baud rate and if it's not successful then don't
+ * continue altering the data format, this is done first to avoid the
+ * format from being altered when an error occurs
+ */
+ Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+ if (Status != (s32)XST_SUCCESS) {
+ ;
+ } else {
+
+ ModeRegister =
+ XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /*
+ * Set the length of data (8,7,6) by first clearing out the bits
+ * that control it in the register, then set the length in the register
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+ ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+ /*
+ * Set the number of stop bits in the mode register by first clearing
+ * out the bits that control it in the register, then set the number
+ * of stop bits in the register.
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+ ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+ /*
+ * Set the parity by first clearing out the bits that control it in the
+ * register, then set the bits in the register, the default is no parity
+ * after clearing the register bits
+ */
+ ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+ ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+ /* Update the mode register */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ Status = XST_SUCCESS;
+ }
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param FormatPtr is a pointer to a format structure that will contain
+* the data format after this call completes.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+ u32 ModeRegister;
+
+
+ /* Assert validates the input arguments */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FormatPtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the baud rate from the instance, this is not retrieved from the
+ * hardware because it is only kept as a divisor such that it is more
+ * difficult to get back to the baud rate
+ */
+ FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+
+ /* Get the length of data (8,7,6,5) */
+ FormatPtr->DataBits =
+ ((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+ XUARTPS_MR_CHARLEN_SHIFT);
+
+ /* Get the number of stop bits */
+ FormatPtr->StopBits =
+ (u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+ XUARTPS_MR_STOPMODE_SHIFT);
+
+ /* Determine what parity is */
+ FormatPtr->Parity =
+ (u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+ XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_selftest.c
new file mode 100644
index 0000000..f26176a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_selftest.c
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+* - XST_SUCCESS if the test was successful
+* - XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+ s32 Status = XST_SUCCESS;
+ u32 IntrRegister;
+ u32 ModeRegister;
+ u8 Index;
+ u32 ReceiveDataResult;
+
+ /* Assert validates the input arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable all interrupts in the interrupt disable register */
+ IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_IMR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+ XUARTPS_IXR_MASK);
+
+ /* Setup for local loopback */
+ ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XUARTPS_MR_OFFSET);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+ (u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+ /* Send a number of bytes and receive them, one at a time. */
+ for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+ /*
+ * Send out the byte and if it was not sent then the failure
+ * will be caught in the comparison at the end
+ */
+ (void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+ /*
+ * Wait until the byte is received. This can hang if the HW
+ * is broken. Watch for the FIFO empty flag to be false.
+ */
+ ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY;
+ while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+ ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY;
+ }
+
+ /* Receive the byte */
+ (void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+ }
+
+ /*
+ * Compare the bytes received to the bytes sent to verify the exact data
+ * was received
+ */
+ for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+ if (TestString[Index] != ReturnString[Index]) {
+ Status = XST_UART_TEST_FAIL;
+ }
+ }
+
+ /*
+ * Restore the registers which were altered to put into polling and
+ * loopback modes so that this test is not destructive
+ */
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+ IntrRegister);
+ XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+ ModeRegister);
+
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_sinit.c
new file mode 100644
index 0000000..c3e809b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/uartps_v3_7/src/xuartps_sinit.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 drg/jz 01/13/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return A pointer to the configuration structure or NULL if the
+* specified device is not in the system.
+*
+* @note None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+ XUartPs_Config *CfgPtr = NULL;
+
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+ if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XUartPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/Makefile
new file mode 100644
index 0000000..837ca13
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xadcps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling xadcps"
+
+xadcps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xadcps_includes
+
+xadcps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.c
new file mode 100644
index 0000000..5ec5a93
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.c
@@ -0,0 +1,1830 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* to fix CR #693371
+* 2.1 bss 08/05/14 Modified Assert for XAdcPs_SetSingleChParams to fix
+* CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address
+* (CR#854437).
+* 2.3 mn 07/09/18 Fix Doxygen warning
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param ConfigPtr points to the XAdcPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address is passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return
+* - XST_SUCCESS if successful.
+*
+* @note The user needs to first call the XAdcPs_LookupConfig() API
+* which returns the Configuration structure pointer which is
+* passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+
+ u32 RegValue;
+ /*
+ * Assert the input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+ /*
+ * Set the values read from the device config and the base address.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+ /* Write Unlock value to Device Config Unlock register */
+ XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
+ XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+ /* Enable the PS access of xadc and set FIFO thresholds */
+
+ RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET);
+
+ RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+ XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET, RegValue);
+
+ /* Release xadc from reset */
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x00);
+
+ /*
+ * Indicate the instance is now ready to use and
+ * initialized without error.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Config Register.
+* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Config Register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Miscellaneous
+* Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+* in xadcps_hw.h to interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous Status Register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write to the Miscellaneous control register Register.
+ */
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the Config Register.
+* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous control register and return the value.
+ */
+ return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param InstancePtr is a pointer to the Xxadc instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Generate the reset by Control
+ * register and release from reset
+ */
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x10);
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+ XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Channel is the channel number. Use the XADCPS_CH_* defined in
+* the file xadcps.h.
+* The valid channels are
+* - 0 to 6
+* - 13 to 31
+*
+* @return A 16-bit value representing the ADC converted data for the
+* specified channel. The XADC Monitor/ADC device guarantees
+* a 10 bit resolution for the ADC converted data and data is the
+* 10 MSB bits of the 16 data read from the device.
+*
+* @note The channels 7,8,9 are used for calibration of the device and
+* hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+ ((Channel >= XADCPS_CH_VCCPINT) &&
+ (Channel <= XADCPS_CH_AUX_MAX)));
+
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_TEMP_OFFSET +
+ Channel));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param CoeffType specifies the calibration coefficient
+* to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+* specify the calibration coefficient to be read.
+*
+* @return A 16-bit value representing the calibration coefficient.
+* The XADC device guarantees a 10 bit resolution for
+* the ADC converted data and data is the 10 MSB bits of the 16
+* data read from the device.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+ /*
+ * Read the selected calibration coefficient.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+ CoeffType));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param MeasurementType specifies the parameter for which the
+* Minimum/Maximum measurement has to be read.
+* Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+* specify the data to be read.
+*
+* @return A 16-bit value representing the maximum/minimum measurement for
+* specified parameter.
+* The XADC device guarantees a 10 bit resolution for
+* the ADC converted data and data is the 10 MSB bits of the 16
+* data read from the device.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+ u32 RegData;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+ ((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+ (MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+ /*
+ * Read and return the specified Minimum/Maximum measurement.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_MAX_TEMP_OFFSET +
+ MeasurementType));
+ return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Average is the number of samples of averaging programmed to the
+* Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+* in xadcps.h file :
+* - XADCPS_AVG_0_SAMPLES for no averaging
+* - XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+* - XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+* - XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+ /*
+ * Write the averaging value into the Configuration Register 0.
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_AVG_VALID_MASK);
+
+ RegData |= (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The averaging read from the Configuration Register 0 is
+* returned. Use the XADCPS_AVG_* bit definitions defined in
+* xadcps.h file to interpret the returned value :
+* - XADCPS_AVG_0_SAMPLES means no averaging
+* - XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+* - XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+* - XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+ u32 Average;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the averaging value from the Configuration Register 0.
+ */
+ Average = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+ return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Channel is the channel number for the singel channel mode.
+* The valid channels are 0 to 6, 8, and 13 to 31.
+* If the external Mux is used then this specifies the channel
+* oonnected to the external Mux. Please read the Device Spec
+* to know which channels are valid.
+* @param IncreaseAcqCycles is a boolean parameter which specifies whether
+* the Acquisition time for the external channels has to be
+* increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+* default 4 ADCCLK cycles (specify FALSE). This parameter is
+* only valid for the external channels.
+* @param IsEventMode specifies whether the operation of the ADC is Event
+* driven or Continuous mode.
+* @param IsDifferentialMode is a boolean parameter which specifies
+* unipolar(specify FALSE) or differential mode (specify TRUE) for
+* the analog inputs. The input mode is only valid for the
+* external channels.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the Configuration Register 0.
+* - XST_FAILURE if the channel sequencer is enabled or the input
+* parameters are not valid for the selected channel.
+*
+* @note
+* - The number of samples for the averaging for all the channels
+* is set by using the function XAdcPs_SetAvg.
+* - The calibration of the device is done by doing a ADC
+* conversion on the calibration channel(channel 8). The input
+* parameters IncreaseAcqCycles, IsDifferentialMode and
+* IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+ (Channel == XADCPS_CH_ADC_CALIB) ||
+ ((Channel >= XADCPS_CH_VCCPINT) &&
+ (Channel <= XADCPS_CH_AUX_MAX)));
+ Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+ (IncreaseAcqCycles == FALSE));
+ Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+ Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+ (IsDifferentialMode == FALSE));
+
+ /*
+ * Check if the device is in single channel mode else return failure
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+ XADCPS_SEQ_MODE_SINGCHAN)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ XADCPS_CFR0_AVG_VALID_MASK;
+
+ /*
+ * Select the number of acquisition cycles. The acquisition cycles is
+ * only valid for the external channels.
+ */
+ if (IncreaseAcqCycles == TRUE) {
+ if (((Channel >= XADCPS_CH_AUX_MIN) &&
+ (Channel <= XADCPS_CH_AUX_MAX)) ||
+ (Channel == XADCPS_CH_VPVN)){
+ RegValue |= XADCPS_CFR0_ACQ_MASK;
+ } else {
+ return XST_FAILURE;
+ }
+
+ }
+
+ /*
+ * Select the input mode. The input mode is only valid for the
+ * external channels.
+ */
+ if (IsDifferentialMode == TRUE) {
+
+ if (((Channel >= XADCPS_CH_AUX_MIN) &&
+ (Channel <= XADCPS_CH_AUX_MAX)) ||
+ (Channel == XADCPS_CH_VPVN)){
+ RegValue |= XADCPS_CFR0_DU_MASK;
+ } else {
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * Select the ADC mode.
+ */
+ if (IsEventMode == TRUE) {
+ RegValue |= XADCPS_CFR0_EC_MASK;
+ }
+
+ /*
+ * Write the given values into the Configuration Register 0.
+ */
+ RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+* in the Configuration Register 1.
+* Bit positions of 1 will be enabled. Bit positions of 0 will be
+* disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+* XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note The implementation of the alarm enables in the Configuration
+* register 1 is such that the alarms for bit positions of 1 will
+* be disabled and alarms for bit positions of 0 will be enabled.
+* The alarm outputs specified by the AlmEnableMask are negated
+* before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+ RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+ RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+ /*
+ * Enable/disables the alarm enables for the specified alarm bits in the
+ * Configuration Register 1.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return This is the bit-mask of the enabled alarm outputs in the
+* Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+* XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+* returned value.
+* Bit positions of 1 indicate that the alarm output is enabled.
+* Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note The implementation of the alarm enables in the Configuration
+* register 1 is such that alarms for the bit positions of 1 will
+* be disabled and alarms for bit positions of 0 will be enabled.
+* The enabled alarm outputs returned by this function is the
+* negated value of the the data read from the Configuration
+* Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the status of alarm output enables from the Configuration
+ * Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+ return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+* correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+* offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+* gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Calibration is the Calibration to be applied.
+* Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+* Multiple calibrations can be enabled at a time by oring the
+* XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+* Calibration can be disabled by specifying
+ XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+ (Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+ (Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+ /*
+ * Set the specified calibration in the Configuration Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET);
+
+ RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+ RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The value of the calibration enables in the Configuration
+* Register 1 :
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+* correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+* correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+* gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the calibration enables from the Configuration Register 1.
+ */
+ return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+* - Default safe mode (XADCPS_SEQ_MODE_SAFE)
+* - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+* - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+* - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+* - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+* - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param SequencerMode is the sequencer mode to be set.
+* Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return None.
+*
+* @note Only one of the modes can be enabled at a time. Please
+* read the Spec of the XADC for further information about the
+* sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+ (SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+ /*
+ * Set the specified sequencer mode in the Configuration Register 1.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET);
+ RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+ RegValue |= ((SequencerMode << XADCPS_CFR1_SEQ_SHIFT) &
+ XADCPS_CFR1_SEQ_VALID_MASK);
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+ RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The channel sequencer mode :
+* - XADCPS_SEQ_MODE_SAFE : Default safe mode
+* - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+* - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+* - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+* - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+* - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel sequencer mode from the Configuration Register 1.
+ */
+ return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+ XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Divisor is clock divisor used to derive ADCCLK from DCLK.
+* Valid values of the divisor are
+* - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+* Refer to the device specification for more details
+*
+* @return None.
+*
+* @note - The ADCCLK is an internal clock used by the ADC and is
+* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+* divided by the user selection in the Configuration Register 2.
+* - There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Write the divisor value into the Configuration Register #2.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+ Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The divisor read from the Configuration Register 2.
+*
+* @note The ADCCLK is an internal clock used by the ADC and is
+* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+* divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+ u16 Divisor;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the divisor value from the Configuration Register 2.
+ */
+ Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET);
+
+ return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param ChEnableMask is the bit mask of all the channels to be enabled.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+* be disabled.
+* The ChEnableMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Selection Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Enable the specified channels in the ADC Channel Selection Sequencer
+ * Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ00_OFFSET,
+ (ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ01_OFFSET,
+ (ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ01_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+* xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+* are the channels that are enabled and bit mask of 0 are
+* the channels that are disabled.
+*
+* @return None
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValEnable;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the channel enable bits for all the channels from the ADC
+ * Channel Selection Register.
+ */
+ RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ00_OFFSET) &
+ XADCPS_SEQ00_CH_VALID_MASK;
+ RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ01_OFFSET) &
+ XADCPS_SEQ01_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+ return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AvgEnableChMask is the bit mask of all the channels for which
+* averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+* xadcps_hw.h to specify the Channel numbers. Averaging will be
+* enabled for bit masks of 1 and disabled for bit mask of 0.
+* The AvgEnableChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Averaging Enables Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Enable/disable the averaging for the specified channels in the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ02_OFFSET,
+ (AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ03_OFFSET,
+ (AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ03_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The status of averaging (enabled/disabled) for all the channels.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* averaging is enabled and bit mask of 0 are the channels for
+* averaging is disabled
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+ u32 RegValAvg;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the averaging enable status for all the channels from the
+ * ADC Channel Averaging Enables Sequencer Registers.
+ */
+ RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+ RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param InputModeChMask is the bit mask of all the channels for which
+* the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+* in xadcps_hw.h to specify the channel numbers. Differential
+* input mode will be set for bit masks of 1 and unipolar input
+* mode for bit masks of 0.
+* The InputModeChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set the input mode for the specified channels in the ADC Channel
+ * Analog-Input Mode Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ04_OFFSET,
+ (InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ05_OFFSET,
+ (InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ05_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The input mode for all the channels.
+* Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* input mode is differential and bit mask of 0 are the channels
+* for which input mode is unipolar.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+ u32 InputMode;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the input mode for all the channels from the ADC Channel
+ * Analog-Input Mode Sequencer Registers.
+ */
+ InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ04_OFFSET) &
+ XADCPS_SEQ04_CH_VALID_MASK;
+ InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ05_OFFSET) &
+ XADCPS_SEQ05_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AcqCyclesChMask is the bit mask of all the channels for which
+* the number of acquisition cycles is to be extended.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+* for bit masks of 1 and will be the default 4 ADCCLK cycles for
+* bit masks of 0.
+* The AcqCyclesChMask is a 32 bit mask that is written to the two
+* 16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+* - XST_SUCCESS if the given values were written successfully to
+* the Channel Sequencer Registers.
+* - XST_FAILURE if the channel sequencer is enabled.
+*
+* @note None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The sequencer must be disabled for writing any of these registers
+ * Return XST_FAILURE if the channel sequencer is enabled.
+ */
+ if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+ XADCPS_SEQ_MODE_SAFE)) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * Set the Acquisition time for the specified channels in the
+ * ADC Channel Acquisition Time Sequencer Registers.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ06_OFFSET,
+ (AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_SEQ07_OFFSET,
+ (AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+ XADCPS_SEQ07_CH_VALID_MASK);
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns The acquisition time for all the channels.
+* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+* Channel numbers. Bit masks of 1 are the channels for which
+* acquisition cycles are extended and bit mask of 0 are the
+* channels for which acquisition cycles are not extended.
+*
+* @note None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+ u32 RegValAcq;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Get the Acquisition cycles for the specified channels from the ADC
+ * Channel Acquisition Time Sequencer Registers.
+ */
+ RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ06_OFFSET) &
+ XADCPS_SEQ06_CH_VALID_MASK;
+ RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_SEQ07_OFFSET) &
+ XADCPS_SEQ07_CH_VALID_MASK) <<
+ XADCPS_SEQ_CH_AUX_SHIFT;
+
+ return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlarmThrReg is the index of an Alarm Threshold Register to
+* be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+* specify the index.
+* @param Value is the 16-bit threshold value to write into the register.
+*
+* @return None.
+*
+* @note Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+* threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+ /*
+ * Write the value into the specified Alarm Threshold Register.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+ AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param AlarmThrReg is the index of an Alarm Threshold Register
+* to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h
+* to specify the index.
+*
+* @return A 16-bit value representing the contents of the selected Alarm
+* Threshold Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+ u32 RegData;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+ /*
+ * Read the specified Alarm Threshold Register and return
+ * the value
+ */
+ RegData = XAdcPs_ReadInternalReg(InstancePtr,
+ (XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+ return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+ u16 OtUpper;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the OT upper Alarm Threshold Register.
+ */
+ OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET);
+ OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+ /*
+ * Preserve the powerdown value and write OT enable value the into the
+ * OT Upper Alarm Threshold Register.
+ */
+ OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+ u16 OtUpper;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the OT Upper Alarm Threshold Register.
+ */
+ OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET);
+ OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+ XAdcPs_WriteInternalReg(InstancePtr,
+ XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param IsEventMode is a boolean parameter that specifies continuous
+* sampling (specify FALSE) or event driven sampling mode (specify
+* TRUE) for the given channel.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_EC_MASK);
+
+ /*
+ * Set the ADC mode.
+ */
+ if (IsEventMode == TRUE) {
+ RegValue |= XADCPS_CFR0_EC_MASK;
+ } else {
+ RegValue &= ~XADCPS_CFR0_EC_MASK;
+ }
+
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return The sampling mode
+* - 0 specifies continuous sampling
+* - 1 specifies event driven sampling mode
+*
+* @note None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+ u32 Mode;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the sampling mode from the Configuration Register 0.
+ */
+ Mode = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ XADCPS_CFR0_EC_MASK;
+ if (Mode) {
+
+ return 1;
+ }
+
+ return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param MuxMode specifies whether External Mux is used
+* - FALSE specifies NO external MUX
+* - TRUE specifies External Mux is used
+* @param Channel specifies the channel to be used for the
+* external Mux. Please read the Device Spec for which
+* channels are valid for which mode.
+*
+* @return None.
+*
+* @note There is no Assert in this function for checking the channel
+* number if the external Mux is used. The user should provide a
+* valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+ /*
+ * Read the Configuration Register 0.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR0_OFFSET) &
+ (~XADCPS_CFR0_MUX_MASK);
+ /*
+ * Select the Mux mode and the channel to be used.
+ */
+ if (MuxMode == TRUE) {
+ RegValue |= XADCPS_CFR0_MUX_MASK;
+ RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+ }
+
+ /*
+ * Write the mux mode into the Configuration Register 0.
+ */
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mode specifies the Power Down Mode
+* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+* ADC B are enabled)
+* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+* - XADCPS_PD_MODE_XADC specifies the Power Down of
+* both ADC A and ADC B.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+ /*
+ * Read the Configuration Register 2.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET) &
+ (~XADCPS_CFR2_PD_MASK);
+ /*
+ * Select the Power Down mode.
+ */
+ RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+ XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Mode specifies the Power Down Mode
+* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+* ADC B are enabled)
+* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+* - XADCPS_PD_MODE_XADC specifies the Power Down of
+* both ADC A and ADC B.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Power Down Mode.
+ */
+ RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+ XADCPS_CFR2_OFFSET) &
+ (~XADCPS_CFR2_PD_MASK);
+ /*
+ * Return the Power Down mode.
+ */
+ return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param RegOffset is the offset of the XADC register to be written.
+* @param Data is the data to be written.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+ u32 RegData;
+
+ /*
+ * Write the Data into the FIFO Register.
+ */
+ RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Read the Read FIFO after any write since for each write
+ * one location of Read FIFO gets updated
+ */
+ XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param RegOffset is the offset of the XADC register to be read.
+*
+* @return Data read from the FIFO
+*
+* @note None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+ u32 RegData;
+
+ RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+ /* Read cmd to FIFO*/
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Do a Dummy read */
+ RegData = XAdcPs_ReadFifo(InstancePtr);
+
+ /* Do a Dummy write to get the actual read */
+ XAdcPs_WriteFifo(InstancePtr, RegData);
+
+ /* Do the Actual read */
+ RegData = XAdcPs_ReadFifo(InstancePtr);
+
+ return RegData;
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.h
new file mode 100644
index 0000000..900edf0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps.h
@@ -0,0 +1,589 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_3
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+* - 10-bit, 200-KSPS (kilo samples per second)
+* Analog-to-Digital Converter (ADC)
+* - Monitoring of on-chip supply voltages and temperature
+* - 1 dedicated differential analog-input pair and
+* 16 auxiliary differential analog-input pairs
+* - Automatic alarms based on user defined limits for the on-chip
+* supply voltages and temperature
+* - Automatic Channel Sequencer, programmable averaging, programmable
+* acquisition time for the external inputs, unipolar or differential
+* input selection for the external inputs
+* - Inbuilt Calibration
+* - Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* XADC Channel Sequencer Modes
+*
+* The XADC Channel Sequencer supports the following operating modes:
+*
+* - Default : This is the default mode after power up.
+* In this mode of operation the XADC operates in
+* a sequence mode, monitoring the on chip sensors:
+* Temperature, VCCINT, and VCCAUX.
+* - One pass through sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers for a single pass and then stops.
+* - Continuous cycling of sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers continuously.
+* - Single channel mode: In this mode the XADC Channel
+* Sequencer is disabled and the XADC operates in a
+* Single Channel Mode.
+* The XADC can operate either in a Continuous or Event
+* driven sampling mode in the single channel mode.
+* - Simultaneous Sampling Mode: In this mode the XADC Channel
+* Sequencer will automatically sequence through eight fixed pairs
+* of auxiliary analog input channels for simulataneous conversion.
+* - Independent ADC mode: In this mode the first ADC (A) is used to
+* is used to implement a fixed monitoring mode similar to the
+* default mode but the alarm fucntions ar eenabled.
+* The second ADC (B) is available to be used with external analog
+* input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* Building the driver
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* Limitations of the driver
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* in xadcps.c to fix CR #693371
+* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
+* CR#749687
+* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+* functions.
+* Modified Assert for XAdcPs_SetSingleChParams in
+* xadcps.c to fix CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
+* xadcps.c (CR#854437).
+* ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
+* 2.3 mn 07/09/18 Fix Doxygen warning
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
+#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
+#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP 0x4 /**< VREFP */
+#define XADCPS_CH_VREFN 0x5 /**< VREFN */
+#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
+#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
+#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
+#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XAdcPs_Config Config; /**< XAdcPs_Config of current device */
+ u32 IsReady; /**< Device is initialized and ready */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in Event Sampling Mode.
+* - FALSE if the device is in Continuous Sampling Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
+ TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in External Mux Mode.
+* - FALSE if the device is NOT in External Mux Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
+ TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param AdcData is the Raw ADC Data from XADC.
+*
+* @return The Temperature in centigrades.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData) \
+ ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param AdcData is the XADC/ADC Raw Data.
+*
+* @return The Voltage in volts.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) \
+ ((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param Temperature is the Temperature in centigrades to be
+* converted to XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature) \
+ ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param Voltage is the Voltage in volts to be converted to
+* XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage) \
+ ((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the value to be written to XADC register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data) \
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Data read from the FIFO
+*
+* @note C-Style signature:
+* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr) \
+ XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+ XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_g.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_g.c
new file mode 100644
index 0000000..fdc8373
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_XADC_0_DEVICE_ID,
+ XPAR_PS7_XADC_0_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_hw.h
new file mode 100644
index 0000000..dd51473
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_hw.h
@@ -0,0 +1,498 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note None.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
+* CR#749687
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+ * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
+ * successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+ *
+ * The definitions are same for the Interrupt Status Register and
+ * Interrupt Mask Register. They are defined only once.
+ * @{
+ */
+#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
+#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
+#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
+#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
+#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
+#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
+#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
+#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+ * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
+#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
+#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
+#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
+#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
+#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
+#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
+#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
+ * Continuous mode selection
+ */
+#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
+ Supply Gain/Offset
+ Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
+ Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+ Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
+ Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be enabled.
+* Bit positions of 1 will be enabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the specified interrupts in the IPIER.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET);
+ RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be disabled.
+* Bit positions of 1 will be disabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enable the specified interrupts in the IPIER.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET);
+ RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET,
+ RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the I.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Enable Register.
+ */
+ return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return A 32-bit value representing the contents of the IPISR.
+*
+* @note The device must be configured at hardware build time to include
+* interrupt component for this function to work.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Status register.
+ */
+ return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Mask is the bit-mask of the interrupts to be cleared.
+* Bit positions of 1 will be cleared. Bit positions of 0 will not
+* change the previous interrupt status. This mask is formed by
+* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Clear the specified interrupts in the Interrupt Status register.
+ */
+ RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XADCPS_INT_STS_OFFSET);
+ RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
+ XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
+ RegValue);
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_selftest.c
new file mode 100644
index 0000000..2d2a7f2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_selftest.c
@@ -0,0 +1,137 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_selftest.c
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This file contains a diagnostic self test function for the XAdcPs driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xadcps.h for more information.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+*
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XADCPS_ATR_TEST_VALUE 0x55
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+* - Resets the device,
+* - Writes a value into the Alarm Threshold register and reads it back
+* for comparison.
+* - Resets the device again.
+*
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - XST_SUCCESS if the value read from the Alarm Threshold
+* register is the same as the value written.
+* - XST_FAILURE Otherwise
+*
+* @note This is a destructive test in that resets of the device are
+* performed. Refer to the device specification for the
+* device status after the reset operation.
+*
+******************************************************************************/
+int XAdcPs_SelfTest(XAdcPs *InstancePtr)
+{
+ int Status;
+ u32 RegValue;
+
+ /*
+ * Assert the argument
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ /*
+ * Reset the device to get it back to its default state
+ */
+ XAdcPs_Reset(InstancePtr);
+
+ /*
+ * Write a value into the Alarm Threshold registers, read it back, and
+ * do the comparison
+ */
+ XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
+ XADCPS_ATR_TEST_VALUE);
+ RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
+
+ if (RegValue == XADCPS_ATR_TEST_VALUE) {
+ Status = XST_SUCCESS;
+ } else {
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Reset the device again to its default state.
+ */
+ XAdcPs_Reset(InstancePtr);
+ /*
+ * Return the test result.
+ */
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_sinit.c
new file mode 100644
index 0000000..5572976
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_3/src/xadcps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_sinit.c
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This file contains the implementation of the XAdcPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XAdcPs_Config XAdcPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks up the device configuration based on the unique device ID.
+* The table XAdcPs_ConfigTable contains the configuration info for each device
+* in the system.
+*
+* @param DeviceId contains the ID of the device for which the
+* device configuration pointer is to be returned.
+*
+* @return
+* - A pointer to the configuration found.
+* - NULL if the specified device ID was not found.
+*
+* @note None.
+*
+******************************************************************************/
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
+{
+ XAdcPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index=0; Index < 1; Index++) {
+ if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XAdcPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_0/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_0/src/Makefile
new file mode 100644
index 0000000..96c5661
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_0/src/Makefile
@@ -0,0 +1,79 @@
+###############################################################################
+#
+# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS =
+LIB=libxilffs.a
+
+ifeq ($(notdir $(COMPILER)) , iccarm)
+ EXTRA_ARCHIVE_FLAGS=--create
+else
+ifeq ($(notdir $(COMPILER)) , armcc)
+ EXTRA_ARCHIVE_FLAGS=--create
+else
+ EXTRA_ARCHIVE_FLAGS=rc
+endif
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+FATFS_DIR = .
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+FATFS_SRCS := $(wildcard *.c)
+FATFS_OBJS = $(addprefix $(FATFS_DIR)/, $(FATFS_SRCS:%.c=%.o))
+
+INCLUDEFILES=$(FATFS_DIR)/include/ff.h \
+ $(FATFS_DIR)/include/ffconf.h \
+ $(FATFS_DIR)/include/diskio.h \
+ $(FATFS_DIR)/include/integer.h
+
+libs: libxilffs.a
+
+libxilffs.a: print_msg_fatfs $(FATFS_OBJS)
+ $(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${FATFS_OBJS}
+
+print_msg_fatfs:
+ @echo "Compiling XilFFs Library"
+
+.PHONY: include
+include: libxilffs_includes
+
+libxilffs_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf $(FATFS_DIR)/${OBJECTS}
+ rm -rf ${RELEASEDIR}/${LIB}
+
+$(FATFS_DIR)/%.o: $(FATFS_DIR)/%.c $(INCLUDEFILES)
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@
diff --git a/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_0/src/diskio.c b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_0/src/diskio.c
new file mode 100644
index 0000000..0135c68
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/FSBL_bsp/ps7_cortexa9_0/libsrc/xilffs_v4_0/src/diskio.c
@@ -0,0 +1,538 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */
+/*-----------------------------------------------------------------------*/
+
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file diskio.c
+* This file is the glue layer between file system and
+* driver.
+* Description related to SD driver:
+* Process to use file system with SD
+* Select xilffs in SDK when creating a BSP
+* In SDK, set "fs_interface" to 1 to select SD interface.
+* This glue layer can currently be used only with one
+* SD controller enabled.
+* In order to use eMMC, in SDK set "Enable MMC" to 1. If not,
+* SD support is enabled by default.
+*
+* Description:
+* This glue layer initializes the host controller and SD card
+* in disk_initialize. If SD card supports it, 4-bit mode and
+* high speed mode will be enabled.
+* The default block size is 512 bytes.
+* disk_read and disk_write functions are used to read and
+* write files using ADMA2 in polled mode.
+* The file system can be used to read from and write to an
+* SD card that is already formatted as FATFS.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hk 10/17/13 First release
+* 2.0 hk 02/12/14 Corrected status check in disk initialize. CR# 772072.
+* 2.1 hk 04/16/14 Move check for ExtCSD high speed bit set inside if
+* condition for high speed support.
+* Include xil_types.h irrespective of xsdps.h. CR# 797086.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 3.0 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Make changes for prototypes of disk_read and
+* disk_write according to latest version.
+* 12/15/14 Modified the code according to MISRAC 2012 Compliant.
+* Updated the FatFs to R0.10b
+* Removed alignment for local buffers as CacheInvalidate
+* will take care of it.
+* sg 03/03/15 Added card detection check logic
+* 04/28/15 Card detection only in case of card detection signal
+* 3.1 sk 06/04/15 Added support for SD1.
+* 3.2 sk 11/24/15 Considered the slot type before checking the CD/WP pins.
+* 3.3 sk 04/01/15 Added one second delay for checking CD pin.
+* 3.4 sk 06/09/16 Added support for mkfs.
+* 3.8 mj 07/31/17 Added support for RAM based FATfs.
+* mn 12/04/17 Resolve errors in XilFFS for ARMCC compiler
+* 3.9 mn 04/18/18 Resolve build warnings for xilffs library
+* mn 07/06/18 Fix Cppcheck and Doxygen warnings
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0 hk 27/01/14 First release
+* 1.4 vns 07/06/17 Added dooxygen tags.
+*
+*
+*
+* @note
+*
+******************************************************************************/
+#ifndef ___XIL_RSA_H___
+#define ___XIL_RSA_H___
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************************** Include Files *********************************/
+
+/*
+ * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
+ * 32-bit digits are approximately 4 times faster
+ */
+
+//#define RSA_DIGIT_16
+#define RSA_DIGIT_32
+
+/*
+ * RSA loop unrolling selection
+ * RSA main loop can be unrolled 2, 4 or 8 ways
+ */
+#define RSA_UNROLL 1
+
+/*
+ * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
+ */
+//#define RSA_ARM_OPTIMIZED
+
+/*
+ * Check the compatibility of the selection
+ */
+#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
+ #error Please select a digit size
+#endif
+#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
+ #error Please select just one digit size
+#endif
+#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
+ #error Assembly level code is only supported for the GCC/ARM combination
+#endif
+#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
+ #error Only 1, 2, 4, and 8 unrolling are supported
+#endif
+
+#ifdef RSA_DIGIT_16
+#define RSA_DIGIT unsigned short
+#define RSA_SDIGIT short
+#define RSA_DDIGIT unsigned long
+#endif
+#ifdef RSA_DIGIT_32
+#define RSA_DIGIT unsigned long
+#define RSA_SDIGIT long
+#define RSA_DDIGIT unsigned long long
+#endif
+
+#define RSA_NUMBER RSA_DIGIT *
+#define RSA_NBITS 2048
+#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
+#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
+
+/*
+ * Double-digit to single digit conversion
+ */
+#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
+#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
+
+#define SHA_BLKSIZE 512
+#define SHA_BLKBYTES (SHA_BLKSIZE/8)
+#define SHA_BLKWORDS (SHA_BLKBYTES/4)
+
+#define SHA_VALSIZE 256
+#define SHA_VALBYTES (SHA_VALSIZE/8)
+#define SHA_VALWORDS (SHA_VALBYTES/4)
+
+/*
+ * SHA-256 context structure
+ * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
+ * total byte length counter (used both to manage the buffer and for padding)
+ */
+ //! [sha2_context]
+typedef struct
+{
+ unsigned int state[8];
+ unsigned char buffer[SHA_BLKBYTES];
+ unsigned long long bytes;
+} sha2_context;
+//! [sha2_context]
+/** @}
+@endcond */
+
+/*
+ * RSA-2048 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to encrypt the data using 2048 bit private key.
+ *
+ * @param modular A char pointer which contains the key modulus
+ * @param modular_ext A char pointer which contains the key modulus
+ * extension
+ * @param exponent A char pointer which contains the private key
+ * exponent
+ * @param result A char pointer which contains the encrypted data
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
+ const unsigned char *modular_ext, const unsigned char *exponent,
+ unsigned char *result);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function is used to decrypt the data using 2048 bit public key
+ *
+ * @param a RSA_NUMBER containing the decrypted data.
+ * @param x RSA_NUMBER containing the input data
+ * @param e Unsigned number containing the public key exponent
+ * @param m RSA_NUMBER containing the public key modulus
+ * @param rrm RSA_NUMBER containing the public key modulus extension.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
+ unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
+
+/*
+ * SHA-256 user interfaces
+ */
+/*****************************************************************************/
+/**
+ * @brief
+ * This function calculates the hash for the input data using SHA-256
+ * algorithm. This function internally calls the sha2_init, updates and
+ * finishes functions and updates the result.
+ *
+ * @param In Char pointer which contains the input data.
+ * @param Size Length of the input data
+ * @param Out Pointer to location where resulting hash will be
+ * written.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function initializes the SHA2 context.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_starts(sha2_context *ctx);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function adds the input data to SHA256 calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param input Pointer to the data to add.
+ * @param Out Length of the input data.
+ *
+ * @return None
+ *
+ ******************************************************************************/
+void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
+/*****************************************************************************/
+/**
+ * @brief
+ * This function finishes the SHA calculation.
+ *
+ * @param ctx Pointer to sha2_context structure that stores status and
+ * buffer.
+ * @param output Pointer to the calculated hash data.
+ *
+ * @return None
+ *
+ *
+ ******************************************************************************/
+void sha2_finish(sha2_context *ctx, unsigned char* output);
+
+/*
+ * Preprocessing interface (pre-computation of R*R mod M)
+ */
+/**@cond xilrsa_internal */
+void modular_ext(const unsigned char *modular, unsigned char *res);
+/** @}
+@endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___XIL_RSA_H___ */
+/** @} */
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/RemoteSystemsTempFiles/.project b/2.FW/Zynq/proj_cal/Vitis/RemoteSystemsTempFiles/.project
new file mode 100644
index 0000000..5447a64
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/RemoteSystemsTempFiles/.project
@@ -0,0 +1,12 @@
+
+
+ RemoteSystemsTempFiles
+
+
+
+
+
+
+ org.eclipse.rse.ui.remoteSystemsTempNature
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/.cproject b/2.FW/Zynq/proj_cal/Vitis/calboard/.cproject
new file mode 100644
index 0000000..7468641
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/.cproject
@@ -0,0 +1,170 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/.project b/2.FW/Zynq/proj_cal/Vitis/calboard/.project
new file mode 100644
index 0000000..a070dd7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/.project
@@ -0,0 +1,26 @@
+
+
+ calboard
+ Created by SDK v2018.3. calboard_bsp - ps7_cortexa9_0
+
+ calboard_bsp
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/Xilinx.spec b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/Xilinx.spec
new file mode 100644
index 0000000..d7ab17f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/Xilinx.spec
@@ -0,0 +1,2 @@
+*startfile:
+crti%O%s crtbegin%O%s
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/calboard.elf.size b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/calboard.elf.size
new file mode 100644
index 0000000..2720890
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/calboard.elf.size
@@ -0,0 +1,2 @@
+ text data bss dec hex filename
+ 132680 3184 5363760 5499624 53eae8 calboard.elf
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/makefile b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/makefile
new file mode 100644
index 0000000..ec437c7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/makefile
@@ -0,0 +1,65 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+ELFSIZE += \
+calboard.elf.size \
+
+
+# All Target
+all: pre-build main-build
+
+# Main-build Target
+main-build: calboard.elf secondary-outputs
+
+# Tool invocations
+calboard.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: ARM v7 gcc linker'
+ arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+calboard.elf.size: calboard.elf
+ @echo 'Invoking: ARM v7 Print Size'
+ arm-none-eabi-size calboard.elf |tee "calboard.elf.size"
+ @echo 'Finished building: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) $(EXECUTABLES)$(OBJS)$(S_UPPER_DEPS)$(C_DEPS)$(ELFSIZE) calboard.elf
+ -@echo ' '
+
+pre-build:
+ -a9-linaro-pre-build-step
+ -@echo ' '
+
+secondary-outputs: $(ELFSIZE)
+
+.PHONY: all clean dependents
+.SECONDARY: main-build pre-build
+
+-include ../makefile.targets
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/objects.mk b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/objects.mk
new file mode 100644
index 0000000..74bc53e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS := -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/sources.mk b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/sources.mk
new file mode 100644
index 0000000..8d2d45f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/sources.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+LD_SRCS :=
+OBJ_SRCS :=
+S_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+O_SRCS :=
+EXECUTABLES :=
+OBJS :=
+S_UPPER_DEPS :=
+C_DEPS :=
+ELFSIZE :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/src/subdir.mk b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/src/subdir.mk
new file mode 100644
index 0000000..df65974
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/Debug/src/subdir.mk
@@ -0,0 +1,72 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+LD_SRCS += \
+../src/lscript.ld
+
+C_SRCS += \
+../src/GPIO_Driv.c \
+../src/SPI_Driv.c \
+../src/cal_meas.c \
+../src/crc16.c \
+../src/dna_read.c \
+../src/echo.c \
+../src/i2c_access.c \
+../src/iic_phyreset.c \
+../src/main.c \
+../src/platform.c \
+../src/platform_mb.c \
+../src/platform_ppc.c \
+../src/platform_zynq.c \
+../src/platform_zynqmp.c \
+../src/sfp.c \
+../src/si5324.c
+
+OBJS += \
+./src/GPIO_Driv.o \
+./src/SPI_Driv.o \
+./src/cal_meas.o \
+./src/crc16.o \
+./src/dna_read.o \
+./src/echo.o \
+./src/i2c_access.o \
+./src/iic_phyreset.o \
+./src/main.o \
+./src/platform.o \
+./src/platform_mb.o \
+./src/platform_ppc.o \
+./src/platform_zynq.o \
+./src/platform_zynqmp.o \
+./src/sfp.o \
+./src/si5324.o
+
+C_DEPS += \
+./src/GPIO_Driv.d \
+./src/SPI_Driv.d \
+./src/cal_meas.d \
+./src/crc16.d \
+./src/dna_read.d \
+./src/echo.d \
+./src/i2c_access.d \
+./src/iic_phyreset.d \
+./src/main.d \
+./src/platform.d \
+./src/platform_mb.d \
+./src/platform_ppc.d \
+./src/platform_zynq.d \
+./src/platform_zynqmp.d \
+./src/sfp.d \
+./src/si5324.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM v7 gcc compiler'
+ arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/bootimage/calboard.bif b/2.FW/Zynq/proj_cal/Vitis/calboard/bootimage/calboard.bif
new file mode 100644
index 0000000..47fc14b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/bootimage/calboard.bif
@@ -0,0 +1,7 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+ [bootloader]E:\CALBOARD\z035_mars1k\bin\bin_11.13\FSBL.elf
+ E:\CALBOARD\z035_mars1k\bin\bin_11.13\system_wrapper.bit
+ E:\CALBOARD\z035_mars1k\bin\bin_11.13\calboard.elf
+}
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/GPIO_Driv.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/GPIO_Driv.c
new file mode 100644
index 0000000..e04d051
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/GPIO_Driv.c
@@ -0,0 +1,108 @@
+/*
+ * GPIO_Driv.c
+ *
+ * Created on: 202157
+ * Author: Administrator
+ */
+#include "GPIO_Driv.h"
+
+XGpioPs psGpioInstancePtr; //˿
+XGpioPs_Config* GpioConfigPtr; //豸ID
+ //sck,cs,sdi,sdo,rst
+u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
+u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
+u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
+
+void EMIO_config(void)
+{
+ int xStatus;
+ GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
+ if(GpioConfigPtr == NULL)
+ return XST_FAILURE;
+
+ xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
+ if(XST_SUCCESS != xStatus)
+ print(" PS GPIO INIT FAILED \n\r");
+
+ /*-------------------------------------CPLD_U1------------------------------------*/
+ //--EMIO
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
+
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
+
+ //ʹEMIO 1=output 0=input
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
+
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
+
+ /*-------------------------------------CPLD_U2------------------------------------*/
+ //--EMIO
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
+
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
+
+ //ʹEMIO 1=output 0=input
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
+
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
+
+ /*-------------------------------------CPLD_U3------------------------------------*/
+ //--EMIO
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---cs
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---sdi
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//79---sdo
+ XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//80---rst_n
+
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
+
+ //ʹEMIO 1=output 0=input
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---cs
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---sdi
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 0);//79---sdo
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 1);//80---rst_n
+
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
+ //XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
+
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/GPIO_Driv.h b/2.FW/Zynq/proj_cal/Vitis/calboard/src/GPIO_Driv.h
new file mode 100644
index 0000000..b6c53cb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/GPIO_Driv.h
@@ -0,0 +1,25 @@
+/*
+ * GPIO_Driv.h
+ *
+ * Created on: 202142
+ * Author: dell
+ */
+
+#ifndef SRC_GPIO_DRIV_H_
+#define SRC_GPIO_DRIV_H_
+
+#include "stdio.h"
+#include "xgpiops.h"
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+
+extern u32 CPLD_U1[11];
+extern u32 CPLD_U2[11];
+extern u32 CPLD_U3[11];
+
+void EMIO_config(void);
+
+#endif /* SRC_GPIO_DRIV_H_ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/README.txt b/2.FW/Zynq/proj_cal/Vitis/calboard/src/README.txt
new file mode 100644
index 0000000..4379dd5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/README.txt
@@ -0,0 +1,84 @@
+lwIP Echo Server
+----------------
+
+The lwIP Echo server application starts an echo server at port 7. Any data sent to
+this port is simply echoed back.
+
+By default, the program assigns the following settings to the board:
+IP Address: 192.168.1.10
+Netmask : 255.255.255.0
+Gateway : 192.168.1.1
+MAC address: 00:0a:35:00:01:02
+These settings can be changed in the file main.c.
+
+The main echo server logic is present in the file echo.c.
+
+platform.c implements certain processor and platform dependent functions.
+The file platform_config.h is generated based on the hardware design. It makes two
+assumptions: The timer has its interrupt line connected to the interrupt controller,
+and all the ethernet peripherals (xps_ethernetlite or xps_ll_temac) accessible from
+the processor can be used with lwIP.
+
+Running the Echo Server example
+-------------------------------
+
+To connect and test the echo server, download and run the program on the board,
+and then issue the following command from your host machine:
+
+$ telnet 192.168.1.10 7
+Trying 192.168.1.10...
+Connected to 192.168.1.10.
+Escape character is '^]'.
+hello world
+hello world
+all messages will be echo'ed back
+all messages will be echo'ed back
+^]
+telnet> quit
+Connection closed.
+$
+
+
+lwIPv6 Echo Server
+----------------
+
+The lwIPv6 Echo server application starts an echo server at port 7. Any data sent to
+this port is simply echoed back.
+
+By default, the program assigns the following settings to the board:
+IPv6 address: FE80:0:0:0:20A:35FF:FE00:102
+MAC address: 00:0a:35:00:01:02
+These settings can be changed in the file main.c.
+
+The main echo server logic is present in the file echo.c.
+
+platform.c implements certain processor and platform dependent functions.
+The file platform_config.h is generated based on the hardware design. It makes two
+assumptions: The timer has its interrupt line connected to the interrupt controller,
+and all the ethernet peripherals (xps_ethernetlite or xps_ll_temac) accessible from
+the processor can be used with lwIP.
+
+Running the Echo Server example
+-------------------------------
+
+To connect and test the echo server, download and run the program on the board,
+and then issue the following command from your host machine:
+
+$ telnet -6 FE80:0:0:0:20A:35FF:FE00:102%eth1 7
+Trying fe80::20a:35ff:fe00:102%eth1...
+Connected to FE80:0:0:0:20A:35FF:FE00:102%eth1.
+Escape character is '^]'.
+hello world
+hello world
+all messages will be echo'ed back
+all messages will be echo'ed back
+^]
+telnet> quit
+Connection closed.
+$
+
+References
+----------
+
+More details regarding the echo server can be obtained from Xilinx XAPP 1026:
+http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/SPI_Driv.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/SPI_Driv.c
new file mode 100644
index 0000000..757dabd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/SPI_Driv.c
@@ -0,0 +1,558 @@
+/*
+ * SPI_Driv.c
+ *
+ * Created on: 202142
+ * Author: dell
+ */
+
+#include "SPI_Driv.h"
+
+XGpioPs psGpioInstancePtr; //˿
+XGpioPs_Config* GpioConfigPtr; //豸ID
+
+
+extern u32 K7_U0[16];
+extern u32 molex_4_bank_3[4];
+extern u32 cs_en_bank_3[4];
+
+/******************************************************************************
+* Function : void interface_initial(u32* device,u32 num_wire)
+* Description : interface initial
+* Parameter : device -- CPLD
+* num_wire -- λ߱
+* Return : void
+******************************************************************************/
+void interface_initial(u32* device) //wire_num = cs sck sdi/o
+ {
+ u32 sck = *(device+0);
+ u32 cs = *(device+1);
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
+
+ }
+
+/******************************************************************************
+* Function : void rst_CPLD(u32* device,u32 num_wire)
+* Description : CPLD reset
+* Parameter : device -- CPLD
+* num_wire -- λ߱
+* Return : void
+******************************************************************************/
+void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
+{
+ u32 rst_n = *(device+num_wire);
+
+ XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
+ usleep(2);
+ XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
+}
+
+/******************************************************************************
+* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
+* Description : spi onewire write
+* Parameter : addr -- ַ
+* data --
+* width -- ݳ
+* device -- CPLD
+* Return : void
+******************************************************************************/
+void spi_write_onewire(char addr, char *data, char width, u32* device)
+{
+ char temp_addr = 0;
+ //u32 temp_data = 0;
+ u32 temp_data = 0;
+ char i = 0,j=0;
+ u32 sck = *(device+0);
+ u32 cs= *(device+1);
+ u32 sdi= *(device+2);
+
+ temp_addr = addr;
+ ///temp_data = data;
+
+ //XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
+ //XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r־λ 1=w 0=r
+ //XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ //XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+
+ for(i = 0; i < 8; i++) // 8bitַ
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+
+ if(temp_addr&0x80)
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck͵ƽ ݴмͨ
+ else
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ temp_addr = temp_addr<<1; //sckߵƽ,˴ΪڶݣһѾ
+ }
+
+ for(j=0;j>16);
+ read_data[1] = (u8)(temp_data>>8);
+ read_data[0] = (u8)(temp_data);
+ return temp_data;
+}
+
+/******************************************************************************
+* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
+* Description : forwire write to reg
+* Parameter : txdata--
+* sdi0,sdi1,sdi2,sdi3--IO
+* Return : void
+******************************************************************************/
+void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
+{
+ switch(txdata & 0x0F)
+ {
+ case 0x00:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x01:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x02:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x03:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x04:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x05:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x06:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x07:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
+ break;
+ }
+ case 0x08:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ case 0x09:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ case 0x0A:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ case 0x0B:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ case 0x0C:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ case 0x0D:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ case 0x0E:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ case 0x0F:
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
+ break;
+ }
+ }
+}
+
+/******************************************************************************
+* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
+* Description : spi fourwire write
+* Parameter : addr -- ַ
+* data --
+* width -- ݳ
+* device -- CPLD
+* Return : void
+******************************************************************************/
+void spi_write_fourwire(char addr, u16 data, u32* device)
+{
+ u8 temp_addr = 0;
+ u16 temp_data = 0;
+ u8 split_addr[2] = {0}; //8bitֱַ֣4ߴ䣬
+ u8 split_data[4] = {0}; //16bitݲ44bit
+ u8 i;
+ u32 sck = *(device+0);
+ u32 cs = *(device+1);
+ u32 sdi0 = *(device+2);
+ u32 sdi1 = *(device+3);
+ u32 sdi2 = *(device+4);
+ u32 sdi3 = *(device+5);
+
+ temp_addr = addr;
+ temp_data = data;
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
+ fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r־λ 1=w 0=r
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+
+ for(i = 0; i < 2;i++) // 8bitַ ĸ߷δ
+ {
+ split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sckߵƽ ݴMCUм
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+
+ fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck͵ƽ ݴмͨ
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ }
+ for(i = 0; i < 4;i++) //16bit 4߷Ĵδ
+ {
+ split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+
+ fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ }
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
+ fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
+ //usleep(20);
+}
+
+/******************************************************************************
+* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
+* Description : forwire read from reg
+* Parameter : sdo0,sdo1,sdo2,sdo3--IO
+* Return : rxdata--
+******************************************************************************/
+u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
+{
+ u32 GPIO_PIN[4];
+ u16 rdata[4];
+ u16 rxdata = 0;
+
+ GPIO_PIN[0] = sdo0;
+ GPIO_PIN[1] = sdo1;
+ GPIO_PIN[2] = sdo2;
+ GPIO_PIN[3] = sdo3;
+
+ for(u8 i = 0; i < 4 ; i++)
+ {
+ rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
+ //xil_printf("rdata[i] = %x\r\n",rdata[i]);
+ rxdata = ((rdata[i])<> 4)&0x0F;
+ split_addr[1] = (temp_addr)&0x0F;
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
+ fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r־λ 1=w 0=r
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+
+ for(i = 0; i < 2; i++) // 8bitַ ĸ߷δ
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+
+ fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck͵ƽ ݴмͨ
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ }
+
+ for(i = 0; i < 4; i++)
+ {
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
+ }
+
+ for(i = 0; i < 4; i++) //16bit 4߷Ĵν
+ {
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+
+ split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck͵ƽ ݴͨߵм
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
+
+ temp_data = temp_data<<4;
+ temp_data = temp_data + split_data[i];
+ //temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sckߵƽ ݴмMCU
+// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
+
+ }
+
+ for(i = 0; i < 4; i++)
+ {
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
+ }
+
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
+ fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
+ *rxdata = temp_data;
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
+ XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
+ //usleep(20);
+}
+
+/******************************************************************************
+* Function : void GPIO_dir_set(u32* device,char dir)
+* Description : change GPIO direction
+* Parameter : device -- CPLD
+* dir -- GPIO_OUT/GPIO_IN
+* Return : void
+******************************************************************************/
+void GPIO_dir_set_16(u32* device,char dir)
+{
+ u32 sdio[16] = {0};
+ u8 i;
+
+ for(i = 0; i < 16;i++)
+ {
+ sdio[i] = *(device+i);
+
+ //XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
+ }
+
+}
+
+void GPIO_dir_set_cs_enable(u32* device,u8 dir)
+{
+ u32 sdio[4] = {0};
+ u8 i;
+ u8 dir_temp = 0;
+
+ for(i = 0; i < 4;i++)
+ {
+ sdio[i] = *(device+i);
+ dir_temp = (((dir >> (3-i))) & 0x01);
+ XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
+ }
+}
+
+
+void rst(char *d)
+{
+ XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
+ XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
+ usleep(20);
+ XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
+}
+
+
+void func_test(void)
+{
+
+ XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/SPI_Driv.h b/2.FW/Zynq/proj_cal/Vitis/calboard/src/SPI_Driv.h
new file mode 100644
index 0000000..88355b2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/SPI_Driv.h
@@ -0,0 +1,47 @@
+/*
+ * SPI_Driv.h
+ *
+ * Created on: 202142
+ * Author: dell
+ */
+
+#ifndef SRC_SPI_DRIV_H_
+#define SRC_SPI_DRIV_H_
+
+#include "sleep.h"
+#include "stdio.h"
+#include "xgpiops.h"
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+#define wr_flag 1
+#define rd_flag 0
+
+#define GPIO_OUT 1
+#define GPIO_IN 0
+
+#define NUM_SCK_CMD 4
+#define NUM_SCK_ADDR 8
+#define NUM_SCK_LENGTH 4
+#define NUM_SCK_ENABLE 8
+#define NUM_SCK_BYTE 2
+
+void interface_initial(u32* device);
+void rst_CPLD(u32* device,u32 num_wire);
+
+void rst(char *d);
+
+void spi_write_onewire(char addr, char *data, char width, u32* device);
+u32 spi_read_onewire(char addr,char width,u32* device,char* read_data);
+
+void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
+u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3);
+void spi_write_fourwire(char addr,u16 data,u32* device);
+void spi_read_fourwire(char addr,u16* rxdata,u32* device);
+
+void GPIO_dir_set_16(u32* device,char dir);
+void GPIO_dir_set_cs_enable(u32* device,u8 dir);
+
+#endif /* SRC_SPI_DRIV_H_ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/Xilinx.spec b/2.FW/Zynq/proj_cal/Vitis/calboard/src/Xilinx.spec
new file mode 100644
index 0000000..9c27dca
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/Xilinx.spec
@@ -0,0 +1,2 @@
+*startfile:
+crti%O%s crtbegin%O%s
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/cal_meas.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/cal_meas.c
new file mode 100644
index 0000000..1f74ebd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/cal_meas.c
@@ -0,0 +1,255 @@
+/*
+ * cal_meas.c
+ *
+ * Created on: 2023719
+ * Author: dell
+ */
+
+#include "cal_meas.h"
+#include "SPI_Driv.h"
+char sw_config_data[3] = {0x00,0x00,0x00};
+
+void sw_config(char *slot_start)
+{
+ char slot = (*slot_start);
+ char m_fun = *(slot_start+1);
+ char ch_num_h = *(slot_start+2);
+ char ch_num_l = *(slot_start+3);
+ char volt_cur = *(slot_start+4);
+ char load = *(slot_start+5);
+ char memt_areal = *(slot_start+6);
+
+ u16 ch_num = 0;
+ u32 ch_num_dat = 0;
+ u32 relay_ctrl = 0;
+ u32 slot_en = 0x00000001;
+
+ u8 cpld_addr = 0;
+ u32 cpld_dat = 0;
+
+ ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
+
+
+ if(slot==1)
+ {
+ cpld_addr = 0x82;
+ }
+ else if(slot==2)
+ {
+ cpld_addr = 0x83;
+ }
+ else if(slot==3)
+ {
+ cpld_addr = 0x84;
+ }
+ else
+ {
+ cpld_addr = 0x85;
+ }
+
+ switch(ch_num)
+ {
+ case 0x0001:
+ {
+ relay_ctrl = 0x00000000;
+ break;
+ }
+ case 0x0002:
+ {
+ relay_ctrl = 0x00020000;
+ break;
+ }
+ case 0x0003:
+ {
+ relay_ctrl = 0x00200000;
+ break;
+ }
+ case 0x0004:
+ {
+ relay_ctrl = 0x00220000;
+ break;
+ }
+ case 0x0005:
+ {
+ relay_ctrl = 0x00800000;
+ break;
+ }
+ case 0x0006:
+ {
+ relay_ctrl = 0x00810000;
+ break;
+ }
+ case 0x0007:
+ {
+ relay_ctrl = 0x00A00000;
+ break;
+ }
+ case 0x0008:
+ {
+ relay_ctrl = 0x00A10000;
+ break;
+ }
+ case 0x0041:
+ {
+ relay_ctrl = 0x00000000;
+ break;
+ }
+ case 0x0042:
+ {
+ relay_ctrl = 0x00008000;
+ break;
+ }
+ case 0x0043:
+ {
+ relay_ctrl = 0x00100000;
+ break;
+ }
+ case 0x0044:
+ {
+ relay_ctrl = 0x00108000;
+ break;
+ }
+ case 0x0045:
+ {
+ relay_ctrl = 0x00800000;
+ break;
+ }
+ case 0x0046:
+ {
+ relay_ctrl = 0x00804000;
+ break;
+ }
+ case 0x0047:
+ {
+ relay_ctrl = 0x00900000;
+ break;
+ }
+ case 0x0048:
+ {
+ relay_ctrl = 0x00904000;
+ break;
+ }
+ case 0x0081:
+ {
+ relay_ctrl = 0x00000000;
+ break;
+ }
+ case 0x0082:
+ {
+ relay_ctrl = 0x00002000;
+ break;
+ }
+ case 0x0083:
+ {
+ relay_ctrl = 0x00080000;
+ break;
+ }
+ case 0x0084:
+ {
+ relay_ctrl = 0x00082000;
+ break;
+ }
+ case 0x0085:
+ {
+ relay_ctrl = 0x00400000;
+ break;
+ }
+ case 0x0086:
+ {
+ relay_ctrl = 0x00401000;
+ break;
+ }
+ case 0x0087:
+ {
+ relay_ctrl = 0x00480000;
+ break;
+ }
+ case 0x0088:
+ {
+ relay_ctrl = 0x00481000;
+ break;
+ }
+ case 0x00C1:
+ {
+ relay_ctrl = 0x00000000;
+ break;
+ }
+ case 0x00C2:
+ {
+ relay_ctrl = 0x00000800;
+ break;
+ }
+ case 0x00C3:
+ {
+ relay_ctrl = 0x00040000;
+ break;
+ }
+ case 0x00C4:
+ {
+ relay_ctrl = 0x00040800;
+ break;
+ }
+ case 0x00C5:
+ {
+ relay_ctrl = 0x00400000;
+ break;
+ }
+ case 0x00C6:
+ {
+ relay_ctrl = 0x00400400;
+ break;
+ }
+ case 0x00C7:
+ {
+ relay_ctrl = 0x00440000;
+ break;
+ }
+ case 0x00C8:
+ {
+ relay_ctrl = 0x00440400;
+ break;
+ }
+ }
+
+ ch_num_dat = ((u32)ch_num)<<1;
+ cpld_dat = relay_ctrl|ch_num_dat|slot_en;
+
+ sw_config_data[0] = (u8)(cpld_dat>>16);
+ sw_config_data[1] = (u8)(cpld_dat>>8);
+ sw_config_data[2] = (u8)(cpld_dat);
+
+ xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
+ xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
+
+ xil_printf("cpld_addr: %d\n\r", cpld_addr);
+ xil_printf("cpld_dat: %d\n\r", cpld_dat);
+
+ xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
+ xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
+ xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
+
+ spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
+ spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
+ spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
+
+ sw_config_data[0] = 0x00;
+ sw_config_data[1] = 0x00;
+ sw_config_data[2] = 0x01;
+ spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
+ spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
+ spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
+
+ slot_en = 0x00000000;
+ cpld_dat = relay_ctrl|ch_num_dat|slot_en;
+
+ sw_config_data[0] = (u8)(cpld_dat>>16);
+ sw_config_data[1] = (u8)(cpld_dat>>8);
+ sw_config_data[2] = (u8)(cpld_dat);
+
+ spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
+ spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
+ spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
+}
+
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/cal_meas.h b/2.FW/Zynq/proj_cal/Vitis/calboard/src/cal_meas.h
new file mode 100644
index 0000000..e0ca773
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/cal_meas.h
@@ -0,0 +1,23 @@
+/*
+ * cal_meas.h
+ *
+ * Created on: 2023719
+ * Author: dell
+ */
+
+#ifndef SRC_CAL_MEAS_H_
+#define SRC_CAL_MEAS_H_
+
+#include "sleep.h"
+#include "stdio.h"
+#include "xgpiops.h"
+#include "SPI_Driv.h"
+#include "GPIO_Driv.h"
+
+
+#define dat_width 3
+
+void sw_config(char *slot_start);
+
+
+#endif /* SRC_CAL_MEAS_H_ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/crc16.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/crc16.c
new file mode 100644
index 0000000..b3b8828
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/crc16.c
@@ -0,0 +1,57 @@
+/*
+ * crc16.c
+ *
+ * Created on: 2022224
+ * Author: Administrator
+ */
+#include "crc16.h"
+
+const unsigned int crc_table[256] = {
+ 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+ 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+ 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+ 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+ 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+ 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+ 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+ 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+ 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+ 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+ 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+ 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+ 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+ 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+ 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+ 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+ 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+ 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+ 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+ 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+ 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+ 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+ 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+ 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+ 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+ 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+ 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+ 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+ 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+ 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+ 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+ 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+unsigned short do_crc_table(unsigned char* ptr, int len)
+{
+ unsigned short crc = 0x0000;
+
+
+ while (len--)
+ {
+ crc = (crc >> 8) ^ crc_table[(crc ^ *ptr++) & 0xff];
+ }
+
+ return crc;
+}
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/crc16.h b/2.FW/Zynq/proj_cal/Vitis/calboard/src/crc16.h
new file mode 100644
index 0000000..2838c23
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/crc16.h
@@ -0,0 +1,13 @@
+/*
+ * crc16.h
+ *
+ * Created on: 2022224
+ * Author: Administrator
+ */
+
+#ifndef SRC_CRC16_H_
+#define SRC_CRC16_H_
+
+unsigned short do_crc_table(unsigned char* ptr, int len);
+
+#endif /* SRC_CRC16_H_ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/dna_read.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/dna_read.c
new file mode 100644
index 0000000..21b920b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/dna_read.c
@@ -0,0 +1,29 @@
+/*
+ * dna_read.c
+ *
+ * Created on: 2023627
+ * Author: dell
+ */
+#include "dna_read.h"
+
+#include "xil_io.h"
+#include "xparameters.h"
+
+#define DNA_ADDR XPAR_MYDNA_READ_V1_0_0_BASEADDR
+
+
+void dna_port_read(char* read_data) //addr_change, because the board is 88d_a.
+{
+ unsigned read_data_mem[2] = {0};
+ Xil_Out32(DNA_ADDR,0x01);
+ usleep(20);
+
+ read_data_mem[0] = Xil_In32(DNA_ADDR+4);
+ read_data_mem[1] = Xil_In32(DNA_ADDR+8);
+
+ for(int i = 0; i < 8; i++)
+ {
+ *(read_data+i) = (u8)(read_data_mem[i/4]>> (24 - (8*(i%4))));
+ }
+
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/dna_read.h b/2.FW/Zynq/proj_cal/Vitis/calboard/src/dna_read.h
new file mode 100644
index 0000000..2ce32a1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/dna_read.h
@@ -0,0 +1,14 @@
+/*
+ * dna_read.h
+ *
+ * Created on: 2023627
+ * Author: dell
+ */
+
+#ifndef SRC_DNA_READ_H_
+#define SRC_DNA_READ_H_
+
+void dna_port_read(char* read_data); //addr_change, because the board is 88d_a.
+
+
+#endif /* SRC_DNA_READ_H_ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/echo.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/echo.c
new file mode 100644
index 0000000..e35a181
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/echo.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2009 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include
+#include
+#include "dna_read.h"
+#include "crc16.h"
+#include "GPIO_Driv.h"
+#include "SPI_Driv.h"
+#include "cal_meas.h"
+
+#include "lwip/err.h"
+#include "lwip/tcp.h"
+#if defined (__arm__) || defined (__aarch64__)
+#include "xil_printf.h"
+#endif
+
+char *recv_data;
+char dna_data[10];
+unsigned short recv_len;
+
+unsigned read_dat = 0;
+char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+unsigned crc_read_dat = 0;
+
+char crc_alg_dat[2] = {0,0};
+
+char send_data_cpld1[2] = {0xAA,0x56};
+
+int transfer_data() {
+ return 0;
+}
+
+void print_app_header()
+{
+#if (LWIP_IPV6==0)
+ xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
+#else
+ xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
+#endif
+ xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
+}
+
+err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
+ struct pbuf *p, err_t err)
+{
+ /* do not read the packet if we are not in ESTABLISHED state */
+ if (!p) {
+ tcp_close(tpcb);
+ tcp_recv(tpcb, NULL);
+ return ERR_OK;
+ }
+
+ /* indicate that the packet has been received */
+ tcp_recved(tpcb, p->len);
+
+ /* echo back the payload */
+ /* in this case, we assume that the payload is < TCP_SND_BUF */
+ if (tcp_sndbuf(tpcb) > p->len) {
+
+ recv_len = p->len;
+ recv_data = (char*)malloc(sizeof(char)*recv_len);
+ memcpy(recv_data,p->payload,recv_len);
+
+ if(recv_data[6] == 0x0E)
+ {
+ crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
+
+ crc_alg_dat[0] = (u8)crc_read_dat;
+ crc_alg_dat[1] = (u8)(crc_read_dat>>8);
+ dat_0[0]= 0x00;
+
+ switch(recv_data[7])
+ {
+
+ case 0xA2://SLOT
+ {
+ dat_0[1]= 0x06;
+ dat_0[2]= recv_data[2];
+ dat_0[3]= recv_data[3];
+ dat_0[4]= recv_data[4];
+ dat_0[5]= recv_data[5];
+ dat_0[6]= recv_data[6];
+ dat_0[7]= recv_data[7];
+ if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
+ {
+ dat_0[8]= 0x01;
+ dat_0[9]= 0x01;
+ }
+ else
+ {
+ dat_0[8]= 0xff;
+ dat_0[9]= 0xff;
+ }
+ dat_0[10]= recv_data[15];
+ dat_0[11]= recv_data[16];
+
+ char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
+ //xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
+ //rst_CPLD(CPLD_U1,4);
+ //rst_CPLD(CPLD_U2,4);
+ //rst_CPLD(CPLD_U3,4);
+ sw_config(slot_start);
+
+ tcp_write(tpcb, dat_0, 12, 1);
+
+ break;
+ }
+
+ case 0xA3://dna_port_read
+ {
+ dna_port_read(dna_data);
+ dat_0[1]=0x0e;
+ dat_0[2]=recv_data[2];
+ dat_0[3]=recv_data[3];
+ dat_0[4]=recv_data[4];
+ dat_0[5]=recv_data[5];
+ dat_0[6]=recv_data[6];
+ dat_0[7]=recv_data[7];
+ if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
+ {
+ dat_0[8]= 0x01;
+ dat_0[9]= 0x01;
+ }
+ else
+ {
+ dat_0[8]= 0xff;
+ dat_0[9]= 0xff;
+ }
+ dat_0[10]= dna_data[0];
+ dat_0[11]= dna_data[1];
+ dat_0[12]= dna_data[2];
+ dat_0[13]= dna_data[3];
+ dat_0[14]= dna_data[4];
+ dat_0[15]= dna_data[5];
+ dat_0[16]= dna_data[6];
+ dat_0[17]= dna_data[7];
+
+ dat_0[18]= recv_data[8];
+ dat_0[19]= recv_data[9];
+
+ tcp_write(tpcb, dat_0, 20, 1);
+ break;
+ }
+ }
+ }
+ } else
+ xil_printf("no space in tcp_sndbuf\n\r");
+
+
+
+ /* free the received pbuf */
+ pbuf_free(p);
+
+ return ERR_OK;
+}
+
+err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+ static int connection = 1;
+
+ /* set the receive callback for this connection */
+ tcp_recv(newpcb, recv_callback);
+
+ /* just use an integer number indicating the connection id as the
+ callback argument */
+ tcp_arg(newpcb, (void*)(UINTPTR)connection);
+
+ /* increment for subsequent accepted connections */
+ connection++;
+
+ return ERR_OK;
+}
+
+
+int start_application()
+{
+ struct tcp_pcb *pcb;
+ err_t err;
+ unsigned port = 200;
+
+ /* create new TCP PCB structure */
+ pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
+ if (!pcb) {
+ xil_printf("Error creating PCB. Out of Memory\n\r");
+ return -1;
+ }
+
+ /* bind to specified @port */
+ err = tcp_bind(pcb, IP_ANY_TYPE, port);
+ if (err != ERR_OK) {
+ xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
+ return -2;
+ }
+
+ /* we do not need any arguments to callback functions */
+ tcp_arg(pcb, NULL);
+
+ /* listen for connections */
+ pcb = tcp_listen(pcb);
+ if (!pcb) {
+ xil_printf("Out of memory while tcp_listen\n\r");
+ return -3;
+ }
+
+ /* specify callback to use for incoming connections */
+ tcp_accept(pcb, accept_callback);
+
+ xil_printf("TCP echo server started @ port %d\n\r", port);
+
+ return 0;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/i2c_access.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/i2c_access.c
new file mode 100644
index 0000000..7fd9815
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/i2c_access.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2013 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+/*****************************************************************************/
+/**
+ * @file i2c_lib.c
+ *
+ * This file contains library functions to initialize, control and access
+ * IIC devices.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ---------------------------------------------------------
+ * 1.0 srt 10/19/13 Initial Version
+ *
+ *
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#if defined (__arm__) && !defined (ARMR5)
+#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
+ XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+#include "xil_exception.h"
+#include "xil_printf.h"
+#include "xiicps.h"
+#include "sleep.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+#define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID
+#define XIIC XIicPs
+#define XIICCFG XIicPs_Config
+#define I2cSetStatusHandler XIicPs_SetStatusHandler
+#define I2cLookupConfig XIicPs_LookupConfig
+#define I2cCfgInitialize XIicPs_CfgInitialize
+#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define IIC_INTR_ID XPAR_XIICPS_0_INTR
+#define INTC_HANDLER XScuGic_InterruptHandler
+#define IIC_HANDLER XIicPs_IntrHandler
+#define INTC XScuGic
+#define IIC_SCLK_RATE 100000
+/**************************** Type Definitions *******************************/
+typedef struct {
+ XIIC I2cInstance;
+ INTC IntcInstance;
+ volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
+ volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
+ volatile u32 TotalErrorCount;
+} XIIC_LIB;
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
+int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
+int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
+int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
+int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
+static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr);
+static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event);
+
+/************************* Global Definitions *****************************/
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * This function configures the IIC hardware.
+ *
+ * @param I2cLibPtr contains a pointer to the instance of the IIC library
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ ******************************************************************************/
+int I2cSetupHardware(XIIC_LIB *I2cLibPtr)
+{
+ int Status;
+ XIICCFG *ConfigPtr;
+ XIIC *I2cInstancePtr;
+
+ I2cInstancePtr = &I2cLibPtr->I2cInstance;
+
+ /*
+ * Initialize the IIC driver so that it is ready to use.
+ */
+ ConfigPtr = I2cLookupConfig(IIC_DEVICE_ID);
+ if (ConfigPtr == NULL) {
+ return XST_FAILURE;
+ }
+
+ Status = I2cCfgInitialize(I2cInstancePtr, ConfigPtr,
+ ConfigPtr->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ /*
+ * GPIO Code to pull MUX out of reset.
+ */
+ Xil_Out32(0xe000a204, 0x2000);
+ Xil_Out32(0xe000a208, 0x2000);
+ Xil_Out32(0xe000a040, 0x2000);
+
+ /*
+ * Setup the Interrupt System.
+ */
+ Status = SetupInterruptSystem(I2cLibPtr);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ I2cSetStatusHandler(I2cInstancePtr, I2cLibPtr, (IIC_HANDLER) StatusHandler);
+
+ /*
+ * Set the IIC serial clock rate.
+ */
+ XIicPs_SetSClk(I2cInstancePtr, IIC_SCLK_RATE);
+
+ I2cLibPtr->TotalErrorCount = 0;
+ I2cLibPtr->TransmitComplete = FALSE;
+ I2cLibPtr->ReceiveComplete = FALSE;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * This function writes data to the PHY.
+ *
+ * @param I2cLibPtr contains a pointer to the instance of the IIC library
+ * @param PhyAddr is the address of PHY to be written
+ * @param Reg is the register address to be written to
+ * @param Data is the pointer which contains the data to be written
+ * @param SlaveAddr is the address of the slave we are sending to.
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ ******************************************************************************/
+int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr)
+{
+ int Status;
+ u8 WrBuffer[3];
+
+ WrBuffer[0] = Reg;
+ WrBuffer[1] = Data >> 8;
+ WrBuffer[2] = Data;
+
+ Status = I2cWriteData(I2cLibPtr, WrBuffer, 3, SlaveAddr);
+ if (Status != XST_SUCCESS) {
+ xil_printf("PhyWrite: Writing data failed\n\r");
+ return Status;
+ }
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * This function reads data from the PHY.
+ *
+ * @param I2cLibPtr contains a pointer to the instance of the IIC library
+ * @param PhyAddr is the address of PHY to be read from
+ * @param Reg is the register address to be read from
+ * @param Data is the pointer which stores the data read
+ * @param SlaveAddr is the address of the slave we are sending to.
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ ******************************************************************************/
+int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr)
+{
+ int Status;
+ u8 WrBuffer[2];
+ u8 RdBuffer[2];
+
+ WrBuffer[0] = Reg;
+
+ Status = I2cWriteData(I2cLibPtr, WrBuffer, 1, SlaveAddr);
+ if (Status != XST_SUCCESS) {
+ xil_printf("PhyWrite: Writing data failed\n\r");
+ return Status;
+ }
+
+ Status = I2cReadData(I2cLibPtr, RdBuffer, 2, SlaveAddr);
+ if (Status != XST_SUCCESS) {
+ xil_printf("PhyRead: Reading data failed\n\r");
+ return Status;
+ }
+
+ *Data = RdBuffer[0] << 8 | RdBuffer[1];
+
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * This function writes a buffer of data to the IIC Device.
+ *
+ * @param I2cLibPtr contains a pointer to the instance of the IIC library
+ * @param WrBuffer is the buffer which contains data to be written
+ * @param ByteCount contains the number of bytes in the buffer to be
+ * written.
+ * @param SlaveAddr is the address of the slave we are sending to.
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ ******************************************************************************/
+int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount,
+ u16 SlaveAddr)
+{
+ XIIC *I2cInstancePtr;
+
+ I2cInstancePtr = &I2cLibPtr->I2cInstance;
+
+ I2cLibPtr->TransmitComplete = FALSE;
+
+ /*
+ * Send the Data.
+ */
+ XIicPs_MasterSend(I2cInstancePtr, WrBuffer, ByteCount, SlaveAddr);
+
+ /*
+ * Wait for the entire buffer to be sent, letting the interrupt
+ * processing work in the background, this function may get
+ * locked up in this loop if the interrupts are not working
+ * correctly.
+ */
+ while (I2cLibPtr->TransmitComplete == FALSE) {
+ if (0 != I2cLibPtr->TotalErrorCount) {
+ xil_printf("I2cWriteData: Failed due to errors\n\r");
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * Wait until bus is idle to start another transfer.
+ */
+ while (XIicPs_BusIsBusy(I2cInstancePtr));
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * This function read data from the IIC Device.
+ *
+ * @param I2cLibPtr contains a pointer to the instance of the IIC library
+ * @param RdBuffer is the buffer into which data read
+ * @param ByteCount contains the number of bytes in the buffer to be
+ * written.
+ * @param SlaveAddr is the address of the slave we are sending to.
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ ******************************************************************************/
+int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr)
+{
+ XIIC *I2cInstancePtr;
+
+ I2cInstancePtr = &I2cLibPtr->I2cInstance;
+
+ I2cLibPtr->ReceiveComplete = FALSE;
+
+ /*
+ * Receive the Data.
+ */
+ XIicPs_MasterRecv(I2cInstancePtr, RdBuffer, ByteCount, SlaveAddr);
+
+ while (I2cLibPtr->ReceiveComplete == FALSE) {
+ if (0 != I2cLibPtr->TotalErrorCount) {
+ xil_printf("I2cReadData: Failed due to errors %d\n\r",
+ I2cLibPtr->TotalErrorCount);
+ return XST_FAILURE;
+ }
+ }
+
+ /*
+ * Wait until bus is idle to start another transfer.
+ */
+ while (XIicPs_BusIsBusy(I2cInstancePtr))
+ ;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * This function setups the interrupt system so interrupts can occur for the
+ * IIC device. The function is application-specific since the actual system may
+ * or may not have an interrupt controller. The IIC device could be directly
+ * connected to a processor without an interrupt controller. The user should
+ * modify this function to fit the application.
+ *
+ * @param IicInstPtr contains a pointer to the instance of the IIC device
+ * which is going to be connected to the interrupt controller.
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
+{
+ int Status;
+ XIIC *I2cInstancePtr;
+ INTC *IntcPtr;
+
+ I2cInstancePtr = &I2cLibPtr->I2cInstance;
+ IntcPtr = &I2cLibPtr->IntcInstance;
+
+ XScuGic_Config *IntcConfig;
+
+ /*
+ * Initialize the interrupt controller driver so that it is ready to
+ * use.
+ */
+ IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
+ if (NULL == IntcConfig) {
+ return XST_FAILURE;
+ }
+
+ Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
+ IntcConfig->CpuBaseAddress);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
+ XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
+
+ /*
+ * Connect the interrupt handler that will be called when an
+ * interrupt occurs for the device.
+ */
+ Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
+ (Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
+ I2cInstancePtr);
+ if (Status != XST_SUCCESS) {
+ return Status;
+ }
+
+ /*
+ * Enable the interrupt for the IIC device.
+ */
+ XScuGic_Enable(IntcPtr, IIC_INTR_ID);
+
+ /*
+ * Initialize the exception table and register the interrupt
+ * controller handler with the exception table
+ */
+ Xil_ExceptionInit();
+
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
+
+ /* Enable non-critical exceptions */Xil_ExceptionEnable();
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * This Status handler is called asynchronously from an interrupt
+ * context and indicates the events that have occurred.
+ *
+ * @param InstancePtr is a pointer to the IIC driver instance for which
+ * the handler is being called for.
+ * @param Event indicates the condition that has occurred.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event)
+{
+ /*
+ * All of the data transfer has been finished.
+ */
+ if (0 != (Event & XIICPS_EVENT_COMPLETE_RECV)) {
+ I2cLibPtr->ReceiveComplete = TRUE;
+ } else if (0 != (Event & XIICPS_EVENT_COMPLETE_SEND)) {
+ I2cLibPtr->TransmitComplete = TRUE;
+ } else if (0 == (Event & XIICPS_EVENT_SLAVE_RDY)) {
+ /*
+ * If it is other interrupt but not slave ready interrupt, it is
+ * an error.
+ * Data was received with an error.
+ */
+ I2cLibPtr->TotalErrorCount++;
+ }
+}
+#endif
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/iic_phyreset.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/iic_phyreset.c
new file mode 100644
index 0000000..d7a54d0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/iic_phyreset.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2016 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include
+
+#include "xparameters.h"
+#if defined (__arm__) || defined(__aarch64__)
+#include "xil_printf.h"
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+#include "xiicps.h"
+
+#define BUF_LEN 10U
+
+#define IOEXPANDER1_ADDR 0x20U
+
+#define IIC_SCLK_RATE_IOEXP 400000
+
+#define CMD_CFG_0_REG 0x06U
+#define CMD_OUTPUT_0_REG 0x02U
+#define DATA_OUTPUT 0x0U
+
+#define DATA_COMMON_CFG 0xE0U
+#define DATA_GT_0000_CFG 0x00U
+
+XIicPs I2c0InstancePtr;
+
+int IicPhyReset(void)
+{
+
+ u8 WriteBuffer[BUF_LEN] = {0};
+ XIicPs_Config *I2c0CfgPtr;
+ int Status = XST_SUCCESS;
+
+ /* Initialize the IIC0 driver so that it is ready to use */
+ I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
+ if (I2c0CfgPtr == NULL) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
+ I2c0CfgPtr->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ /* Set the IIC serial clock rate */
+ XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
+
+ /* Configure I/O pins as Output */
+ WriteBuffer[0] = CMD_CFG_0_REG;
+ WriteBuffer[1] = DATA_OUTPUT;
+ Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
+ WriteBuffer, 2, IOEXPANDER1_ADDR);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ /* Wait until bus is idle to start another transfer */
+ while (XIicPs_BusIsBusy(&I2c0InstancePtr));
+
+ /*
+ * Deasserting I2C_MUX_RESETB
+ * And GEM3 Resetb
+ * Selecting lanes based on configuration
+ */
+ WriteBuffer[0] = CMD_OUTPUT_0_REG;
+ /* gt0000 or no GT configuration */
+ WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
+
+ /* Send the Data */
+ Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
+ WriteBuffer, 2, IOEXPANDER1_ADDR);
+ if (Status != XST_SUCCESS) {
+ Status = XST_FAILURE;
+ return Status;
+ }
+
+ /* Wait until bus is idle */
+ while (XIicPs_BusIsBusy(&I2c0InstancePtr));
+
+ xil_printf("IIC PHY reset on ZCU102 successful \n\r");
+
+ return XST_SUCCESS;
+}
+#endif
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/lscript.ld b/2.FW/Zynq/proj_cal/Vitis/calboard/src/lscript.ld
new file mode 100644
index 0000000..f437fcf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/lscript.ld
@@ -0,0 +1,287 @@
+/*******************************************************************/
+/* */
+/* This file is automatically generated by linker script generator.*/
+/* */
+/* Version: 2018.3 */
+/* */
+/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
+/* */
+/* Description : Cortex-A9 Linker Script */
+/* */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0xA000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0xA000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+ ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
+ ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+ ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+ KEEP (*(.vectors))
+ *(.boot)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu_warning)
+ *(.gcc_execpt_table)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.ARM.extab)
+ *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_0
+
+.init : {
+ KEEP (*(.init))
+} > ps7_ddr_0
+
+.fini : {
+ KEEP (*(.fini))
+} > ps7_ddr_0
+
+.rodata : {
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > ps7_ddr_0
+
+.rodata1 : {
+ __rodata1_start = .;
+ *(.rodata1)
+ *(.rodata1.*)
+ __rodata1_end = .;
+} > ps7_ddr_0
+
+.sdata2 : {
+ __sdata2_start = .;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ __sdata2_end = .;
+} > ps7_ddr_0
+
+.sbss2 : {
+ __sbss2_start = .;
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ __sbss2_end = .;
+} > ps7_ddr_0
+
+.data : {
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ *(.jcr)
+ *(.got)
+ *(.got.plt)
+ __data_end = .;
+} > ps7_ddr_0
+
+.data1 : {
+ __data1_start = .;
+ *(.data1)
+ *(.data1.*)
+ __data1_end = .;
+} > ps7_ddr_0
+
+.got : {
+ *(.got)
+} > ps7_ddr_0
+
+.ctors : {
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > ps7_ddr_0
+
+.dtors : {
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > ps7_ddr_0
+
+.fixup : {
+ __fixup_start = .;
+ *(.fixup)
+ __fixup_end = .;
+} > ps7_ddr_0
+
+.eh_frame : {
+ *(.eh_frame)
+} > ps7_ddr_0
+
+.eh_framehdr : {
+ __eh_framehdr_start = .;
+ *(.eh_framehdr)
+ __eh_framehdr_end = .;
+} > ps7_ddr_0
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > ps7_ddr_0
+
+.mmu_tbl (ALIGN(16384)) : {
+ __mmu_tbl_start = .;
+ *(.mmu_tbl)
+ __mmu_tbl_end = .;
+} > ps7_ddr_0
+
+.ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ *(.gnu.linkonce.armexidix.*.*)
+ __exidx_end = .;
+} > ps7_ddr_0
+
+.preinit_array : {
+ __preinit_array_start = .;
+ KEEP (*(SORT(.preinit_array.*)))
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+} > ps7_ddr_0
+
+.init_array : {
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+} > ps7_ddr_0
+
+.fini_array : {
+ __fini_array_start = .;
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array))
+ __fini_array_end = .;
+} > ps7_ddr_0
+
+.ARM.attributes : {
+ __ARM.attributes_start = .;
+ *(.ARM.attributes)
+ __ARM.attributes_end = .;
+} > ps7_ddr_0
+
+.sdata : {
+ __sdata_start = .;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __sdata_end = .;
+} > ps7_ddr_0
+
+.sbss (NOLOAD) : {
+ __sbss_start = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ __sbss_end = .;
+} > ps7_ddr_0
+
+.tdata : {
+ __tdata_start = .;
+ *(.tdata)
+ *(.tdata.*)
+ *(.gnu.linkonce.td.*)
+ __tdata_end = .;
+} > ps7_ddr_0
+
+.tbss : {
+ __tbss_start = .;
+ *(.tbss)
+ *(.tbss.*)
+ *(.gnu.linkonce.tb.*)
+ __tbss_end = .;
+} > ps7_ddr_0
+
+.bss (NOLOAD) : {
+ __bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end = .;
+} > ps7_ddr_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+ . = ALIGN(16);
+ _heap = .;
+ HeapBase = .;
+ _heap_start = .;
+ . += _HEAP_SIZE;
+ _heap_end = .;
+ HeapLimit = .;
+} > ps7_ddr_0
+
+.stack (NOLOAD) : {
+ . = ALIGN(16);
+ _stack_end = .;
+ . += _STACK_SIZE;
+ . = ALIGN(16);
+ _stack = .;
+ __stack = _stack;
+ . = ALIGN(16);
+ _irq_stack_end = .;
+ . += _IRQ_STACK_SIZE;
+ . = ALIGN(16);
+ __irq_stack = .;
+ _supervisor_stack_end = .;
+ . += _SUPERVISOR_STACK_SIZE;
+ . = ALIGN(16);
+ __supervisor_stack = .;
+ _abort_stack_end = .;
+ . += _ABORT_STACK_SIZE;
+ . = ALIGN(16);
+ __abort_stack = .;
+ _fiq_stack_end = .;
+ . += _FIQ_STACK_SIZE;
+ . = ALIGN(16);
+ __fiq_stack = .;
+ _undef_stack_end = .;
+ . += _UNDEF_STACK_SIZE;
+ . = ALIGN(16);
+ __undef_stack = .;
+} > ps7_ddr_0
+
+_end = .;
+}
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/main.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/main.c
new file mode 100644
index 0000000..13f6c9c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/main.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2009 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include
+#include "xparameters.h"
+#include "netif/xadapter.h"
+#include "platform.h"
+#include "platform_config.h"
+#if defined (__arm__) || defined(__aarch64__)
+#include "xil_printf.h"
+#endif
+
+#include "lwip/tcp.h"
+#include "xil_cache.h"
+
+#include "GPIO_Driv.h"
+#include "SPI_Driv.h"
+#include "cal_meas.h"
+
+#if LWIP_IPV6==1
+#include "lwip/ip.h"
+#else
+#if LWIP_DHCP==1
+#include "lwip/dhcp.h"
+#endif
+#endif
+
+/* defined by each RAW mode application */
+void print_app_header();
+int start_application();
+int transfer_data();
+void tcp_fasttmr(void);
+void tcp_slowtmr(void);
+
+/* missing declaration in lwIP */
+void lwip_init();
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+extern volatile int dhcp_timoutcntr;
+err_t dhcp_start(struct netif *netif);
+#endif
+#endif
+
+extern volatile int TcpFastTmrFlag;
+extern volatile int TcpSlowTmrFlag;
+static struct netif server_netif;
+struct netif *echo_netif;
+
+#if LWIP_IPV6==1
+void print_ip6(char *msg, ip_addr_t *ip)
+{
+ print(msg);
+ xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
+ IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
+ IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
+ IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
+ IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
+ IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
+ IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
+ IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
+ IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
+
+}
+#else
+void
+print_ip(char *msg, ip_addr_t *ip)
+{
+ print(msg);
+ xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
+ ip4_addr3(ip), ip4_addr4(ip));
+}
+
+void
+print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
+{
+
+ print_ip("Board IP: ", ip);
+ print_ip("Netmask : ", mask);
+ print_ip("Gateway : ", gw);
+}
+#endif
+
+#if defined (__arm__) && !defined (ARMR5)
+#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+int ProgramSi5324(void);
+int ProgramSfpPhy(void);
+#endif
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+int IicPhyReset(void);
+#endif
+#endif
+
+int main()
+{
+#if LWIP_IPV6==0
+ ip_addr_t ipaddr, netmask, gw;
+
+#endif
+ /* the mac address of the board. this should be unique per board */
+ unsigned char mac_ethernet_address[] =
+ { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
+
+ echo_netif = &server_netif;
+#if defined (__arm__) && !defined (ARMR5)
+#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+ ProgramSi5324();
+ ProgramSfpPhy();
+#endif
+#endif
+
+/* Define this board specific macro in order perform PHY reset on ZCU102 */
+#ifdef XPS_BOARD_ZCU102
+ if(IicPhyReset()) {
+ xil_printf("Error performing PHY reset \n\r");
+ return -1;
+ }
+#endif
+
+ init_platform();
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+ ipaddr.addr = 0;
+ gw.addr = 0;
+ netmask.addr = 0;
+#else
+ /* initialize IP addresses to be used */
+ IP4_ADDR(&ipaddr, 192, 168, 100, 110);
+ IP4_ADDR(&netmask, 255, 255, 255, 0);
+ IP4_ADDR(&gw, 192, 168, 100, 1);
+#endif
+#endif
+ print_app_header();
+
+ lwip_init();
+
+#if (LWIP_IPV6 == 0)
+ /* Add network interface to the netif_list, and set it as default */
+ if (!xemac_add(echo_netif, &ipaddr, &netmask,
+ &gw, mac_ethernet_address,
+ PLATFORM_EMAC_BASEADDR)) {
+ xil_printf("Error adding N/W interface\n\r");
+ return -1;
+ }
+#else
+ /* Add network interface to the netif_list, and set it as default */
+ if (!xemac_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address,
+ PLATFORM_EMAC_BASEADDR)) {
+ xil_printf("Error adding N/W interface\n\r");
+ return -1;
+ }
+ echo_netif->ip6_autoconfig_enabled = 1;
+
+ netif_create_ip6_linklocal_address(echo_netif, 1);
+ netif_ip6_addr_set_state(echo_netif, 0, IP6_ADDR_VALID);
+
+ print_ip6("\n\rBoard IPv6 address ", &echo_netif->ip6_addr[0].u_addr.ip6);
+
+#endif
+ netif_set_default(echo_netif);
+
+ /* now enable interrupts */
+ platform_enable_interrupts();
+
+ /* specify that the network if is up */
+ netif_set_up(echo_netif);
+
+#if (LWIP_IPV6 == 0)
+#if (LWIP_DHCP==1)
+ /* Create a new DHCP client for this interface.
+ * Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
+ * the predefined regular intervals after starting the client.
+ */
+ dhcp_start(echo_netif);
+ dhcp_timoutcntr = 24;
+
+ while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
+ xemacif_input(echo_netif);
+
+ if (dhcp_timoutcntr <= 0) {
+ if ((echo_netif->ip_addr.addr) == 0) {
+ xil_printf("DHCP Timeout\r\n");
+ xil_printf("Configuring default IP of 192.168.100.110\r\n");
+ IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 100, 110);
+ IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
+ IP4_ADDR(&(echo_netif->gw), 192, 168, 100, 1);
+ }
+ }
+
+ ipaddr.addr = echo_netif->ip_addr.addr;
+ gw.addr = echo_netif->gw.addr;
+ netmask.addr = echo_netif->netmask.addr;
+#endif
+
+ print_ip_settings(&ipaddr, &netmask, &gw);
+
+#endif
+
+ EMIO_config();
+
+ interface_initial(CPLD_U1);
+ interface_initial(CPLD_U2);
+ interface_initial(CPLD_U3);
+ rst_CPLD(CPLD_U1,4);
+ rst_CPLD(CPLD_U2,4);
+ rst_CPLD(CPLD_U3,4);
+
+ /* start the application (web server, rxtest, txtest, etc..) */
+ start_application();
+
+
+ /* receive and process packets */
+ while (1) {
+ if (TcpFastTmrFlag) {
+ tcp_fasttmr();
+ TcpFastTmrFlag = 0;
+ }
+ if (TcpSlowTmrFlag) {
+ tcp_slowtmr();
+ TcpSlowTmrFlag = 0;
+ }
+ xemacif_input(echo_netif);
+ transfer_data();
+ }
+
+ /* never reached */
+ cleanup_platform();
+
+ return 0;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform.c
new file mode 100644
index 0000000..e54890a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2009 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+#if __MICROBLAZE__ || __PPC__
+#include "arch/cc.h"
+#include "platform.h"
+#include "platform_config.h"
+#include "xil_cache.h"
+#include "xparameters.h"
+#include "xintc.h"
+#include "xil_exception.h"
+#include "lwip/tcp.h"
+#include "netif/xadapter.h"
+#ifdef STDOUT_IS_16550
+#include "xuartns550_l.h"
+#endif
+
+#include "lwip/tcp.h"
+
+#if LWIP_DHCP==1
+volatile int dhcp_timoutcntr = 24;
+void dhcp_fine_tmr();
+void dhcp_coarse_tmr();
+#endif
+
+volatile int TcpFastTmrFlag = 0;
+volatile int TcpSlowTmrFlag = 0;
+
+extern struct netif *echo_netif;
+
+void
+timer_callback()
+{
+ static int DetectEthLinkStatus = 0;
+ /* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified by lwIP.
+ * It is not important that the timing is absoluetly accurate.
+ */
+ static int odd = 1;
+#if LWIP_DHCP==1
+ static int dhcp_timer = 0;
+#endif
+ DetectEthLinkStatus++;
+ TcpFastTmrFlag = 1;
+
+ odd = !odd;
+ if (odd) {
+
+#if LWIP_DHCP==1
+ dhcp_timer++;
+ dhcp_timoutcntr--;
+#endif
+ TcpSlowTmrFlag = 1;
+#if LWIP_DHCP==1
+ dhcp_fine_tmr();
+ if (dhcp_timer >= 120) {
+ dhcp_coarse_tmr();
+ dhcp_timer = 0;
+ }
+#endif
+ }
+
+ /* For detecting Ethernet phy link status periodically */
+ if (DetectEthLinkStatus == ETH_LINK_DETECT_INTERVAL) {
+ eth_link_detect(echo_netif);
+ DetectEthLinkStatus = 0;
+ }
+}
+
+static XIntc intc;
+
+void platform_setup_interrupts()
+{
+ XIntc *intcp;
+ intcp = &intc;
+
+ XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
+ XIntc_Start(intcp, XIN_REAL_MODE);
+
+ /* Start the interrupt controller */
+ XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
+
+#ifdef __PPC__
+ Xil_ExceptionInit();
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+ (XExceptionHandler)XIntc_DeviceInterruptHandler,
+ (void*) XPAR_INTC_0_DEVICE_ID);
+#elif __MICROBLAZE__
+ microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
+#endif
+
+ platform_setup_timer();
+
+#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
+ /* Enable timer and EMAC interrupts in the interrupt controller */
+ XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
+#ifdef __MICROBLAZE__
+ PLATFORM_TIMER_INTERRUPT_MASK |
+#endif
+ XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
+#endif
+
+
+#ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID
+#ifdef __MICROBLAZE__
+ XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
+#endif
+ XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);
+#endif
+
+
+#ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID
+ XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
+ XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID);
+#endif
+
+
+#ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID
+#ifdef __MICROBLAZE__
+ XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
+#endif
+ XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID);
+#endif
+
+
+}
+
+void
+enable_caches()
+{
+#ifdef __PPC__
+ Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
+ Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
+#elif __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+ Xil_ICacheEnable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+ Xil_DCacheEnable();
+#endif
+#endif
+}
+
+void
+disable_caches()
+{
+ Xil_DCacheDisable();
+ Xil_ICacheDisable();
+}
+
+void init_platform()
+{
+ enable_caches();
+
+#ifdef STDOUT_IS_16550
+ XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
+ XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
+#endif
+
+ platform_setup_interrupts();
+}
+
+void cleanup_platform()
+{
+ disable_caches();
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform.h b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform.h
new file mode 100644
index 0000000..8704381
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2009 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __PLATFORM_H_
+#define __PLATFORM_H_
+
+/* Platform timer is calibrated for 250 ms, so kept interval value 4 to call
+ * eth_link_detect() at every one second
+ */
+#define ETH_LINK_DETECT_INTERVAL 4
+
+void init_platform();
+void cleanup_platform();
+#ifdef __MICROBLAZE__
+void timer_callback();
+#endif
+#ifdef __PPC__
+void timer_callback();
+#endif
+void platform_setup_timer();
+void platform_enable_interrupts();
+#endif
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_config.h b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_config.h
new file mode 100644
index 0000000..b84bf38
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_config.h
@@ -0,0 +1,10 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+
+#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
+
+#define PLATFORM_ZYNQ
+
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_mb.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_mb.c
new file mode 100644
index 0000000..647a414
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_mb.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+/*
+ * platform_mb.c
+ *
+ * MicroBlaze platform specific functions.
+ */
+
+#ifdef __MICROBLAZE__
+
+#include "platform.h"
+#include "platform_config.h"
+
+#include "mb_interface.h"
+
+#include "xparameters.h"
+#include "xintc.h"
+#include "xtmrctr_l.h"
+
+void
+xadapter_timer_handler(void *p)
+{
+ timer_callback();
+
+ /* Load timer, clear interrupt bit */
+ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0,
+ XTC_CSR_INT_OCCURED_MASK
+ | XTC_CSR_LOAD_MASK);
+
+ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0,
+ XTC_CSR_ENABLE_TMR_MASK
+ | XTC_CSR_ENABLE_INT_MASK
+ | XTC_CSR_AUTO_RELOAD_MASK
+ | XTC_CSR_DOWN_COUNT_MASK);
+
+ XIntc_AckIntr(XPAR_INTC_0_BASEADDR, PLATFORM_TIMER_INTERRUPT_MASK);
+}
+
+#define MHZ (66)
+#define TIMER_TLR (25000000*((float)MHZ/100))
+
+void
+platform_setup_timer()
+{
+ /* set the number of cycles the timer counts before interrupting */
+ /* 100 Mhz clock => .01us for 1 clk tick. For 100ms, 10000000 clk ticks need to elapse */
+ XTmrCtr_SetLoadReg(PLATFORM_TIMER_BASEADDR, 0, TIMER_TLR);
+
+ /* reset the timers, and clear interrupts */
+ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
+
+ /* start the timers */
+ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0,
+ XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK
+ | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
+
+ /* Register Timer handler */
+ XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,
+ PLATFORM_TIMER_INTERRUPT_INTR,
+ (XInterruptHandler)xadapter_timer_handler,
+ 0);
+}
+
+void platform_enable_interrupts()
+{
+ microblaze_enable_interrupts();
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_ppc.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_ppc.c
new file mode 100644
index 0000000..13bed1d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_ppc.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+/*
+ * platform_ppc.c
+ *
+ * PPC specific functions to setup timer
+ */
+
+#ifdef __PPC__
+
+#include "platform.h"
+#include "platform_config.h"
+
+#include "xexception_l.h"
+#include "xil_exception.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+#define MHZ 400
+#define PIT_INTERVAL (250*MHZ*1000)
+
+void
+xadapter_timer_handler(void *p)
+{
+ timer_callback();
+
+ XTime_TSRClearStatusBits(XREG_TSR_CLEAR_ALL);
+}
+
+void
+platform_setup_timer()
+{
+#ifdef XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DEC_INT,
+ (XExceptionHandler)xadapter_timer_handler, NULL);
+
+ /* Set DEC to interrupt every 250 mseconds */
+ XTime_DECSetInterval(PIT_INTERVAL);
+ XTime_TSRClearStatusBits(XREG_TSR_CLEAR_ALL);
+ XTime_DECEnableAutoReload();
+ XTime_DECEnableInterrupt();
+#else
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PIT_INT,
+ (XExceptionHandler)xadapter_timer_handler, NULL);
+
+ /* Set PIT to interrupt every 250 mseconds */
+ XTime_PITSetInterval(PIT_INTERVAL);
+ XTime_TSRClearStatusBits(XREG_TSR_CLEAR_ALL);
+ XTime_PITEnableAutoReload();
+ XTime_PITEnableInterrupt();
+#endif
+}
+
+void
+platform_enable_interrupts()
+{
+ Xil_ExceptionEnable();
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_zynq.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_zynq.c
new file mode 100644
index 0000000..2b78cc4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_zynq.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+/*
+* platform_zynq.c
+*
+* Zynq platform specific functions.
+*
+* 02/29/2012: UART initialization is removed. Timer initializations are
+* removed. All unnecessary include files and hash defines are removed.
+* 03/01/2013: Timer initialization is added back. Support for SI #692601 is
+* added in the timer callback. The SI #692601 refers to the following issue.
+*
+* The EmacPs has a HW bug on the Rx path for heavy Rx traffic.
+* Under heavy Rx traffic because of the HW bug there are times when the Rx path
+* becomes unresponsive. The workaround for it is to check for the Rx path for
+* traffic (by reading the stats registers regularly). If the stats register
+* does not increment for sometime (proving no Rx traffic), the function resets
+* the Rx data path.
+*
+*
+ */
+
+#ifdef __arm__
+
+#include "xparameters.h"
+#include "xparameters_ps.h" /* defines XPAR values */
+#include "xil_cache.h"
+#include "xscugic.h"
+#include "lwip/tcp.h"
+#include "xil_printf.h"
+#include "platform.h"
+#include "platform_config.h"
+#include "netif/xadapter.h"
+#ifdef PLATFORM_ZYNQ
+#include "xscutimer.h"
+
+#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define TIMER_DEVICE_ID XPAR_SCUTIMER_DEVICE_ID
+#define INTC_BASE_ADDR XPAR_SCUGIC_0_CPU_BASEADDR
+#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
+#define TIMER_IRPT_INTR XPAR_SCUTIMER_INTR
+
+#define RESET_RX_CNTR_LIMIT 400
+
+void tcp_fasttmr(void);
+void tcp_slowtmr(void);
+
+static XScuTimer TimerInstance;
+
+#ifndef USE_SOFTETH_ON_ZYNQ
+static int ResetRxCntr = 0;
+#endif
+
+extern struct netif *echo_netif;
+
+volatile int TcpFastTmrFlag = 0;
+volatile int TcpSlowTmrFlag = 0;
+
+#if LWIP_DHCP==1
+volatile int dhcp_timoutcntr = 24;
+void dhcp_fine_tmr();
+void dhcp_coarse_tmr();
+#endif
+
+void
+timer_callback(XScuTimer * TimerInstance)
+{
+ static int DetectEthLinkStatus = 0;
+ /* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified
+ * by lwIP. It is not important that the timing is absoluetly accurate.
+ */
+ static int odd = 1;
+#if LWIP_DHCP==1
+ static int dhcp_timer = 0;
+#endif
+ DetectEthLinkStatus++;
+ TcpFastTmrFlag = 1;
+
+ odd = !odd;
+#ifndef USE_SOFTETH_ON_ZYNQ
+ ResetRxCntr++;
+#endif
+ if (odd) {
+#if LWIP_DHCP==1
+ dhcp_timer++;
+ dhcp_timoutcntr--;
+#endif
+ TcpSlowTmrFlag = 1;
+#if LWIP_DHCP==1
+ dhcp_fine_tmr();
+ if (dhcp_timer >= 120) {
+ dhcp_coarse_tmr();
+ dhcp_timer = 0;
+ }
+#endif
+ }
+
+ /* For providing an SW alternative for the SI #692601. Under heavy
+ * Rx traffic if at some point the Rx path becomes unresponsive, the
+ * following API call will ensures a SW reset of the Rx path. The
+ * API xemacpsif_resetrx_on_no_rxdata is called every 100 milliseconds.
+ * This ensures that if the above HW bug is hit, in the worst case,
+ * the Rx path cannot become unresponsive for more than 100
+ * milliseconds.
+ */
+#ifndef USE_SOFTETH_ON_ZYNQ
+ if (ResetRxCntr >= RESET_RX_CNTR_LIMIT) {
+ xemacpsif_resetrx_on_no_rxdata(echo_netif);
+ ResetRxCntr = 0;
+ }
+#endif
+ /* For detecting Ethernet phy link status periodically */
+ if (DetectEthLinkStatus == ETH_LINK_DETECT_INTERVAL) {
+ eth_link_detect(echo_netif);
+ DetectEthLinkStatus = 0;
+ }
+
+ XScuTimer_ClearInterruptStatus(TimerInstance);
+}
+
+void platform_setup_timer(void)
+{
+ int Status = XST_SUCCESS;
+ XScuTimer_Config *ConfigPtr;
+ int TimerLoadValue = 0;
+
+ ConfigPtr = XScuTimer_LookupConfig(TIMER_DEVICE_ID);
+ Status = XScuTimer_CfgInitialize(&TimerInstance, ConfigPtr,
+ ConfigPtr->BaseAddr);
+ if (Status != XST_SUCCESS) {
+
+ xil_printf("In %s: Scutimer Cfg initialization failed...\r\n",
+ __func__);
+ return;
+ }
+
+ Status = XScuTimer_SelfTest(&TimerInstance);
+ if (Status != XST_SUCCESS) {
+ xil_printf("In %s: Scutimer Self test failed...\r\n",
+ __func__);
+ return;
+
+ }
+
+ XScuTimer_EnableAutoReload(&TimerInstance);
+ /*
+ * Set for 250 milli seconds timeout.
+ */
+ TimerLoadValue = XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 8;
+
+ XScuTimer_LoadTimer(&TimerInstance, TimerLoadValue);
+ return;
+}
+
+void platform_setup_interrupts(void)
+{
+ Xil_ExceptionInit();
+
+ XScuGic_DeviceInitialize(INTC_DEVICE_ID);
+
+ /*
+ * Connect the interrupt controller interrupt handler to the hardware
+ * interrupt handling logic in the processor.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+ (void *)INTC_DEVICE_ID);
+ /*
+ * Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device.
+ */
+ XScuGic_RegisterHandler(INTC_BASE_ADDR, TIMER_IRPT_INTR,
+ (Xil_ExceptionHandler)timer_callback,
+ (void *)&TimerInstance);
+ /*
+ * Enable the interrupt for scu timer.
+ */
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
+
+ return;
+}
+
+void platform_enable_interrupts()
+{
+ /*
+ * Enable non-critical exceptions.
+ */
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+ XScuTimer_EnableInterrupt(&TimerInstance);
+ XScuTimer_Start(&TimerInstance);
+ return;
+}
+
+void init_platform()
+{
+ platform_setup_timer();
+ platform_setup_interrupts();
+
+ return;
+}
+
+void cleanup_platform()
+{
+ Xil_ICacheDisable();
+ Xil_DCacheDisable();
+ return;
+}
+#endif
+#endif
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_zynqmp.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_zynqmp.c
new file mode 100644
index 0000000..b155151
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/platform_zynqmp.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2015 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+/*
+* platform_zynqmp.c
+*
+* ZynqMP platform specific functions.
+*
+*
+*
+ */
+
+#if defined (__arm__) || defined (__aarch64__)
+
+#include "xparameters.h"
+#include "xparameters_ps.h" /* defines XPAR values */
+#include "xil_cache.h"
+#include "xscugic.h"
+#include "lwip/tcp.h"
+#include "xil_printf.h"
+#include "platform.h"
+#include "platform_config.h"
+#include "netif/xadapter.h"
+#if defined(PLATFORM_ZYNQMP) || defined(PLATFORM_VERSAL)
+#include "xttcps.h"
+
+#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
+#define TIMER_DEVICE_ID XPAR_XTTCPS_0_DEVICE_ID
+#define TIMER_IRPT_INTR XPAR_XTTCPS_0_INTR
+#define INTC_BASE_ADDR XPAR_SCUGIC_0_CPU_BASEADDR
+#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
+
+#define PLATFORM_TIMER_INTR_RATE_HZ (4)
+
+static XTtcPs TimerInstance;
+static XInterval Interval;
+static u8 Prescaler;
+
+volatile int TcpFastTmrFlag = 0;
+volatile int TcpSlowTmrFlag = 0;
+
+#if LWIP_DHCP==1
+volatile int dhcp_timoutcntr = 24;
+void dhcp_fine_tmr();
+void dhcp_coarse_tmr();
+#endif
+
+extern struct netif *echo_netif;
+
+void platform_clear_interrupt( XTtcPs * TimerInstance );
+
+void
+timer_callback(XTtcPs * TimerInstance)
+{
+ static int DetectEthLinkStatus = 0;
+ /* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified
+ * by lwIP. It is not important that the timing is absoluetly accurate.
+ */
+ static int odd = 1;
+#if LWIP_DHCP==1
+ static int dhcp_timer = 0;
+#endif
+ DetectEthLinkStatus++;
+ TcpFastTmrFlag = 1;
+ odd = !odd;
+ if (odd) {
+#if LWIP_DHCP==1
+ dhcp_timer++;
+ dhcp_timoutcntr--;
+#endif
+ TcpSlowTmrFlag = 1;
+#if LWIP_DHCP==1
+ dhcp_fine_tmr();
+ if (dhcp_timer >= 120) {
+ dhcp_coarse_tmr();
+ dhcp_timer = 0;
+ }
+#endif
+ }
+
+ /* For detecting Ethernet phy link status periodically */
+ if (DetectEthLinkStatus == ETH_LINK_DETECT_INTERVAL) {
+ eth_link_detect(echo_netif);
+ DetectEthLinkStatus = 0;
+ }
+
+ platform_clear_interrupt(TimerInstance);
+}
+
+void platform_setup_timer(void)
+{
+ int Status;
+ XTtcPs * Timer = &TimerInstance;
+ XTtcPs_Config *Config;
+
+
+ Config = XTtcPs_LookupConfig(TIMER_DEVICE_ID);
+
+ Status = XTtcPs_CfgInitialize(Timer, Config, Config->BaseAddress);
+ if (Status != XST_SUCCESS) {
+ xil_printf("In %s: Timer Cfg initialization failed...\r\n",
+ __func__);
+ return;
+ }
+ XTtcPs_SetOptions(Timer, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE);
+ XTtcPs_CalcIntervalFromFreq(Timer, PLATFORM_TIMER_INTR_RATE_HZ, &Interval, &Prescaler);
+ XTtcPs_SetInterval(Timer, Interval);
+ XTtcPs_SetPrescaler(Timer, Prescaler);
+}
+
+void platform_clear_interrupt( XTtcPs * TimerInstance )
+{
+ u32 StatusEvent;
+
+ StatusEvent = XTtcPs_GetInterruptStatus(TimerInstance);
+ XTtcPs_ClearInterruptStatus(TimerInstance, StatusEvent);
+}
+
+void platform_setup_interrupts(void)
+{
+ Xil_ExceptionInit();
+
+ XScuGic_DeviceInitialize(INTC_DEVICE_ID);
+
+ /*
+ * Connect the interrupt controller interrupt handler to the hardware
+ * interrupt handling logic in the processor.
+ */
+ Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+ (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+ (void *)INTC_DEVICE_ID);
+ /*
+ * Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device.
+ */
+ XScuGic_RegisterHandler(INTC_BASE_ADDR, TIMER_IRPT_INTR,
+ (Xil_ExceptionHandler)timer_callback,
+ (void *)&TimerInstance);
+ /*
+ * Enable the interrupt for scu timer.
+ */
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
+
+ return;
+}
+
+void platform_enable_interrupts()
+{
+ /*
+ * Enable non-critical exceptions.
+ */
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TIMER_IRPT_INTR);
+ XTtcPs_EnableInterrupts(&TimerInstance, XTTCPS_IXR_INTERVAL_MASK);
+ XTtcPs_Start(&TimerInstance);
+ return;
+}
+
+void init_platform()
+{
+ platform_setup_timer();
+ platform_setup_interrupts();
+
+ return;
+}
+
+void cleanup_platform()
+{
+ Xil_ICacheDisable();
+ Xil_DCacheDisable();
+ return;
+}
+#endif
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/sfp.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/sfp.c
new file mode 100644
index 0000000..c557fbc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/sfp.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (C) 2013 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+/*****************************************************************************/
+/**
+* @file sfp.c
+*
+* This file programs sfp phy chip.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.0 srt 10/19/13 Initial Version
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#if defined (__arm__) && !defined (ARMR5)
+#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
+ XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+#include "xil_printf.h"
+#include "xiicps.h"
+#include "sleep.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+#define IIC_SLAVE_ADDR 0x56
+#define IIC_MUX_ADDRESS 0x74
+#define IIC_CHANNEL_ADDRESS 0x01
+
+#define XIIC XIicPs
+#define INTC XScuGic
+/**************************** Type Definitions *******************************/
+typedef struct {
+ XIIC I2cInstance;
+ INTC IntcInstance;
+ volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
+ volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
+ volatile u32 TotalErrorCount;
+} XIIC_LIB;
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
+int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
+int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
+int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
+int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * This function initializes ZC706 MUX.
+ *
+ * @param I2cLibPtr contains a pointer to the instance of the IIC library
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ ******************************************************************************/
+int ZC706MuxInit(XIIC_LIB *I2cLibInstancePtr)
+{
+ u8 WrBuffer;
+ int Status;
+
+ WrBuffer = IIC_CHANNEL_ADDRESS;
+
+ Status = I2cWriteData(I2cLibInstancePtr, &WrBuffer, 1, IIC_MUX_ADDRESS);
+ if (Status != XST_SUCCESS) {
+ xil_printf("SFP_PHY: Writing failed\n\r");
+ return XST_FAILURE;
+ }
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * This function program SFP PHY.
+ *
+ * @return XST_SUCCESS if successful else XST_FAILURE.
+ *
+ ******************************************************************************/
+int ProgramSfpPhy(void)
+{
+ XIIC_LIB I2cLibInstance;
+ int Status;
+ u8 WrBuffer[2];
+ u16 phy_read_val;
+
+ Status = I2cSetupHardware(&I2cLibInstance);
+ if (Status != XST_SUCCESS) {
+ xil_printf("Fail!!!\n\r");
+ xil_printf("SFP_PHY: Configuring HW failed\n\r");
+ return XST_FAILURE;
+ }
+ Status = ZC706MuxInit(&I2cLibInstance);
+ if (Status != XST_SUCCESS) {
+ xil_printf("SFP_PHY: Mux Init failed\n\r");
+ return XST_FAILURE;
+ }
+
+ WrBuffer[0] = 0;
+ Status = I2cWriteData(&I2cLibInstance, WrBuffer, 1, IIC_SLAVE_ADDR);
+ if (Status != XST_SUCCESS) {
+ xil_printf("SFP_PHY: Writing failed\n\r");
+ return XST_FAILURE;
+ }
+
+#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+ /* Enabling 1000BASEX */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9088, IIC_SLAVE_ADDR);
+#else
+ /* Enabling SGMII */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9084, IIC_SLAVE_ADDR);
+#endif
+
+ /* Apply Soft Reset */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
+
+ /* Enable 1000BaseT Full Duplex capabilities */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x09, 0x0E00, IIC_SLAVE_ADDR);
+
+ /* Apply Soft Reset */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
+
+ /* Advertise 10/100 Capabilities else change the capabilities */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x04, 0x0141, IIC_SLAVE_ADDR);
+
+ /* Apply Soft Reset */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
+
+ /* Apply Soft Reset */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
+
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x10, 0xF079, IIC_SLAVE_ADDR);
+ /* Apply Soft Reset */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
+
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
+ usleep(1);
+
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
+ phy_read_val = 0x0;
+
+ while((phy_read_val & 0x0C00) != 0x0C00) {
+ I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
+ }
+ usleep(1);
+
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
+ I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
+
+ /* configure speed */
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x14, 0x0c61, IIC_SLAVE_ADDR);
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
+ I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
+
+ return XST_SUCCESS;
+}
+#endif
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard/src/si5324.c b/2.FW/Zynq/proj_cal/Vitis/calboard/src/si5324.c
new file mode 100644
index 0000000..f740188
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard/src/si5324.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2013 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+/*****************************************************************************/
+/**
+* @file si5324.c
+*
+* This file programs si5324 chip which generates clock for the peripherals.
+*
+* Please refer to Si5324 Datasheet for more information
+* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf
+*
+* Tested on Zynq ZC706 platform
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.0 srt 10/19/13 Initial Version
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#if defined (__arm__) && !defined (ARMR5)
+#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
+ XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+#include "xil_printf.h"
+#include "xiicps.h"
+#include "sleep.h"
+#include "xscugic.h"
+/************************** Constant Definitions *****************************/
+#define IIC_SLAVE_ADDR 0x68
+#define IIC_MUX_ADDRESS 0x74
+#define IIC_CHANNEL_ADDRESS 0x10
+
+#define XIIC XIicPs
+#define INTC XScuGic
+/**************************** Type Definitions *******************************/
+typedef struct SI324Info
+{
+ u32 RegIndex; /* Register Number */
+ u32 Value; /* Value to be Written */
+} SI324Info;
+
+typedef struct {
+ XIIC I2cInstance;
+ INTC IntcInstance;
+ volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
+ volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
+ volatile u32 TotalErrorCount;
+} XIIC_LIB;
+/************************** Function Prototypes *****************************/
+int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
+int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
+int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
+int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
+int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
+/************************* Global Definitions *****************************/
+/*
+ * These configuration values generates 125MHz clock
+ * For more information please refer to Si5324 Datasheet.
+ */
+SI324Info InitTable[] = {
+ { 0, 0x54}, /* Register 0 */
+ { 1, 0xE4}, /* Register 1 */
+ { 2, 0x12}, /* Register 2 */
+ { 3, 0x15}, /* Register 3 */
+ { 4, 0x92}, /* Register 4 */
+ { 5, 0xed}, /* Register 5 */
+ { 6, 0x2d}, /* Register 6 */
+ { 7, 0x2a}, /* Register 7 */
+ { 8, 0x00}, /* Register 8 */
+ { 9, 0xc0}, /* Register 9 */
+ { 10, 0x08}, /* Register 10 */
+ { 11, 0x40}, /* Register 11 */
+ { 19, 0x29}, /* Register 19 */
+ { 20, 0x3e}, /* Register 20 */
+ { 21, 0xff}, /* Register 21 */
+ { 22, 0xdf}, /* Register 22 */
+ { 23, 0x1f}, /* Register 23 */
+ { 24, 0x3f}, /* Register 24 */
+ { 25, 0x60}, /* Register 25 */
+ { 31, 0x00}, /* Register 31 */
+ { 32, 0x00}, /* Register 32 */
+ { 33, 0x05}, /* Register 33 */
+ { 34, 0x00}, /* Register 34 */
+ { 35, 0x00}, /* Register 35 */
+ { 36, 0x05}, /* Register 36 */
+ { 40, 0xc2}, /* Register 40 */
+ { 41, 0x22}, /* Register 41 */
+ { 42, 0xdf}, /* Register 42 */
+ { 43, 0x00}, /* Register 43 */
+ { 44, 0x77}, /* Register 44 */
+ { 45, 0x0b}, /* Register 45 */
+ { 46, 0x00}, /* Register 46 */
+ { 47, 0x77}, /* Register 47 */
+ { 48, 0x0b}, /* Register 48 */
+ { 55, 0x00}, /* Register 55 */
+ {131, 0x1f}, /* Register 131 */
+ {132, 0x02}, /* Register 132 */
+ {137, 0x01}, /* Register 137 */
+ {138, 0x0f}, /* Register 138 */
+ {139, 0xff}, /* Register 139 */
+ {142, 0x00}, /* Register 142 */
+ {143, 0x00}, /* Register 143 */
+ {136, 0x40} /* Register 136 */
+};
+
+/************************** Function Definitions *****************************/
+int MuxInit(XIIC_LIB *I2cLibInstancePtr)
+{
+ u8 WrBuffer[0];
+ int Status;
+
+ WrBuffer[0] = IIC_CHANNEL_ADDRESS;
+
+ Status = I2cWriteData(I2cLibInstancePtr,
+ WrBuffer, 1, IIC_MUX_ADDRESS);
+ if (Status != XST_SUCCESS) {
+ xil_printf("Si5324: Writing failed\n\r");
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+int ProgramSi5324(void)
+{
+ XIIC_LIB I2cLibInstance;
+ int Index;
+ int Status;
+ u8 WrBuffer[2];
+
+ Status = I2cSetupHardware(&I2cLibInstance);
+ if (Status != XST_SUCCESS) {
+ xil_printf("Si5324: Configuring HW failed\n\r");
+ return XST_FAILURE;
+ }
+
+ Status = MuxInit(&I2cLibInstance);
+ if (Status != XST_SUCCESS) {
+ xil_printf("Si5324: Mux Init failed\n\r");
+ return XST_FAILURE;
+ }
+
+ for (Index = 0; Index < sizeof(InitTable)/8; Index++) {
+ WrBuffer[0] = InitTable[Index].RegIndex;
+ WrBuffer[1] = InitTable[Index].Value;
+
+ Status = I2cWriteData(&I2cLibInstance, WrBuffer, 2, IIC_SLAVE_ADDR);
+ if (Status != XST_SUCCESS) {
+ xil_printf("Si5324: Writing failed\n\r");
+ return XST_FAILURE;
+ }
+ }
+ return XST_SUCCESS;
+}
+#endif
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.cproject b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.cproject
new file mode 100644
index 0000000..ec4f052
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.cproject
@@ -0,0 +1,13 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.gitignore b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.gitignore
new file mode 100644
index 0000000..84c048a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.gitignore
@@ -0,0 +1 @@
+/build/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.project b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.project
new file mode 100644
index 0000000..3038e02
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.project
@@ -0,0 +1,75 @@
+
+
+ calboard_bsp
+ Created by SDK v2018.3
+
+
+
+
+ org.eclipse.cdt.make.core.makeBuilder
+
+
+ org.eclipse.cdt.core.errorOutputParser
+ org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;
+
+
+ org.eclipse.cdt.make.core.append_environment
+ true
+
+
+ org.eclipse.cdt.make.core.build.arguments
+
+
+
+ org.eclipse.cdt.make.core.build.command
+ make
+
+
+ org.eclipse.cdt.make.core.build.target.auto
+ all
+
+
+ org.eclipse.cdt.make.core.build.target.clean
+ clean
+
+
+ org.eclipse.cdt.make.core.build.target.inc
+ all
+
+
+ org.eclipse.cdt.make.core.enableAutoBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableCleanBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableFullBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enabledIncrementalBuild
+ true
+
+
+ org.eclipse.cdt.make.core.environment
+
+
+
+ org.eclipse.cdt.make.core.stopOnError
+ false
+
+
+ org.eclipse.cdt.make.core.useDefaultBuildCmd
+ true
+
+
+
+
+
+ com.xilinx.sdk.sw.SwProjectNature
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.make.core.makeNature
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.sdkproject b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.sdkproject
new file mode 100644
index 0000000..923eee0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/.sdkproject
@@ -0,0 +1,4 @@
+THIRPARTY=false
+HW_PROJECT_REFERENCE=system_wrapper_hw_platform_0
+PROCESSOR=ps7_cortexa9_0
+MSS_FILE=system.mss
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/Makefile
new file mode 100644
index 0000000..db5fc27
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/Makefile
@@ -0,0 +1,35 @@
+# Makefile generated by Xilinx.
+
+PROCESSOR = ps7_cortexa9_0
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
+
+all: libs
+ @echo 'Finished building libraries'
+
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+libs: $(addsuffix /make.libs,$(SUBDIRS))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+ cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+ @echo "Running Make include in $(subst /make.include,,$@)"
+ $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
+
+%/make.libs: include
+ @echo "Running Make libs in $(subst /make.libs,,$@)"
+ $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
+
+%/make.clean:
+ $(MAKE) -C $(subst /make.clean,,$@) -s clean
+clean:
+ rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
new file mode 100644
index 0000000..1647600
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
@@ -0,0 +1,308 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+* Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+# define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+# define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+ ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
+ (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
+ ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+ ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
+ (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
+ ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif /* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ * 1. XTime_PITDisableInterrupt() ;
+ * 2. Store the remaining timer clk tick
+ * 3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
+ timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
+ mtspr(XREG_SPR_PIT, 0); \
+ }
+#else
+#define disable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ * 1. Load the remaining timer clk ticks
+ * 2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer() \
+ { \
+ u32 val; \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
+ mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+ }
+#else
+#define enable_timer() \
+ { \
+ u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(addr); \
+ tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+ }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 1. Load the timer clk ticks
+ * 2. Enable AutoReload and Interrupt
+ * 3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack() \
+ { \
+ u32 val; \
+ mtspr(XREG_SPR_PIT, timer_clk_ticks); \
+ mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
+ val=mfspr(XREG_SPR_TCR); \
+ mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+ }
+#else
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
+ ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
+ }
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = ProfIo_In32(Addr); \
+ tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+ u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+ OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ OutAddr += (u32)XTC_TCSR_OFFSET; \
+ ProfIo_Out32(OutAddr, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+ { \
+ u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+ Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+ Addr += (u32)XTC_TCSR_OFFSET; \
+ u32 tmp_v = (u32)ProfIo_In32(Addr); \
+ tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
+ ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+ }
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+ { \
+ u32 csr; \
+ csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
+ ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
+ }
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer() \
+{ \
+ u32 Reg; \
+ Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+ Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+ Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack() \
+{ \
+ Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+ (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif /* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/cc.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/cc.h
new file mode 100644
index 0000000..bae8653
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/cc.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __ARCH_CC_H__
+#define __ARCH_CC_H__
+
+#include
+#include
+
+#include "lwipopts.h"
+
+/** if you want to use the struct timeval provided
+ * by your system, set this to 0 and include in cc.h */
+#define LWIP_TIMEVAL_PRIVATE 0
+#include
+#include "cpu.h"
+
+/* As per new design of lwip-2.0.2,
+ * LWIP_NO_STDINT_H should be defined as 1 in cc.h */
+#define LWIP_NO_STDINT_H 1
+
+typedef unsigned char u8_t;
+typedef signed char s8_t;
+typedef unsigned short u16_t;
+typedef signed short s16_t;
+typedef unsigned int u32_t;
+typedef signed int s32_t;
+typedef unsigned long long u64_t;
+typedef signed long long s64_t;
+
+#define S16_F "d"
+#define U16_F "d"
+#define S32_F "d"
+#define U32_F "x"
+
+#define X16_F "x"
+#define X32_F "x"
+
+#define LWIP_RAND rand
+
+typedef unsigned long mem_ptr_t;
+
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_END
+
+#define LWIP_PLATFORM_ASSERT(x)
+#define LWIP_PLATFORM_DIAG(x) do { xil_printf x; } while(0)
+
+#endif /* __ARCH_CC_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/cpu.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/cpu.h
new file mode 100644
index 0000000..ec05a8c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __ARCH_CPU_H__
+#define __ARCH_CPU_H__
+
+#include "lwipopts.h"
+
+#ifndef BYTE_ORDER
+#ifdef PROCESSOR_LITTLE_ENDIAN
+#define BYTE_ORDER LITTLE_ENDIAN
+#else
+#define BYTE_ORDER BIG_ENDIAN
+#endif
+#endif
+
+#endif /* __ARCH_CPU_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/perf.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/perf.h
new file mode 100644
index 0000000..dd12bf3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/perf.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __ARCH_PERF_H__
+#define __ARCH_PERF_H__
+
+#define PERF_START /* null definition */
+#define PERF_STOP(x) /* null definition */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void perf_init(char *fname);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARCH_PERF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/sys_arch.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/sys_arch.h
new file mode 100644
index 0000000..5e6f978
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/arch/sys_arch.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __SYS_XILINX_ARCH_H__
+#define __SYS_XILINX_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "lwipopts.h"
+
+
+#if !NO_SYS
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+#include "timers.h"
+
+#define SYS_MBOX_NULL ( ( xQueueHandle ) NULL )
+#define SYS_SEM_NULL ( ( xSemaphoreHandle ) NULL )
+#define SYS_DEFAULT_THREAD_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xSemaphoreHandle sys_mutex_t;
+typedef xQueueHandle sys_mbox_t;
+typedef xTaskHandle sys_thread_t;
+
+typedef unsigned long sys_prot_t;
+
+#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL )
+#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
+#endif /* !NO_SYS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYS_XILINX_ARCH_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/bspconfig.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/bspconfig.h
new file mode 100644
index 0000000..69c1dc8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/bspconfig.h
@@ -0,0 +1,44 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+/* Definition for hard-float ABI */
+#define FPU_HARD_FLOAT_ABI_ENABLED 1
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp.h
new file mode 100644
index 0000000..97abc54
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp.h
@@ -0,0 +1,201 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ *
+ * This file contains the generic API.
+ * For more details see @ref altcp_api.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_H
+#define LWIP_HDR_ALTCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcpbase.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct altcp_pcb;
+struct altcp_functions;
+
+typedef err_t (*altcp_accept_fn)(void *arg, struct altcp_pcb *new_conn, err_t err);
+typedef err_t (*altcp_connected_fn)(void *arg, struct altcp_pcb *conn, err_t err);
+typedef err_t (*altcp_recv_fn)(void *arg, struct altcp_pcb *conn, struct pbuf *p, err_t err);
+typedef err_t (*altcp_sent_fn)(void *arg, struct altcp_pcb *conn, u16_t len);
+typedef err_t (*altcp_poll_fn)(void *arg, struct altcp_pcb *conn);
+typedef void (*altcp_err_fn)(void *arg, err_t err);
+
+typedef struct altcp_pcb* (*altcp_new_fn)(void *arg, u8_t ip_type);
+
+struct altcp_pcb {
+ const struct altcp_functions *fns;
+ struct altcp_pcb *inner_conn;
+ void *arg;
+ void *state;
+ /* application callbacks */
+ altcp_accept_fn accept;
+ altcp_connected_fn connected;
+ altcp_recv_fn recv;
+ altcp_sent_fn sent;
+ altcp_poll_fn poll;
+ altcp_err_fn err;
+ u8_t pollinterval;
+};
+
+/** @ingroup altcp */
+typedef struct altcp_allocator_s {
+ /** Allocator function */
+ altcp_new_fn alloc;
+ /** Argument to allocator function */
+ void *arg;
+} altcp_allocator_t;
+
+struct altcp_pcb *altcp_new(altcp_allocator_t *allocator);
+struct altcp_pcb *altcp_new_ip6(altcp_allocator_t *allocator);
+struct altcp_pcb *altcp_new_ip_type(altcp_allocator_t *allocator, u8_t ip_type);
+
+void altcp_arg(struct altcp_pcb *conn, void *arg);
+void altcp_accept(struct altcp_pcb *conn, altcp_accept_fn accept);
+void altcp_recv(struct altcp_pcb *conn, altcp_recv_fn recv);
+void altcp_sent(struct altcp_pcb *conn, altcp_sent_fn sent);
+void altcp_poll(struct altcp_pcb *conn, altcp_poll_fn poll, u8_t interval);
+void altcp_err(struct altcp_pcb *conn, altcp_err_fn err);
+
+void altcp_recved(struct altcp_pcb *conn, u16_t len);
+err_t altcp_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port);
+err_t altcp_connect(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected);
+
+/* return conn for source code compatibility to tcp callback API only */
+struct altcp_pcb *altcp_listen_with_backlog_and_err(struct altcp_pcb *conn, u8_t backlog, err_t *err);
+#define altcp_listen_with_backlog(conn, backlog) altcp_listen_with_backlog_and_err(conn, backlog, NULL)
+/** @ingroup altcp */
+#define altcp_listen(conn) altcp_listen_with_backlog_and_err(conn, TCP_DEFAULT_LISTEN_BACKLOG, NULL)
+
+void altcp_abort(struct altcp_pcb *conn);
+err_t altcp_close(struct altcp_pcb *conn);
+err_t altcp_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx);
+
+err_t altcp_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags);
+err_t altcp_output(struct altcp_pcb *conn);
+
+u16_t altcp_mss(struct altcp_pcb *conn);
+u16_t altcp_sndbuf(struct altcp_pcb *conn);
+u16_t altcp_sndqueuelen(struct altcp_pcb *conn);
+void altcp_nagle_disable(struct altcp_pcb *conn);
+void altcp_nagle_enable(struct altcp_pcb *conn);
+int altcp_nagle_disabled(struct altcp_pcb *conn);
+
+void altcp_setprio(struct altcp_pcb *conn, u8_t prio);
+
+err_t altcp_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port);
+ip_addr_t *altcp_get_ip(struct altcp_pcb *conn, int local);
+u16_t altcp_get_port(struct altcp_pcb *conn, int local);
+
+#ifdef LWIP_DEBUG
+enum tcp_state altcp_dbg_get_tcp_state(struct altcp_pcb *conn);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#else /* LWIP_ALTCP */
+
+/* ALTCP disabled, define everything to link against tcp callback API (e.g. to get a small non-ssl httpd) */
+
+#include "lwip/tcp.h"
+
+#define altcp_accept_fn tcp_accept_fn
+#define altcp_connected_fn tcp_connected_fn
+#define altcp_recv_fn tcp_recv_fn
+#define altcp_sent_fn tcp_sent_fn
+#define altcp_poll_fn tcp_poll_fn
+#define altcp_err_fn tcp_err_fn
+
+#define altcp_pcb tcp_pcb
+#define altcp_tcp_new_ip_type tcp_new_ip_type
+#define altcp_tcp_new tcp_new
+#define altcp_tcp_new_ip6 tcp_new_ip6
+
+#define altcp_new(allocator) tcp_new()
+#define altcp_new_ip6(allocator) tcp_new_ip6()
+#define altcp_new_ip_type(allocator, ip_type) tcp_new_ip_type(ip_type)
+
+#define altcp_arg tcp_arg
+#define altcp_accept tcp_accept
+#define altcp_recv tcp_recv
+#define altcp_sent tcp_sent
+#define altcp_poll tcp_poll
+#define altcp_err tcp_err
+
+#define altcp_recved tcp_recved
+#define altcp_bind tcp_bind
+#define altcp_connect tcp_connect
+
+#define altcp_listen_with_backlog_and_err tcp_listen_with_backlog_and_err
+#define altcp_listen_with_backlog tcp_listen_with_backlog
+#define altcp_listen tcp_listen
+
+#define altcp_abort tcp_abort
+#define altcp_close tcp_close
+#define altcp_shutdown tcp_shutdown
+
+#define altcp_write tcp_write
+#define altcp_output tcp_output
+
+#define altcp_mss tcp_mss
+#define altcp_sndbuf tcp_sndbuf
+#define altcp_sndqueuelen tcp_sndqueuelen
+#define altcp_nagle_disable tcp_nagle_disable
+#define altcp_nagle_enable tcp_nagle_enable
+#define altcp_nagle_disabled tcp_nagle_disabled
+#define altcp_setprio tcp_setprio
+
+#define altcp_get_tcp_addrinfo tcp_get_tcp_addrinfo
+#define altcp_get_ip(pcb, local) ((local) ? (&(pcb)->local_ip) : (&(pcb)->remote_ip))
+
+#ifdef LWIP_DEBUG
+#define altcp_dbg_get_tcp_state tcp_dbg_get_tcp_state
+#endif
+
+#endif /* LWIP_ALTCP */
+
+#endif /* LWIP_HDR_ALTCP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp_tcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp_tcp.h
new file mode 100644
index 0000000..dbde584
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp_tcp.h
@@ -0,0 +1,72 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ * This interface mimics the tcp callback API to the application while preventing
+ * direct linking (much like virtual functions).
+ * This way, an application can make use of other application layer protocols
+ * on top of TCP without knowing the details (e.g. TLS, proxy connection).
+ *
+ * This file contains the base implementation calling into tcp.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_TCP_H
+#define LWIP_HDR_ALTCP_TCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/altcp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct altcp_pcb *altcp_tcp_new_ip_type(u8_t ip_type);
+
+#define altcp_tcp_new() altcp_tcp_new_ip_type(IPADDR_TYPE_V4)
+#define altcp_tcp_new_ip6() altcp_tcp_new_ip_type(IPADDR_TYPE_V6)
+
+struct altcp_pcb *altcp_tcp_alloc(void *arg, u8_t ip_type);
+
+struct tcp_pcb;
+struct altcp_pcb *altcp_tcp_wrap(struct tcp_pcb *tpcb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ALTCP */
+
+#endif /* LWIP_HDR_ALTCP_TCP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp_tls.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp_tls.h
new file mode 100644
index 0000000..7b17c60
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/altcp_tls.h
@@ -0,0 +1,117 @@
+/**
+ * @file
+ * Application layered TCP/TLS connection API (to be used from TCPIP thread)
+ *
+ * @defgroup altcp_tls TLS layer
+ * @ingroup altcp
+ * This file contains function prototypes for a TLS layer.
+ * A port to ARM mbedtls is provided in the apps/ tree
+ * (LWIP_ALTCP_TLS_MBEDTLS option).
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_TLS_H
+#define LWIP_HDR_ALTCP_TLS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#if LWIP_ALTCP_TLS
+
+#include "lwip/altcp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup altcp_tls
+ * ALTCP_TLS configuration handle, content depends on port (e.g. mbedtls)
+ */
+struct altcp_tls_config;
+
+/** @ingroup altcp_tls
+ * Create an ALTCP_TLS server configuration handle
+ */
+struct altcp_tls_config *altcp_tls_create_config_server_privkey_cert(const u8_t *privkey, size_t privkey_len,
+ const u8_t *privkey_pass, size_t privkey_pass_len,
+ const u8_t *cert, size_t cert_len);
+
+/** @ingroup altcp_tls
+ * Create an ALTCP_TLS client configuration handle
+ */
+struct altcp_tls_config *altcp_tls_create_config_client(const u8_t *cert, size_t cert_len);
+
+/** @ingroup altcp_tls
+ * Create an ALTCP_TLS client configuration handle with two-way server/client authentication
+ */
+struct altcp_tls_config *altcp_tls_create_config_client_2wayauth(const u8_t *ca, size_t ca_len, const u8_t *privkey, size_t privkey_len,
+ const u8_t *privkey_pass, size_t privkey_pass_len,
+ const u8_t *cert, size_t cert_len);
+
+/** @ingroup altcp_tls
+ * Free an ALTCP_TLS configuration handle
+ */
+void altcp_tls_free_config(struct altcp_tls_config *conf);
+
+/** @ingroup altcp_tls
+ * Create new ALTCP_TLS layer wrapping an existing pcb as inner connection (e.g. TLS over TCP)
+ */
+struct altcp_pcb *altcp_tls_wrap(struct altcp_tls_config *config, struct altcp_pcb *inner_pcb);
+
+/** @ingroup altcp_tls
+ * Create new ALTCP_TLS pcb and its inner tcp pcb
+ */
+struct altcp_pcb *altcp_tls_new(struct altcp_tls_config *config, u8_t ip_type);
+
+/** @ingroup altcp_tls
+ * Create new ALTCP_TLS layer pcb and its inner tcp pcb.
+ * Same as @ref altcp_tls_new but this allocator function fits to
+ * @ref altcp_allocator_t / @ref altcp_new.\n
+ 'arg' must contain a struct altcp_tls_config *.
+ */
+struct altcp_pcb *altcp_tls_alloc(void *arg, u8_t ip_type);
+
+/** @ingroup altcp_tls
+ * Return pointer to internal TLS context so application can tweak it.
+ * Real type depends on port (e.g. mbedtls)
+ */
+void *altcp_tls_context(struct altcp_pcb *conn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ALTCP_TLS */
+#endif /* LWIP_ALTCP */
+#endif /* LWIP_HDR_ALTCP_TLS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/api.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/api.h
new file mode 100644
index 0000000..739f8be
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/api.h
@@ -0,0 +1,431 @@
+/**
+ * @file
+ * netconn API (to be used from non-TCPIP threads)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_API_H
+#define LWIP_HDR_API_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#include "lwip/arch.h"
+#include "lwip/netbuf.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+
+/* Flags for netconn_write (u8_t) */
+#define NETCONN_NOFLAG 0x00
+#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */
+#define NETCONN_COPY 0x01
+#define NETCONN_MORE 0x02
+#define NETCONN_DONTBLOCK 0x04
+#define NETCONN_NOAUTORCVD 0x08 /* prevent netconn_recv_data_tcp() from updating the tcp window - must be done manually via netconn_tcp_recvd() */
+#define NETCONN_NOFIN 0x10 /* upper layer already received data, leave FIN in queue until called again */
+
+/* Flags for struct netconn.flags (u8_t) */
+/** This netconn had an error, don't block on recvmbox/acceptmbox any more */
+#define NETCONN_FLAG_MBOXCLOSED 0x01
+/** Should this netconn avoid blocking? */
+#define NETCONN_FLAG_NON_BLOCKING 0x02
+/** Was the last connect action a non-blocking one? */
+#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT 0x04
+#if LWIP_NETCONN_FULLDUPLEX
+ /** The mbox of this netconn is being deallocated, don't use it anymore */
+#define NETCONN_FLAG_MBOXINVALID 0x08
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+/** If a nonblocking write has been rejected before, poll_tcp needs to
+ check if the netconn is writable again */
+#define NETCONN_FLAG_CHECK_WRITESPACE 0x10
+#if LWIP_IPV6
+/** If this flag is set then only IPv6 communication is allowed on the
+ netconn. As per RFC#3493 this features defaults to OFF allowing
+ dual-stack usage by default. */
+#define NETCONN_FLAG_IPV6_V6ONLY 0x20
+#endif /* LWIP_IPV6 */
+#if LWIP_NETBUF_RECVINFO
+/** Received packet info will be recorded for this netconn */
+#define NETCONN_FLAG_PKTINFO 0x40
+#endif /* LWIP_NETBUF_RECVINFO */
+/** A FIN has been received but not passed to the application yet */
+#define NETCONN_FIN_RX_PENDING 0x80
+
+/* Helpers to process several netconn_types by the same code */
+#define NETCONNTYPE_GROUP(t) ((t)&0xF0)
+#define NETCONNTYPE_DATAGRAM(t) ((t)&0xE0)
+#if LWIP_IPV6
+#define NETCONN_TYPE_IPV6 0x08
+#define NETCONNTYPE_ISIPV6(t) (((t)&NETCONN_TYPE_IPV6) != 0)
+#define NETCONNTYPE_ISUDPLITE(t) (((t)&0xF3) == NETCONN_UDPLITE)
+#define NETCONNTYPE_ISUDPNOCHKSUM(t) (((t)&0xF3) == NETCONN_UDPNOCHKSUM)
+#else /* LWIP_IPV6 */
+#define NETCONNTYPE_ISIPV6(t) (0)
+#define NETCONNTYPE_ISUDPLITE(t) ((t) == NETCONN_UDPLITE)
+#define NETCONNTYPE_ISUDPNOCHKSUM(t) ((t) == NETCONN_UDPNOCHKSUM)
+#endif /* LWIP_IPV6 */
+
+/** @ingroup netconn_common
+ * Protocol family and type of the netconn
+ */
+enum netconn_type {
+ NETCONN_INVALID = 0,
+ /** TCP IPv4 */
+ NETCONN_TCP = 0x10,
+#if LWIP_IPV6
+ /** TCP IPv6 */
+ NETCONN_TCP_IPV6 = NETCONN_TCP | NETCONN_TYPE_IPV6 /* 0x18 */,
+#endif /* LWIP_IPV6 */
+ /** UDP IPv4 */
+ NETCONN_UDP = 0x20,
+ /** UDP IPv4 lite */
+ NETCONN_UDPLITE = 0x21,
+ /** UDP IPv4 no checksum */
+ NETCONN_UDPNOCHKSUM = 0x22,
+
+#if LWIP_IPV6
+ /** UDP IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+ NETCONN_UDP_IPV6 = NETCONN_UDP | NETCONN_TYPE_IPV6 /* 0x28 */,
+ /** UDP IPv6 lite (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+ NETCONN_UDPLITE_IPV6 = NETCONN_UDPLITE | NETCONN_TYPE_IPV6 /* 0x29 */,
+ /** UDP IPv6 no checksum (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+ NETCONN_UDPNOCHKSUM_IPV6 = NETCONN_UDPNOCHKSUM | NETCONN_TYPE_IPV6 /* 0x2a */,
+#endif /* LWIP_IPV6 */
+
+ /** Raw connection IPv4 */
+ NETCONN_RAW = 0x40
+#if LWIP_IPV6
+ /** Raw connection IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+ , NETCONN_RAW_IPV6 = NETCONN_RAW | NETCONN_TYPE_IPV6 /* 0x48 */
+#endif /* LWIP_IPV6 */
+};
+
+/** Current state of the netconn. Non-TCP netconns are always
+ * in state NETCONN_NONE! */
+enum netconn_state {
+ NETCONN_NONE,
+ NETCONN_WRITE,
+ NETCONN_LISTEN,
+ NETCONN_CONNECT,
+ NETCONN_CLOSE
+};
+
+/** Used to inform the callback function about changes
+ *
+ * Event explanation:
+ *
+ * In the netconn implementation, there are three ways to block a client:
+ *
+ * - accept mbox (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0); in netconn_accept())
+ * - receive mbox (sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); in netconn_recv_data())
+ * - send queue is full (sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); in lwip_netconn_do_write())
+ *
+ * The events have to be seen as events signaling the state of these mboxes/semaphores. For non-blocking
+ * connections, you need to know in advance whether a call to a netconn function call would block or not,
+ * and these events tell you about that.
+ *
+ * RCVPLUS events say: Safe to perform a potentially blocking call call once more.
+ * They are counted in sockets - three RCVPLUS events for accept mbox means you are safe
+ * to call netconn_accept 3 times without being blocked.
+ * Same thing for receive mbox.
+ *
+ * RCVMINUS events say: Your call to to a possibly blocking function is "acknowledged".
+ * Socket implementation decrements the counter.
+ *
+ * For TX, there is no need to count, its merely a flag. SENDPLUS means you may send something.
+ * SENDPLUS occurs when enough data was delivered to peer so netconn_send() can be called again.
+ * A SENDMINUS event occurs when the next call to a netconn_send() would be blocking.
+ */
+enum netconn_evt {
+ NETCONN_EVT_RCVPLUS,
+ NETCONN_EVT_RCVMINUS,
+ NETCONN_EVT_SENDPLUS,
+ NETCONN_EVT_SENDMINUS,
+ NETCONN_EVT_ERROR
+};
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+/** Used for netconn_join_leave_group() */
+enum netconn_igmp {
+ NETCONN_JOIN,
+ NETCONN_LEAVE
+};
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+/* Used for netconn_gethostbyname_addrtype(), these should match the DNS_ADDRTYPE defines in dns.h */
+#define NETCONN_DNS_DEFAULT NETCONN_DNS_IPV4_IPV6
+#define NETCONN_DNS_IPV4 0
+#define NETCONN_DNS_IPV6 1
+#define NETCONN_DNS_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
+#define NETCONN_DNS_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
+#endif /* LWIP_DNS */
+
+/* forward-declare some structs to avoid to include their headers */
+struct ip_pcb;
+struct tcp_pcb;
+struct udp_pcb;
+struct raw_pcb;
+struct netconn;
+struct api_msg;
+
+/** A callback prototype to inform about events for a netconn */
+typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len);
+
+/** A netconn descriptor */
+struct netconn {
+ /** type of the netconn (TCP, UDP or RAW) */
+ enum netconn_type type;
+ /** current state of the netconn */
+ enum netconn_state state;
+ /** the lwIP internal protocol control block */
+ union {
+ struct ip_pcb *ip;
+ struct tcp_pcb *tcp;
+ struct udp_pcb *udp;
+ struct raw_pcb *raw;
+ } pcb;
+ /** the last asynchronous unreported error this netconn had */
+ err_t pending_err;
+#if !LWIP_NETCONN_SEM_PER_THREAD
+ /** sem that is used to synchronously execute functions in the core context */
+ sys_sem_t op_completed;
+#endif
+ /** mbox where received packets are stored until they are fetched
+ by the netconn application thread (can grow quite big) */
+ sys_mbox_t recvmbox;
+#if LWIP_TCP
+ /** mbox where new connections are stored until processed
+ by the application thread */
+ sys_mbox_t acceptmbox;
+#endif /* LWIP_TCP */
+#if LWIP_NETCONN_FULLDUPLEX
+ /** number of threads waiting on an mbox. This is required to unblock
+ all threads when closing while threads are waiting. */
+ int mbox_threads_waiting;
+#endif
+ /** only used for socket layer */
+#if LWIP_SOCKET
+ int socket;
+#endif /* LWIP_SOCKET */
+#if LWIP_SO_SNDTIMEO
+ /** timeout to wait for sending data (which means enqueueing data for sending
+ in internal buffers) in milliseconds */
+ s32_t send_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVTIMEO
+ /** timeout in milliseconds to wait for new data to be received
+ (or connections to arrive for listening netconns) */
+ u32_t recv_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+ /** maximum amount of bytes queued in recvmbox
+ not used for TCP: adjust TCP_WND instead! */
+ int recv_bufsize;
+ /** number of bytes currently in recvmbox to be received,
+ tested against recv_bufsize to limit bytes on recvmbox
+ for UDP and RAW, used for FIONREAD */
+ int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_SO_LINGER
+ /** values <0 mean linger is disabled, values > 0 are seconds to linger */
+ s16_t linger;
+#endif /* LWIP_SO_LINGER */
+ /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */
+ u8_t flags;
+#if LWIP_TCP
+ /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+ this temporarily stores the message.
+ Also used during connect and close. */
+ struct api_msg *current_msg;
+#endif /* LWIP_TCP */
+ /** A callback function that is informed about events for this netconn */
+ netconn_callback callback;
+};
+
+/** This vector type is passed to @ref netconn_write_vectors_partly to send
+ * multiple buffers at once.
+ * ATTENTION: This type has to directly map struct iovec since one is casted
+ * into the other!
+ */
+struct netvector {
+ /** pointer to the application buffer that contains the data to send */
+ const void *ptr;
+ /** size of the application data to send */
+ size_t len;
+};
+
+/** Register an Network connection event */
+#define API_EVENT(c,e,l) if (c->callback) { \
+ (*c->callback)(c, e, l); \
+ }
+
+/* Network connection functions: */
+
+/** @ingroup netconn_common
+ * Create new netconn connection
+ * @param t @ref netconn_type */
+#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL)
+#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c)
+struct netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto,
+ netconn_callback callback);
+err_t netconn_prepare_delete(struct netconn *conn);
+err_t netconn_delete(struct netconn *conn);
+/** Get the type of a netconn (as enum netconn_type). */
+#define netconn_type(conn) (conn->type)
+
+err_t netconn_getaddr(struct netconn *conn, ip_addr_t *addr,
+ u16_t *port, u8_t local);
+/** @ingroup netconn_common */
+#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0)
+/** @ingroup netconn_common */
+#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1)
+
+err_t netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port);
+err_t netconn_bind_if(struct netconn *conn, u8_t if_idx);
+err_t netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port);
+err_t netconn_disconnect (struct netconn *conn);
+err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog);
+/** @ingroup netconn_tcp */
+#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG)
+err_t netconn_accept(struct netconn *conn, struct netconn **new_conn);
+err_t netconn_recv(struct netconn *conn, struct netbuf **new_buf);
+err_t netconn_recv_udp_raw_netbuf(struct netconn *conn, struct netbuf **new_buf);
+err_t netconn_recv_udp_raw_netbuf_flags(struct netconn *conn, struct netbuf **new_buf, u8_t apiflags);
+err_t netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf);
+err_t netconn_recv_tcp_pbuf_flags(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags);
+err_t netconn_tcp_recvd(struct netconn *conn, size_t len);
+err_t netconn_sendto(struct netconn *conn, struct netbuf *buf,
+ const ip_addr_t *addr, u16_t port);
+err_t netconn_send(struct netconn *conn, struct netbuf *buf);
+err_t netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size,
+ u8_t apiflags, size_t *bytes_written);
+err_t netconn_write_vectors_partly(struct netconn *conn, struct netvector *vectors, u16_t vectorcnt,
+ u8_t apiflags, size_t *bytes_written);
+/** @ingroup netconn_tcp */
+#define netconn_write(conn, dataptr, size, apiflags) \
+ netconn_write_partly(conn, dataptr, size, apiflags, NULL)
+err_t netconn_close(struct netconn *conn);
+err_t netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx);
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+err_t netconn_join_leave_group(struct netconn *conn, const ip_addr_t *multiaddr,
+ const ip_addr_t *netif_addr, enum netconn_igmp join_or_leave);
+err_t netconn_join_leave_group_netif(struct netconn *conn, const ip_addr_t *multiaddr,
+ u8_t if_idx, enum netconn_igmp join_or_leave);
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+#if LWIP_DNS
+#if LWIP_IPV4 && LWIP_IPV6
+err_t netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype);
+#define netconn_gethostbyname(name, addr) netconn_gethostbyname_addrtype(name, addr, NETCONN_DNS_DEFAULT)
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+err_t netconn_gethostbyname(const char *name, ip_addr_t *addr);
+#define netconn_gethostbyname_addrtype(name, addr, dns_addrtype) netconn_gethostbyname(name, addr)
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#endif /* LWIP_DNS */
+
+err_t netconn_err(struct netconn *conn);
+#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize)
+
+#define netconn_set_flags(conn, set_flags) do { (conn)->flags = (u8_t)((conn)->flags | (set_flags)); } while(0)
+#define netconn_clear_flags(conn, clr_flags) do { (conn)->flags = (u8_t)((conn)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define netconn_is_flag_set(conn, flag) (((conn)->flags & (flag)) != 0)
+
+/** Set the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_set_nonblocking(conn, val) do { if(val) { \
+ netconn_set_flags(conn, NETCONN_FLAG_NON_BLOCKING); \
+} else { \
+ netconn_clear_flags(conn, NETCONN_FLAG_NON_BLOCKING); }} while(0)
+/** Get the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_is_nonblocking(conn) (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0)
+
+#if LWIP_IPV6
+/** @ingroup netconn_common
+ * TCP: Set the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY)
+ */
+#define netconn_set_ipv6only(conn, val) do { if(val) { \
+ netconn_set_flags(conn, NETCONN_FLAG_IPV6_V6ONLY); \
+} else { \
+ netconn_clear_flags(conn, NETCONN_FLAG_IPV6_V6ONLY); }} while(0)
+/** @ingroup netconn_common
+ * TCP: Get the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY)
+ */
+#define netconn_get_ipv6only(conn) (((conn)->flags & NETCONN_FLAG_IPV6_V6ONLY) != 0)
+#endif /* LWIP_IPV6 */
+
+#if LWIP_SO_SNDTIMEO
+/** Set the send timeout in milliseconds */
+#define netconn_set_sendtimeout(conn, timeout) ((conn)->send_timeout = (timeout))
+/** Get the send timeout in milliseconds */
+#define netconn_get_sendtimeout(conn) ((conn)->send_timeout)
+#endif /* LWIP_SO_SNDTIMEO */
+#if LWIP_SO_RCVTIMEO
+/** Set the receive timeout in milliseconds */
+#define netconn_set_recvtimeout(conn, timeout) ((conn)->recv_timeout = (timeout))
+/** Get the receive timeout in milliseconds */
+#define netconn_get_recvtimeout(conn) ((conn)->recv_timeout)
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+/** Set the receive buffer in bytes */
+#define netconn_set_recvbufsize(conn, recvbufsize) ((conn)->recv_bufsize = (recvbufsize))
+/** Get the receive buffer in bytes */
+#define netconn_get_recvbufsize(conn) ((conn)->recv_bufsize)
+#endif /* LWIP_SO_RCVBUF*/
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+void netconn_thread_init(void);
+void netconn_thread_cleanup(void);
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define netconn_thread_init()
+#define netconn_thread_cleanup()
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#endif /* LWIP_HDR_API_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/FILES b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/FILES
new file mode 100644
index 0000000..adfc0f3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/FILES
@@ -0,0 +1,2 @@
+This directory contains application headers.
+Every application shall provide one api file APP.h and optionally one options file APP_opts.h
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/altcp_proxyconnect.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/altcp_proxyconnect.h
new file mode 100644
index 0000000..65d3127
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/altcp_proxyconnect.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ * Application layered TCP connection API that executes a proxy-connect.
+ *
+ * This file provides a starting layer that executes a proxy-connect e.g. to
+ * set up TLS connections through a http proxy.
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_ALTCP_PROXYCONNECT_H
+#define LWIP_HDR_APPS_ALTCP_PROXYCONNECT_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct altcp_proxyconnect_config {
+ ip_addr_t proxy_addr;
+ u16_t proxy_port;
+};
+
+
+struct altcp_pcb *altcp_proxyconnect_new(struct altcp_proxyconnect_config *config, struct altcp_pcb *inner_pcb);
+struct altcp_pcb *altcp_proxyconnect_new_tcp(struct altcp_proxyconnect_config *config, u8_t ip_type);
+
+struct altcp_pcb *altcp_proxyconnect_alloc(void *arg, u8_t ip_type);
+
+#if LWIP_ALTCP_TLS
+struct altcp_proxyconnect_tls_config {
+ struct altcp_proxyconnect_config proxy;
+ struct altcp_tls_config *tls_config;
+};
+
+struct altcp_pcb *altcp_proxyconnect_tls_alloc(void *arg, u8_t ip_type);
+#endif /* LWIP_ALTCP_TLS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ALTCP */
+#endif /* LWIP_HDR_APPS_ALTCP_PROXYCONNECT_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/altcp_tls_mbedtls_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/altcp_tls_mbedtls_opts.h
new file mode 100644
index 0000000..36cddd9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/altcp_tls_mbedtls_opts.h
@@ -0,0 +1,67 @@
+/**
+ * @file
+ * Application layered TCP/TLS connection API (to be used from TCPIP thread)
+ *
+ * This file contains options for an mbedtls port of the TLS layer.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_TLS_OPTS_H
+#define LWIP_HDR_ALTCP_TLS_OPTS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+/** LWIP_ALTCP_TLS_MBEDTLS==1: use mbedTLS for TLS support for altcp API
+ * mbedtls include directory must be reachable via include search path
+ */
+#ifndef LWIP_ALTCP_TLS_MBEDTLS
+#define LWIP_ALTCP_TLS_MBEDTLS 0
+#endif
+
+/** Configure debug level of this file */
+#ifndef ALTCP_MBEDTLS_DEBUG
+#define ALTCP_MBEDTLS_DEBUG LWIP_DBG_OFF
+#endif
+
+/** Set a session timeout in seconds for the basic session cache
+ * ATTENTION: Using a session cache can lower security by reusing keys!
+ */
+#ifndef ALTCP_MBEDTLS_SESSION_CACHE_TIMEOUT_SECONDS
+#define ALTCP_MBEDTLS_SESSION_CACHE_TIMEOUT_SECONDS 0
+#endif
+
+#endif /* LWIP_ALTCP */
+
+#endif /* LWIP_HDR_ALTCP_TLS_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/fs.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/fs.h
new file mode 100644
index 0000000..5be77c1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/fs.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_APPS_FS_H
+#define LWIP_HDR_APPS_FS_H
+
+#include "httpd_opts.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define FS_READ_EOF -1
+#define FS_READ_DELAYED -2
+
+#if HTTPD_PRECALCULATED_CHECKSUM
+struct fsdata_chksum {
+ u32_t offset;
+ u16_t chksum;
+ u16_t len;
+};
+#endif /* HTTPD_PRECALCULATED_CHECKSUM */
+
+#define FS_FILE_FLAGS_HEADER_INCLUDED 0x01
+#define FS_FILE_FLAGS_HEADER_PERSISTENT 0x02
+#define FS_FILE_FLAGS_HEADER_HTTPVER_1_1 0x04
+#define FS_FILE_FLAGS_SSI 0x08
+
+/** Define FS_FILE_EXTENSION_T_DEFINED if you have typedef'ed to your private
+ * pointer type (defaults to 'void' so the default usage is 'void*')
+ */
+#ifndef FS_FILE_EXTENSION_T_DEFINED
+typedef void fs_file_extension;
+#endif
+
+struct fs_file {
+ const char *data;
+ int len;
+ int index;
+ /* pextension is free for implementations to hold private (extensional)
+ arbitrary data, e.g. holding some file state or file system handle */
+ fs_file_extension *pextension;
+#if HTTPD_PRECALCULATED_CHECKSUM
+ const struct fsdata_chksum *chksum;
+ u16_t chksum_count;
+#endif /* HTTPD_PRECALCULATED_CHECKSUM */
+ u8_t flags;
+#if LWIP_HTTPD_CUSTOM_FILES
+ u8_t is_custom_file;
+#endif /* LWIP_HTTPD_CUSTOM_FILES */
+#if LWIP_HTTPD_FILE_STATE
+ void *state;
+#endif /* LWIP_HTTPD_FILE_STATE */
+};
+
+#if LWIP_HTTPD_FS_ASYNC_READ
+typedef void (*fs_wait_cb)(void *arg);
+#endif /* LWIP_HTTPD_FS_ASYNC_READ */
+
+err_t fs_open(struct fs_file *file, const char *name);
+void fs_close(struct fs_file *file);
+#if LWIP_HTTPD_DYNAMIC_FILE_READ
+#if LWIP_HTTPD_FS_ASYNC_READ
+int fs_read_async(struct fs_file *file, char *buffer, int count, fs_wait_cb callback_fn, void *callback_arg);
+#else /* LWIP_HTTPD_FS_ASYNC_READ */
+int fs_read(struct fs_file *file, char *buffer, int count);
+#endif /* LWIP_HTTPD_FS_ASYNC_READ */
+#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */
+#if LWIP_HTTPD_FS_ASYNC_READ
+int fs_is_file_ready(struct fs_file *file, fs_wait_cb callback_fn, void *callback_arg);
+#endif /* LWIP_HTTPD_FS_ASYNC_READ */
+int fs_bytes_left(struct fs_file *file);
+
+#if LWIP_HTTPD_FILE_STATE
+/** This user-defined function is called when a file is opened. */
+void *fs_state_init(struct fs_file *file, const char *name);
+/** This user-defined function is called when a file is closed. */
+void fs_state_free(struct fs_file *file, void *state);
+#endif /* #if LWIP_HTTPD_FILE_STATE */
+
+struct fsdata_file {
+ const struct fsdata_file *next;
+ const unsigned char *name;
+ const unsigned char *data;
+ int len;
+ u8_t flags;
+#if HTTPD_PRECALCULATED_CHECKSUM
+ u16_t chksum_count;
+ const struct fsdata_chksum *chksum;
+#endif /* HTTPD_PRECALCULATED_CHECKSUM */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_FS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/http_client.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/http_client.h
new file mode 100644
index 0000000..d39e1bf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/http_client.h
@@ -0,0 +1,160 @@
+/**
+ * @file
+ * HTTP client
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_HTTP_CLIENT_H
+#define LWIP_HDR_APPS_HTTP_CLIENT_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/altcp.h"
+#include "lwip/prot/iana.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_TCP && LWIP_CALLBACK_API
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup httpc
+ * HTTPC_HAVE_FILE_IO: define this to 1 to have functions dowloading directly
+ * to disk via fopen/fwrite.
+ * These functions are example implementations of the interface only.
+ */
+#ifndef LWIP_HTTPC_HAVE_FILE_IO
+#define LWIP_HTTPC_HAVE_FILE_IO 0
+#endif
+
+/**
+ * @ingroup httpc
+ * The default TCP port used for HTTP
+ */
+#define HTTP_DEFAULT_PORT LWIP_IANA_PORT_HTTP
+
+/**
+ * @ingroup httpc
+ * HTTP client result codes
+ */
+typedef enum ehttpc_result {
+ /** File successfully received */
+ HTTPC_RESULT_OK = 0,
+ /** Unknown error */
+ HTTPC_RESULT_ERR_UNKNOWN = 1,
+ /** Connection to server failed */
+ HTTPC_RESULT_ERR_CONNECT = 2,
+ /** Failed to resolve server hostname */
+ HTTPC_RESULT_ERR_HOSTNAME = 3,
+ /** Connection unexpectedly closed by remote server */
+ HTTPC_RESULT_ERR_CLOSED = 4,
+ /** Connection timed out (server didn't respond in time) */
+ HTTPC_RESULT_ERR_TIMEOUT = 5,
+ /** Server responded with an error code */
+ HTTPC_RESULT_ERR_SVR_RESP = 6,
+ /** Local memory error */
+ HTTPC_RESULT_ERR_MEM = 7,
+ /** Local abort */
+ HTTPC_RESULT_LOCAL_ABORT = 8,
+ /** Content length mismatch */
+ HTTPC_RESULT_ERR_CONTENT_LEN = 9
+} httpc_result_t;
+
+typedef struct _httpc_state httpc_state_t;
+
+/**
+ * @ingroup httpc
+ * Prototype of a http client callback function
+ *
+ * @param arg argument specified when initiating the request
+ * @param httpc_result result of the http transfer (see enum httpc_result_t)
+ * @param rx_content_len number of bytes received (without headers)
+ * @param srv_res this contains the http status code received (if any)
+ * @param err an error returned by internal lwip functions, can help to specify
+ * the source of the error but must not necessarily be != ERR_OK
+ */
+typedef void (*httpc_result_fn)(void *arg, httpc_result_t httpc_result, u32_t rx_content_len, u32_t srv_res, err_t err);
+
+/**
+ * @ingroup httpc
+ * Prototype of http client callback: called when the headers are received
+ *
+ * @param connection http client connection
+ * @param arg argument specified when initiating the request
+ * @param hdr header pbuf(s) (may contain data also)
+ * @param hdr_len length of the heders in 'hdr'
+ * @param content_len content length as received in the headers (-1 if not received)
+ * @return if != ERR_OK is returned, the connection is aborted
+ */
+typedef err_t (*httpc_headers_done_fn)(httpc_state_t *connection, void *arg, struct pbuf *hdr, u16_t hdr_len, u32_t content_len);
+
+typedef struct _httpc_connection {
+ ip_addr_t proxy_addr;
+ u16_t proxy_port;
+ u8_t use_proxy;
+ /* @todo: add username:pass? */
+
+#if LWIP_ALTCP
+ altcp_allocator_t *altcp_allocator;
+#endif
+
+ /* this callback is called when the transfer is finished (or aborted) */
+ httpc_result_fn result_fn;
+ /* this callback is called after receiving the http headers
+ It can abort the connection by returning != ERR_OK */
+ httpc_headers_done_fn headers_done_fn;
+} httpc_connection_t;
+
+err_t httpc_get_file(const ip_addr_t* server_addr, u16_t port, const char* uri, const httpc_connection_t *settings,
+ altcp_recv_fn recv_fn, void* callback_arg, httpc_state_t **connection);
+err_t httpc_get_file_dns(const char* server_name, u16_t port, const char* uri, const httpc_connection_t *settings,
+ altcp_recv_fn recv_fn, void* callback_arg, httpc_state_t **connection);
+
+#if LWIP_HTTPC_HAVE_FILE_IO
+err_t httpc_get_file_to_disk(const ip_addr_t* server_addr, u16_t port, const char* uri, const httpc_connection_t *settings,
+ void* callback_arg, const char* local_file_name, httpc_state_t **connection);
+err_t httpc_get_file_dns_to_disk(const char* server_name, u16_t port, const char* uri, const httpc_connection_t *settings,
+ void* callback_arg, const char* local_file_name, httpc_state_t **connection);
+#endif /* LWIP_HTTPC_HAVE_FILE_IO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP && LWIP_CALLBACK_API */
+
+#endif /* LWIP_HDR_APPS_HTTP_CLIENT_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/httpd.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/httpd.h
new file mode 100644
index 0000000..e872429
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/httpd.h
@@ -0,0 +1,255 @@
+/**
+ * @file
+ * HTTP server
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ * This version of the file has been modified by Texas Instruments to offer
+ * simple server-side-include (SSI) and Common Gateway Interface (CGI)
+ * capability.
+ */
+
+#ifndef LWIP_HDR_APPS_HTTPD_H
+#define LWIP_HDR_APPS_HTTPD_H
+
+#include "httpd_opts.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_HTTPD_CGI
+
+/**
+ * @ingroup httpd
+ * Function pointer for a CGI script handler.
+ *
+ * This function is called each time the HTTPD server is asked for a file
+ * whose name was previously registered as a CGI function using a call to
+ * http_set_cgi_handlers. The iIndex parameter provides the index of the
+ * CGI within the cgis array passed to http_set_cgi_handlers. Parameters
+ * pcParam and pcValue provide access to the parameters provided along with
+ * the URI. iNumParams provides a count of the entries in the pcParam and
+ * pcValue arrays. Each entry in the pcParam array contains the name of a
+ * parameter with the corresponding entry in the pcValue array containing the
+ * value for that parameter. Note that pcParam may contain multiple elements
+ * with the same name if, for example, a multi-selection list control is used
+ * in the form generating the data.
+ *
+ * The function should return a pointer to a character string which is the
+ * path and filename of the response that is to be sent to the connected
+ * browser, for example "/thanks.htm" or "/response/error.ssi".
+ *
+ * The maximum number of parameters that will be passed to this function via
+ * iNumParams is defined by LWIP_HTTPD_MAX_CGI_PARAMETERS. Any parameters in
+ * the incoming HTTP request above this number will be discarded.
+ *
+ * Requests intended for use by this CGI mechanism must be sent using the GET
+ * method (which encodes all parameters within the URI rather than in a block
+ * later in the request). Attempts to use the POST method will result in the
+ * request being ignored.
+ *
+ */
+typedef const char *(*tCGIHandler)(int iIndex, int iNumParams, char *pcParam[],
+ char *pcValue[]);
+
+/**
+ * @ingroup httpd
+ * Structure defining the base filename (URL) of a CGI and the associated
+ * function which is to be called when that URL is requested.
+ */
+typedef struct
+{
+ const char *pcCGIName;
+ tCGIHandler pfnCGIHandler;
+} tCGI;
+
+void http_set_cgi_handlers(const tCGI *pCGIs, int iNumHandlers);
+
+#endif /* LWIP_HTTPD_CGI */
+
+#if LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI
+
+#if LWIP_HTTPD_CGI_SSI
+/* we have to prototype this struct here to make it available for the handler */
+struct fs_file;
+
+/** Define this generic CGI handler in your application.
+ * It is called once for every URI with parameters.
+ * The parameters can be stored to the object passed as connection_state, which
+ * is allocated to file->state via fs_state_init() from fs_open() or fs_open_custom().
+ * Content creation via SSI or complete dynamic files can retrieve the CGI params from there.
+ */
+extern void httpd_cgi_handler(struct fs_file *file, const char* uri, int iNumParams,
+ char **pcParam, char **pcValue
+#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE
+ , void *connection_state
+#endif /* LWIP_HTTPD_FILE_STATE */
+ );
+#endif /* LWIP_HTTPD_CGI_SSI */
+
+#endif /* LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI */
+
+#if LWIP_HTTPD_SSI
+
+/**
+ * @ingroup httpd
+ * Function pointer for the SSI tag handler callback.
+ *
+ * This function will be called each time the HTTPD server detects a tag of the
+ * form in files with extensions mentioned in the g_pcSSIExtensions
+ * array (currently .shtml, .shtm, .ssi, .xml, .json) where "name" appears as
+ * one of the tags supplied to http_set_ssi_handler in the tags array. The
+ * returned insert string, which will be appended after the the string
+ * "" in file sent back to the client, should be written to pointer
+ * pcInsert. iInsertLen contains the size of the buffer pointed to by
+ * pcInsert. The iIndex parameter provides the zero-based index of the tag as
+ * found in the tags array and identifies the tag that is to be processed.
+ *
+ * The handler returns the number of characters written to pcInsert excluding
+ * any terminating NULL or HTTPD_SSI_TAG_UNKNOWN when tag is not recognized.
+ *
+ * Note that the behavior of this SSI mechanism is somewhat different from the
+ * "normal" SSI processing as found in, for example, the Apache web server. In
+ * this case, the inserted text is appended following the SSI tag rather than
+ * replacing the tag entirely. This allows for an implementation that does not
+ * require significant additional buffering of output data yet which will still
+ * offer usable SSI functionality. One downside to this approach is when
+ * attempting to use SSI within JavaScript. The SSI tag is structured to
+ * resemble an HTML comment but this syntax does not constitute a comment
+ * within JavaScript and, hence, leaving the tag in place will result in
+ * problems in these cases. In order to avoid these problems, define
+ * LWIP_HTTPD_SSI_INCLUDE_TAG as zero in your lwip options file, or use JavaScript
+ * style block comments in the form / * # name * / (without the spaces).
+ */
+typedef u16_t (*tSSIHandler)(
+#if LWIP_HTTPD_SSI_RAW
+ const char* ssi_tag_name,
+#else /* LWIP_HTTPD_SSI_RAW */
+ int iIndex,
+#endif /* LWIP_HTTPD_SSI_RAW */
+ char *pcInsert, int iInsertLen
+#if LWIP_HTTPD_SSI_MULTIPART
+ , u16_t current_tag_part, u16_t *next_tag_part
+#endif /* LWIP_HTTPD_SSI_MULTIPART */
+#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE
+ , void *connection_state
+#endif /* LWIP_HTTPD_FILE_STATE */
+ );
+
+/** Set the SSI handler function
+ * (if LWIP_HTTPD_SSI_RAW==1, only the first argument is used)
+ */
+void http_set_ssi_handler(tSSIHandler pfnSSIHandler,
+ const char **ppcTags, int iNumTags);
+
+/** For LWIP_HTTPD_SSI_RAW==1, return this to indicate the tag is unknown.
+ * In this case, the webserver writes a warning into the page.
+ * You can also just return 0 to write nothing for unknown tags.
+ */
+#define HTTPD_SSI_TAG_UNKNOWN 0xFFFF
+
+#endif /* LWIP_HTTPD_SSI */
+
+#if LWIP_HTTPD_SUPPORT_POST
+
+/* These functions must be implemented by the application */
+
+/**
+ * @ingroup httpd
+ * Called when a POST request has been received. The application can decide
+ * whether to accept it or not.
+ *
+ * @param connection Unique connection identifier, valid until httpd_post_end
+ * is called.
+ * @param uri The HTTP header URI receiving the POST request.
+ * @param http_request The raw HTTP request (the first packet, normally).
+ * @param http_request_len Size of 'http_request'.
+ * @param content_len Content-Length from HTTP header.
+ * @param response_uri Filename of response file, to be filled when denying the
+ * request
+ * @param response_uri_len Size of the 'response_uri' buffer.
+ * @param post_auto_wnd Set this to 0 to let the callback code handle window
+ * updates by calling 'httpd_post_data_recved' (to throttle rx speed)
+ * default is 1 (httpd handles window updates automatically)
+ * @return ERR_OK: Accept the POST request, data may be passed in
+ * another err_t: Deny the POST request, send back 'bad request'.
+ */
+err_t httpd_post_begin(void *connection, const char *uri, const char *http_request,
+ u16_t http_request_len, int content_len, char *response_uri,
+ u16_t response_uri_len, u8_t *post_auto_wnd);
+
+/**
+ * @ingroup httpd
+ * Called for each pbuf of data that has been received for a POST.
+ * ATTENTION: The application is responsible for freeing the pbufs passed in!
+ *
+ * @param connection Unique connection identifier.
+ * @param p Received data.
+ * @return ERR_OK: Data accepted.
+ * another err_t: Data denied, http_post_get_response_uri will be called.
+ */
+err_t httpd_post_receive_data(void *connection, struct pbuf *p);
+
+/**
+ * @ingroup httpd
+ * Called when all data is received or when the connection is closed.
+ * The application must return the filename/URI of a file to send in response
+ * to this POST request. If the response_uri buffer is untouched, a 404
+ * response is returned.
+ *
+ * @param connection Unique connection identifier.
+ * @param response_uri Filename of response file, to be filled when denying the request
+ * @param response_uri_len Size of the 'response_uri' buffer.
+ */
+void httpd_post_finished(void *connection, char *response_uri, u16_t response_uri_len);
+
+#if LWIP_HTTPD_POST_MANUAL_WND
+void httpd_post_data_recved(void *connection, u16_t recved_len);
+#endif /* LWIP_HTTPD_POST_MANUAL_WND */
+
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+
+void httpd_init(void);
+
+#if HTTPD_ENABLE_HTTPS
+struct altcp_tls_config;
+void httpd_inits(struct altcp_tls_config *conf);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_HTTPD_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/httpd_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/httpd_opts.h
new file mode 100644
index 0000000..65296ef
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/httpd_opts.h
@@ -0,0 +1,396 @@
+/**
+ * @file
+ * HTTP server options list
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ * This version of the file has been modified by Texas Instruments to offer
+ * simple server-side-include (SSI) and Common Gateway Interface (CGI)
+ * capability.
+ */
+
+#ifndef LWIP_HDR_APPS_HTTPD_OPTS_H
+#define LWIP_HDR_APPS_HTTPD_OPTS_H
+
+#include "lwip/opt.h"
+#include "lwip/prot/iana.h"
+
+/**
+ * @defgroup httpd_opts Options
+ * @ingroup httpd
+ * @{
+ */
+
+/** Set this to 1 to support CGI (old style).
+ *
+ * This old style CGI support works by registering an array of URLs and
+ * associated CGI handler functions (@ref http_set_cgi_handlers).
+ * This list is scanned just before fs_open is called from request handling.
+ * The handler can return a new URL that is used internally by the httpd to
+ * load the returned page (passed to fs_open).
+ *
+ * Use this CGI type e.g. to execute specific actions and return a page that
+ * does not depend on the CGI parameters.
+ */
+#if !defined LWIP_HTTPD_CGI || defined __DOXYGEN__
+#define LWIP_HTTPD_CGI 0
+#endif
+
+/** Set this to 1 to support CGI (new style).
+ *
+ * This new style CGI support works by calling a global function
+ * (@ref tCGIHandler) for all URLs that are found. fs_open is called first
+ * and the URL can not be written by the CGI handler. Instead, this handler gets
+ * passed the http file state, an object where it can store information derived
+ * from the CGI URL or parameters. This file state is later passed to SSI, so
+ * the SSI code can return data depending on CGI input.
+ *
+ * Use this CGI handler if you want CGI information passed on to SSI.
+ */
+#if !defined LWIP_HTTPD_CGI_SSI || defined __DOXYGEN__
+#define LWIP_HTTPD_CGI_SSI 0
+#endif
+
+/** Set this to 1 to support SSI (Server-Side-Includes)
+ *
+ * In contrast to other http servers, this only calls a preregistered callback
+ * function (@see http_set_ssi_handler) for each tag (in the format of
+ * ) encountered in SSI-enabled pages.
+ * SSI-enabled pages must have one of the predefined SSI-enabled file extensions.
+ * All files with one of these extensions are parsed when sent.
+ *
+ * A downside of the current SSI implementation is that persistent connections
+ * don't work, as the file length is not known in advance (and httpd currently
+ * relies on the Content-Length header for persistent connections).
+ *
+ * To save memory, the maximum tag length is limited (@see LWIP_HTTPD_MAX_TAG_NAME_LEN).
+ * To save memory, the maximum insertion string length is limited (@see
+ * LWIP_HTTPD_MAX_TAG_INSERT_LEN). If this is not enough, @ref LWIP_HTTPD_SSI_MULTIPART
+ * can be used.
+ */
+#if !defined LWIP_HTTPD_SSI || defined __DOXYGEN__
+#define LWIP_HTTPD_SSI 0
+#endif
+
+/** Set this to 1 to implement an SSI tag handler callback that gets a const char*
+ * to the tag (instead of an index into a pre-registered array of known tags)
+ * If this is 0, the SSI handler callback function is only called pre-registered tags.
+ */
+#if !defined LWIP_HTTPD_SSI_RAW || defined __DOXYGEN__
+#define LWIP_HTTPD_SSI_RAW 0
+#endif
+
+/** Set this to 0 to prevent parsing the file extension at runtime to decide
+ * if a file should be scanned for SSI tags or not.
+ * Default is 1 (file extensions are checked using the g_pcSSIExtensions array)
+ * Set to 2 to override this runtime test function.
+ *
+ * This is enabled by default, but if you only use a newer version of makefsdata
+ * supporting the "-ssi" option, this info is already present in
+ */
+#if !defined LWIP_HTTPD_SSI_BY_FILE_EXTENSION || defined __DOXYGEN__
+#define LWIP_HTTPD_SSI_BY_FILE_EXTENSION 1
+#endif
+
+/** Set this to 1 to support HTTP POST */
+#if !defined LWIP_HTTPD_SUPPORT_POST || defined __DOXYGEN__
+#define LWIP_HTTPD_SUPPORT_POST 0
+#endif
+
+/* The maximum number of parameters that the CGI handler can be sent. */
+#if !defined LWIP_HTTPD_MAX_CGI_PARAMETERS || defined __DOXYGEN__
+#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16
+#endif
+
+/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more
+ * arguments indicating a counter for insert string that are too long to be
+ * inserted at once: the SSI handler function must then set 'next_tag_part'
+ * which will be passed back to it in the next call. */
+#if !defined LWIP_HTTPD_SSI_MULTIPART || defined __DOXYGEN__
+#define LWIP_HTTPD_SSI_MULTIPART 0
+#endif
+
+/* The maximum length of the string comprising the SSI tag name
+ * ATTENTION: tags longer than this are ignored, not truncated!
+ */
+#if !defined LWIP_HTTPD_MAX_TAG_NAME_LEN || defined __DOXYGEN__
+#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8
+#endif
+
+/* The maximum length of string that can be returned to replace any given tag
+ * If this buffer is not long enough, use LWIP_HTTPD_SSI_MULTIPART.
+ */
+#if !defined LWIP_HTTPD_MAX_TAG_INSERT_LEN || defined __DOXYGEN__
+#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192
+#endif
+
+#if !defined LWIP_HTTPD_POST_MANUAL_WND || defined __DOXYGEN__
+#define LWIP_HTTPD_POST_MANUAL_WND 0
+#endif
+
+/** This string is passed in the HTTP header as "Server: " */
+#if !defined HTTPD_SERVER_AGENT || defined __DOXYGEN__
+#define HTTPD_SERVER_AGENT "lwIP/" LWIP_VERSION_STRING " (http://savannah.nongnu.org/projects/lwip)"
+#endif
+
+/** Set this to 1 if you want to include code that creates HTTP headers
+ * at runtime. Default is off: HTTP headers are then created statically
+ * by the makefsdata tool. Static headers mean smaller code size, but
+ * the (readonly) fsdata will grow a bit as every file includes the HTTP
+ * header. */
+#if !defined LWIP_HTTPD_DYNAMIC_HEADERS || defined __DOXYGEN__
+#define LWIP_HTTPD_DYNAMIC_HEADERS 0
+#endif
+
+#if !defined HTTPD_DEBUG || defined __DOXYGEN__
+#define HTTPD_DEBUG LWIP_DBG_OFF
+#endif
+
+/** Set this to 1 to use a memp pool for allocating
+ * struct http_state instead of the heap.
+ * If enabled, you'll need to define MEMP_NUM_PARALLEL_HTTPD_CONNS
+ * (and MEMP_NUM_PARALLEL_HTTPD_SSI_CONNS for SSI) to set the size of
+ * the pool(s).
+ */
+#if !defined HTTPD_USE_MEM_POOL || defined __DOXYGEN__
+#define HTTPD_USE_MEM_POOL 0
+#endif
+
+/** The server port for HTTPD to use */
+#if !defined HTTPD_SERVER_PORT || defined __DOXYGEN__
+#define HTTPD_SERVER_PORT LWIP_IANA_PORT_HTTP
+#endif
+
+/** The https server port for HTTPD to use */
+#if !defined HTTPD_SERVER_PORT_HTTPS || defined __DOXYGEN__
+#define HTTPD_SERVER_PORT_HTTPS LWIP_IANA_PORT_HTTPS
+#endif
+
+/** Enable https support? */
+#if !defined HTTPD_ENABLE_HTTPS || defined __DOXYGEN__
+#define HTTPD_ENABLE_HTTPS 0
+#endif
+
+/** Maximum retries before the connection is aborted/closed.
+ * - number of times pcb->poll is called -> default is 4*500ms = 2s;
+ * - reset when pcb->sent is called
+ */
+#if !defined HTTPD_MAX_RETRIES || defined __DOXYGEN__
+#define HTTPD_MAX_RETRIES 4
+#endif
+
+/** The poll delay is X*500ms */
+#if !defined HTTPD_POLL_INTERVAL || defined __DOXYGEN__
+#define HTTPD_POLL_INTERVAL 4
+#endif
+
+/** Priority for tcp pcbs created by HTTPD (very low by default).
+ * Lower priorities get killed first when running out of memory.
+ */
+#if !defined HTTPD_TCP_PRIO || defined __DOXYGEN__
+#define HTTPD_TCP_PRIO TCP_PRIO_MIN
+#endif
+
+/** Set this to 1 to enable timing each file sent */
+#if !defined LWIP_HTTPD_TIMING || defined __DOXYGEN__
+#define LWIP_HTTPD_TIMING 0
+#endif
+/** Set this to 1 to enable timing each file sent */
+#if !defined HTTPD_DEBUG_TIMING || defined __DOXYGEN__
+#define HTTPD_DEBUG_TIMING LWIP_DBG_OFF
+#endif
+
+/** Set this to one to show error pages when parsing a request fails instead
+ of simply closing the connection. */
+#if !defined LWIP_HTTPD_SUPPORT_EXTSTATUS || defined __DOXYGEN__
+#define LWIP_HTTPD_SUPPORT_EXTSTATUS 0
+#endif
+
+/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */
+#if !defined LWIP_HTTPD_SUPPORT_V09 || defined __DOXYGEN__
+#define LWIP_HTTPD_SUPPORT_V09 1
+#endif
+
+/** Set this to 1 to enable HTTP/1.1 persistent connections.
+ * ATTENTION: If the generated file system includes HTTP headers, these must
+ * include the "Connection: keep-alive" header (pass argument "-11" to makefsdata).
+ */
+#if !defined LWIP_HTTPD_SUPPORT_11_KEEPALIVE || defined __DOXYGEN__
+#define LWIP_HTTPD_SUPPORT_11_KEEPALIVE 0
+#endif
+
+/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */
+#if !defined LWIP_HTTPD_SUPPORT_REQUESTLIST || defined __DOXYGEN__
+#define LWIP_HTTPD_SUPPORT_REQUESTLIST 1
+#endif
+
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+/** Number of rx pbufs to enqueue to parse an incoming request (up to the first
+ newline) */
+#if !defined LWIP_HTTPD_REQ_QUEUELEN || defined __DOXYGEN__
+#define LWIP_HTTPD_REQ_QUEUELEN 5
+#endif
+
+/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming
+ request (up to the first double-newline) */
+#if !defined LWIP_HTTPD_REQ_BUFSIZE || defined __DOXYGEN__
+#define LWIP_HTTPD_REQ_BUFSIZE LWIP_HTTPD_MAX_REQ_LENGTH
+#endif
+
+/** Defines the maximum length of a HTTP request line (up to the first CRLF,
+ copied from pbuf into this a global buffer when pbuf- or packet-queues
+ are received - otherwise the input pbuf is used directly) */
+#if !defined LWIP_HTTPD_MAX_REQ_LENGTH || defined __DOXYGEN__
+#define LWIP_HTTPD_MAX_REQ_LENGTH LWIP_MIN(1023, (LWIP_HTTPD_REQ_QUEUELEN * PBUF_POOL_BUFSIZE))
+#endif
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+
+/** This is the size of a static buffer used when URIs end with '/'.
+ * In this buffer, the directory requested is concatenated with all the
+ * configured default file names.
+ * Set to 0 to disable checking default filenames on non-root directories.
+ */
+#if !defined LWIP_HTTPD_MAX_REQUEST_URI_LEN || defined __DOXYGEN__
+#define LWIP_HTTPD_MAX_REQUEST_URI_LEN 63
+#endif
+
+/** Maximum length of the filename to send as response to a POST request,
+ * filled in by the application when a POST is finished.
+ */
+#if !defined LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN || defined __DOXYGEN__
+#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63
+#endif
+
+/** Set this to 0 to not send the SSI tag (default is on, so the tag will
+ * be sent in the HTML page */
+#if !defined LWIP_HTTPD_SSI_INCLUDE_TAG || defined __DOXYGEN__
+#define LWIP_HTTPD_SSI_INCLUDE_TAG 1
+#endif
+
+/** Set this to 1 to call tcp_abort when tcp_close fails with memory error.
+ * This can be used to prevent consuming all memory in situations where the
+ * HTTP server has low priority compared to other communication. */
+#if !defined LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR || defined __DOXYGEN__
+#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR 0
+#endif
+
+/** Set this to 1 to kill the oldest connection when running out of
+ * memory for 'struct http_state' or 'struct http_ssi_state'.
+ * ATTENTION: This puts all connections on a linked list, so may be kind of slow.
+ */
+#if !defined LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED || defined __DOXYGEN__
+#define LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED 0
+#endif
+
+/** Set this to 1 to send URIs without extension without headers
+ * (who uses this at all??) */
+#if !defined LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI || defined __DOXYGEN__
+#define LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI 0
+#endif
+
+/** Default: Tags are sent from struct http_state and are therefore volatile */
+#if !defined HTTP_IS_TAG_VOLATILE || defined __DOXYGEN__
+#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY
+#endif
+
+/* By default, the httpd is limited to send 2*pcb->mss to keep resource usage low
+ when http is not an important protocol in the device. */
+#if !defined HTTPD_LIMIT_SENDING_TO_2MSS || defined __DOXYGEN__
+#define HTTPD_LIMIT_SENDING_TO_2MSS 1
+#endif
+
+/* Define this to a function that returns the maximum amount of data to enqueue.
+ The function have this signature: u16_t fn(struct altcp_pcb* pcb);
+ The best place to define this is the hooks file (@see LWIP_HOOK_FILENAME) */
+#if !defined HTTPD_MAX_WRITE_LEN || defined __DOXYGEN__
+#if HTTPD_LIMIT_SENDING_TO_2MSS
+#define HTTPD_MAX_WRITE_LEN(pcb) ((u16_t)(2 * altcp_mss(pcb)))
+#endif
+#endif
+
+/*------------------- FS OPTIONS -------------------*/
+
+/** Set this to 1 and provide the functions:
+ * - "int fs_open_custom(struct fs_file *file, const char *name)"
+ * Called first for every opened file to allow opening files
+ * that are not included in fsdata(_custom).c
+ * - "void fs_close_custom(struct fs_file *file)"
+ * Called to free resources allocated by fs_open_custom().
+ */
+#if !defined LWIP_HTTPD_CUSTOM_FILES || defined __DOXYGEN__
+#define LWIP_HTTPD_CUSTOM_FILES 0
+#endif
+
+/** Set this to 1 to support fs_read() to dynamically read file data.
+ * Without this (default=off), only one-block files are supported,
+ * and the contents must be ready after fs_open().
+ */
+#if !defined LWIP_HTTPD_DYNAMIC_FILE_READ || defined __DOXYGEN__
+#define LWIP_HTTPD_DYNAMIC_FILE_READ 0
+#endif
+
+/** Set this to 1 to include an application state argument per file
+ * that is opened. This allows to keep a state per connection/file.
+ */
+#if !defined LWIP_HTTPD_FILE_STATE || defined __DOXYGEN__
+#define LWIP_HTTPD_FILE_STATE 0
+#endif
+
+/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for
+ * predefined (MSS-sized) chunks of the files to prevent having to calculate
+ * the checksums at runtime. */
+#if !defined HTTPD_PRECALCULATED_CHECKSUM || defined __DOXYGEN__
+#define HTTPD_PRECALCULATED_CHECKSUM 0
+#endif
+
+/** LWIP_HTTPD_FS_ASYNC_READ==1: support asynchronous read operations
+ * (fs_read_async returns FS_READ_DELAYED and calls a callback when finished).
+ */
+#if !defined LWIP_HTTPD_FS_ASYNC_READ || defined __DOXYGEN__
+#define LWIP_HTTPD_FS_ASYNC_READ 0
+#endif
+
+/** Filename (including path) to use as FS data file */
+#if !defined HTTPD_FSDATA_FILE || defined __DOXYGEN__
+/* HTTPD_USE_CUSTOM_FSDATA: Compatibility with deprecated lwIP option */
+#if defined(HTTPD_USE_CUSTOM_FSDATA) && (HTTPD_USE_CUSTOM_FSDATA != 0)
+#define HTTPD_FSDATA_FILE "fsdata_custom.c"
+#else
+#define HTTPD_FSDATA_FILE "fsdata.c"
+#endif
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_APPS_HTTPD_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/lwiperf.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/lwiperf.h
new file mode 100644
index 0000000..cc86e7f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/lwiperf.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * lwIP iPerf server implementation
+ */
+
+/*
+ * Copyright (c) 2014 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_APPS_LWIPERF_H
+#define LWIP_HDR_APPS_LWIPERF_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LWIPERF_TCP_PORT_DEFAULT 5001
+
+/** lwIPerf test results */
+enum lwiperf_report_type
+{
+ /** The server side test is done */
+ LWIPERF_TCP_DONE_SERVER,
+ /** The client side test is done */
+ LWIPERF_TCP_DONE_CLIENT,
+ /** Local error lead to test abort */
+ LWIPERF_TCP_ABORTED_LOCAL,
+ /** Data check error lead to test abort */
+ LWIPERF_TCP_ABORTED_LOCAL_DATAERROR,
+ /** Transmit error lead to test abort */
+ LWIPERF_TCP_ABORTED_LOCAL_TXERROR,
+ /** Remote side aborted the test */
+ LWIPERF_TCP_ABORTED_REMOTE
+};
+
+/** Control */
+enum lwiperf_client_type
+{
+ /** Unidirectional tx only test */
+ LWIPERF_CLIENT,
+ /** Do a bidirectional test simultaneously */
+ LWIPERF_DUAL,
+ /** Do a bidirectional test individually */
+ LWIPERF_TRADEOFF
+};
+
+/** Prototype of a report function that is called when a session is finished.
+ This report function can show the test results.
+ @param report_type contains the test result */
+typedef void (*lwiperf_report_fn)(void *arg, enum lwiperf_report_type report_type,
+ const ip_addr_t* local_addr, u16_t local_port, const ip_addr_t* remote_addr, u16_t remote_port,
+ u32_t bytes_transferred, u32_t ms_duration, u32_t bandwidth_kbitpsec);
+
+void* lwiperf_start_tcp_server(const ip_addr_t* local_addr, u16_t local_port,
+ lwiperf_report_fn report_fn, void* report_arg);
+void* lwiperf_start_tcp_server_default(lwiperf_report_fn report_fn, void* report_arg);
+void* lwiperf_start_tcp_client(const ip_addr_t* remote_addr, u16_t remote_port,
+ enum lwiperf_client_type type,
+ lwiperf_report_fn report_fn, void* report_arg);
+void* lwiperf_start_tcp_client_default(const ip_addr_t* remote_addr,
+ lwiperf_report_fn report_fn, void* report_arg);
+
+void lwiperf_abort(void* lwiperf_session);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_LWIPERF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns.h
new file mode 100644
index 0000000..20d7ee2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns.h
@@ -0,0 +1,105 @@
+/**
+ * @file
+ * MDNS responder
+ */
+
+ /*
+ * Copyright (c) 2015 Verisure Innovation AB
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Erik Ekman
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_MDNS_H
+#define LWIP_HDR_APPS_MDNS_H
+
+#include "lwip/apps/mdns_opts.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_MDNS_RESPONDER
+
+enum mdns_sd_proto {
+ DNSSD_PROTO_UDP = 0,
+ DNSSD_PROTO_TCP = 1
+};
+
+#define MDNS_PROBING_CONFLICT 0
+#define MDNS_PROBING_SUCCESSFUL 1
+
+#define MDNS_LABEL_MAXLEN 63
+
+struct mdns_host;
+struct mdns_service;
+
+/** Callback function to add text to a reply, called when generating the reply */
+typedef void (*service_get_txt_fn_t)(struct mdns_service *service, void *txt_userdata);
+
+/** Callback function to let application know the result of probing network for name
+ * uniqueness, called with result MDNS_PROBING_SUCCESSFUL if no other node claimed
+ * use for the name for the netif or a service and is safe to use, or MDNS_PROBING_CONFLICT
+ * if another node is already using it and mdns is disabled on this interface */
+typedef void (*mdns_name_result_cb_t)(struct netif* netif, u8_t result);
+
+void mdns_resp_init(void);
+
+void mdns_resp_register_name_result_cb(mdns_name_result_cb_t cb);
+
+err_t mdns_resp_add_netif(struct netif *netif, const char *hostname, u32_t dns_ttl);
+err_t mdns_resp_remove_netif(struct netif *netif);
+err_t mdns_resp_rename_netif(struct netif *netif, const char *hostname);
+
+s8_t mdns_resp_add_service(struct netif *netif, const char *name, const char *service, enum mdns_sd_proto proto, u16_t port, u32_t dns_ttl, service_get_txt_fn_t txt_fn, void *txt_userdata);
+err_t mdns_resp_del_service(struct netif *netif, s8_t slot);
+err_t mdns_resp_rename_service(struct netif *netif, s8_t slot, const char *name);
+
+err_t mdns_resp_add_service_txtitem(struct mdns_service *service, const char *txt, u8_t txt_len);
+
+void mdns_resp_restart(struct netif *netif);
+void mdns_resp_announce(struct netif *netif);
+
+/**
+ * @ingroup mdns
+ * Announce IP settings have changed on netif.
+ * Call this in your callback registered by netif_set_status_callback().
+ * No need to call this function when LWIP_NETIF_EXT_STATUS_CALLBACK==1,
+ * this handled automatically for you.
+ * @param netif The network interface where settings have changed.
+ */
+#define mdns_resp_netif_settings_changed(netif) mdns_resp_announce(netif)
+
+#endif /* LWIP_MDNS_RESPONDER */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_MDNS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns_opts.h
new file mode 100644
index 0000000..ac23220
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns_opts.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ * MDNS responder
+ */
+
+ /*
+ * Copyright (c) 2015 Verisure Innovation AB
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Erik Ekman
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_MDNS_OPTS_H
+#define LWIP_HDR_APPS_MDNS_OPTS_H
+
+#include "lwip/opt.h"
+
+/**
+ * @defgroup mdns_opts Options
+ * @ingroup mdns
+ * @{
+ */
+
+/**
+ * LWIP_MDNS_RESPONDER==1: Turn on multicast DNS module. UDP must be available for MDNS
+ * transport. IGMP is needed for IPv4 multicast.
+ */
+#ifndef LWIP_MDNS_RESPONDER
+#define LWIP_MDNS_RESPONDER 0
+#endif /* LWIP_MDNS_RESPONDER */
+
+/** The maximum number of services per netif */
+#ifndef MDNS_MAX_SERVICES
+#define MDNS_MAX_SERVICES 1
+#endif
+
+/** MDNS_RESP_USENETIF_EXTCALLBACK==1: register an ext_callback on the netif
+ * to automatically restart probing/announcing on status or address change.
+ */
+#ifndef MDNS_RESP_USENETIF_EXTCALLBACK
+#define MDNS_RESP_USENETIF_EXTCALLBACK LWIP_NETIF_EXT_STATUS_CALLBACK
+#endif
+
+/**
+ * MDNS_DEBUG: Enable debugging for multicast DNS.
+ */
+#ifndef MDNS_DEBUG
+#define MDNS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_APPS_MDNS_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns_priv.h
new file mode 100644
index 0000000..9635b5b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mdns_priv.h
@@ -0,0 +1,74 @@
+/**
+ * @file
+ * MDNS responder private definitions
+ */
+
+ /*
+ * Copyright (c) 2015 Verisure Innovation AB
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Erik Ekman
+ *
+ */
+#ifndef LWIP_HDR_MDNS_PRIV_H
+#define LWIP_HDR_MDNS_PRIV_H
+
+#include "lwip/apps/mdns_opts.h"
+#include "lwip/pbuf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_MDNS_RESPONDER
+
+/* Domain struct and methods - visible for unit tests */
+
+#define MDNS_DOMAIN_MAXLEN 256
+#define MDNS_READNAME_ERROR 0xFFFF
+
+struct mdns_domain {
+ /* Encoded domain name */
+ u8_t name[MDNS_DOMAIN_MAXLEN];
+ /* Total length of domain name, including zero */
+ u16_t length;
+ /* Set if compression of this domain is not allowed */
+ u8_t skip_compression;
+};
+
+err_t mdns_domain_add_label(struct mdns_domain *domain, const char *label, u8_t len);
+u16_t mdns_readname(struct pbuf *p, u16_t offset, struct mdns_domain *domain);
+int mdns_domain_eq(struct mdns_domain *a, struct mdns_domain *b);
+u16_t mdns_compress_domain(struct pbuf *pbuf, u16_t *offset, struct mdns_domain *domain);
+
+#endif /* LWIP_MDNS_RESPONDER */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MDNS_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt.h
new file mode 100644
index 0000000..f099812
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt.h
@@ -0,0 +1,205 @@
+/**
+ * @file
+ * MQTT client
+ */
+
+/*
+ * Copyright (c) 2016 Erik Andersson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Erik Andersson
+ *
+ */
+#ifndef LWIP_HDR_APPS_MQTT_CLIENT_H
+#define LWIP_HDR_APPS_MQTT_CLIENT_H
+
+#include "lwip/apps/mqtt_opts.h"
+#include "lwip/err.h"
+#include "lwip/ip_addr.h"
+#include "lwip/prot/iana.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct mqtt_client_s mqtt_client_t;
+
+#if LWIP_ALTCP && LWIP_ALTCP_TLS
+struct altcp_tls_config;
+#endif
+
+/** @ingroup mqtt
+ * Default MQTT port (non-TLS) */
+#define MQTT_PORT LWIP_IANA_PORT_MQTT
+/** @ingroup mqtt
+ * Default MQTT TLS port */
+#define MQTT_TLS_PORT LWIP_IANA_PORT_SECURE_MQTT
+
+/*---------------------------------------------------------------------------------------------- */
+/* Connection with server */
+
+/**
+ * @ingroup mqtt
+ * Client information and connection parameters */
+struct mqtt_connect_client_info_t {
+ /** Client identifier, must be set by caller */
+ const char *client_id;
+ /** User name, set to NULL if not used */
+ const char* client_user;
+ /** Password, set to NULL if not used */
+ const char* client_pass;
+ /** keep alive time in seconds, 0 to disable keep alive functionality*/
+ u16_t keep_alive;
+ /** will topic, set to NULL if will is not to be used,
+ will_msg, will_qos and will retain are then ignored */
+ const char* will_topic;
+ /** will_msg, see will_topic */
+ const char* will_msg;
+ /** will_qos, see will_topic */
+ u8_t will_qos;
+ /** will_retain, see will_topic */
+ u8_t will_retain;
+#if LWIP_ALTCP && LWIP_ALTCP_TLS
+ /** TLS configuration for secure connections */
+ struct altcp_tls_config *tls_config;
+#endif
+};
+
+/**
+ * @ingroup mqtt
+ * Connection status codes */
+typedef enum
+{
+ /** Accepted */
+ MQTT_CONNECT_ACCEPTED = 0,
+ /** Refused protocol version */
+ MQTT_CONNECT_REFUSED_PROTOCOL_VERSION = 1,
+ /** Refused identifier */
+ MQTT_CONNECT_REFUSED_IDENTIFIER = 2,
+ /** Refused server */
+ MQTT_CONNECT_REFUSED_SERVER = 3,
+ /** Refused user credentials */
+ MQTT_CONNECT_REFUSED_USERNAME_PASS = 4,
+ /** Refused not authorized */
+ MQTT_CONNECT_REFUSED_NOT_AUTHORIZED_ = 5,
+ /** Disconnected */
+ MQTT_CONNECT_DISCONNECTED = 256,
+ /** Timeout */
+ MQTT_CONNECT_TIMEOUT = 257
+} mqtt_connection_status_t;
+
+/**
+ * @ingroup mqtt
+ * Function prototype for mqtt connection status callback. Called when
+ * client has connected to the server after initiating a mqtt connection attempt by
+ * calling mqtt_client_connect() or when connection is closed by server or an error
+ *
+ * @param client MQTT client itself
+ * @param arg Additional argument to pass to the callback function
+ * @param status Connect result code or disconnection notification @see mqtt_connection_status_t
+ *
+ */
+typedef void (*mqtt_connection_cb_t)(mqtt_client_t *client, void *arg, mqtt_connection_status_t status);
+
+
+/**
+ * @ingroup mqtt
+ * Data callback flags */
+enum {
+ /** Flag set when last fragment of data arrives in data callback */
+ MQTT_DATA_FLAG_LAST = 1
+};
+
+/**
+ * @ingroup mqtt
+ * Function prototype for MQTT incoming publish data callback function. Called when data
+ * arrives to a subscribed topic @see mqtt_subscribe
+ *
+ * @param arg Additional argument to pass to the callback function
+ * @param data User data, pointed object, data may not be referenced after callback return,
+ NULL is passed when all publish data are delivered
+ * @param len Length of publish data fragment
+ * @param flags MQTT_DATA_FLAG_LAST set when this call contains the last part of data from publish message
+ *
+ */
+typedef void (*mqtt_incoming_data_cb_t)(void *arg, const u8_t *data, u16_t len, u8_t flags);
+
+
+/**
+ * @ingroup mqtt
+ * Function prototype for MQTT incoming publish function. Called when an incoming publish
+ * arrives to a subscribed topic @see mqtt_subscribe
+ *
+ * @param arg Additional argument to pass to the callback function
+ * @param topic Zero terminated Topic text string, topic may not be referenced after callback return
+ * @param tot_len Total length of publish data, if set to 0 (no publish payload) data callback will not be invoked
+ */
+typedef void (*mqtt_incoming_publish_cb_t)(void *arg, const char *topic, u32_t tot_len);
+
+
+/**
+ * @ingroup mqtt
+ * Function prototype for mqtt request callback. Called when a subscribe, unsubscribe
+ * or publish request has completed
+ * @param arg Pointer to user data supplied when invoking request
+ * @param err ERR_OK on success
+ * ERR_TIMEOUT if no response was received within timeout,
+ * ERR_ABRT if (un)subscribe was denied
+ */
+typedef void (*mqtt_request_cb_t)(void *arg, err_t err);
+
+
+err_t mqtt_client_connect(mqtt_client_t *client, const ip_addr_t *ipaddr, u16_t port, mqtt_connection_cb_t cb, void *arg,
+ const struct mqtt_connect_client_info_t *client_info);
+
+void mqtt_disconnect(mqtt_client_t *client);
+
+mqtt_client_t *mqtt_client_new(void);
+void mqtt_client_free(mqtt_client_t* client);
+
+u8_t mqtt_client_is_connected(mqtt_client_t *client);
+
+void mqtt_set_inpub_callback(mqtt_client_t *client, mqtt_incoming_publish_cb_t,
+ mqtt_incoming_data_cb_t data_cb, void *arg);
+
+err_t mqtt_sub_unsub(mqtt_client_t *client, const char *topic, u8_t qos, mqtt_request_cb_t cb, void *arg, u8_t sub);
+
+/** @ingroup mqtt
+ *Subscribe to topic */
+#define mqtt_subscribe(client, topic, qos, cb, arg) mqtt_sub_unsub(client, topic, qos, cb, arg, 1)
+/** @ingroup mqtt
+ * Unsubscribe to topic */
+#define mqtt_unsubscribe(client, topic, cb, arg) mqtt_sub_unsub(client, topic, 0, cb, arg, 0)
+
+err_t mqtt_publish(mqtt_client_t *client, const char *topic, const void *payload, u16_t payload_length, u8_t qos, u8_t retain,
+ mqtt_request_cb_t cb, void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_MQTT_CLIENT_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_opts.h
new file mode 100644
index 0000000..4226d21
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_opts.h
@@ -0,0 +1,103 @@
+/**
+ * @file
+ * MQTT client options
+ */
+
+/*
+ * Copyright (c) 2016 Erik Andersson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Erik Andersson
+ *
+ */
+#ifndef LWIP_HDR_APPS_MQTT_OPTS_H
+#define LWIP_HDR_APPS_MQTT_OPTS_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup mqtt_opts Options
+ * @ingroup mqtt
+ * @{
+ */
+
+/**
+ * Output ring-buffer size, must be able to fit largest outgoing publish message topic+payloads
+ */
+#ifndef MQTT_OUTPUT_RINGBUF_SIZE
+#define MQTT_OUTPUT_RINGBUF_SIZE 256
+#endif
+
+/**
+ * Number of bytes in receive buffer, must be at least the size of the longest incoming topic + 8
+ * If one wants to avoid fragmented incoming publish, set length to max incoming topic length + max payload length + 8
+ */
+#ifndef MQTT_VAR_HEADER_BUFFER_LEN
+#define MQTT_VAR_HEADER_BUFFER_LEN 128
+#endif
+
+/**
+ * Maximum number of pending subscribe, unsubscribe and publish requests to server .
+ */
+#ifndef MQTT_REQ_MAX_IN_FLIGHT
+#define MQTT_REQ_MAX_IN_FLIGHT 4
+#endif
+
+/**
+ * Seconds between each cyclic timer call.
+ */
+#ifndef MQTT_CYCLIC_TIMER_INTERVAL
+#define MQTT_CYCLIC_TIMER_INTERVAL 5
+#endif
+
+/**
+ * Publish, subscribe and unsubscribe request timeout in seconds.
+ */
+#ifndef MQTT_REQ_TIMEOUT
+#define MQTT_REQ_TIMEOUT 30
+#endif
+
+/**
+ * Seconds for MQTT connect response timeout after sending connect request
+ */
+#ifndef MQTT_CONNECT_TIMOUT
+#define MQTT_CONNECT_TIMOUT 100
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_MQTT_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_priv.h
new file mode 100644
index 0000000..b775913
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_priv.h
@@ -0,0 +1,104 @@
+/**
+ * @file
+ * MQTT client (private interface)
+ */
+
+/*
+ * Copyright (c) 2016 Erik Andersson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Erik Andersson
+ *
+ */
+#ifndef LWIP_HDR_APPS_MQTT_PRIV_H
+#define LWIP_HDR_APPS_MQTT_PRIV_H
+
+#include "lwip/apps/mqtt.h"
+#include "lwip/altcp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Pending request item, binds application callback to pending server requests */
+struct mqtt_request_t
+{
+ /** Next item in list, NULL means this is the last in chain,
+ next pointing at itself means request is unallocated */
+ struct mqtt_request_t *next;
+ /** Callback to upper layer */
+ mqtt_request_cb_t cb;
+ void *arg;
+ /** MQTT packet identifier */
+ u16_t pkt_id;
+ /** Expire time relative to element before this */
+ u16_t timeout_diff;
+};
+
+/** Ring buffer */
+struct mqtt_ringbuf_t {
+ u16_t put;
+ u16_t get;
+ u8_t buf[MQTT_OUTPUT_RINGBUF_SIZE];
+};
+
+/** MQTT client */
+struct mqtt_client_s
+{
+ /** Timers and timeouts */
+ u16_t cyclic_tick;
+ u16_t keep_alive;
+ u16_t server_watchdog;
+ /** Packet identifier generator*/
+ u16_t pkt_id_seq;
+ /** Packet identifier of pending incoming publish */
+ u16_t inpub_pkt_id;
+ /** Connection state */
+ u8_t conn_state;
+ struct altcp_pcb *conn;
+ /** Connection callback */
+ void *connect_arg;
+ mqtt_connection_cb_t connect_cb;
+ /** Pending requests to server */
+ struct mqtt_request_t *pend_req_queue;
+ struct mqtt_request_t req_list[MQTT_REQ_MAX_IN_FLIGHT];
+ void *inpub_arg;
+ /** Incoming data callback */
+ mqtt_incoming_data_cb_t data_cb;
+ mqtt_incoming_publish_cb_t pub_cb;
+ /** Input */
+ u32_t msg_idx;
+ u8_t rx_buffer[MQTT_VAR_HEADER_BUFFER_LEN];
+ /** Output ring-buffer */
+ struct mqtt_ringbuf_t output;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_MQTT_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns.h
new file mode 100644
index 0000000..a326d33
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns.h
@@ -0,0 +1,51 @@
+/**
+ * @file
+ * NETBIOS name service responder
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+#ifndef LWIP_HDR_APPS_NETBIOS_H
+#define LWIP_HDR_APPS_NETBIOS_H
+
+#include "lwip/apps/netbiosns_opts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void netbiosns_init(void);
+#ifndef NETBIOS_LWIP_NAME
+void netbiosns_set_name(const char* hostname);
+#endif
+void netbiosns_stop(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_NETBIOS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns_opts.h
new file mode 100644
index 0000000..cc0da95
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns_opts.h
@@ -0,0 +1,66 @@
+/**
+ * @file
+ * NETBIOS name service responder options
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+#ifndef LWIP_HDR_APPS_NETBIOS_OPTS_H
+#define LWIP_HDR_APPS_NETBIOS_OPTS_H
+
+#include "lwip/opt.h"
+
+/**
+ * @defgroup netbiosns_opts Options
+ * @ingroup netbiosns
+ * @{
+ */
+
+/** NetBIOS name of lwip device
+ * This must be uppercase until NETBIOS_STRCMP() is defined to a string
+ * comparison function that is case insensitive.
+ * If you want to use the netif's hostname, use this (with LWIP_NETIF_HOSTNAME):
+ * (ip_current_netif() != NULL ? ip_current_netif()->hostname != NULL ? ip_current_netif()->hostname : "" : "")
+ *
+ * If this is not defined, netbiosns_set_name() can be called at runtime to change the name.
+ */
+#ifdef __DOXYGEN__
+#define NETBIOS_LWIP_NAME "NETBIOSLWIPDEV"
+#endif
+
+/** Respond to NetBIOS name queries
+ * Default is disabled
+ */
+#if !defined LWIP_NETBIOS_RESPOND_NAME_QUERY || defined __DOXYGEN__
+#define LWIP_NETBIOS_RESPOND_NAME_QUERY 0
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_APPS_NETBIOS_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/smtp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/smtp.h
new file mode 100644
index 0000000..fb4a4a7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/smtp.h
@@ -0,0 +1,128 @@
+#ifndef LWIP_HDR_APPS_SMTP_H
+#define LWIP_HDR_APPS_SMTP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/apps/smtp_opts.h"
+#include "lwip/err.h"
+#include "lwip/prot/iana.h"
+
+/** The default TCP port used for SMTP */
+#define SMTP_DEFAULT_PORT LWIP_IANA_PORT_SMTP
+/** The default TCP port used for SMTPS */
+#define SMTPS_DEFAULT_PORT LWIP_IANA_PORT_SMTPS
+
+/** Email successfully sent */
+#define SMTP_RESULT_OK 0
+/** Unknown error */
+#define SMTP_RESULT_ERR_UNKNOWN 1
+/** Connection to server failed */
+#define SMTP_RESULT_ERR_CONNECT 2
+/** Failed to resolve server hostname */
+#define SMTP_RESULT_ERR_HOSTNAME 3
+/** Connection unexpectedly closed by remote server */
+#define SMTP_RESULT_ERR_CLOSED 4
+/** Connection timed out (server didn't respond in time) */
+#define SMTP_RESULT_ERR_TIMEOUT 5
+/** Server responded with an unknown response code */
+#define SMTP_RESULT_ERR_SVR_RESP 6
+/** Out of resources locally */
+#define SMTP_RESULT_ERR_MEM 7
+
+/** Prototype of an smtp callback function
+ *
+ * @param arg argument specified when initiating the email
+ * @param smtp_result result of the mail transfer (see defines SMTP_RESULT_*)
+ * @param srv_err if aborted by the server, this contains the error code received
+ * @param err an error returned by internal lwip functions, can help to specify
+ * the source of the error but must not necessarily be != ERR_OK
+ */
+typedef void (*smtp_result_fn)(void *arg, u8_t smtp_result, u16_t srv_err, err_t err);
+
+/** This structure is used as argument for smtp_send_mail_int(),
+ * which in turn can be used with tcpip_callback() to send mail
+ * from interrupt context, e.g. like this:
+ * struct smtp_send_request *req; (to be filled)
+ * tcpip_try_callback(smtp_send_mail_int, (void*)req);
+ *
+ * For member description, see parameter description of smtp_send_mail().
+ * When using with tcpip_callback, this structure has to stay allocated
+ * (e.g. using mem_malloc/mem_free) until its 'callback_fn' is called.
+ */
+struct smtp_send_request {
+ const char *from;
+ const char* to;
+ const char* subject;
+ const char* body;
+ smtp_result_fn callback_fn;
+ void* callback_arg;
+ /** If this is != 0, data is *not* copied into an extra buffer
+ * but used from the pointers supplied in this struct.
+ * This means less memory usage, but data must stay untouched until
+ * the callback function is called. */
+ u8_t static_data;
+};
+
+
+#if SMTP_BODYDH
+
+#ifndef SMTP_BODYDH_BUFFER_SIZE
+#define SMTP_BODYDH_BUFFER_SIZE 256
+#endif /* SMTP_BODYDH_BUFFER_SIZE */
+
+struct smtp_bodydh {
+ u16_t state;
+ u16_t length; /* Length of content in buffer */
+ char buffer[SMTP_BODYDH_BUFFER_SIZE]; /* buffer for generated content */
+#ifdef SMTP_BODYDH_USER_SIZE
+ u8_t user[SMTP_BODYDH_USER_SIZE];
+#endif /* SMTP_BODYDH_USER_SIZE */
+};
+
+enum bdh_retvals_e {
+ BDH_DONE = 0,
+ BDH_WORKING
+};
+
+/** Prototype of an smtp body callback function
+ * It receives a struct smtp_bodydh, and a buffer to write data,
+ * must return BDH_WORKING to be called again and BDH_DONE when
+ * it has finished processing. This one tries to fill one TCP buffer with
+ * data, your function will be repeatedly called until that happens; so if you
+ * know you'll be taking too long to serve your request, pause once in a while
+ * by writing length=0 to avoid hogging system resources
+ *
+ * @param arg argument specified when initiating the email
+ * @param smtp_bodydh state handling + buffer structure
+ */
+typedef int (*smtp_bodycback_fn)(void *arg, struct smtp_bodydh *bodydh);
+
+err_t smtp_send_mail_bodycback(const char *from, const char* to, const char* subject,
+ smtp_bodycback_fn bodycback_fn, smtp_result_fn callback_fn, void* callback_arg);
+
+#endif /* SMTP_BODYDH */
+
+
+err_t smtp_set_server_addr(const char* server);
+void smtp_set_server_port(u16_t port);
+#if LWIP_ALTCP && LWIP_ALTCP_TLS
+struct altcp_tls_config;
+void smtp_set_tls_config(struct altcp_tls_config *tls_config);
+#endif
+err_t smtp_set_auth(const char* username, const char* pass);
+err_t smtp_send_mail(const char *from, const char* to, const char* subject, const char* body,
+ smtp_result_fn callback_fn, void* callback_arg);
+err_t smtp_send_mail_static(const char *from, const char* to, const char* subject, const char* body,
+ smtp_result_fn callback_fn, void* callback_arg);
+void smtp_send_mail_int(void *arg);
+#ifdef LWIP_DEBUG
+const char* smtp_result_str(u8_t smtp_result);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SMTP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/smtp_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/smtp_opts.h
new file mode 100644
index 0000000..c588fb9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/smtp_opts.h
@@ -0,0 +1,80 @@
+#ifndef LWIP_HDR_APPS_SMTP_OPTS_H
+#define LWIP_HDR_APPS_SMTP_OPTS_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup smtp_opts Options
+ * @ingroup smtp
+ *
+ * @{
+ */
+
+/** Set this to 1 to enable data handler callback on BODY */
+#ifndef SMTP_BODYDH
+#define SMTP_BODYDH 0
+#endif
+
+/** SMTP_DEBUG: Enable debugging for SNTP. */
+#ifndef SMTP_DEBUG
+#define SMTP_DEBUG LWIP_DBG_OFF
+#endif
+
+/** Maximum length reserved for server name including terminating 0 byte */
+#ifndef SMTP_MAX_SERVERNAME_LEN
+#define SMTP_MAX_SERVERNAME_LEN 256
+#endif
+
+/** Maximum length reserved for username */
+#ifndef SMTP_MAX_USERNAME_LEN
+#define SMTP_MAX_USERNAME_LEN 32
+#endif
+
+/** Maximum length reserved for password */
+#ifndef SMTP_MAX_PASS_LEN
+#define SMTP_MAX_PASS_LEN 32
+#endif
+
+/** Set this to 0 if you know the authentication data will not change
+ * during the smtp session, which saves some heap space. */
+#ifndef SMTP_COPY_AUTHDATA
+#define SMTP_COPY_AUTHDATA 1
+#endif
+
+/** Set this to 0 to save some code space if you know for sure that all data
+ * passed to this module conforms to the requirements in the SMTP RFC.
+ * WARNING: use this with care!
+ */
+#ifndef SMTP_CHECK_DATA
+#define SMTP_CHECK_DATA 1
+#endif
+
+/** Set this to 1 to enable AUTH PLAIN support */
+#ifndef SMTP_SUPPORT_AUTH_PLAIN
+#define SMTP_SUPPORT_AUTH_PLAIN 1
+#endif
+
+/** Set this to 1 to enable AUTH LOGIN support */
+#ifndef SMTP_SUPPORT_AUTH_LOGIN
+#define SMTP_SUPPORT_AUTH_LOGIN 1
+#endif
+
+/* Memory allocation/deallocation can be overridden... */
+#ifndef SMTP_STATE_MALLOC
+#define SMTP_STATE_MALLOC(size) mem_malloc(size)
+#define SMTP_STATE_FREE(ptr) mem_free(ptr)
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SMTP_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp.h
new file mode 100644
index 0000000..ab265b7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp.h
@@ -0,0 +1,135 @@
+/**
+ * @file
+ * SNMP server main API - start and basic configuration
+ */
+
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg
+ * Martin Hentschel
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNMP_H
+#define LWIP_HDR_APPS_SNMP_H
+
+#include "lwip/apps/snmp_opts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/apps/snmp_core.h"
+
+/** SNMP variable binding descriptor (publicly needed for traps) */
+struct snmp_varbind
+{
+ /** pointer to next varbind, NULL for last in list */
+ struct snmp_varbind *next;
+ /** pointer to previous varbind, NULL for first in list */
+ struct snmp_varbind *prev;
+
+ /** object identifier */
+ struct snmp_obj_id oid;
+
+ /** value ASN1 type */
+ u8_t type;
+ /** object value length */
+ u16_t value_len;
+ /** object value */
+ void *value;
+};
+
+/**
+ * @ingroup snmp_core
+ * Agent setup, start listening to port 161.
+ */
+void snmp_init(void);
+void snmp_set_mibs(const struct snmp_mib **mibs, u8_t num_mibs);
+
+void snmp_set_device_enterprise_oid(const struct snmp_obj_id* device_enterprise_oid);
+const struct snmp_obj_id* snmp_get_device_enterprise_oid(void);
+
+void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable);
+void snmp_trap_dst_ip_set(u8_t dst_idx, const ip_addr_t *dst);
+
+/** Generic trap: cold start */
+#define SNMP_GENTRAP_COLDSTART 0
+/** Generic trap: warm start */
+#define SNMP_GENTRAP_WARMSTART 1
+/** Generic trap: link down */
+#define SNMP_GENTRAP_LINKDOWN 2
+/** Generic trap: link up */
+#define SNMP_GENTRAP_LINKUP 3
+/** Generic trap: authentication failure */
+#define SNMP_GENTRAP_AUTH_FAILURE 4
+/** Generic trap: EGP neighbor lost */
+#define SNMP_GENTRAP_EGP_NEIGHBOR_LOSS 5
+/** Generic trap: enterprise specific */
+#define SNMP_GENTRAP_ENTERPRISE_SPECIFIC 6
+
+err_t snmp_send_trap_generic(s32_t generic_trap);
+err_t snmp_send_trap_specific(s32_t specific_trap, struct snmp_varbind *varbinds);
+err_t snmp_send_trap(const struct snmp_obj_id* oid, s32_t generic_trap, s32_t specific_trap, struct snmp_varbind *varbinds);
+
+#define SNMP_AUTH_TRAPS_DISABLED 0
+#define SNMP_AUTH_TRAPS_ENABLED 1
+void snmp_set_auth_traps_enabled(u8_t enable);
+u8_t snmp_get_auth_traps_enabled(void);
+
+u8_t snmp_v1_enabled(void);
+u8_t snmp_v2c_enabled(void);
+u8_t snmp_v3_enabled(void);
+void snmp_v1_enable(u8_t enable);
+void snmp_v2c_enable(u8_t enable);
+void snmp_v3_enable(u8_t enable);
+
+const char * snmp_get_community(void);
+const char * snmp_get_community_write(void);
+const char * snmp_get_community_trap(void);
+void snmp_set_community(const char * const community);
+void snmp_set_community_write(const char * const community);
+void snmp_set_community_trap(const char * const community);
+
+void snmp_coldstart_trap(void);
+void snmp_authfail_trap(void);
+
+typedef void (*snmp_write_callback_fct)(const u32_t* oid, u8_t oid_len, void* callback_arg);
+void snmp_set_write_callback(snmp_write_callback_fct write_callback, void* callback_arg);
+
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNMP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_core.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_core.h
new file mode 100644
index 0000000..5a8a49f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_core.h
@@ -0,0 +1,377 @@
+/**
+ * @file
+ * SNMP core API for implementing MIBs
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons
+ * Martin Hentschel
+ */
+
+#ifndef LWIP_HDR_APPS_SNMP_CORE_H
+#define LWIP_HDR_APPS_SNMP_CORE_H
+
+#include "lwip/apps/snmp_opts.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* basic ASN1 defines */
+#define SNMP_ASN1_CLASS_UNIVERSAL 0x00
+#define SNMP_ASN1_CLASS_APPLICATION 0x40
+#define SNMP_ASN1_CLASS_CONTEXT 0x80
+#define SNMP_ASN1_CLASS_PRIVATE 0xC0
+
+#define SNMP_ASN1_CONTENTTYPE_PRIMITIVE 0x00
+#define SNMP_ASN1_CONTENTTYPE_CONSTRUCTED 0x20
+
+/* universal tags (from ASN.1 spec.) */
+#define SNMP_ASN1_UNIVERSAL_END_OF_CONTENT 0
+#define SNMP_ASN1_UNIVERSAL_INTEGER 2
+#define SNMP_ASN1_UNIVERSAL_OCTET_STRING 4
+#define SNMP_ASN1_UNIVERSAL_NULL 5
+#define SNMP_ASN1_UNIVERSAL_OBJECT_ID 6
+#define SNMP_ASN1_UNIVERSAL_SEQUENCE_OF 16
+
+/* application specific (SNMP) tags (from SNMPv2-SMI) */
+#define SNMP_ASN1_APPLICATION_IPADDR 0 /* [APPLICATION 0] IMPLICIT OCTET STRING (SIZE (4)) */
+#define SNMP_ASN1_APPLICATION_COUNTER 1 /* [APPLICATION 1] IMPLICIT INTEGER (0..4294967295) => u32_t */
+#define SNMP_ASN1_APPLICATION_GAUGE 2 /* [APPLICATION 2] IMPLICIT INTEGER (0..4294967295) => u32_t */
+#define SNMP_ASN1_APPLICATION_TIMETICKS 3 /* [APPLICATION 3] IMPLICIT INTEGER (0..4294967295) => u32_t */
+#define SNMP_ASN1_APPLICATION_OPAQUE 4 /* [APPLICATION 4] IMPLICIT OCTET STRING */
+#define SNMP_ASN1_APPLICATION_COUNTER64 6 /* [APPLICATION 6] IMPLICIT INTEGER (0..18446744073709551615) */
+
+/* context specific (SNMP) tags (from RFC 1905) */
+#define SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE 1
+
+/* full ASN1 type defines */
+#define SNMP_ASN1_TYPE_END_OF_CONTENT (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_END_OF_CONTENT)
+#define SNMP_ASN1_TYPE_INTEGER (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_INTEGER)
+#define SNMP_ASN1_TYPE_OCTET_STRING (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OCTET_STRING)
+#define SNMP_ASN1_TYPE_NULL (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_NULL)
+#define SNMP_ASN1_TYPE_OBJECT_ID (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OBJECT_ID)
+#define SNMP_ASN1_TYPE_SEQUENCE (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_UNIVERSAL_SEQUENCE_OF)
+#define SNMP_ASN1_TYPE_IPADDR (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_IPADDR)
+#define SNMP_ASN1_TYPE_IPADDRESS SNMP_ASN1_TYPE_IPADDR
+#define SNMP_ASN1_TYPE_COUNTER (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER)
+#define SNMP_ASN1_TYPE_COUNTER32 SNMP_ASN1_TYPE_COUNTER
+#define SNMP_ASN1_TYPE_GAUGE (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_GAUGE)
+#define SNMP_ASN1_TYPE_GAUGE32 SNMP_ASN1_TYPE_GAUGE
+#define SNMP_ASN1_TYPE_UNSIGNED32 SNMP_ASN1_TYPE_GAUGE
+#define SNMP_ASN1_TYPE_TIMETICKS (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_TIMETICKS)
+#define SNMP_ASN1_TYPE_OPAQUE (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_OPAQUE)
+#if LWIP_HAVE_INT64
+#define SNMP_ASN1_TYPE_COUNTER64 (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER64)
+#endif
+
+#define SNMP_VARBIND_EXCEPTION_OFFSET 0xF0
+#define SNMP_VARBIND_EXCEPTION_MASK 0x0F
+
+/** error codes predefined by SNMP prot. */
+typedef enum {
+ SNMP_ERR_NOERROR = 0,
+/*
+outdated v1 error codes. do not use anmore!
+#define SNMP_ERR_NOSUCHNAME 2 use SNMP_ERR_NOSUCHINSTANCE instead
+#define SNMP_ERR_BADVALUE 3 use SNMP_ERR_WRONGTYPE,SNMP_ERR_WRONGLENGTH,SNMP_ERR_WRONGENCODING or SNMP_ERR_WRONGVALUE instead
+#define SNMP_ERR_READONLY 4 use SNMP_ERR_NOTWRITABLE instead
+*/
+ SNMP_ERR_GENERROR = 5,
+ SNMP_ERR_NOACCESS = 6,
+ SNMP_ERR_WRONGTYPE = 7,
+ SNMP_ERR_WRONGLENGTH = 8,
+ SNMP_ERR_WRONGENCODING = 9,
+ SNMP_ERR_WRONGVALUE = 10,
+ SNMP_ERR_NOCREATION = 11,
+ SNMP_ERR_INCONSISTENTVALUE = 12,
+ SNMP_ERR_RESOURCEUNAVAILABLE = 13,
+ SNMP_ERR_COMMITFAILED = 14,
+ SNMP_ERR_UNDOFAILED = 15,
+ SNMP_ERR_NOTWRITABLE = 17,
+ SNMP_ERR_INCONSISTENTNAME = 18,
+
+ SNMP_ERR_NOSUCHINSTANCE = SNMP_VARBIND_EXCEPTION_OFFSET + SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE
+} snmp_err_t;
+
+/** internal object identifier representation */
+struct snmp_obj_id
+{
+ u8_t len;
+ u32_t id[SNMP_MAX_OBJ_ID_LEN];
+};
+
+struct snmp_obj_id_const_ref
+{
+ u8_t len;
+ const u32_t* id;
+};
+
+extern const struct snmp_obj_id_const_ref snmp_zero_dot_zero; /* administrative identifier from SNMPv2-SMI */
+
+/** SNMP variant value, used as reference in struct snmp_node_instance and table implementation */
+union snmp_variant_value
+{
+ void* ptr;
+ const void* const_ptr;
+ u32_t u32;
+ s32_t s32;
+#if LWIP_HAVE_INT64
+ u64_t u64;
+#endif
+};
+
+
+/**
+SNMP MIB node types
+ tree node is the only node the stack can process in order to walk the tree,
+ all other nodes are assumed to be leaf nodes.
+ This cannot be an enum because users may want to define their own node types.
+*/
+#define SNMP_NODE_TREE 0x00
+/* predefined leaf node types */
+#define SNMP_NODE_SCALAR 0x01
+#define SNMP_NODE_SCALAR_ARRAY 0x02
+#define SNMP_NODE_TABLE 0x03
+#define SNMP_NODE_THREADSYNC 0x04
+
+/** node "base class" layout, the mandatory fields for a node */
+struct snmp_node
+{
+ /** one out of SNMP_NODE_TREE or any leaf node type (like SNMP_NODE_SCALAR) */
+ u8_t node_type;
+ /** the number assigned to this node which used as part of the full OID */
+ u32_t oid;
+};
+
+/** SNMP node instance access types */
+typedef enum {
+ SNMP_NODE_INSTANCE_ACCESS_READ = 1,
+ SNMP_NODE_INSTANCE_ACCESS_WRITE = 2,
+ SNMP_NODE_INSTANCE_READ_ONLY = SNMP_NODE_INSTANCE_ACCESS_READ,
+ SNMP_NODE_INSTANCE_READ_WRITE = (SNMP_NODE_INSTANCE_ACCESS_READ | SNMP_NODE_INSTANCE_ACCESS_WRITE),
+ SNMP_NODE_INSTANCE_WRITE_ONLY = SNMP_NODE_INSTANCE_ACCESS_WRITE,
+ SNMP_NODE_INSTANCE_NOT_ACCESSIBLE = 0
+} snmp_access_t;
+
+struct snmp_node_instance;
+
+typedef s16_t (*node_instance_get_value_method)(struct snmp_node_instance*, void*);
+typedef snmp_err_t (*node_instance_set_test_method)(struct snmp_node_instance*, u16_t, void*);
+typedef snmp_err_t (*node_instance_set_value_method)(struct snmp_node_instance*, u16_t, void*);
+typedef void (*node_instance_release_method)(struct snmp_node_instance*);
+
+#define SNMP_GET_VALUE_RAW_DATA 0x4000 /* do not use 0x8000 because return value of node_instance_get_value_method is signed16 and 0x8000 would be the signed bit */
+
+/** SNMP node instance */
+struct snmp_node_instance
+{
+ /** prefilled with the node, get_instance() is called on; may be changed by user to any value to pass an arbitrary node between calls to get_instance() and get_value/test_value/set_value */
+ const struct snmp_node* node;
+ /** prefilled with the instance id requested; for get_instance() this is the exact oid requested; for get_next_instance() this is the relative starting point, stack expects relative oid of next node here */
+ struct snmp_obj_id instance_oid;
+
+ /** ASN type for this object (see snmp_asn1.h for definitions) */
+ u8_t asn1_type;
+ /** one out of instance access types defined above (SNMP_NODE_INSTANCE_READ_ONLY,...) */
+ snmp_access_t access;
+
+ /** returns object value for the given object identifier. Return values <0 to indicate an error */
+ node_instance_get_value_method get_value;
+ /** tests length and/or range BEFORE setting */
+ node_instance_set_test_method set_test;
+ /** sets object value, only called when set_test() was successful */
+ node_instance_set_value_method set_value;
+ /** called in any case when the instance is not required anymore by stack (useful for freeing memory allocated in get_instance/get_next_instance methods) */
+ node_instance_release_method release_instance;
+
+ /** reference to pass arbitrary value between calls to get_instance() and get_value/test_value/set_value */
+ union snmp_variant_value reference;
+ /** see reference (if reference is a pointer, the length of underlying data may be stored here or anything else) */
+ u32_t reference_len;
+};
+
+
+/** SNMP tree node */
+struct snmp_tree_node
+{
+ /** inherited "base class" members */
+ struct snmp_node node;
+ u16_t subnode_count;
+ const struct snmp_node* const *subnodes;
+};
+
+#define SNMP_CREATE_TREE_NODE(oid, subnodes) \
+ {{ SNMP_NODE_TREE, (oid) }, \
+ (u16_t)LWIP_ARRAYSIZE(subnodes), (subnodes) }
+
+#define SNMP_CREATE_EMPTY_TREE_NODE(oid) \
+ {{ SNMP_NODE_TREE, (oid) }, \
+ 0, NULL }
+
+/** SNMP leaf node */
+struct snmp_leaf_node
+{
+ /** inherited "base class" members */
+ struct snmp_node node;
+ snmp_err_t (*get_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+ snmp_err_t (*get_next_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+};
+
+/** represents a single mib with its base oid and root node */
+struct snmp_mib
+{
+ const u32_t *base_oid;
+ u8_t base_oid_len;
+ const struct snmp_node *root_node;
+};
+
+#define SNMP_MIB_CREATE(oid_list, root_node) { (oid_list), (u8_t)LWIP_ARRAYSIZE(oid_list), root_node }
+
+/** OID range structure */
+struct snmp_oid_range
+{
+ u32_t min;
+ u32_t max;
+};
+
+/** checks if incoming OID length and values are in allowed ranges */
+u8_t snmp_oid_in_range(const u32_t *oid_in, u8_t oid_len, const struct snmp_oid_range *oid_ranges, u8_t oid_ranges_len);
+
+typedef enum {
+ SNMP_NEXT_OID_STATUS_SUCCESS,
+ SNMP_NEXT_OID_STATUS_NO_MATCH,
+ SNMP_NEXT_OID_STATUS_BUF_TO_SMALL
+} snmp_next_oid_status_t;
+
+/** state for next_oid_init / next_oid_check functions */
+struct snmp_next_oid_state
+{
+ const u32_t* start_oid;
+ u8_t start_oid_len;
+
+ u32_t* next_oid;
+ u8_t next_oid_len;
+ u8_t next_oid_max_len;
+
+ snmp_next_oid_status_t status;
+ void* reference;
+};
+
+void snmp_next_oid_init(struct snmp_next_oid_state *state,
+ const u32_t *start_oid, u8_t start_oid_len,
+ u32_t *next_oid_buf, u8_t next_oid_max_len);
+u8_t snmp_next_oid_precheck(struct snmp_next_oid_state *state, const u32_t *oid, u8_t oid_len);
+u8_t snmp_next_oid_check(struct snmp_next_oid_state *state, const u32_t *oid, u8_t oid_len, void* reference);
+
+void snmp_oid_assign(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len);
+void snmp_oid_combine(struct snmp_obj_id* target, const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len);
+void snmp_oid_prefix(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len);
+void snmp_oid_append(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len);
+u8_t snmp_oid_equal(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len);
+s8_t snmp_oid_compare(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len);
+
+#if LWIP_IPV4
+u8_t snmp_oid_to_ip4(const u32_t *oid, ip4_addr_t *ip);
+void snmp_ip4_to_oid(const ip4_addr_t *ip, u32_t *oid);
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+u8_t snmp_oid_to_ip6(const u32_t *oid, ip6_addr_t *ip);
+void snmp_ip6_to_oid(const ip6_addr_t *ip, u32_t *oid);
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4 || LWIP_IPV6
+u8_t snmp_ip_to_oid(const ip_addr_t *ip, u32_t *oid);
+u8_t snmp_ip_port_to_oid(const ip_addr_t *ip, u16_t port, u32_t *oid);
+
+u8_t snmp_oid_to_ip(const u32_t *oid, u8_t oid_len, ip_addr_t *ip);
+u8_t snmp_oid_to_ip_port(const u32_t *oid, u8_t oid_len, ip_addr_t *ip, u16_t *port);
+#endif /* LWIP_IPV4 || LWIP_IPV6 */
+
+struct netif;
+u8_t netif_to_num(const struct netif *netif);
+
+snmp_err_t snmp_set_test_ok(struct snmp_node_instance* instance, u16_t value_len, void* value); /* generic function which can be used if test is always successful */
+
+err_t snmp_decode_bits(const u8_t *buf, u32_t buf_len, u32_t *bit_value);
+err_t snmp_decode_truthvalue(const s32_t *asn1_value, u8_t *bool_value);
+u8_t snmp_encode_bits(u8_t *buf, u32_t buf_len, u32_t bit_value, u8_t bit_count);
+u8_t snmp_encode_truthvalue(s32_t *asn1_value, u32_t bool_value);
+
+struct snmp_statistics
+{
+ u32_t inpkts;
+ u32_t outpkts;
+ u32_t inbadversions;
+ u32_t inbadcommunitynames;
+ u32_t inbadcommunityuses;
+ u32_t inasnparseerrs;
+ u32_t intoobigs;
+ u32_t innosuchnames;
+ u32_t inbadvalues;
+ u32_t inreadonlys;
+ u32_t ingenerrs;
+ u32_t intotalreqvars;
+ u32_t intotalsetvars;
+ u32_t ingetrequests;
+ u32_t ingetnexts;
+ u32_t insetrequests;
+ u32_t ingetresponses;
+ u32_t intraps;
+ u32_t outtoobigs;
+ u32_t outnosuchnames;
+ u32_t outbadvalues;
+ u32_t outgenerrs;
+ u32_t outgetrequests;
+ u32_t outgetnexts;
+ u32_t outsetrequests;
+ u32_t outgetresponses;
+ u32_t outtraps;
+#if LWIP_SNMP_V3
+ u32_t unsupportedseclevels;
+ u32_t notintimewindows;
+ u32_t unknownusernames;
+ u32_t unknownengineids;
+ u32_t wrongdigests;
+ u32_t decryptionerrors;
+#endif
+};
+
+extern struct snmp_statistics snmp_stats;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* LWIP_HDR_APPS_SNMP_CORE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_mib2.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_mib2.h
new file mode 100644
index 0000000..453e519
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_mib2.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ * SNMP MIB2 API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNMP_MIB2_H
+#define LWIP_HDR_APPS_SNMP_MIB2_H
+
+#include "lwip/apps/snmp_opts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+#if SNMP_LWIP_MIB2
+
+#include "lwip/apps/snmp_core.h"
+
+extern const struct snmp_mib mib2;
+
+#if SNMP_USE_NETCONN
+#include "lwip/apps/snmp_threadsync.h"
+void snmp_mib2_lwip_synchronizer(snmp_threadsync_called_fn fn, void* arg);
+extern struct snmp_threadsync_instance snmp_mib2_lwip_locks;
+#endif
+
+#ifndef SNMP_SYSSERVICES
+#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2))
+#endif
+
+void snmp_mib2_set_sysdescr(const u8_t* str, const u16_t* len); /* read-only be definition */
+void snmp_mib2_set_syscontact(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize);
+void snmp_mib2_set_syscontact_readonly(const u8_t *ocstr, const u16_t *ocstrlen);
+void snmp_mib2_set_sysname(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize);
+void snmp_mib2_set_sysname_readonly(const u8_t *ocstr, const u16_t *ocstrlen);
+void snmp_mib2_set_syslocation(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize);
+void snmp_mib2_set_syslocation_readonly(const u8_t *ocstr, const u16_t *ocstrlen);
+
+#endif /* SNMP_LWIP_MIB2 */
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNMP_MIB2_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_opts.h
new file mode 100644
index 0000000..c892d22
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_opts.h
@@ -0,0 +1,297 @@
+/**
+ * @file
+ * SNMP server options list
+ */
+
+/*
+ * Copyright (c) 2015 Dirk Ziegelmeier
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier
+ *
+ */
+#ifndef LWIP_HDR_SNMP_OPTS_H
+#define LWIP_HDR_SNMP_OPTS_H
+
+#include "lwip/opt.h"
+
+/**
+ * @defgroup snmp_opts Options
+ * @ingroup snmp
+ * @{
+ */
+
+/**
+ * LWIP_SNMP==1: This enables the lwIP SNMP agent. UDP must be available
+ * for SNMP transport.
+ * If you want to use your own SNMP agent, leave this disabled.
+ * To integrate MIB2 of an external agent, you need to enable
+ * LWIP_MIB2_CALLBACKS and MIB2_STATS. This will give you the callbacks
+ * and statistics counters you need to get MIB2 working.
+ */
+#if !defined LWIP_SNMP || defined __DOXYGEN__
+#define LWIP_SNMP 0
+#endif
+
+/**
+ * SNMP_USE_NETCONN: Use netconn API instead of raw API.
+ * Makes SNMP agent run in a worker thread, so blocking operations
+ * can be done in MIB calls.
+ */
+#if !defined SNMP_USE_NETCONN || defined __DOXYGEN__
+#define SNMP_USE_NETCONN 0
+#endif
+
+/**
+ * SNMP_USE_RAW: Use raw API.
+ * SNMP agent does not run in a worker thread, so blocking operations
+ * should not be done in MIB calls.
+ */
+#if !defined SNMP_USE_RAW || defined __DOXYGEN__
+#define SNMP_USE_RAW 1
+#endif
+
+#if SNMP_USE_NETCONN && SNMP_USE_RAW
+#error SNMP stack can use only one of the APIs {raw, netconn}
+#endif
+
+#if LWIP_SNMP && !SNMP_USE_NETCONN && !SNMP_USE_RAW
+#error SNMP stack needs a receive API and UDP {raw, netconn}
+#endif
+
+#if SNMP_USE_NETCONN
+/**
+ * SNMP_STACK_SIZE: Stack size of SNMP netconn worker thread
+ */
+#if !defined SNMP_STACK_SIZE || defined __DOXYGEN__
+#define SNMP_STACK_SIZE DEFAULT_THREAD_STACKSIZE
+#endif
+
+/**
+ * SNMP_THREAD_PRIO: SNMP netconn worker thread priority
+ */
+#if !defined SNMP_THREAD_PRIO || defined __DOXYGEN__
+#define SNMP_THREAD_PRIO DEFAULT_THREAD_PRIO
+#endif
+#endif /* SNMP_USE_NETCONN */
+
+/**
+ * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
+ * destination is required
+ */
+#if !defined SNMP_TRAP_DESTINATIONS || defined __DOXYGEN__
+#define SNMP_TRAP_DESTINATIONS 1
+#endif
+
+/**
+ * Only allow SNMP write actions that are 'safe' (e.g. disabling netifs is not
+ * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
+ * Unsafe requests are disabled by default!
+ */
+#if !defined SNMP_SAFE_REQUESTS || defined __DOXYGEN__
+#define SNMP_SAFE_REQUESTS 1
+#endif
+
+/**
+ * The maximum length of strings used.
+ */
+#if !defined SNMP_MAX_OCTET_STRING_LEN || defined __DOXYGEN__
+#define SNMP_MAX_OCTET_STRING_LEN 127
+#endif
+
+/**
+ * The maximum number of Sub ID's inside an object identifier.
+ * Indirectly this also limits the maximum depth of SNMP tree.
+ */
+#if !defined SNMP_MAX_OBJ_ID_LEN || defined __DOXYGEN__
+#define SNMP_MAX_OBJ_ID_LEN 50
+#endif
+
+#if !defined SNMP_MAX_VALUE_SIZE || defined __DOXYGEN__
+/**
+ * The minimum size of a value.
+ */
+#define SNMP_MIN_VALUE_SIZE (2 * sizeof(u32_t*)) /* size required to store the basic types (8 bytes for counter64) */
+/**
+ * The maximum size of a value.
+ */
+#define SNMP_MAX_VALUE_SIZE LWIP_MAX(LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN), sizeof(u32_t)*(SNMP_MAX_OBJ_ID_LEN)), SNMP_MIN_VALUE_SIZE)
+#endif
+
+/**
+ * The snmp read-access community. Used for write-access and traps, too
+ * unless SNMP_COMMUNITY_WRITE or SNMP_COMMUNITY_TRAP are enabled, respectively.
+ */
+#if !defined SNMP_COMMUNITY || defined __DOXYGEN__
+#define SNMP_COMMUNITY "public"
+#endif
+
+/**
+ * The snmp write-access community.
+ * Set this community to "" in order to disallow any write access.
+ */
+#if !defined SNMP_COMMUNITY_WRITE || defined __DOXYGEN__
+#define SNMP_COMMUNITY_WRITE "private"
+#endif
+
+/**
+ * The snmp community used for sending traps.
+ */
+#if !defined SNMP_COMMUNITY_TRAP || defined __DOXYGEN__
+#define SNMP_COMMUNITY_TRAP "public"
+#endif
+
+/**
+ * The maximum length of community string.
+ * If community names shall be adjusted at runtime via snmp_set_community() calls,
+ * enter here the possible maximum length (+1 for terminating null character).
+ */
+#if !defined SNMP_MAX_COMMUNITY_STR_LEN || defined __DOXYGEN__
+#define SNMP_MAX_COMMUNITY_STR_LEN LWIP_MAX(LWIP_MAX(sizeof(SNMP_COMMUNITY), sizeof(SNMP_COMMUNITY_WRITE)), sizeof(SNMP_COMMUNITY_TRAP))
+#endif
+
+/**
+ * The OID identifiying the device. This may be the enterprise OID itself or any OID located below it in tree.
+ */
+#if !defined SNMP_DEVICE_ENTERPRISE_OID || defined __DOXYGEN__
+#define SNMP_LWIP_ENTERPRISE_OID 26381
+/**
+ * IANA assigned enterprise ID for lwIP is 26381
+ * @see http://www.iana.org/assignments/enterprise-numbers
+ *
+ * @note this enterprise ID is assigned to the lwIP project,
+ * all object identifiers living under this ID are assigned
+ * by the lwIP maintainers!
+ * @note don't change this define, use snmp_set_device_enterprise_oid()
+ *
+ * If you need to create your own private MIB you'll need
+ * to apply for your own enterprise ID with IANA:
+ * http://www.iana.org/numbers.html
+ */
+#define SNMP_DEVICE_ENTERPRISE_OID {1, 3, 6, 1, 4, 1, SNMP_LWIP_ENTERPRISE_OID}
+/**
+ * Length of SNMP_DEVICE_ENTERPRISE_OID
+ */
+#define SNMP_DEVICE_ENTERPRISE_OID_LEN 7
+#endif
+
+/**
+ * SNMP_DEBUG: Enable debugging for SNMP messages.
+ */
+#if !defined SNMP_DEBUG || defined __DOXYGEN__
+#define SNMP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
+ */
+#if !defined SNMP_MIB_DEBUG || defined __DOXYGEN__
+#define SNMP_MIB_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * Indicates if the MIB2 implementation of LWIP SNMP stack is used.
+ */
+#if !defined SNMP_LWIP_MIB2 || defined __DOXYGEN__
+#define SNMP_LWIP_MIB2 LWIP_SNMP
+#endif
+
+/**
+ * Value return for sysDesc field of MIB2.
+ */
+#if !defined SNMP_LWIP_MIB2_SYSDESC || defined __DOXYGEN__
+#define SNMP_LWIP_MIB2_SYSDESC "lwIP"
+#endif
+
+/**
+ * Value return for sysName field of MIB2.
+ * To make sysName field settable, call snmp_mib2_set_sysname() to provide the necessary buffers.
+ */
+#if !defined SNMP_LWIP_MIB2_SYSNAME || defined __DOXYGEN__
+#define SNMP_LWIP_MIB2_SYSNAME "FQDN-unk"
+#endif
+
+/**
+ * Value return for sysContact field of MIB2.
+ * To make sysContact field settable, call snmp_mib2_set_syscontact() to provide the necessary buffers.
+ */
+#if !defined SNMP_LWIP_MIB2_SYSCONTACT || defined __DOXYGEN__
+#define SNMP_LWIP_MIB2_SYSCONTACT ""
+#endif
+
+/**
+ * Value return for sysLocation field of MIB2.
+ * To make sysLocation field settable, call snmp_mib2_set_syslocation() to provide the necessary buffers.
+ */
+#if !defined SNMP_LWIP_MIB2_SYSLOCATION || defined __DOXYGEN__
+#define SNMP_LWIP_MIB2_SYSLOCATION ""
+#endif
+
+/**
+ * This value is used to limit the repetitions processed in GetBulk requests (value == 0 means no limitation).
+ * This may be useful to limit the load for a single request.
+ * According to SNMP RFC 1905 it is allowed to not return all requested variables from a GetBulk request if system load would be too high.
+ * so the effect is that the client will do more requests to gather all data.
+ * For the stack this could be useful in case that SNMP processing is done in TCP/IP thread. In this situation a request with many
+ * repetitions could block the thread for a longer time. Setting limit here will keep the stack more responsive.
+ */
+#if !defined SNMP_LWIP_GETBULK_MAX_REPETITIONS || defined __DOXYGEN__
+#define SNMP_LWIP_GETBULK_MAX_REPETITIONS 0
+#endif
+
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------
+ ---------- SNMPv3 options ----------
+ ------------------------------------
+*/
+
+/**
+ * LWIP_SNMP_V3==1: This enables EXPERIMENTAL SNMPv3 support. LWIP_SNMP must
+ * also be enabled.
+ * THIS IS UNDER DEVELOPMENT AND SHOULD NOT BE ENABLED IN PRODUCTS.
+ */
+#ifndef LWIP_SNMP_V3
+#define LWIP_SNMP_V3 0
+#endif
+
+#ifndef LWIP_SNMP_V3_MBEDTLS
+#define LWIP_SNMP_V3_MBEDTLS LWIP_SNMP_V3
+#endif
+
+#ifndef LWIP_SNMP_V3_CRYPTO
+#define LWIP_SNMP_V3_CRYPTO LWIP_SNMP_V3_MBEDTLS
+#endif
+
+#ifndef LWIP_SNMP_CONFIGURE_VERSIONS
+#define LWIP_SNMP_CONFIGURE_VERSIONS 0
+#endif
+
+#endif /* LWIP_HDR_SNMP_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_scalar.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_scalar.h
new file mode 100644
index 0000000..40a060c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_scalar.h
@@ -0,0 +1,113 @@
+/**
+ * @file
+ * SNMP server MIB API to implement scalar nodes
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Martin Hentschel
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_SNMP_SCALAR_H
+#define LWIP_HDR_APPS_SNMP_SCALAR_H
+
+#include "lwip/apps/snmp_opts.h"
+#include "lwip/apps/snmp_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+/** basic scalar node */
+struct snmp_scalar_node
+{
+ /** inherited "base class" members */
+ struct snmp_leaf_node node;
+ u8_t asn1_type;
+ snmp_access_t access;
+ node_instance_get_value_method get_value;
+ node_instance_set_test_method set_test;
+ node_instance_set_value_method set_value;
+};
+
+
+snmp_err_t snmp_scalar_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+snmp_err_t snmp_scalar_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+
+#define SNMP_SCALAR_CREATE_NODE(oid, access, asn1_type, get_value_method, set_test_method, set_value_method) \
+ {{{ SNMP_NODE_SCALAR, (oid) }, \
+ snmp_scalar_get_instance, \
+ snmp_scalar_get_next_instance }, \
+ (asn1_type), (access), (get_value_method), (set_test_method), (set_value_method) }
+
+#define SNMP_SCALAR_CREATE_NODE_READONLY(oid, asn1_type, get_value_method) SNMP_SCALAR_CREATE_NODE(oid, SNMP_NODE_INSTANCE_READ_ONLY, asn1_type, get_value_method, NULL, NULL)
+
+/** scalar array node - a tree node which contains scalars only as children */
+struct snmp_scalar_array_node_def
+{
+ u32_t oid;
+ u8_t asn1_type;
+ snmp_access_t access;
+};
+
+typedef s16_t (*snmp_scalar_array_get_value_method)(const struct snmp_scalar_array_node_def*, void*);
+typedef snmp_err_t (*snmp_scalar_array_set_test_method)(const struct snmp_scalar_array_node_def*, u16_t, void*);
+typedef snmp_err_t (*snmp_scalar_array_set_value_method)(const struct snmp_scalar_array_node_def*, u16_t, void*);
+
+/** basic scalar array node */
+struct snmp_scalar_array_node
+{
+ /** inherited "base class" members */
+ struct snmp_leaf_node node;
+ u16_t array_node_count;
+ const struct snmp_scalar_array_node_def* array_nodes;
+ snmp_scalar_array_get_value_method get_value;
+ snmp_scalar_array_set_test_method set_test;
+ snmp_scalar_array_set_value_method set_value;
+};
+
+snmp_err_t snmp_scalar_array_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+snmp_err_t snmp_scalar_array_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+
+#define SNMP_SCALAR_CREATE_ARRAY_NODE(oid, array_nodes, get_value_method, set_test_method, set_value_method) \
+ {{{ SNMP_NODE_SCALAR_ARRAY, (oid) }, \
+ snmp_scalar_array_get_instance, \
+ snmp_scalar_array_get_next_instance }, \
+ (u16_t)LWIP_ARRAYSIZE(array_nodes), (array_nodes), (get_value_method), (set_test_method), (set_value_method) }
+
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNMP_SCALAR_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_framework.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_framework.h
new file mode 100644
index 0000000..47409cc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_framework.h
@@ -0,0 +1,32 @@
+/*
+Generated by LwipMibCompiler
+*/
+
+#ifndef LWIP_HDR_APPS_SNMP_FRAMEWORK_MIB_H
+#define LWIP_HDR_APPS_SNMP_FRAMEWORK_MIB_H
+
+#include "lwip/apps/snmp_opts.h"
+#if LWIP_SNMP
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "lwip/apps/snmp_core.h"
+
+extern const struct snmp_obj_id usmNoAuthProtocol;
+extern const struct snmp_obj_id usmHMACMD5AuthProtocol;
+extern const struct snmp_obj_id usmHMACSHAAuthProtocol;
+
+extern const struct snmp_obj_id usmNoPrivProtocol;
+extern const struct snmp_obj_id usmDESPrivProtocol;
+extern const struct snmp_obj_id usmAESPrivProtocol;
+
+extern const struct snmp_mib snmpframeworkmib;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LWIP_SNMP */
+#endif /* LWIP_HDR_APPS_SNMP_FRAMEWORK_MIB_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_usm.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_usm.h
new file mode 100644
index 0000000..88cfcd8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_usm.h
@@ -0,0 +1,24 @@
+/*
+Generated by LwipMibCompiler
+*/
+
+#ifndef LWIP_HDR_APPS_SNMP_USER_BASED_SM_MIB_H
+#define LWIP_HDR_APPS_SNMP_USER_BASED_SM_MIB_H
+
+#include "lwip/apps/snmp_opts.h"
+#if LWIP_SNMP
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "lwip/apps/snmp_core.h"
+
+extern const struct snmp_mib snmpusmmib;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LWIP_SNMP */
+#endif /* LWIP_HDR_APPS_SNMP_USER_BASED_SM_MIB_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_table.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_table.h
new file mode 100644
index 0000000..4988b51
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_table.h
@@ -0,0 +1,134 @@
+/**
+ * @file
+ * SNMP server MIB API to implement table nodes
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Martin Hentschel
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_SNMP_TABLE_H
+#define LWIP_HDR_APPS_SNMP_TABLE_H
+
+#include "lwip/apps/snmp_opts.h"
+#include "lwip/apps/snmp_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+/** default (customizable) read/write table */
+struct snmp_table_col_def
+{
+ u32_t index;
+ u8_t asn1_type;
+ snmp_access_t access;
+};
+
+/** table node */
+struct snmp_table_node
+{
+ /** inherited "base class" members */
+ struct snmp_leaf_node node;
+ u16_t column_count;
+ const struct snmp_table_col_def* columns;
+ snmp_err_t (*get_cell_instance)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, struct snmp_node_instance* cell_instance);
+ snmp_err_t (*get_next_cell_instance)(const u32_t* column, struct snmp_obj_id* row_oid, struct snmp_node_instance* cell_instance);
+ /** returns object value for the given object identifier */
+ node_instance_get_value_method get_value;
+ /** tests length and/or range BEFORE setting */
+ node_instance_set_test_method set_test;
+ /** sets object value, only called when set_test() was successful */
+ node_instance_set_value_method set_value;
+};
+
+snmp_err_t snmp_table_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+snmp_err_t snmp_table_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+
+#define SNMP_TABLE_CREATE(oid, columns, get_cell_instance_method, get_next_cell_instance_method, get_value_method, set_test_method, set_value_method) \
+ {{{ SNMP_NODE_TABLE, (oid) }, \
+ snmp_table_get_instance, \
+ snmp_table_get_next_instance }, \
+ (u16_t)LWIP_ARRAYSIZE(columns), (columns), \
+ (get_cell_instance_method), (get_next_cell_instance_method), \
+ (get_value_method), (set_test_method), (set_value_method)}
+
+#define SNMP_TABLE_GET_COLUMN_FROM_OID(oid) ((oid)[1]) /* first array value is (fixed) row entry (fixed to 1) and 2nd value is column, follow3ed by instance */
+
+
+/** simple read-only table */
+typedef enum {
+ SNMP_VARIANT_VALUE_TYPE_U32,
+ SNMP_VARIANT_VALUE_TYPE_S32,
+ SNMP_VARIANT_VALUE_TYPE_PTR,
+ SNMP_VARIANT_VALUE_TYPE_CONST_PTR
+} snmp_table_column_data_type_t;
+
+struct snmp_table_simple_col_def
+{
+ u32_t index;
+ u8_t asn1_type;
+ snmp_table_column_data_type_t data_type; /* depending of what union member is used to store the value*/
+};
+
+/** simple read-only table node */
+struct snmp_table_simple_node
+{
+ /* inherited "base class" members */
+ struct snmp_leaf_node node;
+ u16_t column_count;
+ const struct snmp_table_simple_col_def* columns;
+ snmp_err_t (*get_cell_value)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len);
+ snmp_err_t (*get_next_cell_instance_and_value)(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len);
+};
+
+snmp_err_t snmp_table_simple_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+snmp_err_t snmp_table_simple_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+
+#define SNMP_TABLE_CREATE_SIMPLE(oid, columns, get_cell_value_method, get_next_cell_instance_and_value_method) \
+ {{{ SNMP_NODE_TABLE, (oid) }, \
+ snmp_table_simple_get_instance, \
+ snmp_table_simple_get_next_instance }, \
+ (u16_t)LWIP_ARRAYSIZE(columns), (columns), (get_cell_value_method), (get_next_cell_instance_and_value_method) }
+
+s16_t snmp_table_extract_value_from_s32ref(struct snmp_node_instance* instance, void* value);
+s16_t snmp_table_extract_value_from_u32ref(struct snmp_node_instance* instance, void* value);
+s16_t snmp_table_extract_value_from_refconstptr(struct snmp_node_instance* instance, void* value);
+
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNMP_TABLE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_threadsync.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_threadsync.h
new file mode 100644
index 0000000..76f1118
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmp_threadsync.h
@@ -0,0 +1,114 @@
+/**
+ * @file
+ * SNMP server MIB API to implement thread synchronization
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_SNMP_THREADSYNC_H
+#define LWIP_HDR_APPS_SNMP_THREADSYNC_H
+
+#include "lwip/apps/snmp_opts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/apps/snmp_core.h"
+#include "lwip/sys.h"
+
+typedef void (*snmp_threadsync_called_fn)(void* arg);
+typedef void (*snmp_threadsync_synchronizer_fn)(snmp_threadsync_called_fn fn, void* arg);
+
+
+/** Thread sync runtime data. For internal usage only. */
+struct threadsync_data
+{
+ union {
+ snmp_err_t err;
+ s16_t s16;
+ } retval;
+ union {
+ const u32_t *root_oid;
+ void *value;
+ } arg1;
+ union {
+ u8_t root_oid_len;
+ u16_t len;
+ } arg2;
+ const struct snmp_threadsync_node *threadsync_node;
+ struct snmp_node_instance proxy_instance;
+};
+
+/** Thread sync instance. Needed EXACTLY once for every thread to be synced into. */
+struct snmp_threadsync_instance
+{
+ sys_sem_t sem;
+ sys_mutex_t sem_usage_mutex;
+ snmp_threadsync_synchronizer_fn sync_fn;
+ struct threadsync_data data;
+};
+
+/** SNMP thread sync proxy leaf node */
+struct snmp_threadsync_node
+{
+ /* inherited "base class" members */
+ struct snmp_leaf_node node;
+
+ const struct snmp_leaf_node *target;
+ struct snmp_threadsync_instance *instance;
+};
+
+snmp_err_t snmp_threadsync_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+snmp_err_t snmp_threadsync_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
+
+/** Create thread sync proxy node */
+#define SNMP_CREATE_THREAD_SYNC_NODE(oid, target_leaf_node, threadsync_instance) \
+ {{{ SNMP_NODE_THREADSYNC, (oid) }, \
+ snmp_threadsync_get_instance, \
+ snmp_threadsync_get_next_instance }, \
+ (target_leaf_node), \
+ (threadsync_instance) }
+
+/** Create thread sync instance data */
+void snmp_threadsync_init(struct snmp_threadsync_instance *instance, snmp_threadsync_synchronizer_fn sync_fn);
+
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNMP_THREADSYNC_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmpv3.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmpv3.h
new file mode 100644
index 0000000..e0dda64
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/snmpv3.h
@@ -0,0 +1,114 @@
+/**
+ * @file
+ * Additional SNMPv3 functionality RFC3414 and RFC3826.
+ */
+
+/*
+ * Copyright (c) 2016 Elias Oenal.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Elias Oenal
+ */
+
+#ifndef LWIP_HDR_APPS_SNMP_V3_H
+#define LWIP_HDR_APPS_SNMP_V3_H
+
+#include "lwip/apps/snmp_opts.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_SNMP && LWIP_SNMP_V3
+
+typedef enum
+{
+ SNMP_V3_AUTH_ALGO_INVAL = 0,
+ SNMP_V3_AUTH_ALGO_MD5 = 1,
+ SNMP_V3_AUTH_ALGO_SHA = 2
+} snmpv3_auth_algo_t;
+
+typedef enum
+{
+ SNMP_V3_PRIV_ALGO_INVAL = 0,
+ SNMP_V3_PRIV_ALGO_DES = 1,
+ SNMP_V3_PRIV_ALGO_AES = 2
+} snmpv3_priv_algo_t;
+
+typedef enum
+{
+ SNMP_V3_USER_STORAGETYPE_OTHER = 1,
+ SNMP_V3_USER_STORAGETYPE_VOLATILE = 2,
+ SNMP_V3_USER_STORAGETYPE_NONVOLATILE = 3,
+ SNMP_V3_USER_STORAGETYPE_PERMANENT = 4,
+ SNMP_V3_USER_STORAGETYPE_READONLY = 5
+} snmpv3_user_storagetype_t;
+
+/*
+ * The following callback functions must be implemented by the application.
+ * There is a dummy implementation in snmpv3_dummy.c.
+ */
+
+void snmpv3_get_engine_id(const char **id, u8_t *len);
+err_t snmpv3_set_engine_id(const char* id, u8_t len);
+
+u32_t snmpv3_get_engine_boots(void);
+void snmpv3_set_engine_boots(u32_t boots);
+
+u32_t snmpv3_get_engine_time(void);
+void snmpv3_reset_engine_time(void);
+
+err_t snmpv3_get_user(const char* username, snmpv3_auth_algo_t *auth_algo, u8_t *auth_key, snmpv3_priv_algo_t *priv_algo, u8_t *priv_key);
+u8_t snmpv3_get_amount_of_users(void);
+err_t snmpv3_get_user_storagetype(const char *username, snmpv3_user_storagetype_t *storagetype);
+err_t snmpv3_get_username(char *username, u8_t index);
+
+/* The following functions are provided by the SNMPv3 agent */
+
+void snmpv3_engine_id_changed(void);
+s32_t snmpv3_get_engine_time_internal(void);
+
+void snmpv3_password_to_key_md5(
+ const u8_t *password, /* IN */
+ size_t passwordlen, /* IN */
+ const u8_t *engineID, /* IN - pointer to snmpEngineID */
+ u8_t engineLength, /* IN - length of snmpEngineID */
+ u8_t *key); /* OUT - pointer to caller 16-octet buffer */
+
+void snmpv3_password_to_key_sha(
+ const u8_t *password, /* IN */
+ size_t passwordlen, /* IN */
+ const u8_t *engineID, /* IN - pointer to snmpEngineID */
+ u8_t engineLength, /* IN - length of snmpEngineID */
+ u8_t *key); /* OUT - pointer to caller 20-octet buffer */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNMP_V3_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/sntp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/sntp.h
new file mode 100644
index 0000000..3c0f95f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/sntp.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ * SNTP client API
+ */
+
+/*
+ * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Frédéric Bernon, Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNTP_H
+#define LWIP_HDR_APPS_SNTP_H
+
+#include "lwip/apps/sntp_opts.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* SNTP operating modes: default is to poll using unicast.
+ The mode has to be set before calling sntp_init(). */
+#define SNTP_OPMODE_POLL 0
+#define SNTP_OPMODE_LISTENONLY 1
+void sntp_setoperatingmode(u8_t operating_mode);
+u8_t sntp_getoperatingmode(void);
+
+void sntp_init(void);
+void sntp_stop(void);
+u8_t sntp_enabled(void);
+
+void sntp_setserver(u8_t idx, const ip_addr_t *addr);
+const ip_addr_t* sntp_getserver(u8_t idx);
+
+#if SNTP_MONITOR_SERVER_REACHABILITY
+u8_t sntp_getreachability(u8_t idx);
+#endif /* SNTP_MONITOR_SERVER_REACHABILITY */
+
+#if SNTP_SERVER_DNS
+void sntp_setservername(u8_t idx, const char *server);
+const char *sntp_getservername(u8_t idx);
+#endif /* SNTP_SERVER_DNS */
+
+#if SNTP_GET_SERVERS_FROM_DHCP
+void sntp_servermode_dhcp(int set_servers_from_dhcp);
+#else /* SNTP_GET_SERVERS_FROM_DHCP */
+#define sntp_servermode_dhcp(x)
+#endif /* SNTP_GET_SERVERS_FROM_DHCP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNTP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/sntp_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/sntp_opts.h
new file mode 100644
index 0000000..ed98040
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/sntp_opts.h
@@ -0,0 +1,209 @@
+/**
+ * @file
+ * SNTP client options list
+ */
+
+/*
+ * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Frédéric Bernon, Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNTP_OPTS_H
+#define LWIP_HDR_APPS_SNTP_OPTS_H
+
+#include "lwip/opt.h"
+#include "lwip/prot/iana.h"
+
+/**
+ * @defgroup sntp_opts Options
+ * @ingroup sntp
+ * @{
+ */
+
+/** SNTP macro to change system time in seconds
+ * Define SNTP_SET_SYSTEM_TIME_US(sec, us) to set the time in microseconds
+ * instead of this one if you need the additional precision. Alternatively,
+ * define SNTP_SET_SYSTEM_TIME_NTP(sec, frac) in order to work with native
+ * NTP timestamps instead.
+ */
+#if !defined SNTP_SET_SYSTEM_TIME || defined __DOXYGEN__
+#define SNTP_SET_SYSTEM_TIME(sec) LWIP_UNUSED_ARG(sec)
+#endif
+
+/** The maximum number of SNTP servers that can be set */
+#if !defined SNTP_MAX_SERVERS || defined __DOXYGEN__
+#define SNTP_MAX_SERVERS LWIP_DHCP_MAX_NTP_SERVERS
+#endif
+
+/** Set this to 1 to implement the callback function called by dhcp when
+ * NTP servers are received. */
+#if !defined SNTP_GET_SERVERS_FROM_DHCP || defined __DOXYGEN__
+#define SNTP_GET_SERVERS_FROM_DHCP LWIP_DHCP_GET_NTP_SRV
+#endif
+
+/** Set this to 1 to support DNS names (or IP address strings) to set sntp servers
+ * One server address/name can be defined as default if SNTP_SERVER_DNS == 1:
+ * \#define SNTP_SERVER_ADDRESS "pool.ntp.org"
+ */
+#if !defined SNTP_SERVER_DNS || defined __DOXYGEN__
+#define SNTP_SERVER_DNS 0
+#endif
+
+/**
+ * SNTP_DEBUG: Enable debugging for SNTP.
+ */
+#if !defined SNTP_DEBUG || defined __DOXYGEN__
+#define SNTP_DEBUG LWIP_DBG_OFF
+#endif
+
+/** SNTP server port */
+#if !defined SNTP_PORT || defined __DOXYGEN__
+#define SNTP_PORT LWIP_IANA_PORT_SNTP
+#endif
+
+/** Sanity check:
+ * Define this to
+ * - 0 to turn off sanity checks (default; smaller code)
+ * - >= 1 to check address and port of the response packet to ensure the
+ * response comes from the server we sent the request to.
+ * - >= 2 to check returned Originate Timestamp against Transmit Timestamp
+ * sent to the server (to ensure response to older request).
+ * - >= 3 @todo: discard reply if any of the VN, Stratum, or Transmit Timestamp
+ * fields is 0 or the Mode field is not 4 (unicast) or 5 (broadcast).
+ * - >= 4 @todo: to check that the Root Delay and Root Dispersion fields are each
+ * greater than or equal to 0 and less than infinity, where infinity is
+ * currently a cozy number like one second. This check avoids using a
+ * server whose synchronization source has expired for a very long time.
+ */
+#if !defined SNTP_CHECK_RESPONSE || defined __DOXYGEN__
+#define SNTP_CHECK_RESPONSE 0
+#endif
+
+/** Enable round-trip delay compensation.
+ * Compensate for the round-trip delay by calculating the clock offset from
+ * the originate, receive, transmit and destination timestamps, as per RFC.
+ *
+ * The calculation requires compiler support for 64-bit integers. Also, either
+ * SNTP_SET_SYSTEM_TIME_US or SNTP_SET_SYSTEM_TIME_NTP has to be implemented
+ * for setting the system clock with sub-second precision. Likewise, either
+ * SNTP_GET_SYSTEM_TIME or SNTP_GET_SYSTEM_TIME_NTP needs to be implemented
+ * with sub-second precision.
+ *
+ * Although not strictly required, it makes sense to combine this option with
+ * SNTP_CHECK_RESPONSE >= 2 for sanity-checking of the received timestamps.
+ * Also, in order for the round-trip calculation to work, the difference
+ * between the local clock and the NTP server clock must not be larger than
+ * about 34 years. If that limit is exceeded, the implementation will fall back
+ * to setting the clock without compensation. In order to ensure that the local
+ * clock is always within the permitted range for compensation, even at first
+ * try, it may be necessary to store at least the current year in non-volatile
+ * memory.
+ */
+#if !defined SNTP_COMP_ROUNDTRIP || defined __DOXYGEN__
+#define SNTP_COMP_ROUNDTRIP 0
+#endif
+
+/** According to the RFC, this shall be a random delay
+ * between 1 and 5 minutes (in milliseconds) to prevent load peaks.
+ * This can be defined to a random generation function,
+ * which must return the delay in milliseconds as u32_t.
+ * Turned off by default.
+ */
+#if !defined SNTP_STARTUP_DELAY || defined __DOXYGEN__
+#ifdef LWIP_RAND
+#define SNTP_STARTUP_DELAY 1
+#else
+#define SNTP_STARTUP_DELAY 0
+#endif
+#endif
+
+/** If you want the startup delay to be a function, define this
+ * to a function (including the brackets) and define SNTP_STARTUP_DELAY to 1.
+ */
+#if !defined SNTP_STARTUP_DELAY_FUNC || defined __DOXYGEN__
+#define SNTP_STARTUP_DELAY_FUNC (LWIP_RAND() % 5000)
+#endif
+
+/** SNTP receive timeout - in milliseconds
+ * Also used as retry timeout - this shouldn't be too low.
+ * Default is 15 seconds. Must not be beolw 15 seconds by specification (i.e. 15000)
+ */
+#if !defined SNTP_RECV_TIMEOUT || defined __DOXYGEN__
+#define SNTP_RECV_TIMEOUT 15000
+#endif
+
+/** SNTP update delay - in milliseconds
+ * Default is 1 hour. Must not be beolw 60 seconds by specification (i.e. 60000)
+ */
+#if !defined SNTP_UPDATE_DELAY || defined __DOXYGEN__
+#define SNTP_UPDATE_DELAY 3600000
+#endif
+
+/** SNTP macro to get system time, used with SNTP_CHECK_RESPONSE >= 2
+ * to send in request and compare in response. Also used for round-trip
+ * delay compensation if SNTP_COMP_ROUNDTRIP != 0.
+ * Alternatively, define SNTP_GET_SYSTEM_TIME_NTP(sec, frac) in order to
+ * work with native NTP timestamps instead.
+ */
+#if !defined SNTP_GET_SYSTEM_TIME || defined __DOXYGEN__
+#define SNTP_GET_SYSTEM_TIME(sec, us) do { (sec) = 0; (us) = 0; } while(0)
+#endif
+
+/** Default retry timeout (in milliseconds) if the response
+ * received is invalid.
+ * This is doubled with each retry until SNTP_RETRY_TIMEOUT_MAX is reached.
+ */
+#if !defined SNTP_RETRY_TIMEOUT || defined __DOXYGEN__
+#define SNTP_RETRY_TIMEOUT SNTP_RECV_TIMEOUT
+#endif
+
+/** Maximum retry timeout (in milliseconds). */
+#if !defined SNTP_RETRY_TIMEOUT_MAX || defined __DOXYGEN__
+#define SNTP_RETRY_TIMEOUT_MAX (SNTP_RETRY_TIMEOUT * 10)
+#endif
+
+/** Increase retry timeout with every retry sent
+ * Default is on to conform to RFC.
+ */
+#if !defined SNTP_RETRY_TIMEOUT_EXP || defined __DOXYGEN__
+#define SNTP_RETRY_TIMEOUT_EXP 1
+#endif
+
+/** Keep a reachability shift register per server
+ * Default is on to conform to RFC.
+ */
+#if !defined SNTP_MONITOR_SERVER_REACHABILITY || defined __DOXYGEN__
+#define SNTP_MONITOR_SERVER_REACHABILITY 1
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_APPS_SNTP_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/tftp_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/tftp_opts.h
new file mode 100644
index 0000000..ec0b631
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/tftp_opts.h
@@ -0,0 +1,106 @@
+/**
+ *
+ * @file tftp_opts.h
+ *
+ * @author Logan Gunthorpe
+ *
+ * @brief Trivial File Transfer Protocol (RFC 1350) implementation options
+ *
+ * Copyright (c) Deltatee Enterprises Ltd. 2013
+ * All rights reserved.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification,are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Logan Gunthorpe
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_TFTP_OPTS_H
+#define LWIP_HDR_APPS_TFTP_OPTS_H
+
+#include "lwip/opt.h"
+#include "lwip/prot/iana.h"
+
+/**
+ * @defgroup tftp_opts Options
+ * @ingroup tftp
+ * @{
+ */
+
+/**
+ * Enable TFTP debug messages
+ */
+#if !defined TFTP_DEBUG || defined __DOXYGEN__
+#define TFTP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TFTP server port
+ */
+#if !defined TFTP_PORT || defined __DOXYGEN__
+#define TFTP_PORT LWIP_IANA_PORT_TFTP
+#endif
+
+/**
+ * TFTP timeout
+ */
+#if !defined TFTP_TIMEOUT_MSECS || defined __DOXYGEN__
+#define TFTP_TIMEOUT_MSECS 10000
+#endif
+
+/**
+ * Max. number of retries when a file is read from server
+ */
+#if !defined TFTP_MAX_RETRIES || defined __DOXYGEN__
+#define TFTP_MAX_RETRIES 5
+#endif
+
+/**
+ * TFTP timer cyclic interval
+ */
+#if !defined TFTP_TIMER_MSECS || defined __DOXYGEN__
+#define TFTP_TIMER_MSECS (TFTP_TIMEOUT_MSECS / 10)
+#endif
+
+/**
+ * Max. length of TFTP filename
+ */
+#if !defined TFTP_MAX_FILENAME_LEN || defined __DOXYGEN__
+#define TFTP_MAX_FILENAME_LEN 20
+#endif
+
+/**
+ * Max. length of TFTP mode
+ */
+#if !defined TFTP_MAX_MODE_LEN || defined __DOXYGEN__
+#define TFTP_MAX_MODE_LEN 7
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_APPS_TFTP_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/tftp_server.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/tftp_server.h
new file mode 100644
index 0000000..efd50a0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/apps/tftp_server.h
@@ -0,0 +1,95 @@
+/**
+ *
+ * @file tftp_server.h
+ *
+ * @author Logan Gunthorpe
+ *
+ * @brief Trivial File Transfer Protocol (RFC 1350)
+ *
+ * Copyright (c) Deltatee Enterprises Ltd. 2013
+ * All rights reserved.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification,are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Logan Gunthorpe
+ *
+ */
+
+#ifndef LWIP_HDR_APPS_TFTP_SERVER_H
+#define LWIP_HDR_APPS_TFTP_SERVER_H
+
+#include "lwip/apps/tftp_opts.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup tftp
+ * TFTP context containing callback functions for TFTP transfers
+ */
+struct tftp_context {
+ /**
+ * Open file for read/write.
+ * @param fname Filename
+ * @param mode Mode string from TFTP RFC 1350 (netascii, octet, mail)
+ * @param write Flag indicating read (0) or write (!= 0) access
+ * @returns File handle supplied to other functions
+ */
+ void* (*open)(const char* fname, const char* mode, u8_t write);
+ /**
+ * Close file handle
+ * @param handle File handle returned by open()
+ */
+ void (*close)(void* handle);
+ /**
+ * Read from file
+ * @param handle File handle returned by open()
+ * @param buf Target buffer to copy read data to
+ * @param bytes Number of bytes to copy to buf
+ * @returns >= 0: Success; < 0: Error
+ */
+ int (*read)(void* handle, void* buf, int bytes);
+ /**
+ * Write to file
+ * @param handle File handle returned by open()
+ * @param pbuf PBUF adjusted such that payload pointer points
+ * to the beginning of write data. In other words,
+ * TFTP headers are stripped off.
+ * @returns >= 0: Success; < 0: Error
+ */
+ int (*write)(void* handle, struct pbuf* p);
+};
+
+err_t tftp_init(const struct tftp_context* ctx);
+void tftp_cleanup(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_TFTP_SERVER_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/arch.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/arch.h
new file mode 100644
index 0000000..7b5cea1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/arch.h
@@ -0,0 +1,393 @@
+/**
+ * @file
+ * Support for different processor and compiler architectures
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_ARCH_H
+#define LWIP_HDR_ARCH_H
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+/**
+ * @defgroup compiler_abstraction Compiler/platform abstraction
+ * @ingroup sys_layer
+ * All defines related to this section must not be placed in lwipopts.h,
+ * but in arch/cc.h!
+ * If the compiler does not provide memset() this file must include a
+ * definition of it, or include a file which defines it.
+ * These options cannot be \#defined in lwipopts.h since they are not options
+ * of lwIP itself, but options of the lwIP port to your system.
+ * @{
+ */
+
+/** Define the byte order of the system.
+ * Needed for conversion of network data to host byte order.
+ * Allowed values: LITTLE_ENDIAN and BIG_ENDIAN
+ */
+#ifndef BYTE_ORDER
+#define BYTE_ORDER LITTLE_ENDIAN
+#endif
+
+/** Define random number generator function of your system */
+#ifdef __DOXYGEN__
+#define LWIP_RAND() ((u32_t)rand())
+#endif
+
+/** Platform specific diagnostic output.\n
+ * Note the default implementation pulls in printf, which may
+ * in turn pull in a lot of standard library code. In resource-constrained
+ * systems, this should be defined to something less resource-consuming.
+ */
+#ifndef LWIP_PLATFORM_DIAG
+#define LWIP_PLATFORM_DIAG(x) do {printf x;} while(0)
+#include
+#include
+#endif
+
+/** Platform specific assertion handling.\n
+ * Note the default implementation pulls in printf, fflush and abort, which may
+ * in turn pull in a lot of standard library code. In resource-constrained
+ * systems, this should be defined to something less resource-consuming.
+ */
+#ifndef LWIP_PLATFORM_ASSERT
+#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \
+ x, __LINE__, __FILE__); fflush(NULL); abort();} while(0)
+#include
+#include
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if you do not want to
+ * include stddef.h header to get size_t. You need to typedef size_t
+ * by yourself in this case.
+ */
+#ifndef LWIP_NO_STDDEF_H
+#define LWIP_NO_STDDEF_H 0
+#endif
+
+#if !LWIP_NO_STDDEF_H
+#include /* for size_t */
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the stdint.h header. You need to typedef the generic types listed in
+ * lwip/arch.h yourself in this case (u8_t, u16_t...).
+ */
+#ifndef LWIP_NO_STDINT_H
+#define LWIP_NO_STDINT_H 0
+#endif
+
+/* Define generic types used in lwIP */
+#if !LWIP_NO_STDINT_H
+#include
+/* stdint.h is C99 which should also provide support for 64-bit integers */
+#if !defined(LWIP_HAVE_INT64) && defined(UINT64_MAX)
+#define LWIP_HAVE_INT64 1
+#endif
+typedef uint8_t u8_t;
+typedef int8_t s8_t;
+typedef uint16_t u16_t;
+typedef int16_t s16_t;
+typedef uint32_t u32_t;
+typedef int32_t s32_t;
+#if LWIP_HAVE_INT64
+typedef uint64_t u64_t;
+typedef int64_t s64_t;
+#endif
+typedef uintptr_t mem_ptr_t;
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the inttypes.h header. You need to define the format strings listed in
+ * lwip/arch.h yourself in this case (X8_F, U16_F...).
+ */
+#ifndef LWIP_NO_INTTYPES_H
+#define LWIP_NO_INTTYPES_H 0
+#endif
+
+/* Define (sn)printf formatters for these lwIP types */
+#if !LWIP_NO_INTTYPES_H
+#include
+#ifndef X8_F
+#define X8_F "02" PRIx8
+#endif
+#ifndef U16_F
+#define U16_F PRIu16
+#endif
+#ifndef S16_F
+#define S16_F PRId16
+#endif
+#ifndef X16_F
+#define X16_F PRIx16
+#endif
+#ifndef U32_F
+#define U32_F PRIu32
+#endif
+#ifndef S32_F
+#define S32_F PRId32
+#endif
+#ifndef X32_F
+#define X32_F PRIx32
+#endif
+#ifndef SZT_F
+#define SZT_F PRIuPTR
+#endif
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the limits.h header. You need to define the type limits yourself in this case
+ * (e.g. INT_MAX, SSIZE_MAX).
+ */
+#ifndef LWIP_NO_LIMITS_H
+#define LWIP_NO_LIMITS_H 0
+#endif
+
+/* Include limits.h? */
+#if !LWIP_NO_LIMITS_H
+#include
+#endif
+
+/* Do we need to define ssize_t? This is a compatibility hack:
+ * Unfortunately, this type seems to be unavailable on some systems (even if
+ * sys/types or unistd.h are available).
+ * Being like that, we define it to 'int' if SSIZE_MAX is not defined.
+ */
+#ifdef SSIZE_MAX
+/* If SSIZE_MAX is defined, unistd.h should provide the type as well */
+#ifndef LWIP_NO_UNISTD_H
+#define LWIP_NO_UNISTD_H 0
+#endif
+#if !LWIP_NO_UNISTD_H
+#include
+#endif
+#else /* SSIZE_MAX */
+//typedef int ssize_t;
+#define SSIZE_MAX LONG_MAX
+#endif /* SSIZE_MAX */
+
+/* some maximum values needed in lwip code */
+#define LWIP_UINT32_MAX 0xffffffff
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the ctype.h header. If ctype.h is available, a few character functions
+ * are mapped to the appropriate functions (lwip_islower, lwip_isdigit...), if
+ * not, a private implementation is provided.
+ */
+#ifndef LWIP_NO_CTYPE_H
+#define LWIP_NO_CTYPE_H 0
+#endif
+
+#if LWIP_NO_CTYPE_H
+#define lwip_in_range(c, lo, up) ((u8_t)(c) >= (lo) && (u8_t)(c) <= (up))
+#define lwip_isdigit(c) lwip_in_range((c), '0', '9')
+#define lwip_isxdigit(c) (lwip_isdigit(c) || lwip_in_range((c), 'a', 'f') || lwip_in_range((c), 'A', 'F'))
+#define lwip_islower(c) lwip_in_range((c), 'a', 'z')
+#define lwip_isspace(c) ((c) == ' ' || (c) == '\f' || (c) == '\n' || (c) == '\r' || (c) == '\t' || (c) == '\v')
+#define lwip_isupper(c) lwip_in_range((c), 'A', 'Z')
+#define lwip_tolower(c) (lwip_isupper(c) ? (c) - 'A' + 'a' : c)
+#define lwip_toupper(c) (lwip_islower(c) ? (c) - 'a' + 'A' : c)
+#else
+#include
+#define lwip_isdigit(c) isdigit((unsigned char)(c))
+#define lwip_isxdigit(c) isxdigit((unsigned char)(c))
+#define lwip_islower(c) islower((unsigned char)(c))
+#define lwip_isspace(c) isspace((unsigned char)(c))
+#define lwip_isupper(c) isupper((unsigned char)(c))
+#define lwip_tolower(c) tolower((unsigned char)(c))
+#define lwip_toupper(c) toupper((unsigned char)(c))
+#endif
+
+/** C++ const_cast(val) equivalent to remove constness from a value (GCC -Wcast-qual) */
+#ifndef LWIP_CONST_CAST
+#define LWIP_CONST_CAST(target_type, val) ((target_type)((ptrdiff_t)val))
+#endif
+
+/** Get rid of alignment cast warnings (GCC -Wcast-align) */
+#ifndef LWIP_ALIGNMENT_CAST
+#define LWIP_ALIGNMENT_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
+#endif
+
+/** Get rid of warnings related to pointer-to-numeric and vice-versa casts,
+ * e.g. "conversion from 'u8_t' to 'void *' of greater size"
+ */
+#ifndef LWIP_PTR_NUMERIC_CAST
+#define LWIP_PTR_NUMERIC_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
+#endif
+
+/** Avoid warnings/errors related to implicitly casting away packed attributes by doing a explicit cast */
+#ifndef LWIP_PACKED_CAST
+#define LWIP_PACKED_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
+#endif
+
+/** Allocates a memory buffer of specified size that is of sufficient size to align
+ * its start address using LWIP_MEM_ALIGN.
+ * You can declare your own version here e.g. to enforce alignment without adding
+ * trailing padding bytes (see LWIP_MEM_ALIGN_BUFFER) or your own section placement
+ * requirements.\n
+ * e.g. if you use gcc and need 32 bit alignment:\n
+ * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[size] \_\_attribute\_\_((aligned(4)))\n
+ * or more portable:\n
+ * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u32_t variable_name[(size + sizeof(u32_t) - 1) / sizeof(u32_t)]
+ */
+#ifndef LWIP_DECLARE_MEMORY_ALIGNED
+#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[LWIP_MEM_ALIGN_BUFFER(size)]
+#endif
+
+/** Calculate memory size for an aligned buffer - returns the next highest
+ * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and
+ * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4).
+ */
+#ifndef LWIP_MEM_ALIGN_SIZE
+#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1U) & ~(MEM_ALIGNMENT-1U))
+#endif
+
+/** Calculate safe memory size for an aligned buffer when using an unaligned
+ * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the
+ * start (e.g. if buffer is u8_t[] and actual data will be u32_t*)
+ */
+#ifndef LWIP_MEM_ALIGN_BUFFER
+#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1U))
+#endif
+
+/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT
+ * so that ADDR % MEM_ALIGNMENT == 0
+ */
+#ifndef LWIP_MEM_ALIGN
+#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Packed structs support.
+ * Placed BEFORE declaration of a packed struct.\n
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+/** Packed structs support.
+ * Placed AFTER declaration of a packed struct.\n
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+/** Packed structs support.
+ * Placed between end of declaration of a packed struct and trailing semicolon.\n
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifndef PACK_STRUCT_STRUCT
+#if defined(__GNUC__) || defined(__clang__)
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#else
+#define PACK_STRUCT_STRUCT
+#endif
+#endif /* PACK_STRUCT_STRUCT */
+
+/** Packed structs support.
+ * Wraps u32_t and u16_t members.\n
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+/** Packed structs support.
+ * Wraps u8_t members, where some compilers warn that packing is not necessary.\n
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifndef PACK_STRUCT_FLD_8
+#define PACK_STRUCT_FLD_8(x) PACK_STRUCT_FIELD(x)
+#endif /* PACK_STRUCT_FLD_8 */
+
+/** Packed structs support.
+ * Wraps members that are packed structs themselves, where some compilers warn that packing is not necessary.\n
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifndef PACK_STRUCT_FLD_S
+#define PACK_STRUCT_FLD_S(x) PACK_STRUCT_FIELD(x)
+#endif /* PACK_STRUCT_FLD_S */
+
+/** PACK_STRUCT_USE_INCLUDES==1: Packed structs support using \#include files before and after struct to be packed.\n
+ * The file included BEFORE the struct is "arch/bpstruct.h".\n
+ * The file included AFTER the struct is "arch/epstruct.h".\n
+ * This can be used to implement struct packing on MS Visual C compilers, see
+ * the Win32 port in the lwIP contrib repository for reference.
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifdef __DOXYGEN__
+#define PACK_STRUCT_USE_INCLUDES
+#endif
+
+/** Eliminates compiler warning about unused arguments (GCC -Wextra -Wunused). */
+#ifndef LWIP_UNUSED_ARG
+#define LWIP_UNUSED_ARG(x) (void)x
+#endif /* LWIP_UNUSED_ARG */
+
+/** LWIP_PROVIDE_ERRNO==1: Let lwIP provide ERRNO values and the 'errno' variable.
+ * If this is disabled, cc.h must either define 'errno', include ,
+ * define LWIP_ERRNO_STDINCLUDE to get included or
+ * define LWIP_ERRNO_INCLUDE to or equivalent.
+ */
+#if defined __DOXYGEN__
+#define LWIP_PROVIDE_ERRNO
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ARCH_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/autoip.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/autoip.h
new file mode 100644
index 0000000..1d85bcc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/autoip.h
@@ -0,0 +1,99 @@
+/**
+ * @file
+ *
+ * AutoIP Automatic LinkLocal IP Configuration
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ */
+
+#ifndef LWIP_HDR_AUTOIP_H
+#define LWIP_HDR_AUTOIP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+/* #include "lwip/udp.h" */
+#include "lwip/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AutoIP Timing */
+#define AUTOIP_TMR_INTERVAL 100
+#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
+
+/** AutoIP state information per netif */
+struct autoip
+{
+ /** the currently selected, probed, announced or used LL IP-Address */
+ ip4_addr_t llipaddr;
+ /** current AutoIP state machine state */
+ u8_t state;
+ /** sent number of probes or announces, dependent on state */
+ u8_t sent_num;
+ /** ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
+ u16_t ttw;
+ /** ticks until a conflict can be solved by defending */
+ u8_t lastconflict;
+ /** total number of probed/used Link Local IP-Addresses */
+ u8_t tried_llipaddr;
+};
+
+
+void autoip_set_struct(struct netif *netif, struct autoip *autoip);
+/** Remove a struct autoip previously set to the netif using autoip_set_struct() */
+#define autoip_remove_struct(netif) do { (netif)->autoip = NULL; } while (0)
+err_t autoip_start(struct netif *netif);
+err_t autoip_stop(struct netif *netif);
+void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
+void autoip_tmr(void);
+void autoip_network_changed(struct netif *netif);
+u8_t autoip_supplied_address(const struct netif *netif);
+
+/* for lwIP internal use by ip4.c */
+u8_t autoip_accept_packet(struct netif *netif, const ip4_addr_t *addr);
+
+#define netif_autoip_data(netif) ((struct autoip*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_AUTOIP */
+
+#endif /* LWIP_HDR_AUTOIP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/debug.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/debug.h
new file mode 100644
index 0000000..baa6a40
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/debug.h
@@ -0,0 +1,161 @@
+/**
+ * @file
+ * Debug messages infrastructure
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_DEBUG_H
+#define LWIP_HDR_DEBUG_H
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+
+/**
+ * @defgroup debugging_levels LWIP_DBG_MIN_LEVEL and LWIP_DBG_TYPES_ON values
+ * @ingroup lwip_opts_debugmsg
+ * @{
+ */
+
+/** @name Debug level (LWIP_DBG_MIN_LEVEL)
+ * @{
+ */
+/** Debug level: ALL messages*/
+#define LWIP_DBG_LEVEL_ALL 0x00
+/** Debug level: Warnings. bad checksums, dropped packets, ... */
+#define LWIP_DBG_LEVEL_WARNING 0x01
+/** Debug level: Serious. memory allocation failures, ... */
+#define LWIP_DBG_LEVEL_SERIOUS 0x02
+/** Debug level: Severe */
+#define LWIP_DBG_LEVEL_SEVERE 0x03
+/**
+ * @}
+ */
+
+#define LWIP_DBG_MASK_LEVEL 0x03
+/* compatibility define only */
+#define LWIP_DBG_LEVEL_OFF LWIP_DBG_LEVEL_ALL
+
+/** @name Enable/disable debug messages completely (LWIP_DBG_TYPES_ON)
+ * @{
+ */
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define LWIP_DBG_ON 0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define LWIP_DBG_OFF 0x00U
+/**
+ * @}
+ */
+
+/** @name Debug message types (LWIP_DBG_TYPES_ON)
+ * @{
+ */
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define LWIP_DBG_TRACE 0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define LWIP_DBG_STATE 0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define LWIP_DBG_FRESH 0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define LWIP_DBG_HALT 0x08U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_assertions Assertion handling
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_NOASSERT: Disable LWIP_ASSERT checks:
+ * To disable assertions define LWIP_NOASSERT in arch/cc.h.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_NOASSERT
+#undef LWIP_NOASSERT
+#endif
+/**
+ * @}
+ */
+
+#ifndef LWIP_NOASSERT
+#define LWIP_ASSERT(message, assertion) do { if (!(assertion)) { \
+ LWIP_PLATFORM_ASSERT(message); }} while(0)
+#else /* LWIP_NOASSERT */
+#define LWIP_ASSERT(message, assertion)
+#endif /* LWIP_NOASSERT */
+
+#ifndef LWIP_ERROR
+#ifndef LWIP_NOASSERT
+#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_ASSERT(message)
+#elif defined LWIP_DEBUG
+#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_DIAG((message))
+#else
+#define LWIP_PLATFORM_ERROR(message)
+#endif
+
+/* if "expression" isn't true, then print "message" and execute "handler" expression */
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+ LWIP_PLATFORM_ERROR(message); handler;}} while(0)
+#endif /* LWIP_ERROR */
+
+/** Enable debug message printing, but only if debug message type is enabled
+ * AND is of correct type AND is at least LWIP_DBG_LEVEL.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_DEBUG
+#undef LWIP_DEBUG
+#endif
+
+#ifdef LWIP_DEBUG
+#define LWIP_DEBUGF(debug, message) do { \
+ if ( \
+ ((debug) & LWIP_DBG_ON) && \
+ ((debug) & LWIP_DBG_TYPES_ON) && \
+ ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \
+ LWIP_PLATFORM_DIAG(message); \
+ if ((debug) & LWIP_DBG_HALT) { \
+ while(1); \
+ } \
+ } \
+ } while(0)
+
+#else /* LWIP_DEBUG */
+#define LWIP_DEBUGF(debug, message)
+#endif /* LWIP_DEBUG */
+
+#endif /* LWIP_HDR_DEBUG_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/def.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/def.h
new file mode 100644
index 0000000..dfb266d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/def.h
@@ -0,0 +1,152 @@
+/**
+ * @file
+ * various utility macros
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+/**
+ * @defgroup perf Performance measurement
+ * @ingroup sys_layer
+ * All defines related to this section must not be placed in lwipopts.h,
+ * but in arch/perf.h!
+ * Measurement calls made throughout lwip, these can be defined to nothing.
+ * - PERF_START: start measuring something.
+ * - PERF_STOP(x): stop measuring something, and record the result.
+ */
+
+#ifndef LWIP_HDR_DEF_H
+#define LWIP_HDR_DEF_H
+
+/* arch.h might define NULL already */
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#if LWIP_PERF
+#include "arch/perf.h"
+#else /* LWIP_PERF */
+#define PERF_START /* null definition */
+#define PERF_STOP(x) /* null definition */
+#endif /* LWIP_PERF */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LWIP_MAX(x , y) (((x) > (y)) ? (x) : (y))
+#define LWIP_MIN(x , y) (((x) < (y)) ? (x) : (y))
+
+/* Get the number of entries in an array ('x' must NOT be a pointer!) */
+#define LWIP_ARRAYSIZE(x) (sizeof(x)/sizeof((x)[0]))
+
+/** Create u32_t value from bytes */
+#define LWIP_MAKEU32(a,b,c,d) (((u32_t)((a) & 0xff) << 24) | \
+ ((u32_t)((b) & 0xff) << 16) | \
+ ((u32_t)((c) & 0xff) << 8) | \
+ (u32_t)((d) & 0xff))
+
+#ifndef NULL
+#ifdef __cplusplus
+#define NULL 0
+#else
+#define NULL ((void *)0)
+#endif
+#endif
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define lwip_htons(x) ((u16_t)(x))
+#define lwip_ntohs(x) ((u16_t)(x))
+#define lwip_htonl(x) ((u32_t)(x))
+#define lwip_ntohl(x) ((u32_t)(x))
+#define PP_HTONS(x) ((u16_t)(x))
+#define PP_NTOHS(x) ((u16_t)(x))
+#define PP_HTONL(x) ((u32_t)(x))
+#define PP_NTOHL(x) ((u32_t)(x))
+#else /* BYTE_ORDER != BIG_ENDIAN */
+#ifndef lwip_htons
+u16_t lwip_htons(u16_t x);
+#endif
+#define lwip_ntohs(x) lwip_htons(x)
+
+#ifndef lwip_htonl
+u32_t lwip_htonl(u32_t x);
+#endif
+#define lwip_ntohl(x) lwip_htonl(x)
+
+/* These macros should be calculated by the preprocessor and are used
+ with compile-time constants only (so that there is no little-endian
+ overhead at runtime). */
+#define PP_HTONS(x) ((u16_t)((((x) & (u16_t)0x00ffU) << 8) | (((x) & (u16_t)0xff00U) >> 8)))
+#define PP_NTOHS(x) PP_HTONS(x)
+#define PP_HTONL(x) ((((x) & (u32_t)0x000000ffUL) << 24) | \
+ (((x) & (u32_t)0x0000ff00UL) << 8) | \
+ (((x) & (u32_t)0x00ff0000UL) >> 8) | \
+ (((x) & (u32_t)0xff000000UL) >> 24))
+#define PP_NTOHL(x) PP_HTONL(x)
+#endif /* BYTE_ORDER == BIG_ENDIAN */
+
+/* Provide usual function names as macros for users, but this can be turned off */
+#ifndef LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS
+#define htons(x) lwip_htons(x)
+#define ntohs(x) lwip_ntohs(x)
+#define htonl(x) lwip_htonl(x)
+#define ntohl(x) lwip_ntohl(x)
+#endif
+
+/* Functions that are not available as standard implementations.
+ * In cc.h, you can #define these to implementations available on
+ * your platform to save some code bytes if you use these functions
+ * in your application, too.
+ */
+
+#ifndef lwip_itoa
+/* This can be #defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform */
+void lwip_itoa(char* result, size_t bufsize, int number);
+#endif
+#ifndef lwip_strnicmp
+/* This can be #defined to strnicmp() or strncasecmp() depending on your platform */
+int lwip_strnicmp(const char* str1, const char* str2, size_t len);
+#endif
+#ifndef lwip_stricmp
+/* This can be #defined to stricmp() or strcasecmp() depending on your platform */
+int lwip_stricmp(const char* str1, const char* str2);
+#endif
+#ifndef lwip_strnstr
+/* This can be #defined to strnstr() depending on your platform */
+char* lwip_strnstr(const char* buffer, const char* token, size_t n);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_DEF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dhcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dhcp.h
new file mode 100644
index 0000000..c78aa0b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dhcp.h
@@ -0,0 +1,139 @@
+/**
+ * @file
+ * DHCP client API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Leon Woestenberg
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg
+ *
+ */
+#ifndef LWIP_HDR_DHCP_H
+#define LWIP_HDR_DHCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60
+/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL)
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500
+
+#define DHCP_BOOT_FILE_LEN 128U
+
+/* AutoIP cooperation flags (struct dhcp.autoip_coop_state) */
+typedef enum {
+ DHCP_AUTOIP_COOP_STATE_OFF = 0,
+ DHCP_AUTOIP_COOP_STATE_ON = 1
+} dhcp_autoip_coop_state_enum_t;
+
+struct dhcp
+{
+ /** transaction identifier of last sent request */
+ u32_t xid;
+ /** track PCB allocation state */
+ u8_t pcb_allocated;
+ /** current DHCP state machine state */
+ u8_t state;
+ /** retries of current request */
+ u8_t tries;
+#if LWIP_DHCP_AUTOIP_COOP
+ u8_t autoip_coop_state;
+#endif
+ u8_t subnet_mask_given;
+
+ u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+ u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+ u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+ u16_t t1_renew_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */
+ u16_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */
+ u16_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */
+ u16_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */
+ ip_addr_t server_ip_addr; /* dhcp server address that offered this lease (ip_addr_t because passed to UDP) */
+ ip4_addr_t offered_ip_addr;
+ ip4_addr_t offered_sn_mask;
+ ip4_addr_t offered_gw_addr;
+
+ u32_t offered_t0_lease; /* lease period (in seconds) */
+ u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+ u32_t offered_t2_rebind; /* recommended rebind time (usually 87.5 of lease period) */
+#if LWIP_DHCP_BOOTP_FILE
+ ip4_addr_t offered_si_addr;
+ char boot_file_name[DHCP_BOOT_FILE_LEN];
+#endif /* LWIP_DHCP_BOOTPFILE */
+};
+
+
+void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp);
+/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */
+#define dhcp_remove_struct(netif) netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, NULL)
+void dhcp_cleanup(struct netif *netif);
+err_t dhcp_start(struct netif *netif);
+err_t dhcp_renew(struct netif *netif);
+err_t dhcp_release(struct netif *netif);
+void dhcp_stop(struct netif *netif);
+void dhcp_release_and_stop(struct netif *netif);
+void dhcp_inform(struct netif *netif);
+void dhcp_network_changed(struct netif *netif);
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr);
+#endif
+u8_t dhcp_supplied_address(const struct netif *netif);
+/* to be called every minute */
+void dhcp_coarse_tmr(void);
+/* to be called every half second */
+void dhcp_fine_tmr(void);
+
+#if LWIP_DHCP_GET_NTP_SRV
+/** This function must exist, in other to add offered NTP servers to
+ * the NTP (or SNTP) engine.
+ * See LWIP_DHCP_MAX_NTP_SERVERS */
+extern void dhcp_set_ntp_servers(u8_t num_ntp_servers, const ip4_addr_t* ntp_server_addrs);
+#endif /* LWIP_DHCP_GET_NTP_SRV */
+
+#define netif_dhcp_data(netif) ((struct dhcp*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DHCP */
+
+#endif /*LWIP_HDR_DHCP_H*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dhcp6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dhcp6.h
new file mode 100644
index 0000000..5cc4a01
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dhcp6.h
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * DHCPv6 client: IPv6 address autoconfiguration as per
+ * RFC 3315 (stateful DHCPv6) and
+ * RFC 3736 (stateless DHCPv6).
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ */
+
+#ifndef LWIP_HDR_IP6_DHCP6_H
+#define LWIP_HDR_IP6_DHCP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6_DHCP6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in milliseconds) of the application calling dhcp6_tmr() */
+#define DHCP6_TIMER_MSECS 500
+
+struct dhcp6
+{
+ /** transaction identifier of last sent request */
+ u32_t xid;
+ /** track PCB allocation state */
+ u8_t pcb_allocated;
+ /** current DHCPv6 state machine state */
+ u8_t state;
+ /** retries of current request */
+ u8_t tries;
+ /** if request config is triggered while another action is active, this keeps track of it */
+ u8_t request_config_pending;
+ /** #ticks with period DHCP6_TIMER_MSECS for request timeout */
+ u16_t request_timeout;
+#if LWIP_IPV6_DHCP6_STATEFUL
+ /* @todo: add more members here to keep track of stateful DHCPv6 data, like lease times */
+#endif /* LWIP_IPV6_DHCP6_STATEFUL */
+};
+
+void dhcp6_set_struct(struct netif *netif, struct dhcp6 *dhcp6);
+/** Remove a struct dhcp6 previously set to the netif using dhcp6_set_struct() */
+#define dhcp6_remove_struct(netif) netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, NULL)
+void dhcp6_cleanup(struct netif *netif);
+
+err_t dhcp6_enable_stateful(struct netif *netif);
+err_t dhcp6_enable_stateless(struct netif *netif);
+void dhcp6_disable(struct netif *netif);
+
+void dhcp6_tmr(void);
+
+void dhcp6_nd6_ra_trigger(struct netif *netif, u8_t managed_addr_config, u8_t other_config);
+
+#if LWIP_DHCP6_GET_NTP_SRV
+/** This function must exist, in other to add offered NTP servers to
+ * the NTP (or SNTP) engine.
+ * See LWIP_DHCP6_MAX_NTP_SERVERS */
+extern void dhcp6_set_ntp_servers(u8_t num_ntp_servers, const ip_addr_t* ntp_server_addrs);
+#endif /* LWIP_DHCP6_GET_NTP_SRV */
+
+#define netif_dhcp6_data(netif) ((struct dhcp6*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6_DHCP6 */
+
+#endif /* LWIP_HDR_IP6_DHCP6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dns.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dns.h
new file mode 100644
index 0000000..0913415
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/dns.h
@@ -0,0 +1,131 @@
+/**
+ * @file
+ * DNS API
+ */
+
+/**
+ * lwip DNS resolver header file.
+
+ * Author: Jim Pettinato
+ * April 2007
+
+ * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LWIP_HDR_DNS_H
+#define LWIP_HDR_DNS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DNS timer period */
+#define DNS_TMR_INTERVAL 1000
+
+/* DNS resolve types: */
+#define LWIP_DNS_ADDRTYPE_IPV4 0
+#define LWIP_DNS_ADDRTYPE_IPV6 1
+#define LWIP_DNS_ADDRTYPE_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
+#define LWIP_DNS_ADDRTYPE_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
+#if LWIP_IPV4 && LWIP_IPV6
+#ifndef LWIP_DNS_ADDRTYPE_DEFAULT
+#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV4_IPV6
+#endif
+#elif LWIP_IPV4
+#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV4
+#else
+#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV6
+#endif
+
+#if DNS_LOCAL_HOSTLIST
+/** struct used for local host-list */
+struct local_hostlist_entry {
+ /** static hostname */
+ const char *name;
+ /** static host address in network byteorder */
+ ip_addr_t addr;
+ struct local_hostlist_entry *next;
+};
+#define DNS_LOCAL_HOSTLIST_ELEM(name, addr_init) {name, addr_init, NULL}
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN
+#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN DNS_MAX_NAME_LENGTH
+#endif
+#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1))
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+#endif /* DNS_LOCAL_HOSTLIST */
+
+#if LWIP_IPV4
+extern const ip_addr_t dns_mquery_v4group;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+extern const ip_addr_t dns_mquery_v6group;
+#endif /* LWIP_IPV6 */
+
+/** Callback which is invoked when a hostname is found.
+ * A function of this type must be implemented by the application using the DNS resolver.
+ * @param name pointer to the name that was looked up.
+ * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname,
+ * or NULL if the name could not be found (or on any other error).
+ * @param callback_arg a user-specified callback argument passed to dns_gethostbyname
+*/
+typedef void (*dns_found_callback)(const char *name, const ip_addr_t *ipaddr, void *callback_arg);
+
+void dns_init(void);
+void dns_tmr(void);
+void dns_setserver(u8_t numdns, const ip_addr_t *dnsserver);
+const ip_addr_t* dns_getserver(u8_t numdns);
+err_t dns_gethostbyname(const char *hostname, ip_addr_t *addr,
+ dns_found_callback found, void *callback_arg);
+err_t dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr,
+ dns_found_callback found, void *callback_arg,
+ u8_t dns_addrtype);
+
+
+#if DNS_LOCAL_HOSTLIST
+size_t dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg);
+err_t dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype);
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+int dns_local_removehost(const char *hostname, const ip_addr_t *addr);
+err_t dns_local_addhost(const char *hostname, const ip_addr_t *addr);
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+#endif /* DNS_LOCAL_HOSTLIST */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS */
+
+#endif /* LWIP_HDR_DNS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/err.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/err.h
new file mode 100644
index 0000000..887d9b3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/err.h
@@ -0,0 +1,117 @@
+/**
+ * @file
+ * lwIP Error codes
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_ERR_H
+#define LWIP_HDR_ERR_H
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup infrastructure_errors Error codes
+ * @ingroup infrastructure
+ * @{
+ */
+
+/** Definitions for error constants. */
+typedef enum {
+/** No error, everything OK. */
+ ERR_OK = 0,
+/** Out of memory error. */
+ ERR_MEM = -1,
+/** Buffer error. */
+ ERR_BUF = -2,
+/** Timeout. */
+ ERR_TIMEOUT = -3,
+/** Routing problem. */
+ ERR_RTE = -4,
+/** Operation in progress */
+ ERR_INPROGRESS = -5,
+/** Illegal value. */
+ ERR_VAL = -6,
+/** Operation would block. */
+ ERR_WOULDBLOCK = -7,
+/** Address in use. */
+ ERR_USE = -8,
+/** Already connecting. */
+ ERR_ALREADY = -9,
+/** Conn already established.*/
+ ERR_ISCONN = -10,
+/** Not connected. */
+ ERR_CONN = -11,
+/** Low-level netif error */
+ ERR_IF = -12,
+
+/** Connection aborted. */
+ ERR_ABRT = -13,
+/** Connection reset. */
+ ERR_RST = -14,
+/** Connection closed. */
+ ERR_CLSD = -15,
+/** Illegal argument. */
+ ERR_ARG = -16
+} err_enum_t;
+
+/** Define LWIP_ERR_T in cc.h if you want to use
+ * a different type for your platform (must be signed). */
+#ifdef LWIP_ERR_T
+typedef LWIP_ERR_T err_t;
+#else /* LWIP_ERR_T */
+typedef s8_t err_t;
+#endif /* LWIP_ERR_T*/
+
+/**
+ * @}
+ */
+
+#ifdef LWIP_DEBUG
+extern const char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+
+#if !NO_SYS
+int err_to_errno(err_t err);
+#endif /* !NO_SYS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ERR_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/errno.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/errno.h
new file mode 100644
index 0000000..48d6b53
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/errno.h
@@ -0,0 +1,198 @@
+/**
+ * @file
+ * Posix Errno defines
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_ERRNO_H
+#define LWIP_HDR_ERRNO_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#else /* LWIP_PROVIDE_ERRNO */
+
+/* Define LWIP_ERRNO_STDINCLUDE if you want to include here */
+#ifdef LWIP_ERRNO_STDINCLUDE
+#include
+#else /* LWIP_ERRNO_STDINCLUDE */
+/* Define LWIP_ERRNO_INCLUDE to an equivalent of to include the error defines here */
+#ifdef LWIP_ERRNO_INCLUDE
+#include LWIP_ERRNO_INCLUDE
+#endif /* LWIP_ERRNO_INCLUDE */
+#endif /* LWIP_ERRNO_STDINCLUDE */
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ERRNO_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/etharp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/etharp.h
new file mode 100644
index 0000000..2036b24
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/etharp.h
@@ -0,0 +1,105 @@
+/**
+ * @file
+ * Ethernet output function - handles OUTGOING ethernet level traffic, implements
+ * ARP resolving.
+ * To be used in most low-level netif implementations
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_ETHARP_H
+#define LWIP_HDR_NETIF_ETHARP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip4_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip4.h"
+#include "lwip/prot/ethernet.h"
+
+#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/prot/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** 1 seconds period */
+#define ARP_TMR_INTERVAL 1000
+
+#if ARP_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+ * defined here to be accessed by memp.h
+ */
+struct etharp_q_entry {
+ struct etharp_q_entry *next;
+ struct pbuf *p;
+};
+#endif /* ARP_QUEUEING */
+
+#define etharp_init() /* Compatibility define, no init needed. */
+void etharp_tmr(void);
+ssize_t etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr,
+ struct eth_addr **eth_ret, const ip4_addr_t **ip_ret);
+int etharp_get_entry(size_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret);
+err_t etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
+err_t etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, const ip4_addr_t *ipaddr);
+/** For Ethernet network interfaces, we might want to send "gratuitous ARP";
+ * this is an ARP packet sent by a node in order to spontaneously cause other
+ * nodes to update an entry in their ARP cache.
+ * From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */
+#define etharp_gratuitous(netif) etharp_request((netif), netif_ip4_addr(netif))
+void etharp_cleanup_netif(struct netif *netif);
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+err_t etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr);
+err_t etharp_remove_static_entry(const ip4_addr_t *ipaddr);
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+void etharp_input(struct pbuf *p, struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_ARP */
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+#endif /* LWIP_HDR_NETIF_ETHARP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ethip6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ethip6.h
new file mode 100644
index 0000000..5e88dff
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ethip6.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * Ethernet output for IPv6. Uses ND tables for link-layer addressing.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+
+#ifndef LWIP_HDR_ETHIP6_H
+#define LWIP_HDR_ETHIP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 && LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+err_t ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 && LWIP_ETHERNET */
+
+#endif /* LWIP_HDR_ETHIP6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/icmp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/icmp.h
new file mode 100644
index 0000000..f5a31fd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/icmp.h
@@ -0,0 +1,110 @@
+/**
+ * @file
+ * ICMP API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_ICMP_H
+#define LWIP_HDR_ICMP_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/prot/icmp.h"
+
+#if LWIP_IPV6 && LWIP_ICMP6
+#include "lwip/icmp6.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICMP destination unreachable codes */
+enum icmp_dur_type {
+ /** net unreachable */
+ ICMP_DUR_NET = 0,
+ /** host unreachable */
+ ICMP_DUR_HOST = 1,
+ /** protocol unreachable */
+ ICMP_DUR_PROTO = 2,
+ /** port unreachable */
+ ICMP_DUR_PORT = 3,
+ /** fragmentation needed and DF set */
+ ICMP_DUR_FRAG = 4,
+ /** source route failed */
+ ICMP_DUR_SR = 5
+};
+
+/** ICMP time exceeded codes */
+enum icmp_te_type {
+ /** time to live exceeded in transit */
+ ICMP_TE_TTL = 0,
+ /** fragment reassembly time exceeded */
+ ICMP_TE_FRAG = 1
+};
+
+#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#endif /* LWIP_IPV4 && LWIP_ICMP */
+
+#if LWIP_IPV4 && LWIP_IPV6
+#if LWIP_ICMP && LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) ((isipv6) ? \
+ icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) : \
+ icmp_dest_unreach(pbuf, ICMP_DUR_PORT))
+#elif LWIP_ICMP
+#define icmp_port_unreach(isipv6, pbuf) do{ if(!(isipv6)) { icmp_dest_unreach(pbuf, ICMP_DUR_PORT);}}while(0)
+#elif LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) do{ if(isipv6) { icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT);}}while(0)
+#else
+#define icmp_port_unreach(isipv6, pbuf)
+#endif
+#elif LWIP_IPV6 && LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT)
+#elif LWIP_IPV4 && LWIP_ICMP
+#define icmp_port_unreach(isipv6, pbuf) icmp_dest_unreach(pbuf, ICMP_DUR_PORT)
+#else /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) */
+#define icmp_port_unreach(isipv6, pbuf)
+#endif /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) LWIP_IPV4*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ICMP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/icmp6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/icmp6.h
new file mode 100644
index 0000000..0ccb789
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/icmp6.h
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * IPv6 version of ICMP, as per RFC 4443.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+#ifndef LWIP_HDR_ICMP6_H
+#define LWIP_HDR_ICMP6_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+#include "lwip/prot/icmp6.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+void icmp6_input(struct pbuf *p, struct netif *inp);
+void icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c);
+void icmp6_packet_too_big(struct pbuf *p, u32_t mtu);
+void icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c);
+void icmp6_time_exceeded_with_addrs(struct pbuf *p, enum icmp6_te_code c,
+ const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr);
+void icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, const void *pointer);
+
+#endif /* LWIP_ICMP6 && LWIP_IPV6 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LWIP_HDR_ICMP6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/if_api.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/if_api.h
new file mode 100644
index 0000000..39017ab
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/if_api.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ * Interface Identification APIs from:
+ * RFC 3493: Basic Socket Interface Extensions for IPv6
+ * Section 4: Interface Identification
+ */
+
+/*
+ * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Joel Cunningham
+ *
+ */
+#ifndef LWIP_HDR_IF_H
+#define LWIP_HDR_IF_H
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IF_NAMESIZE NETIF_NAMESIZE
+
+char * lwip_if_indextoname(unsigned int ifindex, char *ifname);
+unsigned int lwip_if_nametoindex(const char *ifname);
+
+#if LWIP_COMPAT_SOCKETS
+#define if_indextoname(ifindex, ifname) lwip_if_indextoname(ifindex,ifname)
+#define if_nametoindex(ifname) lwip_if_nametoindex(ifname)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* LWIP_HDR_IF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/igmp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/igmp.h
new file mode 100644
index 0000000..0a16db0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/igmp.h
@@ -0,0 +1,115 @@
+/**
+ * @file
+ * IGMP API
+ */
+
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+#ifndef LWIP_HDR_IGMP_H
+#define LWIP_HDR_IGMP_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* IGMP timer */
+#define IGMP_TMR_INTERVAL 100 /* Milliseconds */
+#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL)
+#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL)
+
+/* Compatibility defines (don't use for new code) */
+#define IGMP_DEL_MAC_FILTER NETIF_DEL_MAC_FILTER
+#define IGMP_ADD_MAC_FILTER NETIF_ADD_MAC_FILTER
+
+/**
+ * igmp group structure - there is
+ * a list of groups for each interface
+ * these should really be linked from the interface, but
+ * if we keep them separate we will not affect the lwip original code
+ * too much
+ *
+ * There will be a group for the all systems group address but this
+ * will not run the state machine as it is used to kick off reports
+ * from all the other groups
+ */
+struct igmp_group {
+ /** next link */
+ struct igmp_group *next;
+ /** multicast address */
+ ip4_addr_t group_address;
+ /** signifies we were the last person to report */
+ u8_t last_reporter_flag;
+ /** current state of the group */
+ u8_t group_state;
+ /** timer for reporting, negative is OFF */
+ u16_t timer;
+ /** counter of simultaneous uses */
+ u8_t use;
+};
+
+/* Prototypes */
+void igmp_init(void);
+err_t igmp_start(struct netif *netif);
+err_t igmp_stop(struct netif *netif);
+void igmp_report_groups(struct netif *netif);
+struct igmp_group *igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr);
+void igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest);
+err_t igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
+err_t igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
+err_t igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
+err_t igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
+void igmp_tmr(void);
+
+/** @ingroup igmp
+ * Get list head of IGMP groups for netif.
+ * Note: The allsystems group IP is contained in the list as first entry.
+ * @see @ref netif_set_igmp_mac_filter()
+ */
+#define netif_igmp_data(netif) ((struct igmp_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+
+#endif /* LWIP_HDR_IGMP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/inet.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/inet.h
new file mode 100644
index 0000000..76f2a95
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/inet.h
@@ -0,0 +1,169 @@
+/**
+ * @file
+ * This file (together with sockets.h) aims to provide structs and functions from
+ * - arpa/inet.h
+ * - netinet/in.h
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_INET_H
+#define LWIP_HDR_INET_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If your port already typedef's in_addr_t, define _IN_ADDR_T_DECLARED
+ to prevent this code from redefining it. */
+#if !defined(in_addr_t) && !defined(_IN_ADDR_T_DECLARED)
+typedef u32_t in_addr_t;
+#endif
+
+struct in_addr {
+ in_addr_t s_addr;
+};
+
+struct in6_addr {
+ union {
+ u32_t u32_addr[4];
+ u8_t u8_addr[16];
+ } un;
+#define s6_addr un.u8_addr
+};
+
+/** 255.255.255.255 */
+#define INADDR_NONE IPADDR_NONE
+/** 127.0.0.1 */
+#define INADDR_LOOPBACK IPADDR_LOOPBACK
+/** 0.0.0.0 */
+#define INADDR_ANY IPADDR_ANY
+/** 255.255.255.255 */
+#define INADDR_BROADCAST IPADDR_BROADCAST
+
+/** This macro can be used to initialize a variable of type struct in6_addr
+ to the IPv6 wildcard address. */
+#define IN6ADDR_ANY_INIT {{{0,0,0,0}}}
+/** This macro can be used to initialize a variable of type struct in6_addr
+ to the IPv6 loopback address. */
+#define IN6ADDR_LOOPBACK_INIT {{{0,0,0,PP_HTONL(1)}}}
+/** This variable is initialized by the system to contain the wildcard IPv6 address. */
+extern const struct in6_addr in6addr_any;
+
+/* Definitions of the bits in an (IPv4) Internet address integer.
+
+ On subnets, host and network parts are found according to
+ the subnet mask, not these masks. */
+#define IN_CLASSA(a) IP_CLASSA(a)
+#define IN_CLASSA_NET IP_CLASSA_NET
+#define IN_CLASSA_NSHIFT IP_CLASSA_NSHIFT
+#define IN_CLASSA_HOST IP_CLASSA_HOST
+#define IN_CLASSA_MAX IP_CLASSA_MAX
+
+#define IN_CLASSB(b) IP_CLASSB(b)
+#define IN_CLASSB_NET IP_CLASSB_NET
+#define IN_CLASSB_NSHIFT IP_CLASSB_NSHIFT
+#define IN_CLASSB_HOST IP_CLASSB_HOST
+#define IN_CLASSB_MAX IP_CLASSB_MAX
+
+#define IN_CLASSC(c) IP_CLASSC(c)
+#define IN_CLASSC_NET IP_CLASSC_NET
+#define IN_CLASSC_NSHIFT IP_CLASSC_NSHIFT
+#define IN_CLASSC_HOST IP_CLASSC_HOST
+#define IN_CLASSC_MAX IP_CLASSC_MAX
+
+#define IN_CLASSD(d) IP_CLASSD(d)
+#define IN_CLASSD_NET IP_CLASSD_NET /* These ones aren't really */
+#define IN_CLASSD_NSHIFT IP_CLASSD_NSHIFT /* net and host fields, but */
+#define IN_CLASSD_HOST IP_CLASSD_HOST /* routing needn't know. */
+#define IN_CLASSD_MAX IP_CLASSD_MAX
+
+#define IN_MULTICAST(a) IP_MULTICAST(a)
+
+#define IN_EXPERIMENTAL(a) IP_EXPERIMENTAL(a)
+#define IN_BADCLASS(a) IP_BADCLASS(a)
+
+#define IN_LOOPBACKNET IP_LOOPBACKNET
+
+
+#ifndef INET_ADDRSTRLEN
+#define INET_ADDRSTRLEN IP4ADDR_STRLEN_MAX
+#endif
+#if LWIP_IPV6
+#ifndef INET6_ADDRSTRLEN
+#define INET6_ADDRSTRLEN IP6ADDR_STRLEN_MAX
+#endif
+#endif
+
+#if LWIP_IPV4
+
+#define inet_addr_from_ip4addr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr))
+#define inet_addr_to_ip4addr(target_ipaddr, source_inaddr) (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr))
+
+/* directly map this to the lwip internal functions */
+#define inet_addr(cp) ipaddr_addr(cp)
+#define inet_aton(cp, addr) ip4addr_aton(cp, (ip4_addr_t*)addr)
+#define inet_ntoa(addr) ip4addr_ntoa((const ip4_addr_t*)&(addr))
+#define inet_ntoa_r(addr, buf, buflen) ip4addr_ntoa_r((const ip4_addr_t*)&(addr), buf, buflen)
+
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+#define inet6_addr_from_ip6addr(target_in6addr, source_ip6addr) {(target_in6addr)->un.u32_addr[0] = (source_ip6addr)->addr[0]; \
+ (target_in6addr)->un.u32_addr[1] = (source_ip6addr)->addr[1]; \
+ (target_in6addr)->un.u32_addr[2] = (source_ip6addr)->addr[2]; \
+ (target_in6addr)->un.u32_addr[3] = (source_ip6addr)->addr[3];}
+#define inet6_addr_to_ip6addr(target_ip6addr, source_in6addr) {(target_ip6addr)->addr[0] = (source_in6addr)->un.u32_addr[0]; \
+ (target_ip6addr)->addr[1] = (source_in6addr)->un.u32_addr[1]; \
+ (target_ip6addr)->addr[2] = (source_in6addr)->un.u32_addr[2]; \
+ (target_ip6addr)->addr[3] = (source_in6addr)->un.u32_addr[3]; \
+ ip6_addr_clear_zone(target_ip6addr);}
+
+/* directly map this to the lwip internal functions */
+#define inet6_aton(cp, addr) ip6addr_aton(cp, (ip6_addr_t*)addr)
+#define inet6_ntoa(addr) ip6addr_ntoa((const ip6_addr_t*)&(addr))
+#define inet6_ntoa_r(addr, buf, buflen) ip6addr_ntoa_r((const ip6_addr_t*)&(addr), buf, buflen)
+
+#endif /* LWIP_IPV6 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INET_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/inet_chksum.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/inet_chksum.h
new file mode 100644
index 0000000..33296d2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/inet_chksum.h
@@ -0,0 +1,104 @@
+/**
+ * @file
+ * IP checksum calculation functions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_INET_CHKSUM_H
+#define LWIP_HDR_INET_CHKSUM_H
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+/** Swap the bytes in an u16_t: much like lwip_htons() for little-endian */
+#ifndef SWAP_BYTES_IN_WORD
+#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8)
+#endif /* SWAP_BYTES_IN_WORD */
+
+/** Split an u32_t in two u16_ts and add them up */
+#ifndef FOLD_U32T
+#define FOLD_U32T(u) ((u32_t)(((u) >> 16) + ((u) & 0x0000ffffUL)))
+#endif
+
+#if LWIP_CHECKSUM_ON_COPY
+/** Function-like macro: same as MEMCPY but returns the checksum of copied data
+ as u16_t */
+# ifndef LWIP_CHKSUM_COPY
+# define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len)
+# ifndef LWIP_CHKSUM_COPY_ALGORITHM
+# define LWIP_CHKSUM_COPY_ALGORITHM 1
+# endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+# else /* LWIP_CHKSUM_COPY */
+# define LWIP_CHKSUM_COPY_ALGORITHM 0
+# endif /* LWIP_CHKSUM_COPY */
+#else /* LWIP_CHECKSUM_ON_COPY */
+# define LWIP_CHKSUM_COPY_ALGORITHM 0
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(const void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+#if LWIP_CHKSUM_COPY_ALGORITHM
+u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len);
+#endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+
+#if LWIP_IPV4
+u16_t inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+ const ip4_addr_t *src, const ip4_addr_t *dest);
+u16_t inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto,
+ u16_t proto_len, u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest);
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+u16_t ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+ const ip6_addr_t *src, const ip6_addr_t *dest);
+u16_t ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+ u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest);
+#endif /* LWIP_IPV6 */
+
+
+u16_t ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+ const ip_addr_t *src, const ip_addr_t *dest);
+u16_t ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+ u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INET_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/init.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/init.h
new file mode 100644
index 0000000..7497523
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/init.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * lwIP initialization API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_INIT_H
+#define LWIP_HDR_INIT_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lwip_version Version
+ * @ingroup lwip
+ * @{
+ */
+
+/** X.x.x: Major version of the stack */
+#define LWIP_VERSION_MAJOR 2
+/** x.X.x: Minor version of the stack */
+#define LWIP_VERSION_MINOR 1
+/** x.x.X: Revision of the stack */
+#define LWIP_VERSION_REVISION 1
+/** For release candidates, this is set to 1..254
+ * For official releases, this is set to 255 (LWIP_RC_RELEASE)
+ * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */
+#define LWIP_VERSION_RC LWIP_RC_RELEASE
+
+/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
+#define LWIP_RC_RELEASE 255
+/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */
+#define LWIP_RC_DEVELOPMENT 0
+
+#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE)
+#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
+#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
+
+/* Some helper defines to get a version string */
+#define LWIP_VERSTR2(x) #x
+#define LWIP_VERSTR(x) LWIP_VERSTR2(x)
+#if LWIP_VERSION_IS_RELEASE
+#define LWIP_VERSION_STRING_SUFFIX ""
+#elif LWIP_VERSION_IS_DEVELOPMENT
+#define LWIP_VERSION_STRING_SUFFIX "d"
+#else
+#define LWIP_VERSION_STRING_SUFFIX "rc" LWIP_VERSTR(LWIP_VERSION_RC)
+#endif
+
+/** Provides the version of the stack */
+#define LWIP_VERSION ((LWIP_VERSION_MAJOR) << 24 | (LWIP_VERSION_MINOR) << 16 | \
+ (LWIP_VERSION_REVISION) << 8 | (LWIP_VERSION_RC))
+/** Provides the version of the stack as string */
+#define LWIP_VERSION_STRING LWIP_VERSTR(LWIP_VERSION_MAJOR) "." LWIP_VERSTR(LWIP_VERSION_MINOR) "." LWIP_VERSTR(LWIP_VERSION_REVISION) LWIP_VERSION_STRING_SUFFIX
+
+/**
+ * @}
+ */
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INIT_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/init.h.cmake.in b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/init.h.cmake.in
new file mode 100644
index 0000000..9b609b7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/init.h.cmake.in
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * lwIP initialization API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_INIT_H
+#define LWIP_HDR_INIT_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lwip_version Version
+ * @ingroup lwip
+ * @{
+ */
+
+/** X.x.x: Major version of the stack */
+#define LWIP_VERSION_MAJOR ${LWIP_VERSION_MAJOR}
+/** x.X.x: Minor version of the stack */
+#define LWIP_VERSION_MINOR ${LWIP_VERSION_MINOR}
+/** x.x.X: Revision of the stack */
+#define LWIP_VERSION_REVISION ${LWIP_VERSION_REVISION}
+/** For release candidates, this is set to 1..254
+ * For official releases, this is set to 255 (LWIP_RC_RELEASE)
+ * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */
+#define LWIP_VERSION_RC ${LWIP_VERSION_RC}
+
+/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
+#define LWIP_RC_RELEASE 255
+/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */
+#define LWIP_RC_DEVELOPMENT 0
+
+#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE)
+#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
+#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
+
+/* Some helper defines to get a version string */
+#define LWIP_VERSTR2(x) #x
+#define LWIP_VERSTR(x) LWIP_VERSTR2(x)
+#if LWIP_VERSION_IS_RELEASE
+#define LWIP_VERSION_STRING_SUFFIX ""
+#elif LWIP_VERSION_IS_DEVELOPMENT
+#define LWIP_VERSION_STRING_SUFFIX "d"
+#else
+#define LWIP_VERSION_STRING_SUFFIX "rc" LWIP_VERSTR(LWIP_VERSION_RC)
+#endif
+
+/** Provides the version of the stack */
+#define LWIP_VERSION ((LWIP_VERSION_MAJOR) << 24 | (LWIP_VERSION_MINOR) << 16 | \
+ (LWIP_VERSION_REVISION) << 8 | (LWIP_VERSION_RC))
+/** Provides the version of the stack as string */
+#define LWIP_VERSION_STRING LWIP_VERSTR(LWIP_VERSION_MAJOR) "." LWIP_VERSTR(LWIP_VERSION_MINOR) "." LWIP_VERSTR(LWIP_VERSION_REVISION) LWIP_VERSION_STRING_SUFFIX
+
+/**
+ * @}
+ */
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INIT_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip.h
new file mode 100644
index 0000000..68aed6a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip.h
@@ -0,0 +1,328 @@
+/**
+ * @file
+ * IP API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_IP_H
+#define LWIP_HDR_IP_H
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+#include "lwip/ip4.h"
+#include "lwip/ip6.h"
+#include "lwip/prot/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This is passed as the destination address to ip_output_if (not
+ to ip_output), meaning that an IP header already is constructed
+ in the pbuf. This is used when TCP retransmits. */
+#define LWIP_IP_HDRINCL NULL
+
+/** pbufs passed to IP must have a ref-count of 1 as their payload pointer
+ gets altered as the packet is passed down the stack */
+#ifndef LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX
+#define LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p) LWIP_ASSERT("p->ref == 1", (p)->ref == 1)
+#endif
+
+#if LWIP_NETIF_USE_HINTS
+#define IP_PCB_NETIFHINT ;struct netif_hint netif_hints
+#else /* LWIP_NETIF_USE_HINTS */
+#define IP_PCB_NETIFHINT
+#endif /* LWIP_NETIF_USE_HINTS */
+
+/** This is the common part of all PCB types. It needs to be at the
+ beginning of a PCB type definition. It is located here so that
+ changes to this common part are made in one location instead of
+ having to change all PCB structs. */
+#define IP_PCB \
+ /* ip addresses in network byte order */ \
+ ip_addr_t local_ip; \
+ ip_addr_t remote_ip; \
+ /* Bound netif index */ \
+ u8_t netif_idx; \
+ /* Socket options */ \
+ u8_t so_options; \
+ /* Type Of Service */ \
+ u8_t tos; \
+ /* Time To Live */ \
+ u8_t ttl \
+ /* link layer address resolution hint */ \
+ IP_PCB_NETIFHINT
+
+struct ip_pcb {
+ /* Common members of all PCB types */
+ IP_PCB;
+};
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX in sockets.h
+ */
+#define SOF_REUSEADDR 0x04U /* allow local address reuse */
+#define SOF_KEEPALIVE 0x08U /* keep connections alive */
+#define SOF_BROADCAST 0x20U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+
+/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */
+#define SOF_INHERITED (SOF_REUSEADDR|SOF_KEEPALIVE)
+
+/** Global variables of this module, kept in a struct for efficient access using base+index. */
+struct ip_globals
+{
+ /** The interface that accepted the packet for the current callback invocation. */
+ struct netif *current_netif;
+ /** The interface that received the packet for the current callback invocation. */
+ struct netif *current_input_netif;
+#if LWIP_IPV4
+ /** Header of the input packet currently being processed. */
+ const struct ip_hdr *current_ip4_header;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+ /** Header of the input IPv6 packet currently being processed. */
+ struct ip6_hdr *current_ip6_header;
+#endif /* LWIP_IPV6 */
+ /** Total header length of current_ip4/6_header (i.e. after this, the UDP/TCP header starts) */
+ u16_t current_ip_header_tot_len;
+ /** Source IP address of current_header */
+ ip_addr_t current_iphdr_src;
+ /** Destination IP address of current_header */
+ ip_addr_t current_iphdr_dest;
+};
+extern struct ip_globals ip_data;
+
+
+/** Get the interface that accepted the current packet.
+ * This may or may not be the receiving netif, depending on your netif/network setup.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_netif() (ip_data.current_netif)
+/** Get the interface that received the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_input_netif() (ip_data.current_input_netif)
+/** Total header length of ip(6)_current_header() (i.e. after this, the UDP/TCP header starts) */
+#define ip_current_header_tot_len() (ip_data.current_ip_header_tot_len)
+/** Source IP address of current_header */
+#define ip_current_src_addr() (&ip_data.current_iphdr_src)
+/** Destination IP address of current_header */
+#define ip_current_dest_addr() (&ip_data.current_iphdr_dest)
+
+#if LWIP_IPV4 && LWIP_IPV6
+/** Get the IPv4 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip4_current_header() ip_data.current_ip4_header
+/** Get the IPv6 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip6_current_header() ((const struct ip6_hdr*)(ip_data.current_ip6_header))
+/** Returns TRUE if the current IP input packet is IPv6, FALSE if it is IPv4 */
+#define ip_current_is_v6() (ip6_current_header() != NULL)
+/** Source IPv6 address of current_header */
+#define ip6_current_src_addr() (ip_2_ip6(&ip_data.current_iphdr_src))
+/** Destination IPv6 address of current_header */
+#define ip6_current_dest_addr() (ip_2_ip6(&ip_data.current_iphdr_dest))
+/** Get the transport layer protocol */
+#define ip_current_header_proto() (ip_current_is_v6() ? \
+ IP6H_NEXTH(ip6_current_header()) :\
+ IPH_PROTO(ip4_current_header()))
+/** Get the transport layer header */
+#define ip_next_header_ptr() ((const void*)((ip_current_is_v6() ? \
+ (const u8_t*)ip6_current_header() : (const u8_t*)ip4_current_header()) + ip_current_header_tot_len()))
+
+/** Source IP4 address of current_header */
+#define ip4_current_src_addr() (ip_2_ip4(&ip_data.current_iphdr_src))
+/** Destination IP4 address of current_header */
+#define ip4_current_dest_addr() (ip_2_ip4(&ip_data.current_iphdr_dest))
+
+#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
+
+/** Get the IPv4 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip4_current_header() ip_data.current_ip4_header
+/** Always returns FALSE when only supporting IPv4 only */
+#define ip_current_is_v6() 0
+/** Get the transport layer protocol */
+#define ip_current_header_proto() IPH_PROTO(ip4_current_header())
+/** Get the transport layer header */
+#define ip_next_header_ptr() ((const void*)((const u8_t*)ip4_current_header() + ip_current_header_tot_len()))
+/** Source IP4 address of current_header */
+#define ip4_current_src_addr() (&ip_data.current_iphdr_src)
+/** Destination IP4 address of current_header */
+#define ip4_current_dest_addr() (&ip_data.current_iphdr_dest)
+
+#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
+
+/** Get the IPv6 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip6_current_header() ((const struct ip6_hdr*)(ip_data.current_ip6_header))
+/** Always returns TRUE when only supporting IPv6 only */
+#define ip_current_is_v6() 1
+/** Get the transport layer protocol */
+#define ip_current_header_proto() IP6H_NEXTH(ip6_current_header())
+/** Get the transport layer header */
+#define ip_next_header_ptr() ((const void*)(((const u8_t*)ip6_current_header()) + ip_current_header_tot_len()))
+/** Source IP6 address of current_header */
+#define ip6_current_src_addr() (&ip_data.current_iphdr_src)
+/** Destination IP6 address of current_header */
+#define ip6_current_dest_addr() (&ip_data.current_iphdr_dest)
+
+#endif /* LWIP_IPV6 */
+
+/** Union source address of current_header */
+#define ip_current_src_addr() (&ip_data.current_iphdr_src)
+/** Union destination address of current_header */
+#define ip_current_dest_addr() (&ip_data.current_iphdr_dest)
+
+/** Gets an IP pcb option (SOF_* flags) */
+#define ip_get_option(pcb, opt) ((pcb)->so_options & (opt))
+/** Sets an IP pcb option (SOF_* flags) */
+#define ip_set_option(pcb, opt) ((pcb)->so_options = (u8_t)((pcb)->so_options | (opt)))
+/** Resets an IP pcb option (SOF_* flags) */
+#define ip_reset_option(pcb, opt) ((pcb)->so_options = (u8_t)((pcb)->so_options & ~(opt)))
+
+#if LWIP_IPV4 && LWIP_IPV6
+/**
+ * @ingroup ip
+ * Output IP packet, netif is selected by source address
+ */
+#define ip_output(p, src, dest, ttl, tos, proto) \
+ (IP_IS_V6(dest) ? \
+ ip6_output(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto) : \
+ ip4_output(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto))
+/**
+ * @ingroup ip
+ * Output IP packet to specified interface
+ */
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+ (IP_IS_V6(dest) ? \
+ ip6_output_if(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
+ ip4_output_if(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
+/**
+ * @ingroup ip
+ * Output IP packet to interface specifying source address
+ */
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+ (IP_IS_V6(dest) ? \
+ ip6_output_if_src(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
+ ip4_output_if_src(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
+/** Output IP packet that already includes an IP header. */
+#define ip_output_if_hdrincl(p, src, dest, netif) \
+ (IP_IS_V6(dest) ? \
+ ip6_output_if(p, ip_2_ip6(src), LWIP_IP_HDRINCL, 0, 0, 0, netif) : \
+ ip4_output_if(p, ip_2_ip4(src), LWIP_IP_HDRINCL, 0, 0, 0, netif))
+/** Output IP packet with netif_hint */
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \
+ (IP_IS_V6(dest) ? \
+ ip6_output_hinted(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif_hint) : \
+ ip4_output_hinted(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif_hint))
+/**
+ * @ingroup ip
+ * Get netif for address combination. See \ref ip6_route and \ref ip4_route
+ */
+#define ip_route(src, dest) \
+ (IP_IS_V6(dest) ? \
+ ip6_route(ip_2_ip6(src), ip_2_ip6(dest)) : \
+ ip4_route_src(ip_2_ip4(src), ip_2_ip4(dest)))
+/**
+ * @ingroup ip
+ * Get netif for IP.
+ */
+#define ip_netif_get_local_ip(netif, dest) (IP_IS_V6(dest) ? \
+ ip6_netif_get_local_ip(netif, ip_2_ip6(dest)) : \
+ ip4_netif_get_local_ip(netif))
+#define ip_debug_print(is_ipv6, p) ((is_ipv6) ? ip6_debug_print(p) : ip4_debug_print(p))
+
+err_t ip_input(struct pbuf *p, struct netif *inp);
+
+#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define ip_output(p, src, dest, ttl, tos, proto) \
+ ip4_output(p, src, dest, ttl, tos, proto)
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+ ip4_output_if(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+ ip4_output_if_src(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \
+ ip4_output_hinted(p, src, dest, ttl, tos, proto, netif_hint)
+#define ip_output_if_hdrincl(p, src, dest, netif) \
+ ip4_output_if(p, src, LWIP_IP_HDRINCL, 0, 0, 0, netif)
+#define ip_route(src, dest) \
+ ip4_route_src(src, dest)
+#define ip_netif_get_local_ip(netif, dest) \
+ ip4_netif_get_local_ip(netif)
+#define ip_debug_print(is_ipv6, p) ip4_debug_print(p)
+
+#define ip_input ip4_input
+
+#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define ip_output(p, src, dest, ttl, tos, proto) \
+ ip6_output(p, src, dest, ttl, tos, proto)
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+ ip6_output_if(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+ ip6_output_if_src(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \
+ ip6_output_hinted(p, src, dest, ttl, tos, proto, netif_hint)
+#define ip_output_if_hdrincl(p, src, dest, netif) \
+ ip6_output_if(p, src, LWIP_IP_HDRINCL, 0, 0, 0, netif)
+#define ip_route(src, dest) \
+ ip6_route(src, dest)
+#define ip_netif_get_local_ip(netif, dest) \
+ ip6_netif_get_local_ip(netif, dest)
+#define ip_debug_print(is_ipv6, p) ip6_debug_print(p)
+
+#define ip_input ip6_input
+
+#endif /* LWIP_IPV6 */
+
+#define ip_route_get_local_ip(src, dest, netif, ipaddr) do { \
+ (netif) = ip_route(src, dest); \
+ (ipaddr) = ip_netif_get_local_ip(netif, dest); \
+}while(0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4.h
new file mode 100644
index 0000000..4d7228d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4.h
@@ -0,0 +1,109 @@
+/**
+ * @file
+ * IPv4 API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_IP4_H
+#define LWIP_HDR_IP4_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip4_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+#include "lwip/prot/ip4.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef LWIP_HOOK_IP4_ROUTE_SRC
+#define LWIP_IPV4_SRC_ROUTING 1
+#else
+#define LWIP_IPV4_SRC_ROUTING 0
+#endif
+
+/** Currently, the function ip_output_if_opt() is only used with IGMP */
+#define IP_OPTIONS_SEND (LWIP_IPV4 && LWIP_IGMP)
+
+#define ip_init() /* Compatibility define, no init needed. */
+struct netif *ip4_route(const ip4_addr_t *dest);
+#if LWIP_IPV4_SRC_ROUTING
+struct netif *ip4_route_src(const ip4_addr_t *src, const ip4_addr_t *dest);
+#else /* LWIP_IPV4_SRC_ROUTING */
+#define ip4_route_src(src, dest) ip4_route(dest)
+#endif /* LWIP_IPV4_SRC_ROUTING */
+err_t ip4_input(struct pbuf *p, struct netif *inp);
+err_t ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+ u8_t ttl, u8_t tos, u8_t proto);
+err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+ u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+ u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+#if LWIP_NETIF_USE_HINTS
+err_t ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+ u8_t ttl, u8_t tos, u8_t proto, struct netif_hint *netif_hint);
+#endif /* LWIP_NETIF_USE_HINTS */
+#if IP_OPTIONS_SEND
+err_t ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+ u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+ u16_t optlen);
+err_t ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+ u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+ u16_t optlen);
+#endif /* IP_OPTIONS_SEND */
+
+#if LWIP_MULTICAST_TX_OPTIONS
+void ip4_set_default_multicast_netif(struct netif* default_multicast_netif);
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#define ip4_netif_get_local_ip(netif) (((netif) != NULL) ? netif_ip_addr4(netif) : NULL)
+
+#if IP_DEBUG
+void ip4_debug_print(struct pbuf *p);
+#else
+#define ip4_debug_print(p)
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4_addr.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4_addr.h
new file mode 100644
index 0000000..f244c4f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4_addr.h
@@ -0,0 +1,216 @@
+/**
+ * @file
+ * IPv4 address API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_IP4_ADDR_H
+#define LWIP_HDR_IP4_ADDR_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#if LWIP_IPV4
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This is the aligned version of ip4_addr_t,
+ used as local variable, on the stack, etc. */
+struct ip4_addr {
+ u32_t addr;
+};
+
+/** ip4_addr_t uses a struct for convenience only, so that the same defines can
+ * operate both on ip4_addr_t as well as on ip4_addr_p_t. */
+typedef struct ip4_addr ip4_addr_t;
+
+/* Forward declaration to not include netif.h */
+struct netif;
+
+/** 255.255.255.255 */
+#define IPADDR_NONE ((u32_t)0xffffffffUL)
+/** 127.0.0.1 */
+#define IPADDR_LOOPBACK ((u32_t)0x7f000001UL)
+/** 0.0.0.0 */
+#define IPADDR_ANY ((u32_t)0x00000000UL)
+/** 255.255.255.255 */
+#define IPADDR_BROADCAST ((u32_t)0xffffffffUL)
+
+/* Definitions of the bits in an Internet address integer.
+
+ On subnets, host and network parts are found according to
+ the subnet mask, not these masks. */
+#define IP_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0)
+#define IP_CLASSA_NET 0xff000000
+#define IP_CLASSA_NSHIFT 24
+#define IP_CLASSA_HOST (0xffffffff & ~IP_CLASSA_NET)
+#define IP_CLASSA_MAX 128
+
+#define IP_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL)
+#define IP_CLASSB_NET 0xffff0000
+#define IP_CLASSB_NSHIFT 16
+#define IP_CLASSB_HOST (0xffffffff & ~IP_CLASSB_NET)
+#define IP_CLASSB_MAX 65536
+
+#define IP_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL)
+#define IP_CLASSC_NET 0xffffff00
+#define IP_CLASSC_NSHIFT 8
+#define IP_CLASSC_HOST (0xffffffff & ~IP_CLASSC_NET)
+
+#define IP_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL)
+#define IP_CLASSD_NET 0xf0000000 /* These ones aren't really */
+#define IP_CLASSD_NSHIFT 28 /* net and host fields, but */
+#define IP_CLASSD_HOST 0x0fffffff /* routing needn't know. */
+#define IP_MULTICAST(a) IP_CLASSD(a)
+
+#define IP_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+#define IP_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+
+#define IP_LOOPBACKNET 127 /* official! */
+
+/** Set an IP address given by the four byte-parts */
+#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = PP_HTONL(LWIP_MAKEU32(a,b,c,d))
+
+/** Copy IP address - faster than ip4_addr_set: no NULL check */
+#define ip4_addr_copy(dest, src) ((dest).addr = (src).addr)
+/** Safely copy one IP address to another (src may be NULL) */
+#define ip4_addr_set(dest, src) ((dest)->addr = \
+ ((src) == NULL ? 0 : \
+ (src)->addr))
+/** Set complete address to zero */
+#define ip4_addr_set_zero(ipaddr) ((ipaddr)->addr = 0)
+/** Set address to IPADDR_ANY (no need for lwip_htonl()) */
+#define ip4_addr_set_any(ipaddr) ((ipaddr)->addr = IPADDR_ANY)
+/** Set address to loopback address */
+#define ip4_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK))
+/** Check if an address is in the loopback region */
+#define ip4_addr_isloopback(ipaddr) (((ipaddr)->addr & PP_HTONL(IP_CLASSA_NET)) == PP_HTONL(((u32_t)IP_LOOPBACKNET) << 24))
+/** Safely copy one IP address to another and change byte order
+ * from host- to network-order. */
+#define ip4_addr_set_hton(dest, src) ((dest)->addr = \
+ ((src) == NULL ? 0:\
+ lwip_htonl((src)->addr)))
+/** IPv4 only: set the IP address given as an u32_t */
+#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32))
+/** IPv4 only: get the IP address as an u32_t */
+#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr)
+
+/** Get the network address by combining host address with netmask */
+#define ip4_addr_get_network(target, host, netmask) do { ((target)->addr = ((host)->addr) & ((netmask)->addr)); } while(0)
+
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip4_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+ (mask)->addr) == \
+ ((addr2)->addr & \
+ (mask)->addr))
+#define ip4_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip4_addr_isany_val(addr1) ((addr1).addr == IPADDR_ANY)
+#define ip4_addr_isany(addr1) ((addr1) == NULL || ip4_addr_isany_val(*(addr1)))
+
+#define ip4_addr_isbroadcast(addr1, netif) ip4_addr_isbroadcast_u32((addr1)->addr, netif)
+u8_t ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif);
+
+#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr)
+u8_t ip4_addr_netmask_valid(u32_t netmask);
+
+#define ip4_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL))
+
+#define ip4_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL))
+
+#define ip4_addr_debug_print_parts(debug, a, b, c, d) \
+ LWIP_DEBUGF(debug, ("%" U16_F ".%" U16_F ".%" U16_F ".%" U16_F, a, b, c, d))
+#define ip4_addr_debug_print(debug, ipaddr) \
+ ip4_addr_debug_print_parts(debug, \
+ (u16_t)((ipaddr) != NULL ? ip4_addr1_16(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? ip4_addr2_16(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? ip4_addr3_16(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? ip4_addr4_16(ipaddr) : 0))
+#define ip4_addr_debug_print_val(debug, ipaddr) \
+ ip4_addr_debug_print_parts(debug, \
+ ip4_addr1_16_val(ipaddr), \
+ ip4_addr2_16_val(ipaddr), \
+ ip4_addr3_16_val(ipaddr), \
+ ip4_addr4_16_val(ipaddr))
+
+/* Get one byte from the 4-byte address */
+#define ip4_addr_get_byte(ipaddr, idx) (((const u8_t*)(&(ipaddr)->addr))[idx])
+#define ip4_addr1(ipaddr) ip4_addr_get_byte(ipaddr, 0)
+#define ip4_addr2(ipaddr) ip4_addr_get_byte(ipaddr, 1)
+#define ip4_addr3(ipaddr) ip4_addr_get_byte(ipaddr, 2)
+#define ip4_addr4(ipaddr) ip4_addr_get_byte(ipaddr, 3)
+/* Get one byte from the 4-byte address, but argument is 'ip4_addr_t',
+ * not a pointer */
+#define ip4_addr_get_byte_val(ipaddr, idx) ((u8_t)(((ipaddr).addr >> (idx * 8)) & 0xff))
+#define ip4_addr1_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 0)
+#define ip4_addr2_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 1)
+#define ip4_addr3_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 2)
+#define ip4_addr4_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 3)
+/* These are cast to u16_t, with the intent that they are often arguments
+ * to printf using the U16_F format from cc.h. */
+#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr))
+#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr))
+#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr))
+#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr))
+#define ip4_addr1_16_val(ipaddr) ((u16_t)ip4_addr1_val(ipaddr))
+#define ip4_addr2_16_val(ipaddr) ((u16_t)ip4_addr2_val(ipaddr))
+#define ip4_addr3_16_val(ipaddr) ((u16_t)ip4_addr3_val(ipaddr))
+#define ip4_addr4_16_val(ipaddr) ((u16_t)ip4_addr4_val(ipaddr))
+
+#define IP4ADDR_STRLEN_MAX 16
+
+/** For backwards compatibility */
+#define ip_ntoa(ipaddr) ipaddr_ntoa(ipaddr)
+
+u32_t ipaddr_addr(const char *cp);
+int ip4addr_aton(const char *cp, ip4_addr_t *addr);
+/** returns ptr to static buffer; not reentrant! */
+char *ip4addr_ntoa(const ip4_addr_t *addr);
+char *ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP_ADDR_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4_frag.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4_frag.h
new file mode 100644
index 0000000..ed5bf14
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip4_frag.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * IP fragmentation/reassembly
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Jani Monoses
+ *
+ */
+
+#ifndef LWIP_HDR_IP4_FRAG_H
+#define LWIP_HDR_IP4_FRAG_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#if LWIP_IPV4
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if IP_REASSEMBLY
+/* The IP reassembly timer interval in milliseconds. */
+#define IP_TMR_INTERVAL 1000
+
+/** IP reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip_reassdata {
+ struct ip_reassdata *next;
+ struct pbuf *p;
+ struct ip_hdr iphdr;
+ u16_t datagram_len;
+ u8_t flags;
+ u8_t timer;
+};
+
+void ip_reass_init(void);
+void ip_reass_tmr(void);
+struct pbuf * ip4_reass(struct pbuf *p);
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
+#define LWIP_PBUF_CUSTOM_REF_DEFINED
+/** A custom pbuf that holds a reference to another pbuf, which is freed
+ * when this custom pbuf is freed. This is used to create a custom PBUF_REF
+ * that points into the original pbuf. */
+struct pbuf_custom_ref {
+ /** 'base class' */
+ struct pbuf_custom pc;
+ /** pointer to the original pbuf that is referenced */
+ struct pbuf *original;
+};
+#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
+#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
+
+err_t ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest);
+#endif /* IP_FRAG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP4_FRAG_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6.h
new file mode 100644
index 0000000..f894e06
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6.h
@@ -0,0 +1,93 @@
+/**
+ * @file
+ *
+ * IPv6 layer.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+#ifndef LWIP_HDR_IP6_H
+#define LWIP_HDR_IP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/ip6.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netif *ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest);
+const ip_addr_t *ip6_select_source_address(struct netif *netif, const ip6_addr_t * dest);
+err_t ip6_input(struct pbuf *p, struct netif *inp);
+err_t ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+ u8_t hl, u8_t tc, u8_t nexth);
+err_t ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+ u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
+err_t ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+ u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
+#if LWIP_NETIF_USE_HINTS
+err_t ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+ u8_t hl, u8_t tc, u8_t nexth, struct netif_hint *netif_hint);
+#endif /* LWIP_NETIF_USE_HINTS */
+#if LWIP_IPV6_MLD
+err_t ip6_options_add_hbh_ra(struct pbuf * p, u8_t nexth, u8_t value);
+#endif /* LWIP_IPV6_MLD */
+
+#define ip6_netif_get_local_ip(netif, dest) (((netif) != NULL) ? \
+ ip6_select_source_address(netif, dest) : NULL)
+
+#if IP6_DEBUG
+void ip6_debug_print(struct pbuf *p);
+#else
+#define ip6_debug_print(p)
+#endif /* IP6_DEBUG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_IP6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_addr.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_addr.h
new file mode 100644
index 0000000..29c2a34
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_addr.h
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * IPv6 addresses.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ * Structs and macros for handling IPv6 addresses.
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+#ifndef LWIP_HDR_IP6_ADDR_H
+#define LWIP_HDR_IP6_ADDR_H
+
+#include "lwip/opt.h"
+#include "def.h"
+
+#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip6_zone.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** This is the aligned version of ip6_addr_t,
+ used as local variable, on the stack, etc. */
+struct ip6_addr {
+ u32_t addr[4];
+#if LWIP_IPV6_SCOPES
+ u8_t zone;
+#endif /* LWIP_IPV6_SCOPES */
+};
+
+/** IPv6 address */
+typedef struct ip6_addr ip6_addr_t;
+
+/** Set an IPv6 partial address given by byte-parts */
+#define IP6_ADDR_PART(ip6addr, index, a,b,c,d) \
+ (ip6addr)->addr[index] = PP_HTONL(LWIP_MAKEU32(a,b,c,d))
+
+/** Set a full IPv6 address by passing the 4 u32_t indices in network byte order
+ (use PP_HTONL() for constants) */
+#define IP6_ADDR(ip6addr, idx0, idx1, idx2, idx3) do { \
+ (ip6addr)->addr[0] = idx0; \
+ (ip6addr)->addr[1] = idx1; \
+ (ip6addr)->addr[2] = idx2; \
+ (ip6addr)->addr[3] = idx3; \
+ ip6_addr_clear_zone(ip6addr); } while(0)
+
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK1(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK2(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0])) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK3(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK4(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1])) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK5(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK6(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2])) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK7(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK8(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3])) & 0xffff))
+
+/** Copy IPv6 address - faster than ip6_addr_set: no NULL check */
+#define ip6_addr_copy(dest, src) do{(dest).addr[0] = (src).addr[0]; \
+ (dest).addr[1] = (src).addr[1]; \
+ (dest).addr[2] = (src).addr[2]; \
+ (dest).addr[3] = (src).addr[3]; \
+ ip6_addr_copy_zone((dest), (src)); }while(0)
+/** Safely copy one IPv6 address to another (src may be NULL) */
+#define ip6_addr_set(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : (src)->addr[0]; \
+ (dest)->addr[1] = (src) == NULL ? 0 : (src)->addr[1]; \
+ (dest)->addr[2] = (src) == NULL ? 0 : (src)->addr[2]; \
+ (dest)->addr[3] = (src) == NULL ? 0 : (src)->addr[3]; \
+ ip6_addr_set_zone((dest), (src) == NULL ? IP6_NO_ZONE : ip6_addr_zone(src)); }while(0)
+
+/** Copy packed IPv6 address to unpacked IPv6 address; zone is not set */
+#define ip6_addr_copy_from_packed(dest, src) do{(dest).addr[0] = (src).addr[0]; \
+ (dest).addr[1] = (src).addr[1]; \
+ (dest).addr[2] = (src).addr[2]; \
+ (dest).addr[3] = (src).addr[3]; \
+ ip6_addr_clear_zone(&dest); }while(0)
+
+/** Copy unpacked IPv6 address to packed IPv6 address; zone is lost */
+#define ip6_addr_copy_to_packed(dest, src) do{(dest).addr[0] = (src).addr[0]; \
+ (dest).addr[1] = (src).addr[1]; \
+ (dest).addr[2] = (src).addr[2]; \
+ (dest).addr[3] = (src).addr[3]; }while(0)
+
+/** Set complete address to zero */
+#define ip6_addr_set_zero(ip6addr) do{(ip6addr)->addr[0] = 0; \
+ (ip6addr)->addr[1] = 0; \
+ (ip6addr)->addr[2] = 0; \
+ (ip6addr)->addr[3] = 0; \
+ ip6_addr_clear_zone(ip6addr);}while(0)
+
+/** Set address to ipv6 'any' (no need for lwip_htonl()) */
+#define ip6_addr_set_any(ip6addr) ip6_addr_set_zero(ip6addr)
+/** Set address to ipv6 loopback address */
+#define ip6_addr_set_loopback(ip6addr) do{(ip6addr)->addr[0] = 0; \
+ (ip6addr)->addr[1] = 0; \
+ (ip6addr)->addr[2] = 0; \
+ (ip6addr)->addr[3] = PP_HTONL(0x00000001UL); \
+ ip6_addr_clear_zone(ip6addr);}while(0)
+/** Safely copy one IPv6 address to another and change byte order
+ * from host- to network-order. */
+#define ip6_addr_set_hton(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : lwip_htonl((src)->addr[0]); \
+ (dest)->addr[1] = (src) == NULL ? 0 : lwip_htonl((src)->addr[1]); \
+ (dest)->addr[2] = (src) == NULL ? 0 : lwip_htonl((src)->addr[2]); \
+ (dest)->addr[3] = (src) == NULL ? 0 : lwip_htonl((src)->addr[3]); \
+ ip6_addr_set_zone((dest), (src) == NULL ? IP6_NO_ZONE : ip6_addr_zone(src));}while(0)
+
+
+/** Compare IPv6 networks, ignoring zone information. To be used sparingly! */
+#define ip6_addr_netcmp_zoneless(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
+ ((addr1)->addr[1] == (addr2)->addr[1]))
+
+/**
+ * Determine if two IPv6 address are on the same network.
+ *
+ * @param addr1 IPv6 address 1
+ * @param addr2 IPv6 address 2
+ * @return 1 if the network identifiers of both address match, 0 if not
+ */
+#define ip6_addr_netcmp(addr1, addr2) (ip6_addr_netcmp_zoneless((addr1), (addr2)) && \
+ ip6_addr_cmp_zone((addr1), (addr2)))
+
+/* Exact-host comparison *after* ip6_addr_netcmp() succeeded, for efficiency. */
+#define ip6_addr_nethostcmp(addr1, addr2) (((addr1)->addr[2] == (addr2)->addr[2]) && \
+ ((addr1)->addr[3] == (addr2)->addr[3]))
+
+/** Compare IPv6 addresses, ignoring zone information. To be used sparingly! */
+#define ip6_addr_cmp_zoneless(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
+ ((addr1)->addr[1] == (addr2)->addr[1]) && \
+ ((addr1)->addr[2] == (addr2)->addr[2]) && \
+ ((addr1)->addr[3] == (addr2)->addr[3]))
+/**
+ * Determine if two IPv6 addresses are the same. In particular, the address
+ * part of both must be the same, and the zone must be compatible.
+ *
+ * @param addr1 IPv6 address 1
+ * @param addr2 IPv6 address 2
+ * @return 1 if the addresses are considered equal, 0 if not
+ */
+#define ip6_addr_cmp(addr1, addr2) (ip6_addr_cmp_zoneless((addr1), (addr2)) && \
+ ip6_addr_cmp_zone((addr1), (addr2)))
+
+/** Compare IPv6 address to packed address and zone */
+#define ip6_addr_cmp_packed(ip6addr, paddr, zone_idx) (((ip6addr)->addr[0] == (paddr)->addr[0]) && \
+ ((ip6addr)->addr[1] == (paddr)->addr[1]) && \
+ ((ip6addr)->addr[2] == (paddr)->addr[2]) && \
+ ((ip6addr)->addr[3] == (paddr)->addr[3]) && \
+ ip6_addr_equals_zone((ip6addr), (zone_idx)))
+
+#define ip6_get_subnet_id(ip6addr) (lwip_htonl((ip6addr)->addr[2]) & 0x0000ffffUL)
+
+#define ip6_addr_isany_val(ip6addr) (((ip6addr).addr[0] == 0) && \
+ ((ip6addr).addr[1] == 0) && \
+ ((ip6addr).addr[2] == 0) && \
+ ((ip6addr).addr[3] == 0))
+#define ip6_addr_isany(ip6addr) (((ip6addr) == NULL) || ip6_addr_isany_val(*(ip6addr)))
+
+#define ip6_addr_isloopback(ip6addr) (((ip6addr)->addr[0] == 0UL) && \
+ ((ip6addr)->addr[1] == 0UL) && \
+ ((ip6addr)->addr[2] == 0UL) && \
+ ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+
+#define ip6_addr_isglobal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xe0000000UL)) == PP_HTONL(0x20000000UL))
+
+#define ip6_addr_islinklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfe800000UL))
+
+#define ip6_addr_issitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfec00000UL))
+
+#define ip6_addr_isuniquelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xfe000000UL)) == PP_HTONL(0xfc000000UL))
+
+#define ip6_addr_isipv4mappedipv6(ip6addr) (((ip6addr)->addr[0] == 0) && ((ip6addr)->addr[1] == 0) && (((ip6addr)->addr[2]) == PP_HTONL(0x0000FFFFUL)))
+
+#define ip6_addr_ismulticast(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL))
+#define ip6_addr_multicast_transient_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00100000UL))
+#define ip6_addr_multicast_prefix_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00200000UL))
+#define ip6_addr_multicast_rendezvous_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00400000UL))
+#define ip6_addr_multicast_scope(ip6addr) ((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xf)
+#define IP6_MULTICAST_SCOPE_RESERVED 0x0
+#define IP6_MULTICAST_SCOPE_RESERVED0 0x0
+#define IP6_MULTICAST_SCOPE_INTERFACE_LOCAL 0x1
+#define IP6_MULTICAST_SCOPE_LINK_LOCAL 0x2
+#define IP6_MULTICAST_SCOPE_RESERVED3 0x3
+#define IP6_MULTICAST_SCOPE_ADMIN_LOCAL 0x4
+#define IP6_MULTICAST_SCOPE_SITE_LOCAL 0x5
+#define IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL 0x8
+#define IP6_MULTICAST_SCOPE_GLOBAL 0xe
+#define IP6_MULTICAST_SCOPE_RESERVEDF 0xf
+#define ip6_addr_ismulticast_iflocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff010000UL))
+#define ip6_addr_ismulticast_linklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff020000UL))
+#define ip6_addr_ismulticast_adminlocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff040000UL))
+#define ip6_addr_ismulticast_sitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff050000UL))
+#define ip6_addr_ismulticast_orglocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff080000UL))
+#define ip6_addr_ismulticast_global(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff0e0000UL))
+
+/* Scoping note: while interface-local and link-local multicast addresses do
+ * have a scope (i.e., they are meaningful only in the context of a particular
+ * interface), the following functions are not assigning or comparing zone
+ * indices. The reason for this is backward compatibility. Any call site that
+ * produces a non-global multicast address must assign a multicast address as
+ * appropriate itself. */
+
+#define ip6_addr_isallnodes_iflocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff010000UL)) && \
+ ((ip6addr)->addr[1] == 0UL) && \
+ ((ip6addr)->addr[2] == 0UL) && \
+ ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+
+#define ip6_addr_isallnodes_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+ ((ip6addr)->addr[1] == 0UL) && \
+ ((ip6addr)->addr[2] == 0UL) && \
+ ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+#define ip6_addr_set_allnodes_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+ (ip6addr)->addr[1] = 0; \
+ (ip6addr)->addr[2] = 0; \
+ (ip6addr)->addr[3] = PP_HTONL(0x00000001UL); \
+ ip6_addr_clear_zone(ip6addr); }while(0)
+
+#define ip6_addr_isallrouters_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+ ((ip6addr)->addr[1] == 0UL) && \
+ ((ip6addr)->addr[2] == 0UL) && \
+ ((ip6addr)->addr[3] == PP_HTONL(0x00000002UL)))
+#define ip6_addr_set_allrouters_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+ (ip6addr)->addr[1] = 0; \
+ (ip6addr)->addr[2] = 0; \
+ (ip6addr)->addr[3] = PP_HTONL(0x00000002UL); \
+ ip6_addr_clear_zone(ip6addr); }while(0)
+
+#define ip6_addr_issolicitednode(ip6addr) ( ((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+ ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
+ (((ip6addr)->addr[3] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) )
+
+#define ip6_addr_set_solicitednode(ip6addr, if_id) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+ (ip6addr)->addr[1] = 0; \
+ (ip6addr)->addr[2] = PP_HTONL(0x00000001UL); \
+ (ip6addr)->addr[3] = (PP_HTONL(0xff000000UL) | (if_id)); \
+ ip6_addr_clear_zone(ip6addr); }while(0)
+
+#define ip6_addr_cmp_solicitednode(ip6addr, sn_addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+ ((ip6addr)->addr[1] == 0) && \
+ ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
+ ((ip6addr)->addr[3] == (PP_HTONL(0xff000000UL) | (sn_addr)->addr[3])))
+
+/* IPv6 address states. */
+#define IP6_ADDR_INVALID 0x00
+#define IP6_ADDR_TENTATIVE 0x08
+#define IP6_ADDR_TENTATIVE_1 0x09 /* 1 probe sent */
+#define IP6_ADDR_TENTATIVE_2 0x0a /* 2 probes sent */
+#define IP6_ADDR_TENTATIVE_3 0x0b /* 3 probes sent */
+#define IP6_ADDR_TENTATIVE_4 0x0c /* 4 probes sent */
+#define IP6_ADDR_TENTATIVE_5 0x0d /* 5 probes sent */
+#define IP6_ADDR_TENTATIVE_6 0x0e /* 6 probes sent */
+#define IP6_ADDR_TENTATIVE_7 0x0f /* 7 probes sent */
+#define IP6_ADDR_VALID 0x10 /* This bit marks an address as valid (preferred or deprecated) */
+#define IP6_ADDR_PREFERRED 0x30
+#define IP6_ADDR_DEPRECATED 0x10 /* Same as VALID (valid but not preferred) */
+#define IP6_ADDR_DUPLICATED 0x40 /* Failed DAD test, not valid */
+
+#define IP6_ADDR_TENTATIVE_COUNT_MASK 0x07 /* 1-7 probes sent */
+
+#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID)
+#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE)
+#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID) /* Include valid, preferred, and deprecated. */
+#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED)
+#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED)
+#define ip6_addr_isduplicated(addr_state) (addr_state == IP6_ADDR_DUPLICATED)
+
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+#define IP6_ADDR_LIFE_STATIC (0)
+#define IP6_ADDR_LIFE_INFINITE (0xffffffffUL)
+#define ip6_addr_life_isstatic(addr_life) ((addr_life) == IP6_ADDR_LIFE_STATIC)
+#define ip6_addr_life_isinfinite(addr_life) ((addr_life) == IP6_ADDR_LIFE_INFINITE)
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+
+#define ip6_addr_debug_print_parts(debug, a, b, c, d, e, f, g, h) \
+ LWIP_DEBUGF(debug, ("%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F, \
+ a, b, c, d, e, f, g, h))
+#define ip6_addr_debug_print(debug, ipaddr) \
+ ip6_addr_debug_print_parts(debug, \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK1(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK2(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK3(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK4(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK5(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK6(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK7(ipaddr) : 0), \
+ (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK8(ipaddr) : 0))
+#define ip6_addr_debug_print_val(debug, ipaddr) \
+ ip6_addr_debug_print_parts(debug, \
+ IP6_ADDR_BLOCK1(&(ipaddr)), \
+ IP6_ADDR_BLOCK2(&(ipaddr)), \
+ IP6_ADDR_BLOCK3(&(ipaddr)), \
+ IP6_ADDR_BLOCK4(&(ipaddr)), \
+ IP6_ADDR_BLOCK5(&(ipaddr)), \
+ IP6_ADDR_BLOCK6(&(ipaddr)), \
+ IP6_ADDR_BLOCK7(&(ipaddr)), \
+ IP6_ADDR_BLOCK8(&(ipaddr)))
+
+#define IP6ADDR_STRLEN_MAX 46
+
+int ip6addr_aton(const char *cp, ip6_addr_t *addr);
+/** returns ptr to static buffer; not reentrant! */
+char *ip6addr_ntoa(const ip6_addr_t *addr);
+char *ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_IP6_ADDR_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_frag.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_frag.h
new file mode 100644
index 0000000..87e0e86
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_frag.h
@@ -0,0 +1,144 @@
+/**
+ * @file
+ *
+ * IPv6 fragmentation and reassembly.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+#ifndef LWIP_HDR_IP6_FRAG_H
+#define LWIP_HDR_IP6_FRAG_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/ip6.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if LWIP_IPV6 && LWIP_IPV6_REASS /* don't build if not configured for use in lwipopts.h */
+
+/** The IPv6 reassembly timer interval in milliseconds. */
+#define IP6_REASS_TMR_INTERVAL 1000
+
+/** IP6_FRAG_COPYHEADER==1: for platforms where sizeof(void*) > 4, "struct
+ * ip6_reass_helper" is too large to be stored in the IPv6 fragment header, and
+ * will bleed into the header before it, which may be the IPv6 header or an
+ * extension header. This means that for each first fragment packet, we need to
+ * 1) make a copy of some IPv6 header fields (src+dest) that we need later on,
+ * just in case we do overwrite part of the IPv6 header, and 2) make a copy of
+ * the header data that we overwrote, so that we can restore it before either
+ * completing reassembly or sending an ICMPv6 reply. The last part is true even
+ * if this setting is disabled, but if it is enabled, we need to save a bit
+ * more data (up to the size of a pointer) because we overwrite more. */
+#ifndef IPV6_FRAG_COPYHEADER
+#define IPV6_FRAG_COPYHEADER 0
+#endif
+
+/* With IPV6_FRAG_COPYHEADER==1, a helper structure may (or, depending on the
+ * presence of extensions, may not) overwrite part of the IP header. Therefore,
+ * we copy the fields that we need from the IP header for as long as the helper
+ * structure may still be in place. This is easier than temporarily restoring
+ * those fields in the IP header each time we need to perform checks on them. */
+#if IPV6_FRAG_COPYHEADER
+#define IPV6_FRAG_SRC(ipr) ((ipr)->src)
+#define IPV6_FRAG_DEST(ipr) ((ipr)->dest)
+#else /* IPV6_FRAG_COPYHEADER */
+#define IPV6_FRAG_SRC(ipr) ((ipr)->iphdr->src)
+#define IPV6_FRAG_DEST(ipr) ((ipr)->iphdr->dest)
+#endif /* IPV6_FRAG_COPYHEADER */
+
+/** IPv6 reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip6_reassdata {
+ struct ip6_reassdata *next;
+ struct pbuf *p;
+ struct ip6_hdr *iphdr; /* pointer to the first (original) IPv6 header */
+#if IPV6_FRAG_COPYHEADER
+ ip6_addr_p_t src; /* copy of the source address in the IP header */
+ ip6_addr_p_t dest; /* copy of the destination address in the IP header */
+ /* This buffer (for the part of the original header that we overwrite) will
+ * be slightly oversized, but we cannot compute the exact size from here. */
+ u8_t orig_hdr[sizeof(struct ip6_frag_hdr) + sizeof(void*)];
+#else /* IPV6_FRAG_COPYHEADER */
+ /* In this case we still need the buffer, for sending ICMPv6 replies. */
+ u8_t orig_hdr[sizeof(struct ip6_frag_hdr)];
+#endif /* IPV6_FRAG_COPYHEADER */
+ u32_t identification;
+ u16_t datagram_len;
+ u8_t nexth;
+ u8_t timer;
+#if LWIP_IPV6_SCOPES
+ u8_t src_zone; /* zone of original packet's source address */
+ u8_t dest_zone; /* zone of original packet's destination address */
+#endif /* LWIP_IPV6_SCOPES */
+};
+
+#define ip6_reass_init() /* Compatibility define */
+void ip6_reass_tmr(void);
+struct pbuf *ip6_reass(struct pbuf *p);
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
+
+#if LWIP_IPV6 && LWIP_IPV6_FRAG /* don't build if not configured for use in lwipopts.h */
+
+#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
+#define LWIP_PBUF_CUSTOM_REF_DEFINED
+/** A custom pbuf that holds a reference to another pbuf, which is freed
+ * when this custom pbuf is freed. This is used to create a custom PBUF_REF
+ * that points into the original pbuf. */
+struct pbuf_custom_ref {
+ /** 'base class' */
+ struct pbuf_custom pc;
+ /** pointer to the original pbuf that is referenced */
+ struct pbuf *original;
+};
+#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
+
+err_t ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest);
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP6_FRAG_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_zone.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_zone.h
new file mode 100644
index 0000000..525790e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip6_zone.h
@@ -0,0 +1,304 @@
+/**
+ * @file
+ *
+ * IPv6 address scopes, zones, and scoping policy.
+ *
+ * This header provides the means to implement support for IPv6 address scopes,
+ * as per RFC 4007. An address scope can be either global or more constrained.
+ * In lwIP, we say that an address "has a scope" or "is scoped" when its scope
+ * is constrained, in which case the address is meaningful only in a specific
+ * "zone." For unicast addresses, only link-local addresses have a scope; in
+ * that case, the scope is the link. For multicast addresses, there are various
+ * scopes defined by RFC 4007 and others. For any constrained scope, a system
+ * must establish a (potentially one-to-many) mapping between zones and local
+ * interfaces. For example, a link-local address is valid on only one link (its
+ * zone). That link may be attached to one or more local interfaces. The
+ * decisions on which scopes are constrained and the mapping between zones and
+ * interfaces is together what we refer to as the "scoping policy" - more on
+ * this in a bit.
+ *
+ * In lwIP, each IPv6 address has an associated zone index. This zone index may
+ * be set to "no zone" (IP6_NO_ZONE, 0) or an actual zone. We say that an
+ * address "has a zone" or "is zoned" when its zone index is *not* set to "no
+ * zone." In lwIP, in principle, each address should be "properly zoned," which
+ * means that if the address has a zone if and only if has a scope. As such, it
+ * is a rule that an unscoped (e.g., global) address must never have a zone.
+ * Even though one could argue that there is always one zone even for global
+ * scopes, this rule exists for implementation simplicity. Violation of the
+ * rule will trigger assertions or otherwise result in undesired behavior.
+ *
+ * Backward compatibility prevents us from requiring that applications always
+ * provide properly zoned addresses. We do enforce the rule that the in the
+ * lwIP link layer (everything below netif->output_ip6() and in particular ND6)
+ * *all* addresses are properly zoned. Thus, on the output paths down the
+ * stack, various places deal with the case of addresses that lack a zone.
+ * Some of them are best-effort for efficiency (e.g. the PCB bind and connect
+ * API calls' attempts to add missing zones); ultimately the IPv6 output
+ * handler (@ref ip6_output_if_src) will set a zone if necessary.
+ *
+ * Aside from dealing with scoped addresses lacking a zone, a proper IPv6
+ * implementation must also ensure that a packet with a scoped source and/or
+ * destination address does not leave its zone. This is currently implemented
+ * in the input and forward functions. However, for output, these checks are
+ * deliberately omitted in order to keep the implementation lightweight. The
+ * routing algorithm in @ref ip6_route will take decisions such that it will
+ * not cause zone violations unless the application sets bad addresses, though.
+ *
+ * In terms of scoping policy, lwIP implements the default policy from RFC 4007
+ * using macros in this file. This policy considers link-local unicast
+ * addresses and (only) interface-local and link-local multicast addresses as
+ * having a scope. For all these addresses, the zone is equal to the interface.
+ * As shown below in this file, it is possible to implement a custom policy.
+ */
+
+/*
+ * Copyright (c) 2017 The MINIX 3 Project.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: David van Moolenbroek
+ *
+ */
+#ifndef LWIP_HDR_IP6_ZONE_H
+#define LWIP_HDR_IP6_ZONE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup ip6_zones IPv6 Zones
+ * @ingroup ip6
+ * @{
+ */
+
+#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+/** Identifier for "no zone". */
+#define IP6_NO_ZONE 0
+
+#if LWIP_IPV6_SCOPES
+
+/** Zone initializer for static IPv6 address initialization, including comma. */
+#define IPADDR6_ZONE_INIT , IP6_NO_ZONE
+
+/** Return the zone index of the given IPv6 address; possibly "no zone". */
+#define ip6_addr_zone(ip6addr) ((ip6addr)->zone)
+
+/** Does the given IPv6 address have a zone set? (0/1) */
+#define ip6_addr_has_zone(ip6addr) (ip6_addr_zone(ip6addr) != IP6_NO_ZONE)
+
+/** Set the zone field of an IPv6 address to a particular value. */
+#define ip6_addr_set_zone(ip6addr, zone_idx) ((ip6addr)->zone = (zone_idx))
+
+/** Clear the zone field of an IPv6 address, setting it to "no zone". */
+#define ip6_addr_clear_zone(ip6addr) ((ip6addr)->zone = IP6_NO_ZONE)
+
+/** Copy the zone field from the second IPv6 address to the first one. */
+#define ip6_addr_copy_zone(ip6addr1, ip6addr2) ((ip6addr1).zone = (ip6addr2).zone)
+
+/** Is the zone field of the given IPv6 address equal to the given zone index? (0/1) */
+#define ip6_addr_equals_zone(ip6addr, zone_idx) ((ip6addr)->zone == (zone_idx))
+
+/** Are the zone fields of the given IPv6 addresses equal? (0/1)
+ * This macro must only be used on IPv6 addresses of the same scope. */
+#define ip6_addr_cmp_zone(ip6addr1, ip6addr2) ((ip6addr1)->zone == (ip6addr2)->zone)
+
+/** Symbolic constants for the 'type' parameters in some of the macros.
+ * These exist for efficiency only, allowing the macros to avoid certain tests
+ * when the address is known not to be of a certain type. Dead code elimination
+ * will do the rest. IP6_MULTICAST is supported but currently not optimized.
+ * @see ip6_addr_has_scope, ip6_addr_assign_zone, ip6_addr_lacks_zone.
+ */
+enum lwip_ipv6_scope_type
+{
+ /** Unknown */
+ IP6_UNKNOWN = 0,
+ /** Unicast */
+ IP6_UNICAST = 1,
+ /** Multicast */
+ IP6_MULTICAST = 2
+};
+
+/** IPV6_CUSTOM_SCOPES: together, the following three macro definitions,
+ * @ref ip6_addr_has_scope, @ref ip6_addr_assign_zone, and
+ * @ref ip6_addr_test_zone, completely define the lwIP scoping policy.
+ * The definitions below implement the default policy from RFC 4007 Sec. 6.
+ * Should an implementation desire to implement a different policy, it can
+ * define IPV6_CUSTOM_SCOPES to 1 and supply its own definitions for the three
+ * macros instead.
+ */
+#ifndef IPV6_CUSTOM_SCOPES
+#define IPV6_CUSTOM_SCOPES 0
+#endif /* !IPV6_CUSTOM_SCOPES */
+
+#if !IPV6_CUSTOM_SCOPES
+
+/**
+ * Determine whether an IPv6 address has a constrained scope, and as such is
+ * meaningful only if accompanied by a zone index to identify the scope's zone.
+ * The given address type may be used to eliminate at compile time certain
+ * checks that will evaluate to false at run time anyway.
+ *
+ * This default implementation follows the default model of RFC 4007, where
+ * only interface-local and link-local scopes are defined.
+ *
+ * Even though the unicast loopback address does have an implied link-local
+ * scope, in this implementation it does not have an explicitly assigned zone
+ * index. As such it should not be tested for in this macro.
+ *
+ * @param ip6addr the IPv6 address (const); only its address part is examined.
+ * @param type address type; see @ref lwip_ipv6_scope_type.
+ * @return 1 if the address has a constrained scope, 0 if it does not.
+ */
+#define ip6_addr_has_scope(ip6addr, type) \
+ (ip6_addr_islinklocal(ip6addr) || (((type) != IP6_UNICAST) && \
+ (ip6_addr_ismulticast_iflocal(ip6addr) || \
+ ip6_addr_ismulticast_linklocal(ip6addr))))
+
+/**
+ * Assign a zone index to an IPv6 address, based on a network interface. If the
+ * given address has a scope, the assigned zone index is that scope's zone of
+ * the given netif; otherwise, the assigned zone index is "no zone".
+ *
+ * This default implementation follows the default model of RFC 4007, where
+ * only interface-local and link-local scopes are defined, and the zone index
+ * of both of those scopes always equals the index of the network interface.
+ * As such, this default implementation need not distinguish between different
+ * constrained scopes when assigning the zone.
+ *
+ * @param ip6addr the IPv6 address; its address part is examined, and its zone
+ * index is assigned.
+ * @param type address type; see @ref lwip_ipv6_scope_type.
+ * @param netif the network interface (const).
+ */
+#define ip6_addr_assign_zone(ip6addr, type, netif) \
+ (ip6_addr_set_zone((ip6addr), \
+ ip6_addr_has_scope((ip6addr), (type)) ? netif_get_index(netif) : 0))
+
+/**
+ * Test whether an IPv6 address is "zone-compatible" with a network interface.
+ * That is, test whether the network interface is part of the zone associated
+ * with the address. For efficiency, this macro is only ever called if the
+ * given address is either scoped or zoned, and thus, it need not test this.
+ * If an address is scoped but not zoned, or zoned and not scoped, it is
+ * considered not zone-compatible with any netif.
+ *
+ * This default implementation follows the default model of RFC 4007, where
+ * only interface-local and link-local scopes are defined, and the zone index
+ * of both of those scopes always equals the index of the network interface.
+ * As such, there is always only one matching netif for a specific zone index,
+ * but all call sites of this macro currently support multiple matching netifs
+ * as well (at no additional expense in the common case).
+ *
+ * @param ip6addr the IPv6 address (const).
+ * @param netif the network interface (const).
+ * @return 1 if the address is scope-compatible with the netif, 0 if not.
+ */
+#define ip6_addr_test_zone(ip6addr, netif) \
+ (ip6_addr_equals_zone((ip6addr), netif_get_index(netif)))
+
+#endif /* !IPV6_CUSTOM_SCOPES */
+
+/** Does the given IPv6 address have a scope, and as such should also have a
+ * zone to be meaningful, but does not actually have a zone? (0/1) */
+#define ip6_addr_lacks_zone(ip6addr, type) \
+ (!ip6_addr_has_zone(ip6addr) && ip6_addr_has_scope((ip6addr), (type)))
+
+/**
+ * Try to select a zone for a scoped address that does not yet have a zone.
+ * Called from PCB bind and connect routines, for two reasons: 1) to save on
+ * this (relatively expensive) selection for every individual packet route
+ * operation and 2) to allow the application to obtain the selected zone from
+ * the PCB as is customary for e.g. getsockname/getpeername BSD socket calls.
+ *
+ * Ideally, callers would always supply a properly zoned address, in which case
+ * this function would not be needed. It exists both for compatibility with the
+ * BSD socket API (which accepts zoneless destination addresses) and for
+ * backward compatibility with pre-scoping lwIP code.
+ *
+ * It may be impossible to select a zone, e.g. if there are no netifs. In that
+ * case, the address's zone field will be left as is.
+ *
+ * @param dest the IPv6 address for which to select and set a zone.
+ * @param src source IPv6 address (const); may be equal to dest.
+ */
+#define ip6_addr_select_zone(dest, src) do { struct netif *selected_netif; \
+ selected_netif = ip6_route((src), (dest)); \
+ if (selected_netif != NULL) { \
+ ip6_addr_assign_zone((dest), IP6_UNKNOWN, selected_netif); \
+ } } while (0)
+
+/**
+ * @}
+ */
+
+#else /* LWIP_IPV6_SCOPES */
+
+#define IPADDR6_ZONE_INIT
+#define ip6_addr_zone(ip6addr) (IP6_NO_ZONE)
+#define ip6_addr_has_zone(ip6addr) (0)
+#define ip6_addr_set_zone(ip6addr, zone_idx)
+#define ip6_addr_clear_zone(ip6addr)
+#define ip6_addr_copy_zone(ip6addr1, ip6addr2)
+#define ip6_addr_equals_zone(ip6addr, zone_idx) (1)
+#define ip6_addr_cmp_zone(ip6addr1, ip6addr2) (1)
+#define IPV6_CUSTOM_SCOPES 0
+#define ip6_addr_has_scope(ip6addr, type) (0)
+#define ip6_addr_assign_zone(ip6addr, type, netif)
+#define ip6_addr_test_zone(ip6addr, netif) (1)
+#define ip6_addr_lacks_zone(ip6addr, type) (0)
+#define ip6_addr_select_zone(ip6addr, src)
+
+#endif /* LWIP_IPV6_SCOPES */
+
+#if LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG
+
+/** Verify that the given IPv6 address is properly zoned. */
+#define IP6_ADDR_ZONECHECK(ip6addr) LWIP_ASSERT("IPv6 zone check failed", \
+ ip6_addr_has_scope(ip6addr, IP6_UNKNOWN) == ip6_addr_has_zone(ip6addr))
+
+/** Verify that the given IPv6 address is properly zoned for the given netif. */
+#define IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif) LWIP_ASSERT("IPv6 netif zone check failed", \
+ ip6_addr_has_scope(ip6addr, IP6_UNKNOWN) ? \
+ (ip6_addr_has_zone(ip6addr) && \
+ (((netif) == NULL) || ip6_addr_test_zone((ip6addr), (netif)))) : \
+ !ip6_addr_has_zone(ip6addr))
+
+#else /* LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG */
+
+#define IP6_ADDR_ZONECHECK(ip6addr)
+#define IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif)
+
+#endif /* LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG */
+
+#endif /* LWIP_IPV6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP6_ZONE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip_addr.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip_addr.h
new file mode 100644
index 0000000..ee7a0c9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/ip_addr.h
@@ -0,0 +1,438 @@
+/**
+ * @file
+ * IP address API (common IPv4 and IPv6)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_IP_ADDR_H
+#define LWIP_HDR_IP_ADDR_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#include "lwip/ip4_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup ipaddr
+ * IP address types for use in ip_addr_t.type member.
+ * @see tcp_new_ip_type(), udp_new_ip_type(), raw_new_ip_type().
+ */
+enum lwip_ip_addr_type {
+ /** IPv4 */
+ IPADDR_TYPE_V4 = 0U,
+ /** IPv6 */
+ IPADDR_TYPE_V6 = 6U,
+ /** IPv4+IPv6 ("dual-stack") */
+ IPADDR_TYPE_ANY = 46U
+};
+
+#if LWIP_IPV4 && LWIP_IPV6
+/**
+ * @ingroup ipaddr
+ * A union struct for both IP version's addresses.
+ * ATTENTION: watch out for its size when adding IPv6 address scope!
+ */
+typedef struct ip_addr {
+ union {
+ ip6_addr_t ip6;
+ ip4_addr_t ip4;
+ } u_addr;
+ /** @ref lwip_ip_addr_type */
+ u8_t type;
+} ip_addr_t;
+
+extern const ip_addr_t ip_addr_any_type;
+
+/** @ingroup ip4addr */
+#define IPADDR4_INIT(u32val) { { { { u32val, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V4 }
+/** @ingroup ip4addr */
+#define IPADDR4_INIT_BYTES(a,b,c,d) IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d)))
+
+/** @ingroup ip6addr */
+#define IPADDR6_INIT(a, b, c, d) { { { { a, b, c, d } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V6 }
+/** @ingroup ip6addr */
+#define IPADDR6_INIT_HOST(a, b, c, d) { { { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V6 }
+
+/** @ingroup ipaddr */
+#define IP_IS_ANY_TYPE_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_ANY)
+/** @ingroup ipaddr */
+#define IPADDR_ANY_TYPE_INIT { { { { 0ul, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_ANY }
+
+/** @ingroup ip4addr */
+#define IP_IS_V4_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4)
+/** @ingroup ip6addr */
+#define IP_IS_V6_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V6)
+/** @ingroup ip4addr */
+#define IP_IS_V4(ipaddr) (((ipaddr) == NULL) || IP_IS_V4_VAL(*(ipaddr)))
+/** @ingroup ip6addr */
+#define IP_IS_V6(ipaddr) (((ipaddr) != NULL) && IP_IS_V6_VAL(*(ipaddr)))
+
+#define IP_SET_TYPE_VAL(ipaddr, iptype) do { (ipaddr).type = (iptype); }while(0)
+#define IP_SET_TYPE(ipaddr, iptype) do { if((ipaddr) != NULL) { IP_SET_TYPE_VAL(*(ipaddr), iptype); }}while(0)
+#define IP_GET_TYPE(ipaddr) ((ipaddr)->type)
+
+#define IP_ADDR_RAW_SIZE(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4 ? sizeof(ip4_addr_t) : sizeof(ip6_addr_t))
+
+#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) (IP_GET_TYPE(&pcb->local_ip) == IP_GET_TYPE(ipaddr))
+#define IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr) (IP_IS_ANY_TYPE_VAL(pcb->local_ip) || IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr))
+
+/** @ingroup ip6addr
+ * Convert generic ip address to specific protocol version
+ */
+#define ip_2_ip6(ipaddr) (&((ipaddr)->u_addr.ip6))
+/** @ingroup ip4addr
+ * Convert generic ip address to specific protocol version
+ */
+#define ip_2_ip4(ipaddr) (&((ipaddr)->u_addr.ip4))
+
+/** @ingroup ip4addr */
+#define IP_ADDR4(ipaddr,a,b,c,d) do { IP4_ADDR(ip_2_ip4(ipaddr),a,b,c,d); \
+ IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V4); } while(0)
+/** @ingroup ip6addr */
+#define IP_ADDR6(ipaddr,i0,i1,i2,i3) do { IP6_ADDR(ip_2_ip6(ipaddr),i0,i1,i2,i3); \
+ IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V6); } while(0)
+/** @ingroup ip6addr */
+#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3) IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3))
+
+#define ip_clear_no4(ipaddr) do { ip_2_ip6(ipaddr)->addr[1] = \
+ ip_2_ip6(ipaddr)->addr[2] = \
+ ip_2_ip6(ipaddr)->addr[3] = 0; \
+ ip6_addr_clear_zone(ip_2_ip6(ipaddr)); }while(0)
+
+/** @ingroup ipaddr */
+#define ip_addr_copy(dest, src) do{ IP_SET_TYPE_VAL(dest, IP_GET_TYPE(&src)); if(IP_IS_V6_VAL(src)){ \
+ ip6_addr_copy(*ip_2_ip6(&(dest)), *ip_2_ip6(&(src))); }else{ \
+ ip4_addr_copy(*ip_2_ip4(&(dest)), *ip_2_ip4(&(src))); ip_clear_no4(&dest); }}while(0)
+/** @ingroup ip6addr */
+#define ip_addr_copy_from_ip6(dest, src) do{ \
+ ip6_addr_copy(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0)
+/** @ingroup ip6addr */
+#define ip_addr_copy_from_ip6_packed(dest, src) do{ \
+ ip6_addr_copy_from_packed(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0)
+/** @ingroup ip4addr */
+#define ip_addr_copy_from_ip4(dest, src) do{ \
+ ip4_addr_copy(*ip_2_ip4(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V4); ip_clear_no4(&dest); }while(0)
+/** @ingroup ip4addr */
+#define ip_addr_set_ip4_u32(ipaddr, val) do{if(ipaddr){ip4_addr_set_u32(ip_2_ip4(ipaddr), val); \
+ IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ip4addr */
+#define ip_addr_set_ip4_u32_val(ipaddr, val) do{ ip4_addr_set_u32(ip_2_ip4(&(ipaddr)), val); \
+ IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }while(0)
+/** @ingroup ip4addr */
+#define ip_addr_get_ip4_u32(ipaddr) (((ipaddr) && IP_IS_V4(ipaddr)) ? \
+ ip4_addr_get_u32(ip_2_ip4(ipaddr)) : 0)
+/** @ingroup ipaddr */
+#define ip_addr_set(dest, src) do{ IP_SET_TYPE(dest, IP_GET_TYPE(src)); if(IP_IS_V6(src)){ \
+ ip6_addr_set(ip_2_ip6(dest), ip_2_ip6(src)); }else{ \
+ ip4_addr_set(ip_2_ip4(dest), ip_2_ip4(src)); ip_clear_no4(dest); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_ipaddr(dest, src) ip_addr_set(dest, src)
+/** @ingroup ipaddr */
+#define ip_addr_set_zero(ipaddr) do{ \
+ ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, 0); }while(0)
+/** @ingroup ip5addr */
+#define ip_addr_set_zero_ip4(ipaddr) do{ \
+ ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }while(0)
+/** @ingroup ip6addr */
+#define ip_addr_set_zero_ip6(ipaddr) do{ \
+ ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_any(is_ipv6, ipaddr) do{if(is_ipv6){ \
+ ip6_addr_set_any(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
+ ip4_addr_set_any(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_any_val(is_ipv6, ipaddr) do{if(is_ipv6){ \
+ ip6_addr_set_any(ip_2_ip6(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V6); }else{ \
+ ip4_addr_set_any(ip_2_ip4(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_loopback(is_ipv6, ipaddr) do{if(is_ipv6){ \
+ ip6_addr_set_loopback(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
+ ip4_addr_set_loopback(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_loopback_val(is_ipv6, ipaddr) do{if(is_ipv6){ \
+ ip6_addr_set_loopback(ip_2_ip6(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V6); }else{ \
+ ip4_addr_set_loopback(ip_2_ip4(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_hton(dest, src) do{if(IP_IS_V6(src)){ \
+ ip6_addr_set_hton(ip_2_ip6(dest), ip_2_ip6(src)); IP_SET_TYPE(dest, IPADDR_TYPE_V6); }else{ \
+ ip4_addr_set_hton(ip_2_ip4(dest), ip_2_ip4(src)); IP_SET_TYPE(dest, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_get_network(target, host, netmask) do{if(IP_IS_V6(host)){ \
+ ip4_addr_set_zero(ip_2_ip4(target)); IP_SET_TYPE(target, IPADDR_TYPE_V6); } else { \
+ ip4_addr_get_network(ip_2_ip4(target), ip_2_ip4(host), ip_2_ip4(netmask)); IP_SET_TYPE(target, IPADDR_TYPE_V4); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_netcmp(addr1, addr2, mask) ((IP_IS_V6(addr1) && IP_IS_V6(addr2)) ? \
+ 0 : \
+ ip4_addr_netcmp(ip_2_ip4(addr1), ip_2_ip4(addr2), mask))
+/** @ingroup ipaddr */
+#define ip_addr_cmp(addr1, addr2) ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \
+ ip6_addr_cmp(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \
+ ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2))))
+/** @ingroup ipaddr */
+#define ip_addr_cmp_zoneless(addr1, addr2) ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \
+ ip6_addr_cmp_zoneless(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \
+ ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2))))
+/** @ingroup ipaddr */
+#define ip_addr_isany(ipaddr) (((ipaddr) == NULL) ? 1 : ((IP_IS_V6(ipaddr)) ? \
+ ip6_addr_isany(ip_2_ip6(ipaddr)) : \
+ ip4_addr_isany(ip_2_ip4(ipaddr))))
+/** @ingroup ipaddr */
+#define ip_addr_isany_val(ipaddr) ((IP_IS_V6_VAL(ipaddr)) ? \
+ ip6_addr_isany_val(*ip_2_ip6(&(ipaddr))) : \
+ ip4_addr_isany_val(*ip_2_ip4(&(ipaddr))))
+/** @ingroup ipaddr */
+#define ip_addr_isbroadcast(ipaddr, netif) ((IP_IS_V6(ipaddr)) ? \
+ 0 : \
+ ip4_addr_isbroadcast(ip_2_ip4(ipaddr), netif))
+/** @ingroup ipaddr */
+#define ip_addr_ismulticast(ipaddr) ((IP_IS_V6(ipaddr)) ? \
+ ip6_addr_ismulticast(ip_2_ip6(ipaddr)) : \
+ ip4_addr_ismulticast(ip_2_ip4(ipaddr)))
+/** @ingroup ipaddr */
+#define ip_addr_isloopback(ipaddr) ((IP_IS_V6(ipaddr)) ? \
+ ip6_addr_isloopback(ip_2_ip6(ipaddr)) : \
+ ip4_addr_isloopback(ip_2_ip4(ipaddr)))
+/** @ingroup ipaddr */
+#define ip_addr_islinklocal(ipaddr) ((IP_IS_V6(ipaddr)) ? \
+ ip6_addr_islinklocal(ip_2_ip6(ipaddr)) : \
+ ip4_addr_islinklocal(ip_2_ip4(ipaddr)))
+#define ip_addr_debug_print(debug, ipaddr) do { if(IP_IS_V6(ipaddr)) { \
+ ip6_addr_debug_print(debug, ip_2_ip6(ipaddr)); } else { \
+ ip4_addr_debug_print(debug, ip_2_ip4(ipaddr)); }}while(0)
+#define ip_addr_debug_print_val(debug, ipaddr) do { if(IP_IS_V6_VAL(ipaddr)) { \
+ ip6_addr_debug_print_val(debug, *ip_2_ip6(&(ipaddr))); } else { \
+ ip4_addr_debug_print_val(debug, *ip_2_ip4(&(ipaddr))); }}while(0)
+char *ipaddr_ntoa(const ip_addr_t *addr);
+char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen);
+int ipaddr_aton(const char *cp, ip_addr_t *addr);
+
+/** @ingroup ipaddr */
+#define IPADDR_STRLEN_MAX IP6ADDR_STRLEN_MAX
+
+/** @ingroup ipaddr */
+#define ip4_2_ipv4_mapped_ipv6(ip6addr, ip4addr) do { \
+ (ip6addr)->addr[3] = (ip4addr)->addr; \
+ (ip6addr)->addr[2] = PP_HTONL(0x0000FFFFUL); \
+ (ip6addr)->addr[1] = 0; \
+ (ip6addr)->addr[0] = 0; \
+ ip6_addr_clear_zone(ip6addr); } while(0);
+
+/** @ingroup ipaddr */
+#define unmap_ipv4_mapped_ipv6(ip4addr, ip6addr) \
+ (ip4addr)->addr = (ip6addr)->addr[3];
+
+#define IP46_ADDR_ANY(type) (((type) == IPADDR_TYPE_V6)? IP6_ADDR_ANY : IP4_ADDR_ANY)
+
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define IP_ADDR_PCB_VERSION_MATCH(addr, pcb) 1
+#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) 1
+
+#define ip_addr_set_any_val(is_ipv6, ipaddr) ip_addr_set_any(is_ipv6, &(ipaddr))
+#define ip_addr_set_loopback_val(is_ipv6, ipaddr) ip_addr_set_loopback(is_ipv6, &(ipaddr))
+
+#if LWIP_IPV4
+
+typedef ip4_addr_t ip_addr_t;
+#define IPADDR4_INIT(u32val) { u32val }
+#define IPADDR4_INIT_BYTES(a,b,c,d) IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d)))
+#define IP_IS_V4_VAL(ipaddr) 1
+#define IP_IS_V6_VAL(ipaddr) 0
+#define IP_IS_V4(ipaddr) 1
+#define IP_IS_V6(ipaddr) 0
+#define IP_IS_ANY_TYPE_VAL(ipaddr) 0
+#define IP_SET_TYPE_VAL(ipaddr, iptype)
+#define IP_SET_TYPE(ipaddr, iptype)
+#define IP_GET_TYPE(ipaddr) IPADDR_TYPE_V4
+#define IP_ADDR_RAW_SIZE(ipaddr) sizeof(ip4_addr_t)
+#define ip_2_ip4(ipaddr) (ipaddr)
+#define IP_ADDR4(ipaddr,a,b,c,d) IP4_ADDR(ipaddr,a,b,c,d)
+
+#define ip_addr_copy(dest, src) ip4_addr_copy(dest, src)
+#define ip_addr_copy_from_ip4(dest, src) ip4_addr_copy(dest, src)
+#define ip_addr_set_ip4_u32(ipaddr, val) ip4_addr_set_u32(ip_2_ip4(ipaddr), val)
+#define ip_addr_set_ip4_u32_val(ipaddr, val) ip_addr_set_ip4_u32(&(ipaddr), val)
+#define ip_addr_get_ip4_u32(ipaddr) ip4_addr_get_u32(ip_2_ip4(ipaddr))
+#define ip_addr_set(dest, src) ip4_addr_set(dest, src)
+#define ip_addr_set_ipaddr(dest, src) ip4_addr_set(dest, src)
+#define ip_addr_set_zero(ipaddr) ip4_addr_set_zero(ipaddr)
+#define ip_addr_set_zero_ip4(ipaddr) ip4_addr_set_zero(ipaddr)
+#define ip_addr_set_any(is_ipv6, ipaddr) ip4_addr_set_any(ipaddr)
+#define ip_addr_set_loopback(is_ipv6, ipaddr) ip4_addr_set_loopback(ipaddr)
+#define ip_addr_set_hton(dest, src) ip4_addr_set_hton(dest, src)
+#define ip_addr_get_network(target, host, mask) ip4_addr_get_network(target, host, mask)
+#define ip_addr_netcmp(addr1, addr2, mask) ip4_addr_netcmp(addr1, addr2, mask)
+#define ip_addr_cmp(addr1, addr2) ip4_addr_cmp(addr1, addr2)
+#define ip_addr_isany(ipaddr) ip4_addr_isany(ipaddr)
+#define ip_addr_isany_val(ipaddr) ip4_addr_isany_val(ipaddr)
+#define ip_addr_isloopback(ipaddr) ip4_addr_isloopback(ipaddr)
+#define ip_addr_islinklocal(ipaddr) ip4_addr_islinklocal(ipaddr)
+#define ip_addr_isbroadcast(addr, netif) ip4_addr_isbroadcast(addr, netif)
+#define ip_addr_ismulticast(ipaddr) ip4_addr_ismulticast(ipaddr)
+#define ip_addr_debug_print(debug, ipaddr) ip4_addr_debug_print(debug, ipaddr)
+#define ip_addr_debug_print_val(debug, ipaddr) ip4_addr_debug_print_val(debug, ipaddr)
+#define ipaddr_ntoa(ipaddr) ip4addr_ntoa(ipaddr)
+#define ipaddr_ntoa_r(ipaddr, buf, buflen) ip4addr_ntoa_r(ipaddr, buf, buflen)
+#define ipaddr_aton(cp, addr) ip4addr_aton(cp, addr)
+
+#define IPADDR_STRLEN_MAX IP4ADDR_STRLEN_MAX
+
+#define IP46_ADDR_ANY(type) (IP4_ADDR_ANY)
+
+#else /* LWIP_IPV4 */
+
+typedef ip6_addr_t ip_addr_t;
+#define IPADDR6_INIT(a, b, c, d) { { a, b, c, d } IPADDR6_ZONE_INIT }
+#define IPADDR6_INIT_HOST(a, b, c, d) { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } IPADDR6_ZONE_INIT }
+#define IP_IS_V4_VAL(ipaddr) 0
+#define IP_IS_V6_VAL(ipaddr) 1
+#define IP_IS_V4(ipaddr) 0
+#define IP_IS_V6(ipaddr) 1
+#define IP_IS_ANY_TYPE_VAL(ipaddr) 0
+#define IP_SET_TYPE_VAL(ipaddr, iptype)
+#define IP_SET_TYPE(ipaddr, iptype)
+#define IP_GET_TYPE(ipaddr) IPADDR_TYPE_V6
+#define IP_ADDR_RAW_SIZE(ipaddr) sizeof(ip6_addr_t)
+#define ip_2_ip6(ipaddr) (ipaddr)
+#define IP_ADDR6(ipaddr,i0,i1,i2,i3) IP6_ADDR(ipaddr,i0,i1,i2,i3)
+#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3) IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3))
+
+#define ip_addr_copy(dest, src) ip6_addr_copy(dest, src)
+#define ip_addr_copy_from_ip6(dest, src) ip6_addr_copy(dest, src)
+#define ip_addr_copy_from_ip6_packed(dest, src) ip6_addr_copy_from_packed(dest, src)
+#define ip_addr_set(dest, src) ip6_addr_set(dest, src)
+#define ip_addr_set_ipaddr(dest, src) ip6_addr_set(dest, src)
+#define ip_addr_set_zero(ipaddr) ip6_addr_set_zero(ipaddr)
+#define ip_addr_set_zero_ip6(ipaddr) ip6_addr_set_zero(ipaddr)
+#define ip_addr_set_any(is_ipv6, ipaddr) ip6_addr_set_any(ipaddr)
+#define ip_addr_set_loopback(is_ipv6, ipaddr) ip6_addr_set_loopback(ipaddr)
+#define ip_addr_set_hton(dest, src) ip6_addr_set_hton(dest, src)
+#define ip_addr_get_network(target, host, mask) ip6_addr_set_zero(target)
+#define ip_addr_netcmp(addr1, addr2, mask) 0
+#define ip_addr_cmp(addr1, addr2) ip6_addr_cmp(addr1, addr2)
+#define ip_addr_cmp_zoneless(addr1, addr2) ip6_addr_cmp_zoneless(addr1, addr2)
+#define ip_addr_isany(ipaddr) ip6_addr_isany(ipaddr)
+#define ip_addr_isany_val(ipaddr) ip6_addr_isany_val(ipaddr)
+#define ip_addr_isloopback(ipaddr) ip6_addr_isloopback(ipaddr)
+#define ip_addr_islinklocal(ipaddr) ip6_addr_islinklocal(ipaddr)
+#define ip_addr_isbroadcast(addr, netif) 0
+#define ip_addr_ismulticast(ipaddr) ip6_addr_ismulticast(ipaddr)
+#define ip_addr_debug_print(debug, ipaddr) ip6_addr_debug_print(debug, ipaddr)
+#define ip_addr_debug_print_val(debug, ipaddr) ip6_addr_debug_print_val(debug, ipaddr)
+#define ipaddr_ntoa(ipaddr) ip6addr_ntoa(ipaddr)
+#define ipaddr_ntoa_r(ipaddr, buf, buflen) ip6addr_ntoa_r(ipaddr, buf, buflen)
+#define ipaddr_aton(cp, addr) ip6addr_aton(cp, addr)
+
+#define IPADDR_STRLEN_MAX IP6ADDR_STRLEN_MAX
+
+#define IP46_ADDR_ANY(type) (IP6_ADDR_ANY)
+
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#if LWIP_IPV4
+
+extern const ip_addr_t ip_addr_any;
+extern const ip_addr_t ip_addr_broadcast;
+
+/**
+ * @ingroup ip4addr
+ * Can be used as a fixed/const ip_addr_t
+ * for the IP wildcard.
+ * Defined to @ref IP4_ADDR_ANY when IPv4 is enabled.
+ * Defined to @ref IP6_ADDR_ANY in IPv6 only systems.
+ * Use this if you can handle IPv4 _AND_ IPv6 addresses.
+ * Use @ref IP4_ADDR_ANY or @ref IP6_ADDR_ANY when the IP
+ * type matters.
+ */
+#define IP_ADDR_ANY IP4_ADDR_ANY
+/**
+ * @ingroup ip4addr
+ * Can be used as a fixed/const ip_addr_t
+ * for the IPv4 wildcard and the broadcast address
+ */
+#define IP4_ADDR_ANY (&ip_addr_any)
+/**
+ * @ingroup ip4addr
+ * Can be used as a fixed/const ip4_addr_t
+ * for the wildcard and the broadcast address
+ */
+#define IP4_ADDR_ANY4 (ip_2_ip4(&ip_addr_any))
+
+/** @ingroup ip4addr */
+#define IP_ADDR_BROADCAST (&ip_addr_broadcast)
+/** @ingroup ip4addr */
+#define IP4_ADDR_BROADCAST (ip_2_ip4(&ip_addr_broadcast))
+
+#endif /* LWIP_IPV4*/
+
+#if LWIP_IPV6
+
+extern const ip_addr_t ip6_addr_any;
+
+/**
+ * @ingroup ip6addr
+ * IP6_ADDR_ANY can be used as a fixed ip_addr_t
+ * for the IPv6 wildcard address
+ */
+#define IP6_ADDR_ANY (&ip6_addr_any)
+/**
+ * @ingroup ip6addr
+ * IP6_ADDR_ANY6 can be used as a fixed ip6_addr_t
+ * for the IPv6 wildcard address
+ */
+#define IP6_ADDR_ANY6 (ip_2_ip6(&ip6_addr_any))
+
+#if !LWIP_IPV4
+/** IPv6-only configurations */
+#define IP_ADDR_ANY IP6_ADDR_ANY
+#endif /* !LWIP_IPV4 */
+
+#endif
+
+#if LWIP_IPV4 && LWIP_IPV6
+/** @ingroup ipaddr */
+#define IP_ANY_TYPE (&ip_addr_any_type)
+#else
+#define IP_ANY_TYPE IP_ADDR_ANY
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP_ADDR_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/mem.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/mem.h
new file mode 100644
index 0000000..ff208d2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/mem.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ * Heap API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_MEM_H
+#define LWIP_HDR_MEM_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if MEM_LIBC_MALLOC
+
+#include "lwip/arch.h"
+
+typedef size_t mem_size_t;
+#define MEM_SIZE_F SZT_F
+
+#elif MEM_USE_POOLS
+
+typedef u16_t mem_size_t;
+#define MEM_SIZE_F U16_F
+
+#else
+
+/* MEM_SIZE would have to be aligned, but using 64000 here instead of
+ * 65535 leaves some room for alignment...
+ */
+#if MEM_SIZE > 64000L
+typedef u32_t mem_size_t;
+#define MEM_SIZE_F U32_F
+#else
+typedef u16_t mem_size_t;
+#define MEM_SIZE_F U16_F
+#endif /* MEM_SIZE > 64000 */
+#endif
+
+void mem_init(void);
+void *mem_trim(void *mem, mem_size_t size);
+void *mem_malloc(mem_size_t size);
+void *mem_calloc(mem_size_t count, mem_size_t size);
+void mem_free(void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEM_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/memp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/memp.h
new file mode 100644
index 0000000..1630b26
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/memp.h
@@ -0,0 +1,155 @@
+/**
+ * @file
+ * Memory pool API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef LWIP_HDR_MEMP_H
+#define LWIP_HDR_MEMP_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* run once with empty definition to handle all custom includes in lwippools.h */
+#define LWIP_MEMPOOL(name,num,size,desc)
+#include "lwip/priv/memp_std.h"
+
+/** Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */
+typedef enum {
+#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name,
+#include "lwip/priv/memp_std.h"
+ MEMP_MAX
+} memp_t;
+
+#include "lwip/priv/memp_priv.h"
+#include "lwip/stats.h"
+
+extern const struct memp_desc* const memp_pools[MEMP_MAX];
+
+/**
+ * @ingroup mempool
+ * Declare prototype for private memory pool if it is used in multiple files
+ */
+#define LWIP_MEMPOOL_PROTOTYPE(name) extern const struct memp_desc memp_ ## name
+
+#if MEMP_MEM_MALLOC
+
+#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
+ LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \
+ const struct memp_desc memp_ ## name = { \
+ DECLARE_LWIP_MEMPOOL_DESC(desc) \
+ LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \
+ LWIP_MEM_ALIGN_SIZE(size) \
+ };
+
+#else /* MEMP_MEM_MALLOC */
+
+/**
+ * @ingroup mempool
+ * Declare a private memory pool
+ * Private mempools example:
+ * .h: only when pool is used in multiple .c files: LWIP_MEMPOOL_PROTOTYPE(my_private_pool);
+ * .c:
+ * - in global variables section: LWIP_MEMPOOL_DECLARE(my_private_pool, 10, sizeof(foo), "Some description")
+ * - call ONCE before using pool (e.g. in some init() function): LWIP_MEMPOOL_INIT(my_private_pool);
+ * - allocate: void* my_new_mem = LWIP_MEMPOOL_ALLOC(my_private_pool);
+ * - free: LWIP_MEMPOOL_FREE(my_private_pool, my_new_mem);
+ *
+ * To relocate a pool, declare it as extern in cc.h. Example for GCC:
+ * extern u8_t \_\_attribute\_\_((section(".onchip_mem"))) memp_memory_my_private_pool_base[];
+ */
+#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
+ LWIP_DECLARE_MEMORY_ALIGNED(memp_memory_ ## name ## _base, ((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))); \
+ \
+ LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \
+ \
+ static struct memp *memp_tab_ ## name; \
+ \
+ const struct memp_desc memp_ ## name = { \
+ DECLARE_LWIP_MEMPOOL_DESC(desc) \
+ LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \
+ LWIP_MEM_ALIGN_SIZE(size), \
+ (num), \
+ memp_memory_ ## name ## _base, \
+ &memp_tab_ ## name \
+ };
+
+#endif /* MEMP_MEM_MALLOC */
+
+/**
+ * @ingroup mempool
+ * Initialize a private memory pool
+ */
+#define LWIP_MEMPOOL_INIT(name) memp_init_pool(&memp_ ## name)
+/**
+ * @ingroup mempool
+ * Allocate from a private memory pool
+ */
+#define LWIP_MEMPOOL_ALLOC(name) memp_malloc_pool(&memp_ ## name)
+/**
+ * @ingroup mempool
+ * Free element from a private memory pool
+ */
+#define LWIP_MEMPOOL_FREE(name, x) memp_free_pool(&memp_ ## name, (x))
+
+#if MEM_USE_POOLS
+/** This structure is used to save the pool one element came from.
+ * This has to be defined here as it is required for pool size calculation. */
+struct memp_malloc_helper
+{
+ memp_t poolnr;
+#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS)
+ u16_t size;
+#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */
+};
+#endif /* MEM_USE_POOLS */
+
+void memp_init(void);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_fn(memp_t type, const char* file, const int line);
+#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__)
+#else
+void *memp_malloc(memp_t type);
+#endif
+void memp_free(memp_t type, void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/mld6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/mld6.h
new file mode 100644
index 0000000..2764fdd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/mld6.h
@@ -0,0 +1,99 @@
+/**
+ * @file
+ *
+ * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710.
+ * No support for MLDv2.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+
+#ifndef LWIP_HDR_MLD6_H
+#define LWIP_HDR_MLD6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6_MLD && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MLD group */
+struct mld_group {
+ /** next link */
+ struct mld_group *next;
+ /** multicast address */
+ ip6_addr_t group_address;
+ /** signifies we were the last person to report */
+ u8_t last_reporter_flag;
+ /** current state of the group */
+ u8_t group_state;
+ /** timer for reporting */
+ u16_t timer;
+ /** counter of simultaneous uses */
+ u8_t use;
+};
+
+#define MLD6_TMR_INTERVAL 100 /* Milliseconds */
+
+err_t mld6_stop(struct netif *netif);
+void mld6_report_groups(struct netif *netif);
+void mld6_tmr(void);
+struct mld_group *mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr);
+void mld6_input(struct pbuf *p, struct netif *inp);
+err_t mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
+err_t mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
+err_t mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
+err_t mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
+
+/** @ingroup mld6
+ * Get list head of MLD6 groups for netif.
+ * Note: The allnodes group IP is NOT in the list, since it must always
+ * be received for correct IPv6 operation.
+ * @see @ref netif_set_mld_mac_filter()
+ */
+#define netif_mld6_data(netif) ((struct mld_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6_MLD && LWIP_IPV6 */
+
+#endif /* LWIP_HDR_MLD6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/nd6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/nd6.h
new file mode 100644
index 0000000..c30e624
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/nd6.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ *
+ * Neighbor discovery and stateless address autoconfiguration for IPv6.
+ * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
+ * (Address autoconfiguration).
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+
+#ifndef LWIP_HDR_ND6_H
+#define LWIP_HDR_ND6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip6_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** 1 second period */
+#define ND6_TMR_INTERVAL 1000
+
+/** Router solicitations are sent in 4 second intervals (see RFC 4861, ch. 6.3.7) */
+#ifndef ND6_RTR_SOLICITATION_INTERVAL
+#define ND6_RTR_SOLICITATION_INTERVAL 4000
+#endif
+
+struct pbuf;
+struct netif;
+
+void nd6_tmr(void);
+void nd6_input(struct pbuf *p, struct netif *inp);
+void nd6_clear_destination_cache(void);
+struct netif *nd6_find_route(const ip6_addr_t *ip6addr);
+err_t nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp);
+u16_t nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif);
+#if LWIP_ND6_TCP_REACHABILITY_HINTS
+void nd6_reachability_hint(const ip6_addr_t *ip6addr);
+#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */
+void nd6_cleanup_netif(struct netif *netif);
+#if LWIP_IPV6_MLD
+void nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state);
+#endif /* LWIP_IPV6_MLD */
+void nd6_restart_netif(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_ND6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netbuf.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netbuf.h
new file mode 100644
index 0000000..73e5425
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netbuf.h
@@ -0,0 +1,121 @@
+/**
+ * @file
+ * netbuf API (for netconn API)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_NETBUF_H
+#define LWIP_HDR_NETBUF_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This netbuf has dest-addr/port set */
+#define NETBUF_FLAG_DESTADDR 0x01
+/** This netbuf includes a checksum */
+#define NETBUF_FLAG_CHKSUM 0x02
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+#define NETBUF_FLAG_UDP_BLOCL_TX_TILL_COMPLETE 0x04
+#endif
+
+/** "Network buffer" - contains data and addressing info */
+struct netbuf {
+ struct pbuf *p, *ptr;
+ ip_addr_t addr;
+ u16_t port;
+#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY || LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ u8_t flags;
+#endif
+#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY
+ u16_t toport_chksum;
+#if LWIP_NETBUF_RECVINFO
+ ip_addr_t toaddr;
+#endif /* LWIP_NETBUF_RECVINFO */
+#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */
+};
+
+/* Network buffer functions: */
+struct netbuf * netbuf_new (void);
+void netbuf_delete (struct netbuf *buf);
+void * netbuf_alloc (struct netbuf *buf, u16_t size);
+void netbuf_free (struct netbuf *buf);
+err_t netbuf_ref (struct netbuf *buf,
+ const void *dataptr, u16_t size);
+void netbuf_chain (struct netbuf *head, struct netbuf *tail);
+
+err_t netbuf_data (struct netbuf *buf,
+ void **dataptr, u16_t *len);
+s8_t netbuf_next (struct netbuf *buf);
+void netbuf_first (struct netbuf *buf);
+
+
+#define netbuf_copy_partial(buf, dataptr, len, offset) \
+ pbuf_copy_partial((buf)->p, (dataptr), (len), (offset))
+#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0)
+#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len)
+#define netbuf_len(buf) ((buf)->p->tot_len)
+#define netbuf_fromaddr(buf) (&((buf)->addr))
+#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set(&((buf)->addr), fromaddr)
+#define netbuf_fromport(buf) ((buf)->port)
+#if LWIP_NETBUF_RECVINFO
+#define netbuf_destaddr(buf) (&((buf)->toaddr))
+#define netbuf_set_destaddr(buf, destaddr) ip_addr_set(&((buf)->toaddr), destaddr)
+#if LWIP_CHECKSUM_ON_COPY
+#define netbuf_destport(buf) (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0)
+#else /* LWIP_CHECKSUM_ON_COPY */
+#define netbuf_destport(buf) ((buf)->toport_chksum)
+#endif /* LWIP_CHECKSUM_ON_COPY */
+#endif /* LWIP_NETBUF_RECVINFO */
+#if LWIP_CHECKSUM_ON_COPY
+#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \
+ (buf)->toport_chksum = chksum; } while(0)
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#endif /* LWIP_HDR_NETBUF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netdb.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netdb.h
new file mode 100644
index 0000000..d3d15df
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netdb.h
@@ -0,0 +1,150 @@
+/**
+ * @file
+ * NETDB API (sockets)
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_NETDB_H
+#define LWIP_HDR_NETDB_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include "lwip/arch.h"
+#include "lwip/inet.h"
+#include "lwip/sockets.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* some rarely used options */
+#ifndef LWIP_DNS_API_DECLARE_H_ERRNO
+#define LWIP_DNS_API_DECLARE_H_ERRNO 1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_ERRORS
+#define LWIP_DNS_API_DEFINE_ERRORS 1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_FLAGS
+#define LWIP_DNS_API_DEFINE_FLAGS 1
+#endif
+
+#ifndef LWIP_DNS_API_DECLARE_STRUCTS
+#define LWIP_DNS_API_DECLARE_STRUCTS 1
+#endif
+
+#if LWIP_DNS_API_DEFINE_ERRORS
+/** Errors used by the DNS API functions, h_errno can be one of them */
+#define EAI_NONAME 200
+#define EAI_SERVICE 201
+#define EAI_FAIL 202
+#define EAI_MEMORY 203
+#define EAI_FAMILY 204
+
+#define HOST_NOT_FOUND 210
+#define NO_DATA 211
+#define NO_RECOVERY 212
+#define TRY_AGAIN 213
+#endif /* LWIP_DNS_API_DEFINE_ERRORS */
+
+#if LWIP_DNS_API_DEFINE_FLAGS
+/* input flags for struct addrinfo */
+#define AI_PASSIVE 0x01
+#define AI_CANONNAME 0x02
+#define AI_NUMERICHOST 0x04
+#define AI_NUMERICSERV 0x08
+#define AI_V4MAPPED 0x10
+#define AI_ALL 0x20
+#define AI_ADDRCONFIG 0x40
+#endif /* LWIP_DNS_API_DEFINE_FLAGS */
+
+#if LWIP_DNS_API_DECLARE_STRUCTS
+struct hostent {
+ char *h_name; /* Official name of the host. */
+ char **h_aliases; /* A pointer to an array of pointers to alternative host names,
+ terminated by a null pointer. */
+ int h_addrtype; /* Address type. */
+ int h_length; /* The length, in bytes, of the address. */
+ char **h_addr_list; /* A pointer to an array of pointers to network addresses (in
+ network byte order) for the host, terminated by a null pointer. */
+#define h_addr h_addr_list[0] /* for backward compatibility */
+};
+
+struct addrinfo {
+ int ai_flags; /* Input flags. */
+ int ai_family; /* Address family of socket. */
+ int ai_socktype; /* Socket type. */
+ int ai_protocol; /* Protocol of socket. */
+ socklen_t ai_addrlen; /* Length of socket address. */
+ struct sockaddr *ai_addr; /* Socket address of socket. */
+ char *ai_canonname; /* Canonical name of service location. */
+ struct addrinfo *ai_next; /* Pointer to next in list. */
+};
+#endif /* LWIP_DNS_API_DECLARE_STRUCTS */
+
+#define NETDB_ELEM_SIZE (sizeof(struct addrinfo) + sizeof(struct sockaddr_storage) + DNS_MAX_NAME_LENGTH + 1)
+
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+/* application accessible error code set by the DNS API functions */
+extern int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/
+
+struct hostent *lwip_gethostbyname(const char *name);
+int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+ size_t buflen, struct hostent **result, int *h_errnop);
+void lwip_freeaddrinfo(struct addrinfo *ai);
+int lwip_getaddrinfo(const char *nodename,
+ const char *servname,
+ const struct addrinfo *hints,
+ struct addrinfo **res);
+
+#if LWIP_COMPAT_SOCKETS
+/** @ingroup netdbapi */
+#define gethostbyname(name) lwip_gethostbyname(name)
+/** @ingroup netdbapi */
+#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
+ lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
+/** @ingroup netdbapi */
+#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo)
+/** @ingroup netdbapi */
+#define getaddrinfo(nodname, servname, hints, res) \
+ lwip_getaddrinfo(nodname, servname, hints, res)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
+
+#endif /* LWIP_HDR_NETDB_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netif.h
new file mode 100644
index 0000000..cf91f46
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netif.h
@@ -0,0 +1,682 @@
+/**
+ * @file
+ * netif API (to be used from TCPIP thread)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_NETIF_H
+#define LWIP_HDR_NETIF_H
+
+#include "lwip/opt.h"
+
+#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF)
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses are expected to be in
+ * the same byte order as in IP_PCB. */
+
+/** Must be the maximum of all used hardware address lengths
+ across all types of interfaces in use.
+ This does not have to be changed, normally. */
+#ifndef NETIF_MAX_HWADDR_LEN
+#define NETIF_MAX_HWADDR_LEN 6U
+#endif
+
+/** The size of a fully constructed netif name which the
+ * netif can be identified by in APIs. Composed of
+ * 2 chars, 3 (max) digits, and 1 \0
+ */
+#define NETIF_NAMESIZE 6
+
+/**
+ * @defgroup netif_flags Flags
+ * @ingroup netif
+ * @{
+ */
+
+/** Whether the network interface is 'up'. This is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ * It must be set by the startup code before this netif can be used
+ * (also for dhcp/autoip).
+ */
+#define NETIF_FLAG_UP 0x01U
+/** If set, the netif has broadcast capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_BROADCAST 0x02U
+/** If set, the interface has an active link
+ * (set by the network interface driver).
+ * Either set by the netif driver in its init function (if the link
+ * is up at that time) or at a later point once the link comes up
+ * (if link detection is supported by the hardware). */
+#define NETIF_FLAG_LINK_UP 0x04U
+/** If set, the netif is an ethernet device using ARP.
+ * Set by the netif driver in its init function.
+ * Used to check input packet types and use of DHCP. */
+#define NETIF_FLAG_ETHARP 0x08U
+/** If set, the netif is an ethernet device. It might not use
+ * ARP or TCP/IP if it is used for PPPoE only.
+ */
+#define NETIF_FLAG_ETHERNET 0x10U
+/** If set, the netif has IGMP capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_IGMP 0x20U
+/** If set, the netif has MLD6 capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_MLD6 0x40U
+
+/**
+ * @}
+ */
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+#define NETIF_ENABLE_BLOCKING_TX_FOR_PACKET 0x20
+#endif
+
+enum lwip_internal_netif_client_data_index
+{
+#if LWIP_IPV4
+#if LWIP_DHCP
+ LWIP_NETIF_CLIENT_DATA_INDEX_DHCP,
+#endif
+#if LWIP_AUTOIP
+ LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP,
+#endif
+#if LWIP_IGMP
+ LWIP_NETIF_CLIENT_DATA_INDEX_IGMP,
+#endif
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+#if LWIP_IPV6_DHCP6
+ LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6,
+#endif
+#if LWIP_IPV6_MLD
+ LWIP_NETIF_CLIENT_DATA_INDEX_MLD6,
+#endif
+#endif /* LWIP_IPV6 */
+ LWIP_NETIF_CLIENT_DATA_INDEX_MAX
+};
+
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+#define NETIF_CHECKSUM_GEN_IP 0x0001
+#define NETIF_CHECKSUM_GEN_UDP 0x0002
+#define NETIF_CHECKSUM_GEN_TCP 0x0004
+#define NETIF_CHECKSUM_GEN_ICMP 0x0008
+#define NETIF_CHECKSUM_GEN_ICMP6 0x0010
+#define NETIF_CHECKSUM_CHECK_IP 0x0100
+#define NETIF_CHECKSUM_CHECK_UDP 0x0200
+#define NETIF_CHECKSUM_CHECK_TCP 0x0400
+#define NETIF_CHECKSUM_CHECK_ICMP 0x0800
+#define NETIF_CHECKSUM_CHECK_ICMP6 0x1000
+#define NETIF_CHECKSUM_ENABLE_ALL 0xFFFF
+#define NETIF_CHECKSUM_DISABLE_ALL 0x0000
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+
+struct netif;
+
+/** MAC Filter Actions, these are passed to a netif's igmp_mac_filter or
+ * mld_mac_filter callback function. */
+enum netif_mac_filter_action {
+ /** Delete a filter entry */
+ NETIF_DEL_MAC_FILTER = 0,
+ /** Add a filter entry */
+ NETIF_ADD_MAC_FILTER = 1
+};
+
+/** Function prototype for netif init functions. Set up flags and output/linkoutput
+ * callback functions in this function.
+ *
+ * @param netif The netif to initialize
+ */
+typedef err_t (*netif_init_fn)(struct netif *netif);
+/** Function prototype for netif->input functions. This function is saved as 'input'
+ * callback function in the netif struct. Call it when a packet has been received.
+ *
+ * @param p The received packet, copied into a pbuf
+ * @param inp The netif which received the packet
+ * @return ERR_OK if the packet was handled
+ * != ERR_OK is the packet was NOT handled, in this case, the caller has
+ * to free the pbuf
+ */
+typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp);
+
+#if LWIP_IPV4
+/** Function prototype for netif->output functions. Called by lwIP when a packet
+ * shall be sent. For ethernet netif, set this to 'etharp_output' and set
+ * 'linkoutput'.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (p->payload points to IP header)
+ * @param ipaddr The IP address to which the packet shall be sent
+ */
+typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p,
+ const ip4_addr_t *ipaddr);
+#endif /* LWIP_IPV4*/
+
+#if LWIP_IPV6
+/** Function prototype for netif->output_ip6 functions. Called by lwIP when a packet
+ * shall be sent. For ethernet netif, set this to 'ethip6_output' and set
+ * 'linkoutput'.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (p->payload points to IP header)
+ * @param ipaddr The IPv6 address to which the packet shall be sent
+ */
+typedef err_t (*netif_output_ip6_fn)(struct netif *netif, struct pbuf *p,
+ const ip6_addr_t *ipaddr);
+#endif /* LWIP_IPV6 */
+
+/** Function prototype for netif->linkoutput functions. Only used for ethernet
+ * netifs. This function is called by ARP when a packet shall be sent.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (raw ethernet packet)
+ */
+typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p);
+/** Function prototype for netif status- or link-callback functions. */
+typedef void (*netif_status_callback_fn)(struct netif *netif);
+#if LWIP_IPV4 && LWIP_IGMP
+/** Function prototype for netif igmp_mac_filter functions */
+typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif,
+ const ip4_addr_t *group, enum netif_mac_filter_action action);
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+/** Function prototype for netif mld_mac_filter functions */
+typedef err_t (*netif_mld_mac_filter_fn)(struct netif *netif,
+ const ip6_addr_t *group, enum netif_mac_filter_action action);
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+#if LWIP_DHCP || LWIP_AUTOIP || LWIP_IGMP || LWIP_IPV6_MLD || LWIP_IPV6_DHCP6 || (LWIP_NUM_NETIF_CLIENT_DATA > 0)
+#if LWIP_NUM_NETIF_CLIENT_DATA > 0
+u8_t netif_alloc_client_data_id(void);
+#endif
+/** @ingroup netif_cd
+ * Set client data. Obtain ID from netif_alloc_client_data_id().
+ */
+#define netif_set_client_data(netif, id, data) netif_get_client_data(netif, id) = (data)
+/** @ingroup netif_cd
+ * Get client data. Obtain ID from netif_alloc_client_data_id().
+ */
+#define netif_get_client_data(netif, id) (netif)->client_data[(id)]
+#endif
+
+#if (LWIP_IPV4 && LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) || (LWIP_IPV6 && (LWIP_ND6_NUM_DESTINATIONS > 0x7f))
+typedef u16_t netif_addr_idx_t;
+#define NETIF_ADDR_IDX_MAX 0x7FFF
+#else
+typedef u8_t netif_addr_idx_t;
+#define NETIF_ADDR_IDX_MAX 0x7F
+#endif
+
+#if LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_USE_HINTS 1
+struct netif_hint {
+ netif_addr_idx_t addr_hint;
+};
+#else /* LWIP_NETIF_HWADDRHINT */
+#define LWIP_NETIF_USE_HINTS 0
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/** Generic data structure used for all lwIP network interfaces.
+ * The following fields should be filled in by the initialization
+ * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+struct netif {
+#if !LWIP_SINGLE_NETIF
+ /** pointer to next in linked list */
+ struct netif *next;
+#endif
+
+#if LWIP_IPV4
+ /** IP address configuration in network byte order */
+ ip_addr_t ip_addr;
+ ip_addr_t netmask;
+ ip_addr_t gw;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+ /** Array of IPv6 addresses for this netif. */
+ ip_addr_t ip6_addr[LWIP_IPV6_NUM_ADDRESSES];
+ /** The state of each IPv6 address (Tentative, Preferred, etc).
+ * @see ip6_addr.h */
+ u8_t ip6_addr_state[LWIP_IPV6_NUM_ADDRESSES];
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+ /** Remaining valid and preferred lifetime of each IPv6 address, in seconds.
+ * For valid lifetimes, the special value of IP6_ADDR_LIFE_STATIC (0)
+ * indicates the address is static and has no lifetimes. */
+ u32_t ip6_addr_valid_life[LWIP_IPV6_NUM_ADDRESSES];
+ u32_t ip6_addr_pref_life[LWIP_IPV6_NUM_ADDRESSES];
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+#endif /* LWIP_IPV6 */
+ /** This function is called by the network device driver
+ * to pass a packet up the TCP/IP stack. */
+ netif_input_fn input;
+#if LWIP_IPV4
+ /** This function is called by the IP module when it wants
+ * to send a packet on the interface. This function typically
+ * first resolves the hardware address, then sends the packet.
+ * For ethernet physical layer, this is usually etharp_output() */
+ netif_output_fn output;
+#endif /* LWIP_IPV4 */
+ /** This function is called by ethernet_output() when it wants
+ * to send a packet on the interface. This function outputs
+ * the pbuf as-is on the link medium. */
+ netif_linkoutput_fn linkoutput;
+#if LWIP_IPV6
+ /** This function is called by the IPv6 module when it wants
+ * to send a packet on the interface. This function typically
+ * first resolves the hardware address, then sends the packet.
+ * For ethernet physical layer, this is usually ethip6_output() */
+ netif_output_ip6_fn output_ip6;
+#endif /* LWIP_IPV6 */
+#if LWIP_NETIF_STATUS_CALLBACK
+ /** This function is called when the netif state is set to up or down
+ */
+ netif_status_callback_fn status_callback;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+ /** This function is called when the netif link is set to up or down
+ */
+ netif_status_callback_fn link_callback;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+#if LWIP_NETIF_REMOVE_CALLBACK
+ /** This function is called when the netif has been removed */
+ netif_status_callback_fn remove_callback;
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+ /** This field can be set by the device driver and could point
+ * to state information for the device. */
+ void *state;
+#ifdef netif_get_client_data
+ void* client_data[LWIP_NETIF_CLIENT_DATA_INDEX_MAX + LWIP_NUM_NETIF_CLIENT_DATA];
+#endif
+#if LWIP_NETIF_HOSTNAME
+ /* the hostname for this netif, NULL is a valid value */
+ const char* hostname;
+#endif /* LWIP_NETIF_HOSTNAME */
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+ u16_t chksum_flags;
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
+ /** maximum transfer unit (in bytes) */
+ u16_t mtu;
+#if LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES
+ /** maximum transfer unit (in bytes), updated by RA */
+ u16_t mtu6;
+#endif /* LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES */
+ /** link level hardware address of this interface */
+ u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+ /** number of bytes used in hwaddr */
+ u8_t hwaddr_len;
+ /** flags (@see @ref netif_flags) */
+ u8_t flags;
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ /** flags that are used to support the feature where for UDP Tx, the adapter send routine
+ * returns only when the respective packet is transmitted out */
+ u8_t block_tx_till_complt;
+#endif
+ /** descriptive abbreviation */
+ char name[2];
+ /** number of this interface. Used for @ref if_api and @ref netifapi_netif,
+ * as well as for IPv6 zones */
+ u8_t num;
+#if LWIP_IPV6_AUTOCONFIG
+ /** is this netif enabled for IPv6 autoconfiguration */
+ u8_t ip6_autoconfig_enabled;
+#endif /* LWIP_IPV6_AUTOCONFIG */
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+ /** Number of Router Solicitation messages that remain to be sent. */
+ u8_t rs_count;
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+#if MIB2_STATS
+ /** link type (from "snmp_ifType" enum from snmp_mib2.h) */
+ u8_t link_type;
+ /** (estimate) link speed */
+ u32_t link_speed;
+ /** timestamp at last change made (up/down) */
+ u32_t ts;
+ /** counters */
+ struct stats_mib2_netif_ctrs mib2_counters;
+#endif /* MIB2_STATS */
+#if LWIP_IPV4 && LWIP_IGMP
+ /** This function could be called to add or delete an entry in the multicast
+ filter table of the ethernet MAC.*/
+ netif_igmp_mac_filter_fn igmp_mac_filter;
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+ /** This function could be called to add or delete an entry in the IPv6 multicast
+ filter table of the ethernet MAC. */
+ netif_mld_mac_filter_fn mld_mac_filter;
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+#if LWIP_NETIF_USE_HINTS
+ struct netif_hint *hints;
+#endif /* LWIP_NETIF_USE_HINTS */
+#if ENABLE_LOOPBACK
+ /* List of packets to be queued for ourselves. */
+ struct pbuf *loop_first;
+ struct pbuf *loop_last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+ u16_t loop_cnt_current;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+#endif /* ENABLE_LOOPBACK */
+};
+
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) do { \
+ (netif)->chksum_flags = chksumflags; } while(0)
+#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) if (((netif) == NULL) || (((netif)->chksum_flags & (chksumflag)) != 0))
+#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags)
+#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag)
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+
+#if LWIP_SINGLE_NETIF
+#define NETIF_FOREACH(netif) if (((netif) = netif_default) != NULL)
+#else /* LWIP_SINGLE_NETIF */
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+#define NETIF_FOREACH(netif) for ((netif) = netif_list; (netif) != NULL; (netif) = (netif)->next)
+#endif /* LWIP_SINGLE_NETIF */
+/** The default network interface. */
+extern struct netif *netif_default;
+
+void netif_init(void);
+
+struct netif *netif_add_noaddr(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input);
+
+#if LWIP_IPV4
+struct netif *netif_add(struct netif *netif,
+ const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+ void *state, netif_init_fn init, netif_input_fn input);
+void netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
+ const ip4_addr_t *gw);
+#else /* LWIP_IPV4 */
+struct netif *netif_add(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input);
+#endif /* LWIP_IPV4 */
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+ "et0", where the first two letters are the "name" field in the
+ netif structure, and the digit is in the num field in the same
+ structure. */
+struct netif *netif_find(const char *name);
+
+void netif_set_default(struct netif *netif);
+
+#if LWIP_IPV4
+void netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr);
+void netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask);
+void netif_set_gw(struct netif *netif, const ip4_addr_t *gw);
+/** @ingroup netif_ip4 */
+#define netif_ip4_addr(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->ip_addr)))
+/** @ingroup netif_ip4 */
+#define netif_ip4_netmask(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->netmask)))
+/** @ingroup netif_ip4 */
+#define netif_ip4_gw(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->gw)))
+/** @ingroup netif_ip4 */
+#define netif_ip_addr4(netif) ((const ip_addr_t*)&((netif)->ip_addr))
+/** @ingroup netif_ip4 */
+#define netif_ip_netmask4(netif) ((const ip_addr_t*)&((netif)->netmask))
+/** @ingroup netif_ip4 */
+#define netif_ip_gw4(netif) ((const ip_addr_t*)&((netif)->gw))
+#endif /* LWIP_IPV4 */
+
+#define netif_set_flags(netif, set_flags) do { (netif)->flags = (u8_t)((netif)->flags | (set_flags)); } while(0)
+#define netif_clear_flags(netif, clr_flags) do { (netif)->flags = (u8_t)((netif)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define netif_is_flag_set(nefif, flag) (((netif)->flags & (flag)) != 0)
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+#define netif_set_opt_block_tx(netif, set_flags) do { (netif)->block_tx_till_complt = (u8_t)((netif)->block_tx_till_complt | (set_flags)); } while(0)
+#define netif_clear_opt_block_tx(netif, clr_flags) do { (netif)->block_tx_till_complt = (u8_t)((netif)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define netif_is_opt_block_tx_set(nefif, flag) (((netif)->block_tx_till_complt & (flag)) != 0)
+#endif
+
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+/** @ingroup netif
+ * Ask if an interface is up
+ */
+#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_STATUS_CALLBACK
+void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback);
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_REMOVE_CALLBACK
+void netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback);
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+
+void netif_set_link_up(struct netif *netif);
+void netif_set_link_down(struct netif *netif);
+/** Ask if a link is up */
+#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_LINK_CALLBACK
+void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback);
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if LWIP_NETIF_HOSTNAME
+/** @ingroup netif */
+#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0)
+/** @ingroup netif */
+#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL)
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if LWIP_IGMP
+/** @ingroup netif */
+#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0)
+#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL)
+#endif /* LWIP_IGMP */
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+/** @ingroup netif */
+#define netif_set_mld_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->mld_mac_filter = function; }}while(0)
+#define netif_get_mld_mac_filter(netif) (((netif) != NULL) ? ((netif)->mld_mac_filter) : NULL)
+#define netif_mld_mac_filter(netif, addr, action) do { if((netif) && (netif)->mld_mac_filter) { (netif)->mld_mac_filter((netif), (addr), (action)); }}while(0)
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+#if ENABLE_LOOPBACK
+err_t netif_loop_output(struct netif *netif, struct pbuf *p);
+void netif_poll(struct netif *netif);
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+void netif_poll_all(void);
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+err_t netif_input(struct pbuf *p, struct netif *inp);
+
+#if LWIP_IPV6
+/** @ingroup netif_ip6 */
+#define netif_ip_addr6(netif, i) ((const ip_addr_t*)(&((netif)->ip6_addr[i])))
+/** @ingroup netif_ip6 */
+#define netif_ip6_addr(netif, i) ((const ip6_addr_t*)ip_2_ip6(&((netif)->ip6_addr[i])))
+void netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6);
+void netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3);
+#define netif_ip6_addr_state(netif, i) ((netif)->ip6_addr_state[i])
+void netif_ip6_addr_set_state(struct netif* netif, s8_t addr_idx, u8_t state);
+s8_t netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr);
+void netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit);
+err_t netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx);
+#define netif_set_ip6_autoconfig_enabled(netif, action) do { if(netif) { (netif)->ip6_autoconfig_enabled = (action); }}while(0)
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+#define netif_ip6_addr_valid_life(netif, i) \
+ (((netif) != NULL) ? ((netif)->ip6_addr_valid_life[i]) : IP6_ADDR_LIFE_STATIC)
+#define netif_ip6_addr_set_valid_life(netif, i, secs) \
+ do { if (netif != NULL) { (netif)->ip6_addr_valid_life[i] = (secs); }} while (0)
+#define netif_ip6_addr_pref_life(netif, i) \
+ (((netif) != NULL) ? ((netif)->ip6_addr_pref_life[i]) : IP6_ADDR_LIFE_STATIC)
+#define netif_ip6_addr_set_pref_life(netif, i, secs) \
+ do { if (netif != NULL) { (netif)->ip6_addr_pref_life[i] = (secs); }} while (0)
+#define netif_ip6_addr_isstatic(netif, i) \
+ (netif_ip6_addr_valid_life((netif), (i)) == IP6_ADDR_LIFE_STATIC)
+#else /* !LWIP_IPV6_ADDRESS_LIFETIMES */
+#define netif_ip6_addr_isstatic(netif, i) (1) /* all addresses are static */
+#endif /* !LWIP_IPV6_ADDRESS_LIFETIMES */
+#if LWIP_ND6_ALLOW_RA_UPDATES
+#define netif_mtu6(netif) ((netif)->mtu6)
+#else /* LWIP_ND6_ALLOW_RA_UPDATES */
+#define netif_mtu6(netif) ((netif)->mtu)
+#endif /* LWIP_ND6_ALLOW_RA_UPDATES */
+#endif /* LWIP_IPV6 */
+
+#if LWIP_NETIF_USE_HINTS
+#define NETIF_SET_HINTS(netif, netifhint) (netif)->hints = (netifhint)
+#define NETIF_RESET_HINTS(netif) (netif)->hints = NULL
+#else /* LWIP_NETIF_USE_HINTS */
+#define NETIF_SET_HINTS(netif, netifhint)
+#define NETIF_RESET_HINTS(netif)
+#endif /* LWIP_NETIF_USE_HINTS */
+
+u8_t netif_name_to_index(const char *name);
+char * netif_index_to_name(u8_t idx, char *name);
+struct netif* netif_get_by_index(u8_t idx);
+
+/* Interface indexes always start at 1 per RFC 3493, section 4, num starts at 0 (internal index is 0..254)*/
+#define netif_get_index(netif) ((u8_t)((netif)->num + 1))
+#define NETIF_NO_INDEX (0)
+
+/**
+ * @ingroup netif
+ * Extended netif status callback (NSC) reasons flags.
+ * May be extended in the future!
+ */
+typedef u16_t netif_nsc_reason_t;
+
+/* used for initialization only */
+#define LWIP_NSC_NONE 0x0000
+/** netif was added. arg: NULL. Called AFTER netif was added. */
+#define LWIP_NSC_NETIF_ADDED 0x0001
+/** netif was removed. arg: NULL. Called BEFORE netif is removed. */
+#define LWIP_NSC_NETIF_REMOVED 0x0002
+/** link changed */
+#define LWIP_NSC_LINK_CHANGED 0x0004
+/** netif administrative status changed.\n
+ * up is called AFTER netif is set up.\n
+ * down is called BEFORE the netif is actually set down. */
+#define LWIP_NSC_STATUS_CHANGED 0x0008
+/** IPv4 address has changed */
+#define LWIP_NSC_IPV4_ADDRESS_CHANGED 0x0010
+/** IPv4 gateway has changed */
+#define LWIP_NSC_IPV4_GATEWAY_CHANGED 0x0020
+/** IPv4 netmask has changed */
+#define LWIP_NSC_IPV4_NETMASK_CHANGED 0x0040
+/** called AFTER IPv4 address/gateway/netmask changes have been applied */
+#define LWIP_NSC_IPV4_SETTINGS_CHANGED 0x0080
+/** IPv6 address was added */
+#define LWIP_NSC_IPV6_SET 0x0100
+/** IPv6 address state has changed */
+#define LWIP_NSC_IPV6_ADDR_STATE_CHANGED 0x0200
+
+/** @ingroup netif
+ * Argument supplied to netif_ext_callback_fn.
+ */
+typedef union
+{
+ /** Args to LWIP_NSC_LINK_CHANGED callback */
+ struct link_changed_s
+ {
+ /** 1: up; 0: down */
+ u8_t state;
+ } link_changed;
+ /** Args to LWIP_NSC_STATUS_CHANGED callback */
+ struct status_changed_s
+ {
+ /** 1: up; 0: down */
+ u8_t state;
+ } status_changed;
+ /** Args to LWIP_NSC_IPV4_ADDRESS_CHANGED|LWIP_NSC_IPV4_GATEWAY_CHANGED|LWIP_NSC_IPV4_NETMASK_CHANGED|LWIP_NSC_IPV4_SETTINGS_CHANGED callback */
+ struct ipv4_changed_s
+ {
+ /** Old IPv4 address */
+ const ip_addr_t* old_address;
+ const ip_addr_t* old_netmask;
+ const ip_addr_t* old_gw;
+ } ipv4_changed;
+ /** Args to LWIP_NSC_IPV6_SET callback */
+ struct ipv6_set_s
+ {
+ /** Index of changed IPv6 address */
+ s8_t addr_index;
+ /** Old IPv6 address */
+ const ip_addr_t* old_address;
+ } ipv6_set;
+ /** Args to LWIP_NSC_IPV6_ADDR_STATE_CHANGED callback */
+ struct ipv6_addr_state_changed_s
+ {
+ /** Index of affected IPv6 address */
+ s8_t addr_index;
+ /** Old IPv6 address state */
+ u8_t old_state;
+ /** Affected IPv6 address */
+ const ip_addr_t* address;
+ } ipv6_addr_state_changed;
+} netif_ext_callback_args_t;
+
+/**
+ * @ingroup netif
+ * Function used for extended netif status callbacks
+ * Note: When parsing reason argument, keep in mind that more reasons may be added in the future!
+ * @param netif netif that is affected by change
+ * @param reason change reason
+ * @param args depends on reason, see reason description
+ */
+typedef void (*netif_ext_callback_fn)(struct netif* netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t* args);
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+struct netif_ext_callback;
+typedef struct netif_ext_callback
+{
+ netif_ext_callback_fn callback_fn;
+ struct netif_ext_callback* next;
+} netif_ext_callback_t;
+
+#define NETIF_DECLARE_EXT_CALLBACK(name) static netif_ext_callback_t name;
+void netif_add_ext_callback(netif_ext_callback_t* callback, netif_ext_callback_fn fn);
+void netif_remove_ext_callback(netif_ext_callback_t* callback);
+void netif_invoke_ext_callback(struct netif* netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t* args);
+#else
+#define NETIF_DECLARE_EXT_CALLBACK(name)
+#define netif_add_ext_callback(callback, fn)
+#define netif_remove_ext_callback(callback)
+#define netif_invoke_ext_callback(netif, reason, args)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netifapi.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netifapi.h
new file mode 100644
index 0000000..e063179
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/netifapi.h
@@ -0,0 +1,161 @@
+/**
+ * @file
+ * netif API (to be used from non-TCPIP threads)
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+#ifndef LWIP_HDR_NETIFAPI_H
+#define LWIP_HDR_NETIFAPI_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "lwip/priv/api_msg.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* API for application */
+#if LWIP_ARP && LWIP_IPV4
+/* Used for netfiapi_arp_* APIs */
+enum netifapi_arp_entry {
+ NETIFAPI_ARP_PERM /* Permanent entry */
+ /* Other entry types can be added here */
+};
+
+/** @ingroup netifapi_arp */
+err_t netifapi_arp_add(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, enum netifapi_arp_entry type);
+/** @ingroup netifapi_arp */
+err_t netifapi_arp_remove(const ip4_addr_t *ipaddr, enum netifapi_arp_entry type);
+#endif /* LWIP_ARP && LWIP_IPV4 */
+
+err_t netifapi_netif_add(struct netif *netif,
+#if LWIP_IPV4
+ const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+#endif /* LWIP_IPV4 */
+ void *state, netif_init_fn init, netif_input_fn input);
+
+#if LWIP_IPV4
+err_t netifapi_netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr,
+ const ip4_addr_t *netmask, const ip4_addr_t *gw);
+#endif /* LWIP_IPV4*/
+
+err_t netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc,
+ netifapi_errt_fn errtfunc);
+
+/** @ingroup netifapi_netif */
+err_t netifapi_netif_name_to_index(const char *name, u8_t *index);
+/** @ingroup netifapi_netif */
+err_t netifapi_netif_index_to_name(u8_t index, char *name);
+
+/** @ingroup netifapi_netif
+ * @see netif_remove()
+ */
+#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL)
+/** @ingroup netifapi_netif
+ * @see netif_set_up()
+ */
+#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL)
+/** @ingroup netifapi_netif
+ * @see netif_set_down()
+ */
+#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL)
+/** @ingroup netifapi_netif
+ * @see netif_set_default()
+ */
+#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL)
+/** @ingroup netifapi_netif
+ * @see netif_set_link_up()
+ */
+#define netifapi_netif_set_link_up(n) netifapi_netif_common(n, netif_set_link_up, NULL)
+/** @ingroup netifapi_netif
+ * @see netif_set_link_down()
+ */
+#define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL)
+
+/**
+ * @defgroup netifapi_dhcp4 DHCPv4
+ * @ingroup netifapi
+ * To be called from non-TCPIP threads
+ */
+/** @ingroup netifapi_dhcp4
+ * @see dhcp_start()
+ */
+#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start)
+/**
+ * @ingroup netifapi_dhcp4
+ * @deprecated Use netifapi_dhcp_release_and_stop() instead.
+ */
+#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL)
+/** @ingroup netifapi_dhcp4
+ * @see dhcp_inform()
+ */
+#define netifapi_dhcp_inform(n) netifapi_netif_common(n, dhcp_inform, NULL)
+/** @ingroup netifapi_dhcp4
+ * @see dhcp_renew()
+ */
+#define netifapi_dhcp_renew(n) netifapi_netif_common(n, NULL, dhcp_renew)
+/**
+ * @ingroup netifapi_dhcp4
+ * @deprecated Use netifapi_dhcp_release_and_stop() instead.
+ */
+#define netifapi_dhcp_release(n) netifapi_netif_common(n, NULL, dhcp_release)
+/** @ingroup netifapi_dhcp4
+ * @see dhcp_release_and_stop()
+ */
+#define netifapi_dhcp_release_and_stop(n) netifapi_netif_common(n, dhcp_release_and_stop, NULL)
+
+/**
+ * @defgroup netifapi_autoip AUTOIP
+ * @ingroup netifapi
+ * To be called from non-TCPIP threads
+ */
+/** @ingroup netifapi_autoip
+ * @see autoip_start()
+ */
+#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start)
+/** @ingroup netifapi_autoip
+ * @see autoip_stop()
+ */
+#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETIF_API */
+
+#endif /* LWIP_HDR_NETIFAPI_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/opt.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/opt.h
new file mode 100644
index 0000000..3957dc7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/opt.h
@@ -0,0 +1,3523 @@
+/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+/*
+ * NOTE: || defined __DOXYGEN__ is a workaround for doxygen bug -
+ * without this, doxygen does not see the actual #define
+ */
+
+#if !defined LWIP_HDR_OPT_H
+#define LWIP_HDR_OPT_H
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you don't like!
+ */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+#ifdef __MICROBLAZE__
+#include "mb_interface.h"
+#endif
+
+/**
+ * @defgroup lwip_opts Options (lwipopts.h)
+ * @ingroup lwip
+ *
+ * @defgroup lwip_opts_debug Debugging
+ * @ingroup lwip_opts
+ *
+ * @defgroup lwip_opts_infrastructure Infrastructure
+ * @ingroup lwip_opts
+ *
+ * @defgroup lwip_opts_callback Callback-style APIs
+ * @ingroup lwip_opts
+ *
+ * @defgroup lwip_opts_threadsafe_apis Thread-safe APIs
+ * @ingroup lwip_opts
+ */
+
+ /*
+ ------------------------------------
+ -------------- NO SYS --------------
+ ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_nosys NO_SYS
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * NO_SYS==1: Use lwIP without OS-awareness (no thread, semaphores, mutexes or
+ * mboxes). This means threaded APIs cannot be used (socket, netconn,
+ * i.e. everything in the 'api' folder), only the callback-style raw API is
+ * available (and you have to watch out for yourself that you don't access
+ * lwIP functions/structures from more than one context at a time!)
+ */
+#if !defined NO_SYS || defined __DOXYGEN__
+#define NO_SYS 0
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_timers Timers
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_TIMERS==0: Drop support for sys_timeout and lwip-internal cyclic timers.
+ * (the array of lwip-internal cyclic timers is still provided)
+ * (check NO_SYS_NO_TIMERS for compatibility to old versions)
+ */
+#if !defined LWIP_TIMERS || defined __DOXYGEN__
+#ifdef NO_SYS_NO_TIMERS
+#define LWIP_TIMERS (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS))
+#else
+#define LWIP_TIMERS 1
+#endif
+#endif
+
+/**
+ * LWIP_TIMERS_CUSTOM==1: Provide your own timer implementation.
+ * Function prototypes in timeouts.h and the array of lwip-internal cyclic timers
+ * are still included, but the implementation is not. The following functions
+ * will be required: sys_timeouts_init(), sys_timeout(), sys_untimeout(),
+ * sys_timeouts_mbox_fetch()
+ */
+#if !defined LWIP_TIMERS_CUSTOM || defined __DOXYGEN__
+#define LWIP_TIMERS_CUSTOM 0
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_memcpy memcpy
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#if !defined MEMCPY || defined __DOXYGEN__
+#define MEMCPY(dst,src,len) memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#if !defined SMEMCPY || defined __DOXYGEN__
+#define SMEMCPY(dst,src,len) memcpy(dst,src,len)
+#endif
+
+/**
+ * MEMMOVE: override this if you have a faster implementation at hand than the
+ * one included in your C library. lwIP currently uses MEMMOVE only when IPv6
+ * fragmentation support is enabled.
+ */
+#if !defined MEMMOVE || defined __DOXYGEN__
+#define MEMMOVE(dst,src,len) memmove(dst,src,len)
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------
+ ----------- Core locking -----------
+ ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_lock Core locking and MPU
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_MPU_COMPATIBLE: enables special memory management mechanism
+ * which makes lwip able to work on MPU (Memory Protection Unit) system
+ * by not passing stack-pointers to other threads
+ * (this decreases performance as memory is allocated from pools instead
+ * of keeping it on the stack)
+ */
+#if !defined LWIP_MPU_COMPATIBLE || defined __DOXYGEN__
+#define LWIP_MPU_COMPATIBLE 0
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING
+ * Creates a global mutex that is held during TCPIP thread operations.
+ * Can be locked by client code to perform lwIP operations without changing
+ * into TCPIP thread using callbacks. See LOCK_TCPIP_CORE() and
+ * UNLOCK_TCPIP_CORE().
+ * Your system should provide mutexes supporting priority inversion to use this.
+ */
+#if !defined LWIP_TCPIP_CORE_LOCKING || defined __DOXYGEN__
+#define LWIP_TCPIP_CORE_LOCKING 1
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING_INPUT: when LWIP_TCPIP_CORE_LOCKING is enabled,
+ * this lets tcpip_input() grab the mutex for input packets as well,
+ * instead of allocating a message and passing it to tcpip_thread.
+ *
+ * ATTENTION: this does not work when tcpip_input() is called from
+ * interrupt context!
+ */
+#if !defined LWIP_TCPIP_CORE_LOCKING_INPUT || defined __DOXYGEN__
+#define LWIP_TCPIP_CORE_LOCKING_INPUT 0
+#endif
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: enable inter-task protection (and task-vs-interrupt
+ * protection) for certain critical regions during buffer allocation, deallocation
+ * and memory allocation and deallocation.
+ * ATTENTION: This is required when using lwIP from more than one context! If
+ * you disable this, you must be sure what you are doing!
+ */
+#if !defined SYS_LIGHTWEIGHT_PROT || defined __DOXYGEN__
+#define SYS_LIGHTWEIGHT_PROT 1
+#endif
+
+/**
+ * Macro/function to check whether lwIP's threading/locking
+ * requirements are satisfied during current function call.
+ * This macro usually calls a function that is implemented in the OS-dependent
+ * sys layer and performs the following checks:
+ * - Not in ISR (this should be checked for NO_SYS==1, too!)
+ * - If @ref LWIP_TCPIP_CORE_LOCKING = 1: TCPIP core lock is held
+ * - If @ref LWIP_TCPIP_CORE_LOCKING = 0: function is called from TCPIP thread
+ * @see @ref multithreading
+ */
+#if !defined LWIP_ASSERT_CORE_LOCKED || defined __DOXYGEN__
+#define LWIP_ASSERT_CORE_LOCKED()
+#endif
+
+/**
+ * Called as first thing in the lwIP TCPIP thread. Can be used in conjunction
+ * with @ref LWIP_ASSERT_CORE_LOCKED to check core locking.
+ * @see @ref multithreading
+ */
+#if !defined LWIP_MARK_TCPIP_THREAD || defined __DOXYGEN__
+#define LWIP_MARK_TCPIP_THREAD()
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------
+ ---------- Memory options ----------
+ ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_mem Heap and memory pools
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#if !defined MEM_LIBC_MALLOC || defined __DOXYGEN__
+#define MEM_LIBC_MALLOC 0
+#endif
+
+/**
+ * MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+ * Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+ * speed (heap alloc can be much slower than pool alloc) and usage from interrupts
+ * (especially if your netif driver allocates PBUF_POOL pbufs for received frames
+ * from interrupt)!
+ * ATTENTION: Currently, this uses the heap for ALL pools (also for private pools,
+ * not only for internal pools defined in memp_std.h)!
+ */
+#if !defined MEMP_MEM_MALLOC || defined __DOXYGEN__
+#define MEMP_MEM_MALLOC 0
+#endif
+
+/**
+ * MEMP_MEM_INIT==1: Force use of memset to initialize pool memory.
+ * Useful if pool are moved in uninitialized section of memory. This will ensure
+ * default values in pcbs struct are well initialized in all conditions.
+ */
+#if !defined MEMP_MEM_INIT || defined __DOXYGEN__
+#define MEMP_MEM_INIT 0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ * 4 byte alignment -> \#define MEM_ALIGNMENT 4
+ * 2 byte alignment -> \#define MEM_ALIGNMENT 2
+ */
+#if !defined MEM_ALIGNMENT || defined __DOXYGEN__
+#define MEM_ALIGNMENT 1
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#if !defined MEM_SIZE || defined __DOXYGEN__
+#define MEM_SIZE 1600
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ * MEMP_OVERFLOW_CHECK == 0 no checking
+ * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ * memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#if !defined MEMP_OVERFLOW_CHECK || defined __DOXYGEN__
+#define MEMP_OVERFLOW_CHECK 0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#if !defined MEMP_SANITY_CHECK || defined __DOXYGEN__
+#define MEMP_SANITY_CHECK 0
+#endif
+
+/**
+ * MEM_OVERFLOW_CHECK: mem overflow protection reserves a configurable
+ * amount of bytes before and after each heap allocation chunk and fills
+ * it with a prominent default value.
+ * MEM_OVERFLOW_CHECK == 0 no checking
+ * MEM_OVERFLOW_CHECK == 1 checks each element when it is freed
+ * MEM_OVERFLOW_CHECK >= 2 checks all heap elements every time
+ * mem_malloc() or mem_free() is called (useful but slow!)
+ */
+#if !defined MEM_OVERFLOW_CHECK || defined __DOXYGEN__
+#define MEM_OVERFLOW_CHECK 0
+#endif
+
+/**
+ * MEM_SANITY_CHECK==1: run a sanity check after each mem_free() to make
+ * sure that the linked list of heap elements is not corrupted.
+ */
+#if !defined MEM_SANITY_CHECK || defined __DOXYGEN__
+#define MEM_SANITY_CHECK 0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the length needed is returned.
+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
+ */
+#if !defined MEM_USE_POOLS || defined __DOXYGEN__
+#define MEM_USE_POOLS 0
+#endif
+
+/**
+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
+ * reliable. */
+#if !defined MEM_USE_POOLS_TRY_BIGGER_POOL || defined __DOXYGEN__
+#define MEM_USE_POOLS_TRY_BIGGER_POOL 0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your
+ * include path somewhere.
+ */
+#if !defined MEMP_USE_CUSTOM_POOLS || defined __DOXYGEN__
+#define MEMP_USE_CUSTOM_POOLS 0
+#endif
+
+/**
+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
+ * interrupt context (or another context that doesn't allow waiting for a
+ * semaphore).
+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
+ * with each loop so that mem_free can run.
+ *
+ * ATTENTION: As you can see from the above description, this leads to dis-/
+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
+ * can need longer.
+ *
+ * If you don't want that, at least for NO_SYS=0, you can still use the following
+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
+ * context:
+ * - pbuf_free_callback(p);
+ * - mem_free_callback(m);
+ */
+#if !defined LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT || defined __DOXYGEN__
+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------------------
+ ---------- Internal Memory Pool Sizes ----------
+ ------------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_memp Internal memory pools
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#if !defined MEMP_NUM_PBUF || defined __DOXYGEN__
+#define MEMP_NUM_PBUF 16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#if !defined MEMP_NUM_RAW_PCB || defined __DOXYGEN__
+#define MEMP_NUM_RAW_PCB 4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#if !defined MEMP_NUM_UDP_PCB || defined __DOXYGEN__
+#define MEMP_NUM_UDP_PCB 4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#if !defined MEMP_NUM_TCP_PCB || defined __DOXYGEN__
+#define MEMP_NUM_TCP_PCB 5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#if !defined MEMP_NUM_TCP_PCB_LISTEN || defined __DOXYGEN__
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#if !defined MEMP_NUM_TCP_SEG || defined __DOXYGEN__
+#define MEMP_NUM_TCP_SEG 16
+#endif
+
+/**
+ * MEMP_NUM_ALTCP_PCB: the number of simultaneously active altcp layer pcbs.
+ * (requires the LWIP_ALTCP option)
+ * Connections with multiple layers require more than one altcp_pcb (e.g. TLS
+ * over TCP requires 2 altcp_pcbs, one for TLS and one for TCP).
+ */
+#if !defined MEMP_NUM_ALTCP_PCB || defined __DOXYGEN__
+#define MEMP_NUM_ALTCP_PCB MEMP_NUM_TCP_PCB
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#if !defined MEMP_NUM_REASSDATA || defined __DOXYGEN__
+#define MEMP_NUM_REASSDATA 5
+#endif
+
+/**
+ * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent
+ * (fragments, not whole packets!).
+ * This is only used with LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1
+ * with DMA-enabled MACs where the packet is not yet sent when netif->output
+ * returns.
+ */
+#if !defined MEMP_NUM_FRAG_PBUF || defined __DOXYGEN__
+#define MEMP_NUM_FRAG_PBUF 15
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simultaneously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#if !defined MEMP_NUM_ARP_QUEUE || defined __DOXYGEN__
+#define MEMP_NUM_ARP_QUEUE 30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members at the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#if !defined MEMP_NUM_IGMP_GROUP || defined __DOXYGEN__
+#define MEMP_NUM_IGMP_GROUP 8
+#endif
+
+/**
+ * The number of sys timeouts used by the core stack (not apps)
+ * The default number of timeouts is calculated here for all enabled modules.
+ */
+#define LWIP_NUM_SYS_TIMEOUT_INTERNAL (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_NUM_TIMEOUTS + (LWIP_IPV6 * (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD)))
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active timeouts.
+ * The default number of timeouts is calculated here for all enabled modules.
+ * The formula expects settings to be either '0' or '1'.
+ */
+#if !defined MEMP_NUM_SYS_TIMEOUT || defined __DOXYGEN__
+#define MEMP_NUM_SYS_TIMEOUT LWIP_NUM_SYS_TIMEOUT_INTERNAL
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#if !defined MEMP_NUM_NETBUF || defined __DOXYGEN__
+#define MEMP_NUM_NETBUF 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#if !defined MEMP_NUM_NETCONN || defined __DOXYGEN__
+#define MEMP_NUM_NETCONN 4
+#endif
+
+/**
+ * MEMP_NUM_SELECT_CB: the number of struct lwip_select_cb.
+ * (Only needed if you have LWIP_MPU_COMPATIBLE==1 and use the socket API.
+ * In that case, you need one per thread calling lwip_select.)
+ */
+#if !defined MEMP_NUM_SELECT_CB || defined __DOXYGEN__
+#define MEMP_NUM_SELECT_CB 4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication.
+ * (only needed if you use tcpip.c)
+ */
+#if !defined MEMP_NUM_TCPIP_MSG_API || defined __DOXYGEN__
+#define MEMP_NUM_TCPIP_MSG_API 8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets.
+ * (only needed if you use tcpip.c)
+ */
+#if !defined MEMP_NUM_TCPIP_MSG_INPKT || defined __DOXYGEN__
+#define MEMP_NUM_TCPIP_MSG_INPKT 8
+#endif
+
+/**
+ * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls
+ * (before freeing the corresponding memory using lwip_freeaddrinfo()).
+ */
+#if !defined MEMP_NUM_NETDB || defined __DOXYGEN__
+#define MEMP_NUM_NETDB 1
+#endif
+
+/**
+ * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list
+ * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
+ */
+#if !defined MEMP_NUM_LOCALHOSTLIST || defined __DOXYGEN__
+#define MEMP_NUM_LOCALHOSTLIST 1
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
+ */
+#if !defined PBUF_POOL_SIZE || defined __DOXYGEN__
+#define PBUF_POOL_SIZE 16
+#endif
+
+/** MEMP_NUM_API_MSG: the number of concurrently active calls to various
+ * socket, netconn, and tcpip functions
+ */
+#if !defined MEMP_NUM_API_MSG || defined __DOXYGEN__
+#define MEMP_NUM_API_MSG MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_DNS_API_MSG: the number of concurrently active calls to netconn_gethostbyname
+ */
+#if !defined MEMP_NUM_DNS_API_MSG || defined __DOXYGEN__
+#define MEMP_NUM_DNS_API_MSG MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: the number of concurrently active calls
+ * to getsockopt/setsockopt
+ */
+#if !defined MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA || defined __DOXYGEN__
+#define MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_NETIFAPI_MSG: the number of concurrently active calls to the
+ * netifapi functions
+ */
+#if !defined MEMP_NUM_NETIFAPI_MSG || defined __DOXYGEN__
+#define MEMP_NUM_NETIFAPI_MSG MEMP_NUM_TCPIP_MSG_API
+#endif
+/**
+ * @}
+ */
+
+/*
+ ---------------------------------
+ ---------- ARP options ----------
+ ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_arp ARP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#if !defined LWIP_ARP || defined __DOXYGEN__
+#define LWIP_ARP 1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#if !defined ARP_TABLE_SIZE || defined __DOXYGEN__
+#define ARP_TABLE_SIZE 10
+#endif
+
+/** the time an ARP entry stays valid after its last update,
+ * for ARP_TMR_INTERVAL = 1000, this is
+ * (60 * 5) seconds = 5 minutes.
+ */
+#if !defined ARP_MAXAGE || defined __DOXYGEN__
+#define ARP_MAXAGE 300
+#endif
+
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#if !defined ARP_QUEUEING || defined __DOXYGEN__
+#define ARP_QUEUEING 0
+#endif
+
+/** The maximum number of packets which may be queued for each
+ * unresolved address by other network layers. Defaults to 3, 0 means disabled.
+ * Old packets are dropped, new packets are queued.
+ */
+#if !defined ARP_QUEUE_LEN || defined __DOXYGEN__
+#define ARP_QUEUE_LEN 3
+#endif
+
+/**
+ * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with
+ * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and
+ * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers.
+ * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
+ * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
+ * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
+ * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan)
+ * that returns 1 to accept a packet or 0 to drop a packet.
+ */
+#if !defined ETHARP_SUPPORT_VLAN || defined __DOXYGEN__
+#define ETHARP_SUPPORT_VLAN 0
+#endif
+
+/** LWIP_ETHERNET==1: enable ethernet support even though ARP might be disabled
+ */
+#if !defined LWIP_ETHERNET || defined __DOXYGEN__
+#define LWIP_ETHERNET LWIP_ARP
+#endif
+
+/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure
+ * alignment of payload after that header. Since the header is 14 bytes long,
+ * without this padding e.g. addresses in the IP header will not be aligned
+ * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms.
+ */
+#if !defined ETH_PAD_SIZE || defined __DOXYGEN__
+#define ETH_PAD_SIZE 0
+#endif
+
+/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table
+ * entries (using etharp_add_static_entry/etharp_remove_static_entry).
+ */
+#if !defined ETHARP_SUPPORT_STATIC_ENTRIES || defined __DOXYGEN__
+#define ETHARP_SUPPORT_STATIC_ENTRIES 0
+#endif
+
+/** ETHARP_TABLE_MATCH_NETIF==1: Match netif for ARP table entries.
+ * If disabled, duplicate IP address on multiple netifs are not supported
+ * (but this should only occur for AutoIP).
+ */
+#if !defined ETHARP_TABLE_MATCH_NETIF || defined __DOXYGEN__
+#define ETHARP_TABLE_MATCH_NETIF !LWIP_SINGLE_NETIF
+#endif
+/**
+ * @}
+ */
+
+/*
+ --------------------------------
+ ---------- IP options ----------
+ --------------------------------
+*/
+/**
+ * @defgroup lwip_opts_ipv4 IPv4
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * LWIP_IPV4==1: Enable IPv4
+ */
+#if !defined LWIP_IPV4 || defined __DOXYGEN__
+#define LWIP_IPV4 1
+#endif
+
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#if !defined IP_FORWARD || defined __DOXYGEN__
+#define IP_FORWARD 0
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#if !defined IP_REASSEMBLY || defined __DOXYGEN__
+#define IP_REASSEMBLY 1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#if !defined IP_FRAG || defined __DOXYGEN__
+#define IP_FRAG 1
+#endif
+
+#if !LWIP_IPV4
+/* disable IPv4 extensions when IPv4 is disabled */
+#undef IP_FORWARD
+#define IP_FORWARD 0
+#undef IP_REASSEMBLY
+#define IP_REASSEMBLY 0
+#undef IP_FRAG
+#define IP_FRAG 0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#if !defined IP_OPTIONS_ALLOWED || defined __DOXYGEN__
+#define IP_OPTIONS_ALLOWED 1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#if !defined IP_REASS_MAXAGE || defined __DOXYGEN__
+#define IP_REASS_MAXAGE 15
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ * When IPv4 *and* IPv6 are enabled, this even changes to
+ * (PBUF_POOL_SIZE > 2 * IP_REASS_MAX_PBUFS)!
+ */
+#if !defined IP_REASS_MAX_PBUFS || defined __DOXYGEN__
+#define IP_REASS_MAX_PBUFS 10
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#if !defined IP_DEFAULT_TTL || defined __DOXYGEN__
+#define IP_DEFAULT_TTL 255
+#endif
+
+/**
+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
+ * filter per pcb on udp and raw send operations. To enable broadcast filter
+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
+ */
+#if !defined IP_SOF_BROADCAST || defined __DOXYGEN__
+#define IP_SOF_BROADCAST 0
+#endif
+
+/**
+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
+ * filter on recv operations.
+ */
+#if !defined IP_SOF_BROADCAST_RECV || defined __DOXYGEN__
+#define IP_SOF_BROADCAST_RECV 0
+#endif
+
+/**
+ * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back
+ * out on the netif where it was received. This should only be used for
+ * wireless networks.
+ * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming
+ * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags!
+ */
+#if !defined IP_FORWARD_ALLOW_TX_ON_RX_NETIF || defined __DOXYGEN__
+#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------
+ ---------- ICMP options ----------
+ ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_icmp ICMP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#if !defined LWIP_ICMP || defined __DOXYGEN__
+#define LWIP_ICMP 1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#if !defined ICMP_TTL || defined __DOXYGEN__
+#define ICMP_TTL IP_DEFAULT_TTL
+#endif
+
+/**
+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
+ */
+#if !defined LWIP_BROADCAST_PING || defined __DOXYGEN__
+#define LWIP_BROADCAST_PING 0
+#endif
+
+/**
+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
+ */
+#if !defined LWIP_MULTICAST_PING || defined __DOXYGEN__
+#define LWIP_MULTICAST_PING 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ---------------------------------
+ ---------- RAW options ----------
+ ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_raw RAW
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#if !defined LWIP_RAW || defined __DOXYGEN__
+#define LWIP_RAW 0
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#if !defined RAW_TTL || defined __DOXYGEN__
+#define RAW_TTL IP_DEFAULT_TTL
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------
+ ---------- DHCP options ----------
+ ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_dhcp DHCP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#if !defined LWIP_DHCP || defined __DOXYGEN__
+#define LWIP_DHCP 0
+#endif
+#if !LWIP_IPV4
+/* disable DHCP when IPv4 is disabled */
+#undef LWIP_DHCP
+#define LWIP_DHCP 0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#if !defined DHCP_DOES_ARP_CHECK || defined __DOXYGEN__
+#define DHCP_DOES_ARP_CHECK (LWIP_DHCP && LWIP_ARP)
+#endif
+
+/**
+ * LWIP_DHCP_BOOTP_FILE==1: Store offered_si_addr and boot_file_name.
+ */
+#if !defined LWIP_DHCP_BOOTP_FILE || defined __DOXYGEN__
+#define LWIP_DHCP_BOOTP_FILE 0
+#endif
+
+/**
+ * LWIP_DHCP_GETS_NTP==1: Request NTP servers with discover/select. For each
+ * response packet, an callback is called, which has to be provided by the port:
+ * void dhcp_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs);
+*/
+#if !defined LWIP_DHCP_GET_NTP_SRV || defined __DOXYGEN__
+#define LWIP_DHCP_GET_NTP_SRV 0
+#endif
+
+/**
+ * The maximum of NTP servers requested
+ */
+#if !defined LWIP_DHCP_MAX_NTP_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP_MAX_NTP_SERVERS 1
+#endif
+
+/**
+ * LWIP_DHCP_MAX_DNS_SERVERS > 0: Request DNS servers with discover/select.
+ * DNS servers received in the response are passed to DNS via @ref dns_setserver()
+ * (up to the maximum limit defined here).
+ */
+#if !defined LWIP_DHCP_MAX_DNS_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP_MAX_DNS_SERVERS DNS_MAX_SERVERS
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------
+ ---------- AUTOIP options ----------
+ ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_autoip AUTOIP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#if !defined LWIP_AUTOIP || defined __DOXYGEN__
+#define LWIP_AUTOIP 0
+#endif
+#if !LWIP_IPV4
+/* disable AUTOIP when IPv4 is disabled */
+#undef LWIP_AUTOIP
+#define LWIP_AUTOIP 0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#if !defined LWIP_DHCP_AUTOIP_COOP || defined __DOXYGEN__
+#define LWIP_DHCP_AUTOIP_COOP 0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
+ * that should be sent before falling back on AUTOIP (the DHCP client keeps
+ * running in this case). This can be set as low as 1 to get an AutoIP address
+ * very quickly, but you should be prepared to handle a changing IP address
+ * when DHCP overrides AutoIP.
+ */
+#if !defined LWIP_DHCP_AUTOIP_COOP_TRIES || defined __DOXYGEN__
+#define LWIP_DHCP_AUTOIP_COOP_TRIES 9
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------
+ ----- SNMP MIB2 support -----
+ ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_mib2 SNMP MIB2 callbacks
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_MIB2_CALLBACKS==1: Turn on SNMP MIB2 callbacks.
+ * Turn this on to get callbacks needed to implement MIB2.
+ * Usually MIB2_STATS should be enabled, too.
+ */
+#if !defined LWIP_MIB2_CALLBACKS || defined __DOXYGEN__
+#define LWIP_MIB2_CALLBACKS 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------
+ -------- Multicast options -------
+ ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_multicast Multicast
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_MULTICAST_TX_OPTIONS==1: Enable multicast TX support like the socket options
+ * IP_MULTICAST_TTL/IP_MULTICAST_IF/IP_MULTICAST_LOOP, as well as (currently only)
+ * core support for the corresponding IPv6 options.
+ */
+#if !defined LWIP_MULTICAST_TX_OPTIONS || defined __DOXYGEN__
+#define LWIP_MULTICAST_TX_OPTIONS ((LWIP_IGMP || LWIP_IPV6_MLD) && (LWIP_UDP || LWIP_RAW))
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------
+ ---------- IGMP options ----------
+ ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_igmp IGMP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_IGMP==1: Turn on IGMP module.
+ */
+#if !defined LWIP_IGMP || defined __DOXYGEN__
+#define LWIP_IGMP 0
+#endif
+#if !LWIP_IPV4
+#undef LWIP_IGMP
+#define LWIP_IGMP 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------
+ ---------- DNS options -----------
+ ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_dns DNS
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#if !defined LWIP_DNS || defined __DOXYGEN__
+#define LWIP_DNS 0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#if !defined DNS_TABLE_SIZE || defined __DOXYGEN__
+#define DNS_TABLE_SIZE 4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#if !defined DNS_MAX_NAME_LENGTH || defined __DOXYGEN__
+#define DNS_MAX_NAME_LENGTH 256
+#endif
+
+/** The maximum of DNS servers
+ * The first server can be initialized automatically by defining
+ * DNS_SERVER_ADDRESS(ipaddr), where 'ipaddr' is an 'ip_addr_t*'
+ */
+#if !defined DNS_MAX_SERVERS || defined __DOXYGEN__
+#define DNS_MAX_SERVERS 2
+#endif
+
+/** DNS maximum number of retries when asking for a name, before "timeout". */
+#if !defined DNS_MAX_RETRIES || defined __DOXYGEN__
+#define DNS_MAX_RETRIES 4
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#if !defined DNS_DOES_NAME_CHECK || defined __DOXYGEN__
+#define DNS_DOES_NAME_CHECK 1
+#endif
+
+/** LWIP_DNS_SECURE: controls the security level of the DNS implementation
+ * Use all DNS security features by default.
+ * This is overridable but should only be needed by very small targets
+ * or when using against non standard DNS servers. */
+#if !defined LWIP_DNS_SECURE || defined __DOXYGEN__
+#define LWIP_DNS_SECURE (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT)
+#endif
+
+/* A list of DNS security features follows */
+#define LWIP_DNS_SECURE_RAND_XID 1
+#define LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING 2
+#define LWIP_DNS_SECURE_RAND_SRC_PORT 4
+
+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, you have to define an initializer:
+ * \#define DNS_LOCAL_HOSTLIST_INIT {DNS_LOCAL_HOSTLIST_ELEM("host_ip4", IPADDR4_INIT_BYTES(1,2,3,4)), \
+ * DNS_LOCAL_HOSTLIST_ELEM("host_ip6", IPADDR6_INIT_HOST(123, 234, 345, 456)}
+ *
+ * Instead, you can also use an external function:
+ * \#define DNS_LOOKUP_LOCAL_EXTERN(x) extern err_t my_lookup_function(const char *name, ip_addr_t *addr, u8_t dns_addrtype)
+ * that looks up the IP address and returns ERR_OK if found (LWIP_DNS_ADDRTYPE_xxx is passed in dns_addrtype).
+ */
+#if !defined DNS_LOCAL_HOSTLIST || defined __DOXYGEN__
+#define DNS_LOCAL_HOSTLIST 0
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** If this is turned on, the local host-list can be dynamically changed
+ * at runtime. */
+#if !defined DNS_LOCAL_HOSTLIST_IS_DYNAMIC || defined __DOXYGEN__
+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/** Set this to 1 to enable querying ".local" names via mDNS
+ * using a One-Shot Multicast DNS Query */
+#if !defined LWIP_DNS_SUPPORT_MDNS_QUERIES || defined __DOXYGEN__
+#define LWIP_DNS_SUPPORT_MDNS_QUERIES 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ---------------------------------
+ ---------- UDP options ----------
+ ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_udp UDP
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#if !defined LWIP_UDP || defined __DOXYGEN__
+#define LWIP_UDP 1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#if !defined LWIP_UDPLITE || defined __DOXYGEN__
+#define LWIP_UDPLITE 0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#if !defined UDP_TTL || defined __DOXYGEN__
+#define UDP_TTL IP_DEFAULT_TTL
+#endif
+
+/**
+ * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
+ */
+#if !defined LWIP_NETBUF_RECVINFO || defined __DOXYGEN__
+#define LWIP_NETBUF_RECVINFO 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ---------------------------------
+ ---------- TCP options ----------
+ ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_tcp TCP
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#if !defined LWIP_TCP || defined __DOXYGEN__
+#define LWIP_TCP 1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#if !defined TCP_TTL || defined __DOXYGEN__
+#define TCP_TTL IP_DEFAULT_TTL
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window. This must be at least
+ * (2 * TCP_MSS) for things to work well.
+ * ATTENTION: when using TCP_RCV_SCALE, TCP_WND is the total size
+ * with scaling applied. Maximum window value in the TCP header
+ * will be TCP_WND >> TCP_RCV_SCALE
+ */
+#if !defined TCP_WND || defined __DOXYGEN__
+#define TCP_WND (4 * TCP_MSS)
+#endif
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#if !defined TCP_MAXRTX || defined __DOXYGEN__
+#define TCP_MAXRTX 12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#if !defined TCP_SYNMAXRTX || defined __DOXYGEN__
+#define TCP_SYNMAXRTX 6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#if !defined TCP_QUEUE_OOSEQ || defined __DOXYGEN__
+#define TCP_QUEUE_OOSEQ LWIP_TCP
+#endif
+
+/**
+ * LWIP_TCP_SACK_OUT==1: TCP will support sending selective acknowledgements (SACKs).
+ */
+#if !defined LWIP_TCP_SACK_OUT || defined __DOXYGEN__
+#define LWIP_TCP_SACK_OUT 0
+#endif
+
+/**
+ * LWIP_TCP_MAX_SACK_NUM: The maximum number of SACK values to include in TCP segments.
+ * Must be at least 1, but is only used if LWIP_TCP_SACK_OUT is enabled.
+ * NOTE: Even though we never send more than 3 or 4 SACK ranges in a single segment
+ * (depending on other options), setting this option to values greater than 4 is not pointless.
+ * This is basically the max number of SACK ranges we want to keep track of.
+ * As new data is delivered, some of the SACK ranges may be removed or merged.
+ * In that case some of those older SACK ranges may be used again.
+ * The amount of memory used to store SACK ranges is LWIP_TCP_MAX_SACK_NUM * 8 bytes for each TCP PCB.
+ */
+#if !defined LWIP_TCP_MAX_SACK_NUM || defined __DOXYGEN__
+#define LWIP_TCP_MAX_SACK_NUM 4
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
+ * you might want to increase this.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#if !defined TCP_MSS || defined __DOXYGEN__
+#define TCP_MSS 536
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#if !defined TCP_CALCULATE_EFF_SEND_MSS || defined __DOXYGEN__
+#define TCP_CALCULATE_EFF_SEND_MSS 1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes).
+ * To achieve good performance, this should be at least 2 * TCP_MSS.
+ */
+#if !defined TCP_SND_BUF || defined __DOXYGEN__
+#define TCP_SND_BUF (2 * TCP_MSS)
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#if !defined TCP_SND_QUEUELEN || defined __DOXYGEN__
+#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than
+ * TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT).
+ */
+#if !defined TCP_SNDLOWAT || defined __DOXYGEN__
+#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1)
+#endif
+
+/**
+ * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less
+ * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below
+ * this number, select returns writable (combined with TCP_SNDLOWAT).
+ */
+#if !defined TCP_SNDQUEUELOWAT || defined __DOXYGEN__
+#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5)
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_BYTES: The default maximum number of bytes queued on ooseq per
+ * pcb if TCP_OOSEQ_BYTES_LIMIT is not defined. Default is 0 (no limit).
+ * Only valid for TCP_QUEUE_OOSEQ==1.
+ */
+#if !defined TCP_OOSEQ_MAX_BYTES || defined __DOXYGEN__
+#define TCP_OOSEQ_MAX_BYTES 0
+#endif
+
+/**
+ * TCP_OOSEQ_BYTES_LIMIT(pcb): Return the maximum number of bytes to be queued
+ * on ooseq per pcb, given the pcb. Only valid for TCP_QUEUE_OOSEQ==1 &&
+ * TCP_OOSEQ_MAX_BYTES==1.
+ * Use this to override TCP_OOSEQ_MAX_BYTES to a dynamic value per pcb.
+ */
+#if !defined TCP_OOSEQ_BYTES_LIMIT
+#if TCP_OOSEQ_MAX_BYTES
+#define TCP_OOSEQ_BYTES_LIMIT(pcb) TCP_OOSEQ_MAX_BYTES
+#elif defined __DOXYGEN__
+#define TCP_OOSEQ_BYTES_LIMIT(pcb)
+#endif
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_PBUFS: The default maximum number of pbufs queued on ooseq per
+ * pcb if TCP_OOSEQ_BYTES_LIMIT is not defined. Default is 0 (no limit).
+ * Only valid for TCP_QUEUE_OOSEQ==1.
+ */
+#if !defined TCP_OOSEQ_MAX_PBUFS || defined __DOXYGEN__
+#define TCP_OOSEQ_MAX_PBUFS 0
+#endif
+
+/**
+ * TCP_OOSEQ_PBUFS_LIMIT(pcb): Return the maximum number of pbufs to be queued
+ * on ooseq per pcb, given the pcb. Only valid for TCP_QUEUE_OOSEQ==1 &&
+ * TCP_OOSEQ_MAX_PBUFS==1.
+ * Use this to override TCP_OOSEQ_MAX_PBUFS to a dynamic value per pcb.
+ */
+#if !defined TCP_OOSEQ_PBUFS_LIMIT
+#if TCP_OOSEQ_MAX_PBUFS
+#define TCP_OOSEQ_PBUFS_LIMIT(pcb) TCP_OOSEQ_MAX_PBUFS
+#elif defined __DOXYGEN__
+#define TCP_OOSEQ_PBUFS_LIMIT(pcb)
+#endif
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#if !defined TCP_LISTEN_BACKLOG || defined __DOXYGEN__
+#define TCP_LISTEN_BACKLOG 0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#if !defined TCP_DEFAULT_LISTEN_BACKLOG || defined __DOXYGEN__
+#define TCP_DEFAULT_LISTEN_BACKLOG 0xff
+#endif
+
+/**
+ * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
+ * allocate ahead of time in an attempt to create shorter pbuf chains
+ * for transmission. The meaningful range is 0 to TCP_MSS. Some
+ * suggested values are:
+ *
+ * 0: Disable oversized allocation. Each tcp_write() allocates a new
+ pbuf (old behaviour).
+ * 1: Allocate size-aligned pbufs with minimal excess. Use this if your
+ * scatter-gather DMA requires aligned fragments.
+ * 128: Limit the pbuf/memory overhead to 20%.
+ * TCP_MSS: Try to create unfragmented TCP packets.
+ * TCP_MSS/4: Try to create 4 fragments or less per TCP packet.
+ */
+#if !defined TCP_OVERSIZE || defined __DOXYGEN__
+#define TCP_OVERSIZE TCP_MSS
+#endif
+
+/**
+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
+ * The timestamp option is currently only used to help remote hosts, it is not
+ * really used locally. Therefore, it is only enabled when a TS option is
+ * received in the initial SYN packet from a remote host.
+ */
+#if !defined LWIP_TCP_TIMESTAMPS || defined __DOXYGEN__
+#define LWIP_TCP_TIMESTAMPS 0
+#endif
+
+/**
+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
+ * explicit window update
+ */
+#if !defined TCP_WND_UPDATE_THRESHOLD || defined __DOXYGEN__
+#define TCP_WND_UPDATE_THRESHOLD LWIP_MIN((TCP_WND / 4), (TCP_MSS * 4))
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ * events (accept, sent, etc) that happen in the system.
+ * LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ * for the event. This is the default.
+ */
+#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) || defined __DOXYGEN__
+#define LWIP_EVENT_API 0
+#define LWIP_CALLBACK_API 1
+#else
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API 0
+#endif
+#ifndef LWIP_CALLBACK_API
+#define LWIP_CALLBACK_API 0
+#endif
+#endif
+
+/**
+ * LWIP_WND_SCALE and TCP_RCV_SCALE:
+ * Set LWIP_WND_SCALE to 1 to enable window scaling.
+ * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the
+ * range of [0..14]).
+ * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large
+ * send window while having a small receive window only.
+ */
+#if !defined LWIP_WND_SCALE || defined __DOXYGEN__
+#define LWIP_WND_SCALE 0
+#define TCP_RCV_SCALE 0
+#endif
+
+/**
+ * LWIP_TCP_PCB_NUM_EXT_ARGS:
+ * When this is > 0, every tcp pcb (including listen pcb) includes a number of
+ * additional argument entries in an array (see tcp_ext_arg_alloc_id)
+ */
+#if !defined LWIP_TCP_PCB_NUM_EXT_ARGS || defined __DOXYGEN__
+#define LWIP_TCP_PCB_NUM_EXT_ARGS 0
+#endif
+
+/** LWIP_ALTCP==1: enable the altcp API.
+ * altcp is an abstraction layer that prevents applications linking against the
+ * tcp.h functions but provides the same functionality. It is used to e.g. add
+ * SSL/TLS or proxy-connect support to an application written for the tcp callback
+ * API without that application knowing the protocol details.
+ *
+ * With LWIP_ALTCP==0, applications written against the altcp API can still be
+ * compiled but are directly linked against the tcp.h callback API and then
+ * cannot use layered protocols.
+ *
+ * See @ref altcp_api
+ */
+#if !defined LWIP_ALTCP || defined __DOXYGEN__
+#define LWIP_ALTCP 0
+#endif
+
+/** LWIP_ALTCP_TLS==1: enable TLS support for altcp API.
+ * This needs a port of the functions in altcp_tls.h to a TLS library.
+ * A port to ARM mbedtls is provided with lwIP, see apps/altcp_tls/ directory
+ * and LWIP_ALTCP_TLS_MBEDTLS option.
+ */
+#if !defined LWIP_ALTCP_TLS || defined __DOXYGEN__
+#define LWIP_ALTCP_TLS 0
+#endif
+
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------
+ ---------- Pbuf options ----------
+ ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_pbuf PBUF
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#if !defined PBUF_LINK_HLEN || defined __DOXYGEN__
+#if defined LWIP_HOOK_VLAN_SET && !defined __DOXYGEN__
+#define PBUF_LINK_HLEN (18 + ETH_PAD_SIZE)
+#else /* LWIP_HOOK_VLAN_SET */
+#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE)
+#endif /* LWIP_HOOK_VLAN_SET */
+#endif
+
+/**
+ * PBUF_LINK_ENCAPSULATION_HLEN: the number of bytes that should be allocated
+ * for an additional encapsulation header before ethernet headers (e.g. 802.11)
+ */
+#if !defined PBUF_LINK_ENCAPSULATION_HLEN || defined __DOXYGEN__
+#define PBUF_LINK_ENCAPSULATION_HLEN 0
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accommodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#if !defined PBUF_POOL_BUFSIZE || defined __DOXYGEN__
+#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN)
+#endif
+
+/**
+ * LWIP_PBUF_REF_T: Refcount type in pbuf.
+ * Default width of u8_t can be increased if 255 refs are not enough for you.
+ */
+#if !defined LWIP_PBUF_REF_T || defined __DOXYGEN__
+#define LWIP_PBUF_REF_T u8_t
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------------------
+ ---------- Network Interfaces options ----------
+ ------------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_netif NETIF
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * LWIP_SINGLE_NETIF==1: use a single netif only. This is the common case for
+ * small real-life targets. Some code like routing etc. can be left out.
+ */
+#if !defined LWIP_SINGLE_NETIF || defined __DOXYGEN__
+#define LWIP_SINGLE_NETIF 0
+#endif
+
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#if !defined LWIP_NETIF_HOSTNAME || defined __DOXYGEN__
+#define LWIP_NETIF_HOSTNAME 0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#if !defined LWIP_NETIF_API || defined __DOXYGEN__
+#define LWIP_NETIF_API 0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquisition)
+ */
+#if !defined LWIP_NETIF_STATUS_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_STATUS_CALLBACK 0
+#endif
+
+/**
+ * LWIP_NETIF_EXT_STATUS_CALLBACK==1: Support an extended callback function
+ * for several netif related event that supports multiple subscribers.
+ * @see netif_ext_status_callback
+ */
+#if !defined LWIP_NETIF_EXT_STATUS_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_EXT_STATUS_CALLBACK 0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#if !defined LWIP_NETIF_LINK_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_LINK_CALLBACK 0
+#endif
+
+/**
+ * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called
+ * when a netif has been removed
+ */
+#if !defined LWIP_NETIF_REMOVE_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_REMOVE_CALLBACK 0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#if !defined LWIP_NETIF_HWADDRHINT || defined __DOXYGEN__
+#define LWIP_NETIF_HWADDRHINT 0
+#endif
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP *tries* to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * ATTENTION: a driver should *NOT* rely on getting single pbufs but check TX
+ * pbufs for being in one piece. If not, @ref pbuf_clone can be used to get
+ * a single pbuf:
+ * if (p->next != NULL) {
+ * struct pbuf *q = pbuf_clone(PBUF_RAW, PBUF_RAM, p);
+ * if (q == NULL) {
+ * return ERR_MEM;
+ * }
+ * p = q; ATTENTION: do NOT free the old 'p' as the ref belongs to the caller!
+ * }
+ */
+#if !defined LWIP_NETIF_TX_SINGLE_PBUF || defined __DOXYGEN__
+#define LWIP_NETIF_TX_SINGLE_PBUF 0
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+/**
+ * LWIP_NUM_NETIF_CLIENT_DATA: Number of clients that may store
+ * data in client_data member array of struct netif (max. 256).
+ */
+#if !defined LWIP_NUM_NETIF_CLIENT_DATA || defined __DOXYGEN__
+#define LWIP_NUM_NETIF_CLIENT_DATA 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------
+ ---------- LOOPIF options ----------
+ ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_loop Loopback interface
+ * @ingroup lwip_opts_netif
+ * @{
+ */
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1).
+ * This is only needed when no real netifs are available. If at least one other
+ * netif is available, loopback traffic uses this netif.
+ */
+#if !defined LWIP_HAVE_LOOPIF || defined __DOXYGEN__
+#define LWIP_HAVE_LOOPIF (LWIP_NETIF_LOOPBACK && !LWIP_SINGLE_NETIF)
+#endif
+
+/**
+ * LWIP_LOOPIF_MULTICAST==1: Support multicast/IGMP on loop interface (127.0.0.1).
+ */
+#if !defined LWIP_LOOPIF_MULTICAST || defined __DOXYGEN__
+#define LWIP_LOOPIF_MULTICAST 0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
+ * address equal to the netif IP address, looping them back up the stack.
+ */
+#if !defined LWIP_NETIF_LOOPBACK || defined __DOXYGEN__
+#define LWIP_NETIF_LOOPBACK 0
+#endif
+
+/**
+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
+ * sending for each netif (0 = disabled)
+ */
+#if !defined LWIP_LOOPBACK_MAX_PBUFS || defined __DOXYGEN__
+#define LWIP_LOOPBACK_MAX_PBUFS 0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as netifs must change how they behave depending on this setting
+ * for the LWIP_NETIF_LOOPBACK option to work.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
+ * multithreaded environment like tcpip.c. In this case, netif->input()
+ * is called directly.
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ * The packets are put on a list and netif_poll() must be called in
+ * the main application loop.
+ */
+#if !defined LWIP_NETIF_LOOPBACK_MULTITHREADING || defined __DOXYGEN__
+#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS)
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------
+ ---------- Thread options ----------
+ ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_thread Threading
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#if !defined TCPIP_THREAD_NAME || defined __DOXYGEN__
+#define TCPIP_THREAD_NAME "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined TCPIP_THREAD_STACKSIZE || defined __DOXYGEN__
+#define TCPIP_THREAD_STACKSIZE 0
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined TCPIP_THREAD_PRIO || defined __DOXYGEN__
+#define TCPIP_THREAD_PRIO 1
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#if !defined TCPIP_MBOX_SIZE || defined __DOXYGEN__
+#define TCPIP_MBOX_SIZE 0
+#endif
+
+/**
+ * Define this to something that triggers a watchdog. This is called from
+ * tcpip_thread after processing a message.
+ */
+#if !defined LWIP_TCPIP_THREAD_ALIVE || defined __DOXYGEN__
+#define LWIP_TCPIP_THREAD_ALIVE()
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#if !defined SLIPIF_THREAD_NAME || defined __DOXYGEN__
+#define SLIPIF_THREAD_NAME "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined SLIPIF_THREAD_STACKSIZE || defined __DOXYGEN__
+#define SLIPIF_THREAD_STACKSIZE 0
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined SLIPIF_THREAD_PRIO || defined __DOXYGEN__
+#define SLIPIF_THREAD_PRIO 1
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#if !defined DEFAULT_THREAD_NAME || defined __DOXYGEN__
+#define DEFAULT_THREAD_NAME "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined DEFAULT_THREAD_STACKSIZE || defined __DOXYGEN__
+#define DEFAULT_THREAD_STACKSIZE 0
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined DEFAULT_THREAD_PRIO || defined __DOXYGEN__
+#define DEFAULT_THREAD_PRIO 1
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#if !defined DEFAULT_RAW_RECVMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_RAW_RECVMBOX_SIZE 0
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#if !defined DEFAULT_UDP_RECVMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_UDP_RECVMBOX_SIZE 0
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#if !defined DEFAULT_TCP_RECVMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_TCP_RECVMBOX_SIZE 0
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#if !defined DEFAULT_ACCEPTMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_ACCEPTMBOX_SIZE 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------------------
+ ---------- Sequential layer options ----------
+ ----------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_netconn Netconn
+ * @ingroup lwip_opts_threadsafe_apis
+ * @{
+ */
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#if !defined LWIP_NETCONN || defined __DOXYGEN__
+#define LWIP_NETCONN 1
+#endif
+
+/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout to create
+ * timers running in tcpip_thread from another thread.
+ */
+#if !defined LWIP_TCPIP_TIMEOUT || defined __DOXYGEN__
+#define LWIP_TCPIP_TIMEOUT 0
+#endif
+
+/** LWIP_NETCONN_SEM_PER_THREAD==1: Use one (thread-local) semaphore per
+ * thread calling socket/netconn functions instead of allocating one
+ * semaphore per netconn (and per select etc.)
+ * ATTENTION: a thread-local semaphore for API calls is needed:
+ * - LWIP_NETCONN_THREAD_SEM_GET() returning a sys_sem_t*
+ * - LWIP_NETCONN_THREAD_SEM_ALLOC() creating the semaphore
+ * - LWIP_NETCONN_THREAD_SEM_FREE() freeing the semaphore
+ * The latter 2 can be invoked up by calling netconn_thread_init()/netconn_thread_cleanup().
+ * Ports may call these for threads created with sys_thread_new().
+ */
+#if !defined LWIP_NETCONN_SEM_PER_THREAD || defined __DOXYGEN__
+#define LWIP_NETCONN_SEM_PER_THREAD 0
+#endif
+
+/** LWIP_NETCONN_FULLDUPLEX==1: Enable code that allows reading from one thread,
+ * writing from a 2nd thread and closing from a 3rd thread at the same time.
+ * ATTENTION: This is currently really alpha! Some requirements:
+ * - LWIP_NETCONN_SEM_PER_THREAD==1 is required to use one socket/netconn from
+ * multiple threads at once
+ * - sys_mbox_free() has to unblock receive tasks waiting on recvmbox/acceptmbox
+ * and prevent a task pending on this during/after deletion
+ */
+#if !defined LWIP_NETCONN_FULLDUPLEX || defined __DOXYGEN__
+#define LWIP_NETCONN_FULLDUPLEX 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ------------------------------------
+ ---------- Socket options ----------
+ ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_socket Sockets
+ * @ingroup lwip_opts_threadsafe_apis
+ * @{
+ */
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#if !defined LWIP_SOCKET || defined __DOXYGEN__
+#define LWIP_SOCKET 1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names through defines.
+ * LWIP_COMPAT_SOCKETS==2: Same as ==1 but correctly named functions are created.
+ * While this helps code completion, it might conflict with existing libraries.
+ * (only used if you use sockets.c)
+ */
+#if !defined LWIP_COMPAT_SOCKETS || defined __DOXYGEN__
+#define LWIP_COMPAT_SOCKETS 1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#if !defined LWIP_POSIX_SOCKETS_IO_NAMES || defined __DOXYGEN__
+#define LWIP_POSIX_SOCKETS_IO_NAMES 1
+#endif
+
+/**
+ * LWIP_SOCKET_OFFSET==n: Increases the file descriptor number created by LwIP with n.
+ * This can be useful when there are multiple APIs which create file descriptors.
+ * When they all start with a different offset and you won't make them overlap you can
+ * re implement read/write/close/ioctl/fnctl to send the requested action to the right
+ * library (sharing select will need more work though).
+ */
+#if !defined LWIP_SOCKET_OFFSET || defined __DOXYGEN__
+#define LWIP_SOCKET_OFFSET 0
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#if !defined LWIP_TCP_KEEPALIVE || defined __DOXYGEN__
+#define LWIP_TCP_KEEPALIVE 0
+#endif
+
+/**
+ * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
+ * SO_SNDTIMEO processing.
+ */
+#if !defined LWIP_SO_SNDTIMEO || defined __DOXYGEN__
+#define LWIP_SO_SNDTIMEO 0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
+ * SO_RCVTIMEO processing.
+ */
+#if !defined LWIP_SO_RCVTIMEO || defined __DOXYGEN__
+#define LWIP_SO_RCVTIMEO 0
+#endif
+
+/**
+ * LWIP_SO_SNDRCVTIMEO_NONSTANDARD==1: SO_RCVTIMEO/SO_SNDTIMEO take an int
+ * (milliseconds, much like winsock does) instead of a struct timeval (default).
+ */
+#if !defined LWIP_SO_SNDRCVTIMEO_NONSTANDARD || defined __DOXYGEN__
+#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#if !defined LWIP_SO_RCVBUF || defined __DOXYGEN__
+#define LWIP_SO_RCVBUF 0
+#endif
+
+/**
+ * LWIP_SO_LINGER==1: Enable SO_LINGER processing.
+ */
+#if !defined LWIP_SO_LINGER || defined __DOXYGEN__
+#define LWIP_SO_LINGER 0
+#endif
+
+/**
+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
+ */
+#if !defined RECV_BUFSIZE_DEFAULT || defined __DOXYGEN__
+#define RECV_BUFSIZE_DEFAULT INT_MAX
+#endif
+
+/**
+ * By default, TCP socket/netconn close waits 20 seconds max to send the FIN
+ */
+#if !defined LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT || defined __DOXYGEN__
+#define LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT 20000
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ */
+#if !defined SO_REUSE || defined __DOXYGEN__
+#define SO_REUSE 0
+#endif
+
+/**
+ * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
+ * to all local matches if SO_REUSEADDR is turned on.
+ * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
+ */
+#if !defined SO_REUSE_RXTOALL || defined __DOXYGEN__
+#define SO_REUSE_RXTOALL 0
+#endif
+
+/**
+ * LWIP_FIONREAD_LINUXMODE==0 (default): ioctl/FIONREAD returns the amount of
+ * pending data in the network buffer. This is the way windows does it. It's
+ * the default for lwIP since it is smaller.
+ * LWIP_FIONREAD_LINUXMODE==1: ioctl/FIONREAD returns the size of the next
+ * pending datagram in bytes. This is the way linux does it. This code is only
+ * here for compatibility.
+ */
+#if !defined LWIP_FIONREAD_LINUXMODE || defined __DOXYGEN__
+#define LWIP_FIONREAD_LINUXMODE 0
+#endif
+
+/**
+ * LWIP_SOCKET_SELECT==1 (default): enable select() for sockets (uses a netconn
+ * callback to keep track of events).
+ * This saves RAM (counters per socket) and code (netconn event callback), which
+ * should improve performance a bit).
+ */
+#if !defined LWIP_SOCKET_SELECT || defined __DOXYGEN__
+#define LWIP_SOCKET_SELECT 1
+#endif
+
+/**
+ * LWIP_SOCKET_POLL==1 (default): enable poll() for sockets (including
+ * struct pollfd, nfds_t, and constants)
+ */
+#if !defined LWIP_SOCKET_POLL || defined __DOXYGEN__
+#define LWIP_SOCKET_POLL 1
+#endif
+/**
+ * @}
+ */
+
+/*
+ ----------------------------------------
+ ---------- Statistics options ----------
+ ----------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_stats Statistics
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#if !defined LWIP_STATS || defined __DOXYGEN__
+#define LWIP_STATS 1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#if !defined LWIP_STATS_DISPLAY || defined __DOXYGEN__
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#if !defined LINK_STATS || defined __DOXYGEN__
+#define LINK_STATS 1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#if !defined ETHARP_STATS || defined __DOXYGEN__
+#define ETHARP_STATS (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#if !defined IP_STATS || defined __DOXYGEN__
+#define IP_STATS 1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#if !defined IPFRAG_STATS || defined __DOXYGEN__
+#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#if !defined ICMP_STATS || defined __DOXYGEN__
+#define ICMP_STATS 1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#if !defined IGMP_STATS || defined __DOXYGEN__
+#define IGMP_STATS (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#if !defined UDP_STATS || defined __DOXYGEN__
+#define UDP_STATS (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#if !defined TCP_STATS || defined __DOXYGEN__
+#define TCP_STATS (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#if !defined MEM_STATS || defined __DOXYGEN__
+#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#if !defined MEMP_STATS || defined __DOXYGEN__
+#define MEMP_STATS (MEMP_MEM_MALLOC == 0)
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#if !defined SYS_STATS || defined __DOXYGEN__
+#define SYS_STATS (NO_SYS == 0)
+#endif
+
+/**
+ * IP6_STATS==1: Enable IPv6 stats.
+ */
+#if !defined IP6_STATS || defined __DOXYGEN__
+#define IP6_STATS (LWIP_IPV6)
+#endif
+
+/**
+ * ICMP6_STATS==1: Enable ICMP for IPv6 stats.
+ */
+#if !defined ICMP6_STATS || defined __DOXYGEN__
+#define ICMP6_STATS (LWIP_IPV6 && LWIP_ICMP6)
+#endif
+
+/**
+ * IP6_FRAG_STATS==1: Enable IPv6 fragmentation stats.
+ */
+#if !defined IP6_FRAG_STATS || defined __DOXYGEN__
+#define IP6_FRAG_STATS (LWIP_IPV6 && (LWIP_IPV6_FRAG || LWIP_IPV6_REASS))
+#endif
+
+/**
+ * MLD6_STATS==1: Enable MLD for IPv6 stats.
+ */
+#if !defined MLD6_STATS || defined __DOXYGEN__
+#define MLD6_STATS (LWIP_IPV6 && LWIP_IPV6_MLD)
+#endif
+
+/**
+ * ND6_STATS==1: Enable Neighbor discovery for IPv6 stats.
+ */
+#if !defined ND6_STATS || defined __DOXYGEN__
+#define ND6_STATS (LWIP_IPV6)
+#endif
+
+/**
+ * MIB2_STATS==1: Stats for SNMP MIB2.
+ */
+#if !defined MIB2_STATS || defined __DOXYGEN__
+#define MIB2_STATS 0
+#endif
+
+#else
+
+#define LINK_STATS 0
+#define ETHARP_STATS 0
+#define IP_STATS 0
+#define IPFRAG_STATS 0
+#define ICMP_STATS 0
+#define IGMP_STATS 0
+#define UDP_STATS 0
+#define TCP_STATS 0
+#define MEM_STATS 0
+#define MEMP_STATS 0
+#define SYS_STATS 0
+#define LWIP_STATS_DISPLAY 0
+#define IP6_STATS 0
+#define ICMP6_STATS 0
+#define IP6_FRAG_STATS 0
+#define MLD6_STATS 0
+#define ND6_STATS 0
+#define MIB2_STATS 0
+
+#endif /* LWIP_STATS */
+/**
+ * @}
+ */
+
+/*
+ --------------------------------------
+ ---------- Checksum options ----------
+ --------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_checksum Checksum
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_CHECKSUM_CTRL_PER_NETIF==1: Checksum generation/check can be enabled/disabled
+ * per netif.
+ * ATTENTION: if enabled, the CHECKSUM_GEN_* and CHECKSUM_CHECK_* defines must be enabled!
+ */
+#if !defined LWIP_CHECKSUM_CTRL_PER_NETIF || defined __DOXYGEN__
+#define LWIP_CHECKSUM_CTRL_PER_NETIF 0
+#endif
+
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#if !defined CHECKSUM_GEN_IP || defined __DOXYGEN__
+#define CHECKSUM_GEN_IP 1
+#endif
+
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#if !defined CHECKSUM_GEN_UDP || defined __DOXYGEN__
+#define CHECKSUM_GEN_UDP 1
+#endif
+
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#if !defined CHECKSUM_GEN_TCP || defined __DOXYGEN__
+#define CHECKSUM_GEN_TCP 1
+#endif
+
+/**
+ * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets.
+ */
+#if !defined CHECKSUM_GEN_ICMP || defined __DOXYGEN__
+#define CHECKSUM_GEN_ICMP 1
+#endif
+
+/**
+ * CHECKSUM_GEN_ICMP6==1: Generate checksums in software for outgoing ICMP6 packets.
+ */
+#if !defined CHECKSUM_GEN_ICMP6 || defined __DOXYGEN__
+#define CHECKSUM_GEN_ICMP6 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#if !defined CHECKSUM_CHECK_IP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_IP 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#if !defined CHECKSUM_CHECK_UDP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_UDP 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#if !defined CHECKSUM_CHECK_TCP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_TCP 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_ICMP==1: Check checksums in software for incoming ICMP packets.
+ */
+#if !defined CHECKSUM_CHECK_ICMP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_ICMP 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_ICMP6==1: Check checksums in software for incoming ICMPv6 packets
+ */
+#if !defined CHECKSUM_CHECK_ICMP6 || defined __DOXYGEN__
+#define CHECKSUM_CHECK_ICMP6 1
+#endif
+
+/**
+ * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
+ * application buffers to pbufs.
+ */
+#if !defined LWIP_CHECKSUM_ON_COPY || defined __DOXYGEN__
+#define LWIP_CHECKSUM_ON_COPY 0
+#endif
+/**
+ * @}
+ */
+
+/*
+ ---------------------------------------
+ ---------- IPv6 options ---------------
+ ---------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_ipv6 IPv6
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * LWIP_IPV6==1: Enable IPv6
+ */
+#if !defined LWIP_IPV6 || defined __DOXYGEN__
+#define LWIP_IPV6 0
+#endif
+
+/**
+ * IPV6_REASS_MAXAGE: Maximum time (in multiples of IP6_REASS_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#if !defined IPV6_REASS_MAXAGE || defined __DOXYGEN__
+#define IPV6_REASS_MAXAGE 60
+#endif
+
+/**
+ * LWIP_IPV6_SCOPES==1: Enable support for IPv6 address scopes, ensuring that
+ * e.g. link-local addresses are really treated as link-local. Disable this
+ * setting only for single-interface configurations.
+ * All addresses that have a scope according to the default policy (link-local
+ * unicast addresses, interface-local and link-local multicast addresses) should
+ * now have a zone set on them before being passed to the core API, although
+ * lwIP will currently attempt to select a zone on the caller's behalf when
+ * necessary. Applications that directly assign IPv6 addresses to interfaces
+ * (which is NOT recommended) must now ensure that link-local addresses carry
+ * the netif's zone. See the new ip6_zone.h header file for more information and
+ * relevant macros. For now it is still possible to turn off scopes support
+ * through the new LWIP_IPV6_SCOPES option. When upgrading an implementation that
+ * uses the core API directly, it is highly recommended to enable
+ * LWIP_IPV6_SCOPES_DEBUG at least for a while, to ensure e.g. proper address
+ * initialization.
+ */
+#if !defined LWIP_IPV6_SCOPES || defined __DOXYGEN__
+#define LWIP_IPV6_SCOPES (LWIP_IPV6 && !LWIP_SINGLE_NETIF)
+#endif
+
+/**
+ * LWIP_IPV6_SCOPES_DEBUG==1: Perform run-time checks to verify that addresses
+ * are properly zoned (see ip6_zone.h on what that means) where it matters.
+ * Enabling this setting is highly recommended when upgrading from an existing
+ * installation that is not yet scope-aware; otherwise it may be too expensive.
+ */
+#if !defined LWIP_IPV6_SCOPES_DEBUG || defined __DOXYGEN__
+#define LWIP_IPV6_SCOPES_DEBUG 0
+#endif
+
+/**
+ * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif.
+ */
+#if !defined LWIP_IPV6_NUM_ADDRESSES || defined __DOXYGEN__
+#define LWIP_IPV6_NUM_ADDRESSES 3
+#endif
+
+/**
+ * LWIP_IPV6_FORWARD==1: Forward IPv6 packets across netifs
+ */
+#if !defined LWIP_IPV6_FORWARD || defined __DOXYGEN__
+#define LWIP_IPV6_FORWARD 0
+#endif
+
+/**
+ * LWIP_IPV6_FRAG==1: Fragment outgoing IPv6 packets that are too big.
+ */
+#if !defined LWIP_IPV6_FRAG || defined __DOXYGEN__
+#define LWIP_IPV6_FRAG 1
+#endif
+
+/**
+ * LWIP_IPV6_REASS==1: reassemble incoming IPv6 packets that fragmented
+ */
+#if !defined LWIP_IPV6_REASS || defined __DOXYGEN__
+#define LWIP_IPV6_REASS LWIP_IPV6
+#endif
+
+/**
+ * LWIP_IPV6_SEND_ROUTER_SOLICIT==1: Send router solicitation messages during
+ * network startup.
+ */
+#if !defined LWIP_IPV6_SEND_ROUTER_SOLICIT || defined __DOXYGEN__
+#define LWIP_IPV6_SEND_ROUTER_SOLICIT 1
+#endif
+
+/**
+ * LWIP_IPV6_AUTOCONFIG==1: Enable stateless address autoconfiguration as per RFC 4862.
+ */
+#if !defined LWIP_IPV6_AUTOCONFIG || defined __DOXYGEN__
+#define LWIP_IPV6_AUTOCONFIG LWIP_IPV6
+#endif
+
+/**
+ * LWIP_IPV6_ADDRESS_LIFETIMES==1: Keep valid and preferred lifetimes for each
+ * IPv6 address. Required for LWIP_IPV6_AUTOCONFIG. May still be enabled
+ * otherwise, in which case the application may assign address lifetimes with
+ * the appropriate macros. Addresses with no lifetime are assumed to be static.
+ * If this option is disabled, all addresses are assumed to be static.
+ */
+#if !defined LWIP_IPV6_ADDRESS_LIFETIMES || defined __DOXYGEN__
+#define LWIP_IPV6_ADDRESS_LIFETIMES LWIP_IPV6_AUTOCONFIG
+#endif
+
+/**
+ * LWIP_IPV6_DUP_DETECT_ATTEMPTS=[0..7]: Number of duplicate address detection attempts.
+ */
+#if !defined LWIP_IPV6_DUP_DETECT_ATTEMPTS || defined __DOXYGEN__
+#define LWIP_IPV6_DUP_DETECT_ATTEMPTS 1
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_icmp6 ICMP6
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_ICMP6==1: Enable ICMPv6 (mandatory per RFC)
+ */
+#if !defined LWIP_ICMP6 || defined __DOXYGEN__
+#define LWIP_ICMP6 LWIP_IPV6
+#endif
+
+/**
+ * LWIP_ICMP6_DATASIZE: bytes from original packet to send back in
+ * ICMPv6 error messages.
+ */
+#if !defined LWIP_ICMP6_DATASIZE || defined __DOXYGEN__
+#define LWIP_ICMP6_DATASIZE 8
+#endif
+
+/**
+ * LWIP_ICMP6_HL: default hop limit for ICMPv6 messages
+ */
+#if !defined LWIP_ICMP6_HL || defined __DOXYGEN__
+#define LWIP_ICMP6_HL 255
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_mld6 Multicast listener discovery
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_IPV6_MLD==1: Enable multicast listener discovery protocol.
+ * If LWIP_IPV6 is enabled but this setting is disabled, the MAC layer must
+ * indiscriminately pass all inbound IPv6 multicast traffic to lwIP.
+ */
+#if !defined LWIP_IPV6_MLD || defined __DOXYGEN__
+#define LWIP_IPV6_MLD LWIP_IPV6
+#endif
+
+/**
+ * MEMP_NUM_MLD6_GROUP: Max number of IPv6 multicast groups that can be joined.
+ * There must be enough groups so that each netif can join the solicited-node
+ * multicast group for each of its local addresses, plus one for MDNS if
+ * applicable, plus any number of groups to be joined on UDP sockets.
+ */
+#if !defined MEMP_NUM_MLD6_GROUP || defined __DOXYGEN__
+#define MEMP_NUM_MLD6_GROUP 4
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_nd6 Neighbor discovery
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address
+ * is being resolved.
+ */
+#if !defined LWIP_ND6_QUEUEING || defined __DOXYGEN__
+#define LWIP_ND6_QUEUEING LWIP_IPV6
+#endif
+
+/**
+ * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution.
+ */
+#if !defined MEMP_NUM_ND6_QUEUE || defined __DOXYGEN__
+#define MEMP_NUM_ND6_QUEUE 20
+#endif
+
+/**
+ * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache
+ */
+#if !defined LWIP_ND6_NUM_NEIGHBORS || defined __DOXYGEN__
+#define LWIP_ND6_NUM_NEIGHBORS 10
+#endif
+
+/**
+ * LWIP_ND6_NUM_DESTINATIONS: number of entries in IPv6 destination cache
+ */
+#if !defined LWIP_ND6_NUM_DESTINATIONS || defined __DOXYGEN__
+#define LWIP_ND6_NUM_DESTINATIONS 10
+#endif
+
+/**
+ * LWIP_ND6_NUM_PREFIXES: number of entries in IPv6 on-link prefixes cache
+ */
+#if !defined LWIP_ND6_NUM_PREFIXES || defined __DOXYGEN__
+#define LWIP_ND6_NUM_PREFIXES 5
+#endif
+
+/**
+ * LWIP_ND6_NUM_ROUTERS: number of entries in IPv6 default router cache
+ */
+#if !defined LWIP_ND6_NUM_ROUTERS || defined __DOXYGEN__
+#define LWIP_ND6_NUM_ROUTERS 3
+#endif
+
+/**
+ * LWIP_ND6_MAX_MULTICAST_SOLICIT: max number of multicast solicit messages to send
+ * (neighbor solicit and router solicit)
+ */
+#if !defined LWIP_ND6_MAX_MULTICAST_SOLICIT || defined __DOXYGEN__
+#define LWIP_ND6_MAX_MULTICAST_SOLICIT 3
+#endif
+
+/**
+ * LWIP_ND6_MAX_UNICAST_SOLICIT: max number of unicast neighbor solicitation messages
+ * to send during neighbor reachability detection.
+ */
+#if !defined LWIP_ND6_MAX_UNICAST_SOLICIT || defined __DOXYGEN__
+#define LWIP_ND6_MAX_UNICAST_SOLICIT 3
+#endif
+
+/**
+ * Unused: See ND RFC (time in milliseconds).
+ */
+#if !defined LWIP_ND6_MAX_ANYCAST_DELAY_TIME || defined __DOXYGEN__
+#define LWIP_ND6_MAX_ANYCAST_DELAY_TIME 1000
+#endif
+
+/**
+ * Unused: See ND RFC
+ */
+#if !defined LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT || defined __DOXYGEN__
+#define LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT 3
+#endif
+
+/**
+ * LWIP_ND6_REACHABLE_TIME: default neighbor reachable time (in milliseconds).
+ * May be updated by router advertisement messages.
+ */
+#if !defined LWIP_ND6_REACHABLE_TIME || defined __DOXYGEN__
+#define LWIP_ND6_REACHABLE_TIME 30000
+#endif
+
+/**
+ * LWIP_ND6_RETRANS_TIMER: default retransmission timer for solicitation messages
+ */
+#if !defined LWIP_ND6_RETRANS_TIMER || defined __DOXYGEN__
+#define LWIP_ND6_RETRANS_TIMER 1000
+#endif
+
+/**
+ * LWIP_ND6_DELAY_FIRST_PROBE_TIME: Delay before first unicast neighbor solicitation
+ * message is sent, during neighbor reachability detection.
+ */
+#if !defined LWIP_ND6_DELAY_FIRST_PROBE_TIME || defined __DOXYGEN__
+#define LWIP_ND6_DELAY_FIRST_PROBE_TIME 5000
+#endif
+
+/**
+ * LWIP_ND6_ALLOW_RA_UPDATES==1: Allow Router Advertisement messages to update
+ * Reachable time and retransmission timers, and netif MTU.
+ */
+#if !defined LWIP_ND6_ALLOW_RA_UPDATES || defined __DOXYGEN__
+#define LWIP_ND6_ALLOW_RA_UPDATES 1
+#endif
+
+/**
+ * LWIP_ND6_TCP_REACHABILITY_HINTS==1: Allow TCP to provide Neighbor Discovery
+ * with reachability hints for connected destinations. This helps avoid sending
+ * unicast neighbor solicitation messages.
+ */
+#if !defined LWIP_ND6_TCP_REACHABILITY_HINTS || defined __DOXYGEN__
+#define LWIP_ND6_TCP_REACHABILITY_HINTS 1
+#endif
+
+/**
+ * LWIP_ND6_RDNSS_MAX_DNS_SERVERS > 0: Use IPv6 Router Advertisement Recursive
+ * DNS Server Option (as per RFC 6106) to copy a defined maximum number of DNS
+ * servers to the DNS module.
+ */
+#if !defined LWIP_ND6_RDNSS_MAX_DNS_SERVERS || defined __DOXYGEN__
+#define LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_dhcpv6 DHCPv6
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_IPV6_DHCP6==1: enable DHCPv6 stateful/stateless address autoconfiguration.
+ */
+#if !defined LWIP_IPV6_DHCP6 || defined __DOXYGEN__
+#define LWIP_IPV6_DHCP6 0
+#endif
+
+/**
+ * LWIP_IPV6_DHCP6_STATEFUL==1: enable DHCPv6 stateful address autoconfiguration.
+ * (not supported, yet!)
+ */
+#if !defined LWIP_IPV6_DHCP6_STATEFUL || defined __DOXYGEN__
+#define LWIP_IPV6_DHCP6_STATEFUL 0
+#endif
+
+/**
+ * LWIP_IPV6_DHCP6_STATELESS==1: enable DHCPv6 stateless address autoconfiguration.
+ */
+#if !defined LWIP_IPV6_DHCP6_STATELESS || defined __DOXYGEN__
+#define LWIP_IPV6_DHCP6_STATELESS LWIP_IPV6_DHCP6
+#endif
+
+/**
+ * LWIP_DHCP6_GETS_NTP==1: Request NTP servers via DHCPv6. For each
+ * response packet, a callback is called, which has to be provided by the port:
+ * void dhcp6_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs);
+*/
+#if !defined LWIP_DHCP6_GET_NTP_SRV || defined __DOXYGEN__
+#define LWIP_DHCP6_GET_NTP_SRV 0
+#endif
+
+/**
+ * The maximum of NTP servers requested
+ */
+#if !defined LWIP_DHCP6_MAX_NTP_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP6_MAX_NTP_SERVERS 1
+#endif
+
+/**
+ * LWIP_DHCP6_MAX_DNS_SERVERS > 0: Request DNS servers via DHCPv6.
+ * DNS servers received in the response are passed to DNS via @ref dns_setserver()
+ * (up to the maximum limit defined here).
+ */
+#if !defined LWIP_DHCP6_MAX_DNS_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP6_MAX_DNS_SERVERS DNS_MAX_SERVERS
+#endif
+/**
+ * @}
+ */
+
+/*
+ ---------------------------------------
+ ---------- Hook options ---------------
+ ---------------------------------------
+*/
+
+/**
+ * @defgroup lwip_opts_hooks Hooks
+ * @ingroup lwip_opts_infrastructure
+ * Hooks are undefined by default, define them to a function if you need them.
+ * @{
+ */
+
+/**
+ * LWIP_HOOK_FILENAME: Custom filename to \#include in files that provide hooks.
+ * Declare your hook function prototypes in there, you may also \#include all headers
+ * providing data types that are need in this file.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_FILENAME "path/to/my/lwip_hooks.h"
+#endif
+
+/**
+ * LWIP_HOOK_TCP_ISN:
+ * Hook for generation of the Initial Sequence Number (ISN) for a new TCP
+ * connection. The default lwIP ISN generation algorithm is very basic and may
+ * allow for TCP spoofing attacks. This hook provides the means to implement
+ * the standardized ISN generation algorithm from RFC 6528 (see contrib/adons/tcp_isn),
+ * or any other desired algorithm as a replacement.
+ * Called from tcp_connect() and tcp_listen_input() when an ISN is needed for
+ * a new TCP connection, if TCP support (@ref LWIP_TCP) is enabled.\n
+ * Signature:\code{.c}
+ * u32_t my_hook_tcp_isn(const ip_addr_t* local_ip, u16_t local_port, const ip_addr_t* remote_ip, u16_t remote_port);
+ * \endcode
+ * - it may be necessary to use "struct ip_addr" (ip4_addr, ip6_addr) instead of "ip_addr_t" in function declarations\n
+ * Arguments:
+ * - local_ip: pointer to the local IP address of the connection
+ * - local_port: local port number of the connection (host-byte order)
+ * - remote_ip: pointer to the remote IP address of the connection
+ * - remote_port: remote port number of the connection (host-byte order)\n
+ * Return value:
+ * - the 32-bit Initial Sequence Number to use for the new TCP connection.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_ISN(local_ip, local_port, remote_ip, remote_port)
+#endif
+
+/**
+ * LWIP_HOOK_TCP_INPACKET_PCB:
+ * Hook for intercepting incoming packets before they are passed to a pcb. This
+ * allows updating some state or even dropping a packet.
+ * Signature:\code{.c}
+ * err_t my_hook_tcp_inpkt(struct tcp_pcb *pcb, struct tcp_hdr *hdr, u16_t optlen, u16_t opt1len, u8_t *opt2, struct pbuf *p);
+ * \endcode
+ * Arguments:
+ * - pcb: tcp_pcb selected for input of this packet (ATTENTION: this may be
+ * struct tcp_pcb_listen if pcb->state == LISTEN)
+ * - hdr: pointer to tcp header (ATTENTION: tcp options may not be in one piece!)
+ * - optlen: tcp option length
+ * - opt1len: tcp option length 1st part
+ * - opt2: if this is != NULL, tcp options are split among 2 pbufs. In that case,
+ * options start at right after the tcp header ('(u8_t*)(hdr + 1)') for
+ * the first 'opt1len' bytes and the rest starts at 'opt2'. opt2len can
+ * be simply calculated: 'opt2len = optlen - opt1len;'
+ * - p: input packet, p->payload points to application data (that's why tcp hdr
+ * and options are passed in separately)
+ * Return value:
+ * - ERR_OK: continue input of this packet as normal
+ * - != ERR_OK: drop this packet for input (don't continue input processing)
+ *
+ * ATTENTION: don't call any tcp api functions that might change tcp state (pcb
+ * state or any pcb lists) from this callback!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_INPACKET_PCB(pcb, hdr, optlen, opt1len, opt2, p)
+#endif
+
+/**
+ * LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH:
+ * Hook for increasing the size of the options allocated with a tcp header.
+ * Together with LWIP_HOOK_TCP_OUT_ADD_TCPOPTS, this can be used to add custom
+ * options to outgoing tcp segments.
+ * Signature:\code{.c}
+ * u8_t my_hook_tcp_out_tcpopt_length(const struct tcp_pcb *pcb, u8_t internal_option_length);
+ * \endcode
+ * Arguments:
+ * - pcb: tcp_pcb that transmits (ATTENTION: this may be NULL or
+ * struct tcp_pcb_listen if pcb->state == LISTEN)
+ * - internal_option_length: tcp option length used by the stack internally
+ * Return value:
+ * - a number of bytes to allocate for tcp options (internal_option_length <= ret <= 40)
+ *
+ * ATTENTION: don't call any tcp api functions that might change tcp state (pcb
+ * state or any pcb lists) from this callback!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH(pcb, internal_len)
+#endif
+
+/**
+ * LWIP_HOOK_TCP_OUT_ADD_TCPOPTS:
+ * Hook for adding custom options to outgoing tcp segments.
+ * Space for these custom options has to be reserved via LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH.
+ * Signature:\code{.c}
+ * u32_t *my_hook_tcp_out_add_tcpopts(struct pbuf *p, struct tcp_hdr *hdr, const struct tcp_pcb *pcb, u32_t *opts);
+ * \endcode
+ * Arguments:
+ * - p: output packet, p->payload pointing to tcp header, data follows
+ * - hdr: tcp header
+ * - pcb: tcp_pcb that transmits (ATTENTION: this may be NULL or
+ * struct tcp_pcb_listen if pcb->state == LISTEN)
+ * - opts: pointer where to add the custom options (there may already be options
+ * between the header and these)
+ * Return value:
+ * - pointer pointing directly after the inserted options
+ *
+ * ATTENTION: don't call any tcp api functions that might change tcp state (pcb
+ * state or any pcb lists) from this callback!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, hdr, pcb, opts)
+#endif
+
+/**
+ * LWIP_HOOK_IP4_INPUT(pbuf, input_netif):
+ * Called from ip_input() (IPv4)
+ * Signature:\code{.c}
+ * int my_hook(struct pbuf *pbuf, struct netif *input_netif);
+ * \endcode
+ * Arguments:
+ * - pbuf: received struct pbuf passed to ip_input()
+ * - input_netif: struct netif on which the packet has been received
+ * Return values:
+ * - 0: Hook has not consumed the packet, packet is processed as normal
+ * - != 0: Hook has consumed the packet.
+ * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
+ * (i.e. free it when done).
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_INPUT(pbuf, input_netif)
+#endif
+
+/**
+ * LWIP_HOOK_IP4_ROUTE(dest):
+ * Called from ip_route() (IPv4)
+ * Signature:\code{.c}
+ * struct netif *my_hook(const ip4_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - dest: destination IPv4 address
+ * Returns values:
+ * - the destination netif
+ * - NULL if no destination netif is found. In that case, ip_route() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_ROUTE()
+#endif
+
+/**
+ * LWIP_HOOK_IP4_ROUTE_SRC(src, dest):
+ * Source-based routing for IPv4 - called from ip_route() (IPv4)
+ * Signature:\code{.c}
+ * struct netif *my_hook(const ip4_addr_t *src, const ip4_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - src: local/source IPv4 address
+ * - dest: destination IPv4 address
+ * Returns values:
+ * - the destination netif
+ * - NULL if no destination netif is found. In that case, ip_route() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_ROUTE_SRC(src, dest)
+#endif
+
+/**
+ * LWIP_HOOK_IP4_CANFORWARD(src, dest):
+ * Check if an IPv4 can be forwarded - called from:
+ * ip4_input() -> ip4_forward() -> ip4_canforward() (IPv4)
+ * - source address is available via ip4_current_src_addr()
+ * - calling an output function in this context (e.g. multicast router) is allowed
+ * Signature:\code{.c}
+ * int my_hook(struct pbuf *p, u32_t dest_addr_hostorder);
+ * \endcode
+ * Arguments:
+ * - p: packet to forward
+ * - dest: destination IPv4 address
+ * Returns values:
+ * - 1: forward
+ * - 0: don't forward
+ * - -1: no decision. In that case, ip4_canforward() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_CANFORWARD(src, dest)
+#endif
+
+/**
+ * LWIP_HOOK_ETHARP_GET_GW(netif, dest):
+ * Called from etharp_output() (IPv4)
+ * Signature:\code{.c}
+ * const ip4_addr_t *my_hook(struct netif *netif, const ip4_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - netif: the netif used for sending
+ * - dest: the destination IPv4 address
+ * Return values:
+ * - the IPv4 address of the gateway to handle the specified destination IPv4 address
+ * - NULL, in which case the netif's default gateway is used
+ *
+ * The returned address MUST be directly reachable on the specified netif!
+ * This function is meant to implement advanced IPv4 routing together with
+ * LWIP_HOOK_IP4_ROUTE(). The actual routing/gateway table implementation is
+ * not part of lwIP but can e.g. be hidden in the netif's state argument.
+*/
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_ETHARP_GET_GW(netif, dest)
+#endif
+
+/**
+ * LWIP_HOOK_IP6_INPUT(pbuf, input_netif):
+ * Called from ip6_input() (IPv6)
+ * Signature:\code{.c}
+ * int my_hook(struct pbuf *pbuf, struct netif *input_netif);
+ * \endcode
+ * Arguments:
+ * - pbuf: received struct pbuf passed to ip6_input()
+ * - input_netif: struct netif on which the packet has been received
+ * Return values:
+ * - 0: Hook has not consumed the packet, packet is processed as normal
+ * - != 0: Hook has consumed the packet.
+ * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
+ * (i.e. free it when done).
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP6_INPUT(pbuf, input_netif)
+#endif
+
+/**
+ * LWIP_HOOK_IP6_ROUTE(src, dest):
+ * Called from ip_route() (IPv6)
+ * Signature:\code{.c}
+ * struct netif *my_hook(const ip6_addr_t *dest, const ip6_addr_t *src);
+ * \endcode
+ * Arguments:
+ * - src: source IPv6 address
+ * - dest: destination IPv6 address
+ * Return values:
+ * - the destination netif
+ * - NULL if no destination netif is found. In that case, ip6_route() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP6_ROUTE(src, dest)
+#endif
+
+/**
+ * LWIP_HOOK_ND6_GET_GW(netif, dest):
+ * Called from nd6_get_next_hop_entry() (IPv6)
+ * Signature:\code{.c}
+ * const ip6_addr_t *my_hook(struct netif *netif, const ip6_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - netif: the netif used for sending
+ * - dest: the destination IPv6 address
+ * Return values:
+ * - the IPv6 address of the next hop to handle the specified destination IPv6 address
+ * - NULL, in which case a NDP-discovered router is used instead
+ *
+ * The returned address MUST be directly reachable on the specified netif!
+ * This function is meant to implement advanced IPv6 routing together with
+ * LWIP_HOOK_IP6_ROUTE(). The actual routing/gateway table implementation is
+ * not part of lwIP but can e.g. be hidden in the netif's state argument.
+*/
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_ND6_GET_GW(netif, dest)
+#endif
+
+/**
+ * LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr):
+ * Called from ethernet_input() if VLAN support is enabled
+ * Signature:\code{.c}
+ * int my_hook(struct netif *netif, struct eth_hdr *eth_hdr, struct eth_vlan_hdr *vlan_hdr);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif on which the packet has been received
+ * - eth_hdr: struct eth_hdr of the packet
+ * - vlan_hdr: struct eth_vlan_hdr of the packet
+ * Return values:
+ * - 0: Packet must be dropped.
+ * - != 0: Packet must be accepted.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr)
+#endif
+
+/**
+ * LWIP_HOOK_VLAN_SET:
+ * Hook can be used to set prio_vid field of vlan_hdr. If you need to store data
+ * on per-netif basis to implement this callback, see @ref netif_cd.
+ * Called from ethernet_output() if VLAN support (@ref ETHARP_SUPPORT_VLAN) is enabled.\n
+ * Signature:\code{.c}
+ * s32_t my_hook_vlan_set(struct netif* netif, struct pbuf* pbuf, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);\n
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - p: struct pbuf packet to be sent
+ * - src: source eth address
+ * - dst: destination eth address
+ * - eth_type: ethernet type to packet to be sent\n
+ *
+ *
+ * Return values:
+ * - <0: Packet shall not contain VLAN header.
+ * - 0 <= return value <= 0xFFFF: Packet shall contain VLAN header. Return value is prio_vid in host byte order.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type)
+#endif
+
+/**
+ * LWIP_HOOK_MEMP_AVAILABLE(memp_t_type):
+ * Called from memp_free() when a memp pool was empty and an item is now available
+ * Signature:\code{.c}
+ * void my_hook(memp_t type);
+ * \endcode
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_MEMP_AVAILABLE(memp_t_type)
+#endif
+
+/**
+ * LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif):
+ * Called from ethernet_input() when an unknown eth type is encountered.
+ * Signature:\code{.c}
+ * err_t my_hook(struct pbuf* pbuf, struct netif* netif);
+ * \endcode
+ * Arguments:
+ * - p: rx packet with unknown eth type
+ * - netif: netif on which the packet has been received
+ * Return values:
+ * - ERR_OK if packet is accepted (hook function now owns the pbuf)
+ * - any error code otherwise (pbuf is freed)
+ *
+ * Payload points to ethernet header!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif)
+#endif
+
+/**
+ * LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr):
+ * Called from various dhcp functions when sending a DHCP message.
+ * This hook is called just before the DHCP message trailer is added, so the
+ * options are at the end of a DHCP message.
+ * Signature:\code{.c}
+ * void my_hook(struct netif *netif, struct dhcp *dhcp, u8_t state, struct dhcp_msg *msg,
+ * u8_t msg_type, u16_t *options_len_ptr);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - dhcp: struct dhcp on that netif
+ * - state: current dhcp state (dhcp_state_enum_t as an u8_t)
+ * - msg: struct dhcp_msg that will be sent
+ * - msg_type: dhcp message type to be sent (u8_t)
+ * - options_len_ptr: pointer to the current length of options in the dhcp_msg "msg"
+ * (must be increased when options are added!)
+ *
+ * Options need to appended like this:
+ * LWIP_ASSERT("dhcp option overflow", *options_len_ptr + option_len + 2 <= DHCP_OPTIONS_LEN);
+ * msg->options[(*options_len_ptr)++] = <option_number>;
+ * msg->options[(*options_len_ptr)++] = <option_len>;
+ * msg->options[(*options_len_ptr)++] = <option_bytes>;
+ * [...]
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr)
+#endif
+
+/**
+ * LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, option_value_offset):
+ * Called from dhcp_parse_reply when receiving a DHCP message.
+ * This hook is called for every option in the received message that is not handled internally.
+ * Signature:\code{.c}
+ * void my_hook(struct netif *netif, struct dhcp *dhcp, u8_t state, struct dhcp_msg *msg,
+ * u8_t msg_type, u8_t option, u8_t option_len, struct pbuf *pbuf, u16_t option_value_offset);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - dhcp: struct dhcp on that netif
+ * - state: current dhcp state (dhcp_state_enum_t as an u8_t)
+ * - msg: struct dhcp_msg that was received
+ * - msg_type: dhcp message type received (u8_t, ATTENTION: only valid after
+ * the message type option has been parsed!)
+ * - option: option value (u8_t)
+ * - len: option data length (u8_t)
+ * - pbuf: pbuf where option data is contained
+ * - option_value_offset: offset in pbuf where option data begins
+ *
+ * A nice way to get the option contents is pbuf_get_contiguous():
+ * u8_t buf[32];
+ * u8_t *ptr = (u8_t*)pbuf_get_contiguous(p, buf, sizeof(buf), LWIP_MIN(option_len, sizeof(buf)), offset);
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, offset)
+#endif
+
+/**
+ * LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len):
+ * Called from various dhcp6 functions when sending a DHCP6 message.
+ * This hook is called just before the DHCP6 message is sent, so the
+ * options are at the end of a DHCP6 message.
+ * Signature:\code{.c}
+ * void my_hook(struct netif *netif, struct dhcp6 *dhcp, u8_t state, struct dhcp6_msg *msg,
+ * u8_t msg_type, u16_t *options_len_ptr);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - dhcp6: struct dhcp6 on that netif
+ * - state: current dhcp6 state (dhcp6_state_enum_t as an u8_t)
+ * - msg: struct dhcp6_msg that will be sent
+ * - msg_type: dhcp6 message type to be sent (u8_t)
+ * - options_len_ptr: pointer to the current length of options in the dhcp6_msg "msg"
+ * (must be increased when options are added!)
+ *
+ * Options need to appended like this:
+ * u8_t *options = (u8_t *)(msg + 1);
+ * LWIP_ASSERT("dhcp option overflow", sizeof(struct dhcp6_msg) + *options_len_ptr + newoptlen <= max_len);
+ * options[(*options_len_ptr)++] = <option_data>;
+ * [...]
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len)
+#endif
+
+/**
+ * LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+ * Called from socket API to implement setsockopt() for options not provided by lwIP.
+ * Core lock is held when this hook is called.
+ * Signature:\code{.c}
+ * int my_hook(int s, struct lwip_sock *sock, int level, int optname, const void *optval, socklen_t optlen, int *err)
+ * \endcode
+ * Arguments:
+ * - s: socket file descriptor
+ * - sock: internal socket descriptor (see lwip/priv/sockets_priv.h)
+ * - level: protocol level at which the option resides
+ * - optname: option to set
+ * - optval: value to set
+ * - optlen: size of optval
+ * - err: output error
+ * Return values:
+ * - 0: Hook has not consumed the option, code continues as normal (to internal options)
+ * - != 0: Hook has consumed the option, 'err' is returned
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+#endif
+
+/**
+ * LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+ * Called from socket API to implement getsockopt() for options not provided by lwIP.
+ * Core lock is held when this hook is called.
+ * Signature:\code{.c}
+ * int my_hook(int s, struct lwip_sock *sock, int level, int optname, void *optval, socklen_t *optlen, int *err)
+ * \endcode
+ * Arguments:
+ * - s: socket file descriptor
+ * - sock: internal socket descriptor (see lwip/priv/sockets_priv.h)
+ * - level: protocol level at which the option resides
+ * - optname: option to get
+ * - optval: value to get
+ * - optlen: size of optval
+ * - err: output error
+ * Return values:
+ * - 0: Hook has not consumed the option, code continues as normal (to internal options)
+ * - != 0: Hook has consumed the option, 'err' is returned
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+#endif
+
+/**
+ * LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, addrtype, err)
+ * Called from netconn APIs (not usable with callback apps) allowing an
+ * external DNS resolver (which uses sequential API) to handle the query.
+ * Signature:\code{.c}
+ * int my_hook(const char *name, ip_addr_t *addr, u8_t addrtype, err_t *err)
+ * \endcode
+ * Arguments:
+ * - name: hostname to resolve
+ * - addr: output host address
+ * - addrtype: type of address to query
+ * - err: output error
+ * Return values:
+ * - 0: Hook has not consumed hostname query, query continues into DNS module
+ * - != 0: Hook has consumed the query
+ *
+ * err must also be checked to determine if the hook consumed the query, but
+ * the query failed
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, addrtype, err)
+#endif
+/**
+ * @}
+ */
+
+/*
+ ---------------------------------------
+ ---------- Debugging options ----------
+ ---------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_debugmsg Debug messages
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ * @see debugging_levels
+ */
+#if !defined LWIP_DBG_MIN_LEVEL || defined __DOXYGEN__
+#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ * @see debugging_levels
+ */
+#if !defined LWIP_DBG_TYPES_ON || defined __DOXYGEN__
+#define LWIP_DBG_TYPES_ON LWIP_DBG_ON
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#if !defined ETHARP_DEBUG || defined __DOXYGEN__
+#define ETHARP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#if !defined NETIF_DEBUG || defined __DOXYGEN__
+#define NETIF_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#if !defined PBUF_DEBUG || defined __DOXYGEN__
+#define PBUF_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#if !defined API_LIB_DEBUG || defined __DOXYGEN__
+#define API_LIB_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#if !defined API_MSG_DEBUG || defined __DOXYGEN__
+#define API_MSG_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#if !defined SOCKETS_DEBUG || defined __DOXYGEN__
+#define SOCKETS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#if !defined ICMP_DEBUG || defined __DOXYGEN__
+#define ICMP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#if !defined IGMP_DEBUG || defined __DOXYGEN__
+#define IGMP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#if !defined INET_DEBUG || defined __DOXYGEN__
+#define INET_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#if !defined IP_DEBUG || defined __DOXYGEN__
+#define IP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#if !defined IP_REASS_DEBUG || defined __DOXYGEN__
+#define IP_REASS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#if !defined RAW_DEBUG || defined __DOXYGEN__
+#define RAW_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#if !defined MEM_DEBUG || defined __DOXYGEN__
+#define MEM_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#if !defined MEMP_DEBUG || defined __DOXYGEN__
+#define MEMP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#if !defined SYS_DEBUG || defined __DOXYGEN__
+#define SYS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TIMERS_DEBUG: Enable debugging in timers.c.
+ */
+#if !defined TIMERS_DEBUG || defined __DOXYGEN__
+#define TIMERS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#if !defined TCP_DEBUG || defined __DOXYGEN__
+#define TCP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#if !defined TCP_INPUT_DEBUG || defined __DOXYGEN__
+#define TCP_INPUT_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#if !defined TCP_FR_DEBUG || defined __DOXYGEN__
+#define TCP_FR_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#if !defined TCP_RTO_DEBUG || defined __DOXYGEN__
+#define TCP_RTO_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#if !defined TCP_CWND_DEBUG || defined __DOXYGEN__
+#define TCP_CWND_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#if !defined TCP_WND_DEBUG || defined __DOXYGEN__
+#define TCP_WND_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#if !defined TCP_OUTPUT_DEBUG || defined __DOXYGEN__
+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#if !defined TCP_RST_DEBUG || defined __DOXYGEN__
+#define TCP_RST_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#if !defined TCP_QLEN_DEBUG || defined __DOXYGEN__
+#define TCP_QLEN_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#if !defined UDP_DEBUG || defined __DOXYGEN__
+#define UDP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#if !defined TCPIP_DEBUG || defined __DOXYGEN__
+#define TCPIP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#if !defined SLIP_DEBUG || defined __DOXYGEN__
+#define SLIP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#if !defined DHCP_DEBUG || defined __DOXYGEN__
+#define DHCP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#if !defined AUTOIP_DEBUG || defined __DOXYGEN__
+#define AUTOIP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#if !defined DNS_DEBUG || defined __DOXYGEN__
+#define DNS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * IP6_DEBUG: Enable debugging for IPv6.
+ */
+#if !defined IP6_DEBUG || defined __DOXYGEN__
+#define IP6_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP6_DEBUG: Enable debugging in dhcp6.c.
+ */
+#if !defined DHCP6_DEBUG || defined __DOXYGEN__
+#define DHCP6_DEBUG LWIP_DBG_OFF
+#endif
+/**
+ * @}
+ */
+
+/**
+ * LWIP_TESTMODE: Changes to make unit test possible
+ */
+#if !defined LWIP_TESTMODE
+#define LWIP_TESTMODE 0
+#endif
+
+/*
+ --------------------------------------------------
+ ---------- Performance tracking options ----------
+ --------------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_perf Performance
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_PERF: Enable performance testing for lwIP
+ * (if enabled, arch/perf.h is included)
+ */
+#if !defined LWIP_PERF || defined __DOXYGEN__
+#define LWIP_PERF 0
+#endif
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_OPT_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/pbuf.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/pbuf.h
new file mode 100644
index 0000000..2ddd913
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/pbuf.h
@@ -0,0 +1,322 @@
+/**
+ * @file
+ * pbuf API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef LWIP_HDR_PBUF_H
+#define LWIP_HDR_PBUF_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LWIP_SUPPORT_CUSTOM_PBUF==1: Custom pbufs behave much like their pbuf type
+ * but they are allocated by external code (initialised by calling
+ * pbuf_alloced_custom()) and when pbuf_free gives up their last reference, they
+ * are freed by calling pbuf_custom->custom_free_function().
+ * Currently, the pbuf_custom code is only needed for one specific configuration
+ * of IP_FRAG, unless required by external driver/application code. */
+#ifndef LWIP_SUPPORT_CUSTOM_PBUF
+#define LWIP_SUPPORT_CUSTOM_PBUF ((IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG))
+#endif
+
+/** @ingroup pbuf
+ * PBUF_NEEDS_COPY(p): return a boolean value indicating whether the given
+ * pbuf needs to be copied in order to be kept around beyond the current call
+ * stack without risking being corrupted. The default setting provides safety:
+ * it will make a copy iof any pbuf chain that does not consist entirely of
+ * PBUF_ROM type pbufs. For setups with zero-copy support, it may be redefined
+ * to evaluate to true in all cases, for example. However, doing so also has an
+ * effect on the application side: any buffers that are *not* copied must also
+ * *not* be reused by the application after passing them to lwIP. For example,
+ * when setting PBUF_NEEDS_COPY to (0), after using udp_send() with a PBUF_RAM
+ * pbuf, the application must free the pbuf immediately, rather than reusing it
+ * for other purposes. For more background information on this, see tasks #6735
+ * and #7896, and bugs #11400 and #49914. */
+#ifndef PBUF_NEEDS_COPY
+#define PBUF_NEEDS_COPY(p) ((p)->type_internal & PBUF_TYPE_FLAG_DATA_VOLATILE)
+#endif /* PBUF_NEEDS_COPY */
+
+/* @todo: We need a mechanism to prevent wasting memory in every pbuf
+ (TCP vs. UDP, IPv4 vs. IPv6: UDP/IPv4 packets may waste up to 28 bytes) */
+
+#define PBUF_TRANSPORT_HLEN 20
+#if LWIP_IPV6
+#define PBUF_IP_HLEN 40
+#else
+#define PBUF_IP_HLEN 20
+#endif
+
+/**
+ * @ingroup pbuf
+ * Enumeration of pbuf layers
+ */
+typedef enum {
+ /** Includes spare room for transport layer header, e.g. UDP header.
+ * Use this if you intend to pass the pbuf to functions like udp_send().
+ */
+ PBUF_TRANSPORT = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN,
+ /** Includes spare room for IP header.
+ * Use this if you intend to pass the pbuf to functions like raw_send().
+ */
+ PBUF_IP = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN,
+ /** Includes spare room for link layer header (ethernet header).
+ * Use this if you intend to pass the pbuf to functions like ethernet_output().
+ * @see PBUF_LINK_HLEN
+ */
+ PBUF_LINK = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN,
+ /** Includes spare room for additional encapsulation header before ethernet
+ * headers (e.g. 802.11).
+ * Use this if you intend to pass the pbuf to functions like netif->linkoutput().
+ * @see PBUF_LINK_ENCAPSULATION_HLEN
+ */
+ PBUF_RAW_TX = PBUF_LINK_ENCAPSULATION_HLEN,
+ /** Use this for input packets in a netif driver when calling netif->input()
+ * in the most common case - ethernet-layer netif driver. */
+ PBUF_RAW = 0
+} pbuf_layer;
+
+
+/* Base flags for pbuf_type definitions: */
+
+/** Indicates that the payload directly follows the struct pbuf.
+ * This makes @ref pbuf_header work in both directions. */
+#define PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS 0x80
+/** Indicates the data stored in this pbuf can change. If this pbuf needs
+ * to be queued, it must be copied/duplicated. */
+#define PBUF_TYPE_FLAG_DATA_VOLATILE 0x40
+/** 4 bits are reserved for 16 allocation sources (e.g. heap, pool1, pool2, etc)
+ * Internally, we use: 0=heap, 1=MEMP_PBUF, 2=MEMP_PBUF_POOL -> 13 types free*/
+#define PBUF_TYPE_ALLOC_SRC_MASK 0x0F
+/** Indicates this pbuf is used for RX (if not set, indicates use for TX).
+ * This information can be used to keep some spare RX buffers e.g. for
+ * receiving TCP ACKs to unblock a connection) */
+#define PBUF_ALLOC_FLAG_RX 0x0100
+/** Indicates the application needs the pbuf payload to be in one piece */
+#define PBUF_ALLOC_FLAG_DATA_CONTIGUOUS 0x0200
+
+#define PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP 0x00
+#define PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF 0x01
+#define PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL 0x02
+/** First pbuf allocation type for applications */
+#define PBUF_TYPE_ALLOC_SRC_MASK_APP_MIN 0x03
+/** Last pbuf allocation type for applications */
+#define PBUF_TYPE_ALLOC_SRC_MASK_APP_MAX PBUF_TYPE_ALLOC_SRC_MASK
+
+/**
+ * @ingroup pbuf
+ * Enumeration of pbuf types
+ */
+typedef enum {
+ /** pbuf data is stored in RAM, used for TX mostly, struct pbuf and its payload
+ are allocated in one piece of contiguous memory (so the first payload byte
+ can be calculated from struct pbuf).
+ pbuf_alloc() allocates PBUF_RAM pbufs as unchained pbufs (although that might
+ change in future versions).
+ This should be used for all OUTGOING packets (TX).*/
+ PBUF_RAM = (PBUF_ALLOC_FLAG_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP),
+ /** pbuf data is stored in ROM, i.e. struct pbuf and its payload are located in
+ totally different memory areas. Since it points to ROM, payload does not
+ have to be copied when queued for transmission. */
+ PBUF_ROM = PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF,
+ /** pbuf comes from the pbuf pool. Much like PBUF_ROM but payload might change
+ so it has to be duplicated when queued before transmitting, depending on
+ who has a 'ref' to it. */
+ PBUF_REF = (PBUF_TYPE_FLAG_DATA_VOLATILE | PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF),
+ /** pbuf payload refers to RAM. This one comes from a pool and should be used
+ for RX. Payload can be chained (scatter-gather RX) but like PBUF_RAM, struct
+ pbuf and its payload are allocated in one piece of contiguous memory (so
+ the first payload byte can be calculated from struct pbuf).
+ Don't use this for TX, if the pool becomes empty e.g. because of TCP queuing,
+ you are unable to receive TCP acks! */
+ PBUF_POOL = (PBUF_ALLOC_FLAG_RX | PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL)
+} pbuf_type;
+
+
+/** indicates this packet's data should be immediately passed to the application */
+#define PBUF_FLAG_PUSH 0x01U
+/** indicates this is a custom pbuf: pbuf_free calls pbuf_custom->custom_free_function()
+ when the last reference is released (plus custom PBUF_RAM cannot be trimmed) */
+#define PBUF_FLAG_IS_CUSTOM 0x02U
+/** indicates this pbuf is UDP multicast to be looped back */
+#define PBUF_FLAG_MCASTLOOP 0x04U
+/** indicates this pbuf was received as link-level broadcast */
+#define PBUF_FLAG_LLBCAST 0x08U
+/** indicates this pbuf was received as link-level multicast */
+#define PBUF_FLAG_LLMCAST 0x10U
+/** indicates this pbuf includes a TCP FIN flag */
+#define PBUF_FLAG_TCP_FIN 0x20U
+
+/** Main packet buffer struct */
+struct pbuf {
+ /** next pbuf in singly linked pbuf chain */
+ struct pbuf *next;
+
+ /** pointer to the actual data in the buffer */
+ void *payload;
+
+ /**
+ * total length of this buffer and all next buffers in chain
+ * belonging to the same packet.
+ *
+ * For non-queue packet chains this is the invariant:
+ * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+ */
+ u16_t tot_len;
+
+ /** length of this buffer */
+ u16_t len;
+
+ /** a bit field indicating pbuf type and allocation sources
+ (see PBUF_TYPE_FLAG_*, PBUF_ALLOC_FLAG_* and PBUF_TYPE_ALLOC_SRC_MASK)
+ */
+ u8_t type_internal;
+
+ /** misc flags */
+ u8_t flags;
+
+ /**
+ * the reference count always equals the number of pointers
+ * that refer to this pbuf. This can be pointers from an application,
+ * the stack itself, or pbuf->next pointers from a chain.
+ */
+ LWIP_PBUF_REF_T ref;
+
+ /** For incoming packets, this contains the input netif's index */
+ u8_t if_idx;
+};
+
+
+/** Helper struct for const-correctness only.
+ * The only meaning of this one is to provide a const payload pointer
+ * for PBUF_ROM type.
+ */
+struct pbuf_rom {
+ /** next pbuf in singly linked pbuf chain */
+ struct pbuf *next;
+
+ /** pointer to the actual data in the buffer */
+ const void *payload;
+};
+
+#if LWIP_SUPPORT_CUSTOM_PBUF
+/** Prototype for a function to free a custom pbuf */
+typedef void (*pbuf_free_custom_fn)(struct pbuf *p);
+
+/** A custom pbuf: like a pbuf, but following a function pointer to free it. */
+struct pbuf_custom {
+ /** The actual pbuf */
+ struct pbuf pbuf;
+ /** This function is called when pbuf_free deallocates this pbuf(_custom) */
+ pbuf_free_custom_fn custom_free_function;
+};
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+
+/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */
+#ifndef PBUF_POOL_FREE_OOSEQ
+#define PBUF_POOL_FREE_OOSEQ 1
+#endif /* PBUF_POOL_FREE_OOSEQ */
+#if LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ
+extern volatile u8_t pbuf_free_ooseq_pending;
+void pbuf_free_ooseq(void);
+/** When not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ()
+ at regular intervals from main level to check if ooseq pbufs need to be
+ freed! */
+#define PBUF_CHECK_FREE_OOSEQ() do { if(pbuf_free_ooseq_pending) { \
+ /* pbuf_alloc() reported PBUF_POOL to be empty -> try to free some \
+ ooseq queued pbufs now */ \
+ pbuf_free_ooseq(); }}while(0)
+#else /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ */
+ /* Otherwise declare an empty PBUF_CHECK_FREE_OOSEQ */
+ #define PBUF_CHECK_FREE_OOSEQ()
+#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ*/
+
+/* Initializes the pbuf module. This call is empty for now, but may not be in future. */
+#define pbuf_init()
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type);
+struct pbuf *pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type);
+#if LWIP_SUPPORT_CUSTOM_PBUF
+struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type,
+ struct pbuf_custom *p, void *payload_mem,
+ u16_t payload_mem_len);
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+void pbuf_realloc(struct pbuf *p, u16_t size);
+#define pbuf_get_allocsrc(p) ((p)->type_internal & PBUF_TYPE_ALLOC_SRC_MASK)
+#define pbuf_match_allocsrc(p, type) (pbuf_get_allocsrc(p) == ((type) & PBUF_TYPE_ALLOC_SRC_MASK))
+#define pbuf_match_type(p, type) pbuf_match_allocsrc(p, type)
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+u8_t pbuf_header_force(struct pbuf *p, s16_t header_size);
+u8_t pbuf_add_header(struct pbuf *p, size_t header_size_increment);
+u8_t pbuf_add_header_force(struct pbuf *p, size_t header_size_increment);
+u8_t pbuf_remove_header(struct pbuf *p, size_t header_size);
+struct pbuf *pbuf_free_header(struct pbuf *q, u16_t size);
+void pbuf_ref(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u16_t pbuf_clen(const struct pbuf *p);
+void pbuf_cat(struct pbuf *head, struct pbuf *tail);
+void pbuf_chain(struct pbuf *head, struct pbuf *tail);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+err_t pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from);
+u16_t pbuf_copy_partial(const struct pbuf *p, void *dataptr, u16_t len, u16_t offset);
+void *pbuf_get_contiguous(const struct pbuf *p, void *buffer, size_t bufsize, u16_t len, u16_t offset);
+err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len);
+err_t pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset);
+struct pbuf *pbuf_skip(struct pbuf* in, u16_t in_offset, u16_t* out_offset);
+struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer);
+struct pbuf *pbuf_clone(pbuf_layer l, pbuf_type type, struct pbuf *p);
+#if LWIP_CHECKSUM_ON_COPY
+err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr,
+ u16_t len, u16_t *chksum);
+#endif /* LWIP_CHECKSUM_ON_COPY */
+#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+void pbuf_split_64k(struct pbuf *p, struct pbuf **rest);
+#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+u8_t pbuf_get_at(const struct pbuf* p, u16_t offset);
+int pbuf_try_get_at(const struct pbuf* p, u16_t offset);
+void pbuf_put_at(struct pbuf* p, u16_t offset, u8_t data);
+u16_t pbuf_memcmp(const struct pbuf* p, u16_t offset, const void* s2, u16_t n);
+u16_t pbuf_memfind(const struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset);
+u16_t pbuf_strstr(const struct pbuf* p, const char* substr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PBUF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/altcp_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/altcp_priv.h
new file mode 100644
index 0000000..2d3b2fd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/altcp_priv.h
@@ -0,0 +1,146 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ * This interface mimics the tcp callback API to the application while preventing
+ * direct linking (much like virtual functions).
+ * This way, an application can make use of other application layer protocols
+ * on top of TCP without knowing the details (e.g. TLS, proxy connection).
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_PRIV_H
+#define LWIP_HDR_ALTCP_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/altcp.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct altcp_pcb *altcp_alloc(void);
+void altcp_free(struct altcp_pcb *conn);
+
+/* Function prototypes for application layers */
+typedef void (*altcp_set_poll_fn)(struct altcp_pcb *conn, u8_t interval);
+typedef void (*altcp_recved_fn)(struct altcp_pcb *conn, u16_t len);
+typedef err_t (*altcp_bind_fn)(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port);
+typedef err_t (*altcp_connect_fn)(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected);
+
+typedef struct altcp_pcb *(*altcp_listen_fn)(struct altcp_pcb *conn, u8_t backlog, err_t *err);
+
+typedef void (*altcp_abort_fn)(struct altcp_pcb *conn);
+typedef err_t (*altcp_close_fn)(struct altcp_pcb *conn);
+typedef err_t (*altcp_shutdown_fn)(struct altcp_pcb *conn, int shut_rx, int shut_tx);
+
+typedef err_t (*altcp_write_fn)(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags);
+typedef err_t (*altcp_output_fn)(struct altcp_pcb *conn);
+
+typedef u16_t (*altcp_mss_fn)(struct altcp_pcb *conn);
+typedef u16_t (*altcp_sndbuf_fn)(struct altcp_pcb *conn);
+typedef u16_t (*altcp_sndqueuelen_fn)(struct altcp_pcb *conn);
+typedef void (*altcp_nagle_disable_fn)(struct altcp_pcb *conn);
+typedef void (*altcp_nagle_enable_fn)(struct altcp_pcb *conn);
+typedef int (*altcp_nagle_disabled_fn)(struct altcp_pcb *conn);
+
+typedef void (*altcp_setprio_fn)(struct altcp_pcb *conn, u8_t prio);
+
+typedef void (*altcp_dealloc_fn)(struct altcp_pcb *conn);
+
+typedef err_t (*altcp_get_tcp_addrinfo_fn)(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port);
+typedef ip_addr_t *(*altcp_get_ip_fn)(struct altcp_pcb *conn, int local);
+typedef u16_t (*altcp_get_port_fn)(struct altcp_pcb *conn, int local);
+
+#ifdef LWIP_DEBUG
+typedef enum tcp_state (*altcp_dbg_get_tcp_state_fn)(struct altcp_pcb *conn);
+#endif
+
+struct altcp_functions {
+ altcp_set_poll_fn set_poll;
+ altcp_recved_fn recved;
+ altcp_bind_fn bind;
+ altcp_connect_fn connect;
+ altcp_listen_fn listen;
+ altcp_abort_fn abort;
+ altcp_close_fn close;
+ altcp_shutdown_fn shutdown;
+ altcp_write_fn write;
+ altcp_output_fn output;
+ altcp_mss_fn mss;
+ altcp_sndbuf_fn sndbuf;
+ altcp_sndqueuelen_fn sndqueuelen;
+ altcp_nagle_disable_fn nagle_disable;
+ altcp_nagle_enable_fn nagle_enable;
+ altcp_nagle_disabled_fn nagle_disabled;
+ altcp_setprio_fn setprio;
+ altcp_dealloc_fn dealloc;
+ altcp_get_tcp_addrinfo_fn addrinfo;
+ altcp_get_ip_fn getip;
+ altcp_get_port_fn getport;
+#ifdef LWIP_DEBUG
+ altcp_dbg_get_tcp_state_fn dbg_get_tcp_state;
+#endif
+};
+
+void altcp_default_set_poll(struct altcp_pcb *conn, u8_t interval);
+void altcp_default_recved(struct altcp_pcb *conn, u16_t len);
+err_t altcp_default_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port);
+err_t altcp_default_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx);
+err_t altcp_default_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags);
+err_t altcp_default_output(struct altcp_pcb *conn);
+u16_t altcp_default_mss(struct altcp_pcb *conn);
+u16_t altcp_default_sndbuf(struct altcp_pcb *conn);
+u16_t altcp_default_sndqueuelen(struct altcp_pcb *conn);
+void altcp_default_nagle_disable(struct altcp_pcb *conn);
+void altcp_default_nagle_enable(struct altcp_pcb *conn);
+int altcp_default_nagle_disabled(struct altcp_pcb *conn);
+void altcp_default_setprio(struct altcp_pcb *conn, u8_t prio);
+void altcp_default_dealloc(struct altcp_pcb *conn);
+err_t altcp_default_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port);
+ip_addr_t *altcp_default_get_ip(struct altcp_pcb *conn, int local);
+u16_t altcp_default_get_port(struct altcp_pcb *conn, int local);
+#ifdef LWIP_DEBUG
+enum tcp_state altcp_default_dbg_get_tcp_state(struct altcp_pcb *conn);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ALTCP */
+
+#endif /* LWIP_HDR_ALTCP_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/api_msg.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/api_msg.h
new file mode 100644
index 0000000..9e8ffc9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/api_msg.h
@@ -0,0 +1,272 @@
+/**
+ * @file
+ * netconn API lwIP internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_API_MSG_H
+#define LWIP_HDR_API_MSG_H
+
+#include "lwip/opt.h"
+
+#include "lwip/arch.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+#include "lwip/priv/tcpip_priv.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#if LWIP_MPU_COMPATIBLE
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define API_MSG_M_DEF_SEM(m) *m
+#else
+#define API_MSG_M_DEF_SEM(m) API_MSG_M_DEF(m)
+#endif
+#else /* LWIP_MPU_COMPATIBLE */
+#define API_MSG_M_DEF_SEM(m) API_MSG_M_DEF(m)
+#endif /* LWIP_MPU_COMPATIBLE */
+
+/* For the netconn API, these values are use as a bitmask! */
+#define NETCONN_SHUT_RD 1
+#define NETCONN_SHUT_WR 2
+#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR)
+
+/* IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+/** This struct includes everything that is necessary to execute a function
+ for a netconn in another thread context (mainly used to process netconns
+ in the tcpip_thread context to be thread safe). */
+struct api_msg {
+ /** The netconn which to process - always needed: it includes the semaphore
+ which is used to block the application thread until the function finished. */
+ struct netconn *conn;
+ /** The return value of the function executed in tcpip_thread. */
+ err_t err;
+ /** Depending on the executed function, one of these union members is used */
+ union {
+ /** used for lwip_netconn_do_send */
+ struct netbuf *b;
+ /** used for lwip_netconn_do_newconn */
+ struct {
+ u8_t proto;
+ } n;
+ /** used for lwip_netconn_do_bind and lwip_netconn_do_connect */
+ struct {
+ API_MSG_M_DEF_C(ip_addr_t, ipaddr);
+ u16_t port;
+ u8_t if_idx;
+ } bc;
+ /** used for lwip_netconn_do_getaddr */
+ struct {
+ ip_addr_t API_MSG_M_DEF(ipaddr);
+ u16_t API_MSG_M_DEF(port);
+ u8_t local;
+ } ad;
+ /** used for lwip_netconn_do_write */
+ struct {
+ /** current vector to write */
+ const struct netvector *vector;
+ /** number of unwritten vectors */
+ u16_t vector_cnt;
+ /** offset into current vector */
+ size_t vector_off;
+ /** total length across vectors */
+ size_t len;
+ /** offset into total length/output of bytes written when err == ERR_OK */
+ size_t offset;
+ u8_t apiflags;
+#if LWIP_SO_SNDTIMEO
+ u32_t time_started;
+#endif /* LWIP_SO_SNDTIMEO */
+ } w;
+ /** used for lwip_netconn_do_recv */
+ struct {
+ size_t len;
+ } r;
+#if LWIP_TCP
+ /** used for lwip_netconn_do_close (/shutdown) */
+ struct {
+ u8_t shut;
+#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
+ u32_t time_started;
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+ u8_t polls_left;
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+ } sd;
+#endif /* LWIP_TCP */
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+ /** used for lwip_netconn_do_join_leave_group */
+ struct {
+ API_MSG_M_DEF_C(ip_addr_t, multiaddr);
+ API_MSG_M_DEF_C(ip_addr_t, netif_addr);
+ u8_t if_idx;
+ enum netconn_igmp join_or_leave;
+ } jl;
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+#if TCP_LISTEN_BACKLOG
+ struct {
+ u8_t backlog;
+ } lb;
+#endif /* TCP_LISTEN_BACKLOG */
+ } msg;
+#if LWIP_NETCONN_SEM_PER_THREAD
+ sys_sem_t* op_completed_sem;
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+};
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define LWIP_API_MSG_SEM(msg) ((msg)->op_completed_sem)
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define LWIP_API_MSG_SEM(msg) (&(msg)->conn->op_completed)
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+
+#if LWIP_DNS
+/** As lwip_netconn_do_gethostbyname requires more arguments but doesn't require a netconn,
+ it has its own struct (to avoid struct api_msg getting bigger than necessary).
+ lwip_netconn_do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg
+ (see netconn_gethostbyname). */
+struct dns_api_msg {
+ /** Hostname to query or dotted IP address string */
+#if LWIP_MPU_COMPATIBLE
+ char name[DNS_MAX_NAME_LENGTH];
+#else /* LWIP_MPU_COMPATIBLE */
+ const char *name;
+#endif /* LWIP_MPU_COMPATIBLE */
+ /** The resolved address is stored here */
+ ip_addr_t API_MSG_M_DEF(addr);
+#if LWIP_IPV4 && LWIP_IPV6
+ /** Type of resolve call */
+ u8_t dns_addrtype;
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+ /** This semaphore is posted when the name is resolved, the application thread
+ should wait on it. */
+ sys_sem_t API_MSG_M_DEF_SEM(sem);
+ /** Errors are given back here */
+ err_t API_MSG_M_DEF(err);
+};
+#endif /* LWIP_DNS */
+
+#if LWIP_NETCONN_FULLDUPLEX
+int lwip_netconn_is_deallocated_msg(void *msg);
+#endif
+int lwip_netconn_is_err_msg(void *msg, err_t *err);
+void lwip_netconn_do_newconn (void *m);
+void lwip_netconn_do_delconn (void *m);
+void lwip_netconn_do_bind (void *m);
+void lwip_netconn_do_bind_if (void *m);
+void lwip_netconn_do_connect (void *m);
+void lwip_netconn_do_disconnect (void *m);
+void lwip_netconn_do_listen (void *m);
+void lwip_netconn_do_send (void *m);
+void lwip_netconn_do_recv (void *m);
+#if TCP_LISTEN_BACKLOG
+void lwip_netconn_do_accepted (void *m);
+#endif /* TCP_LISTEN_BACKLOG */
+void lwip_netconn_do_write (void *m);
+void lwip_netconn_do_getaddr (void *m);
+void lwip_netconn_do_close (void *m);
+void lwip_netconn_do_shutdown (void *m);
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+void lwip_netconn_do_join_leave_group(void *m);
+void lwip_netconn_do_join_leave_group_netif(void *m);
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+void lwip_netconn_do_gethostbyname(void *arg);
+#endif /* LWIP_DNS */
+
+struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback);
+void netconn_free(struct netconn *conn);
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+/* netifapi related lwIP internal definitions */
+
+#if LWIP_MPU_COMPATIBLE
+#define NETIFAPI_IPADDR_DEF(type, m) type m
+#else /* LWIP_MPU_COMPATIBLE */
+#define NETIFAPI_IPADDR_DEF(type, m) const type * m
+#endif /* LWIP_MPU_COMPATIBLE */
+
+typedef void (*netifapi_void_fn)(struct netif *netif);
+typedef err_t (*netifapi_errt_fn)(struct netif *netif);
+
+struct netifapi_msg {
+ struct tcpip_api_call_data call;
+ struct netif *netif;
+ union {
+ struct {
+#if LWIP_IPV4
+ NETIFAPI_IPADDR_DEF(ip4_addr_t, ipaddr);
+ NETIFAPI_IPADDR_DEF(ip4_addr_t, netmask);
+ NETIFAPI_IPADDR_DEF(ip4_addr_t, gw);
+#endif /* LWIP_IPV4 */
+ void *state;
+ netif_init_fn init;
+ netif_input_fn input;
+ } add;
+ struct {
+ netifapi_void_fn voidfunc;
+ netifapi_errt_fn errtfunc;
+ } common;
+ struct {
+#if LWIP_MPU_COMPATIBLE
+ char name[NETIF_NAMESIZE];
+#else /* LWIP_MPU_COMPATIBLE */
+ char *name;
+#endif /* LWIP_MPU_COMPATIBLE */
+ u8_t index;
+ } ifs;
+ } msg;
+};
+
+#endif /* LWIP_NETIF_API */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_API_MSG_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/mem_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/mem_priv.h
new file mode 100644
index 0000000..8630d75
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/mem_priv.h
@@ -0,0 +1,84 @@
+/**
+ * @file
+ * lwIP internal memory implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2018 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#ifndef LWIP_HDR_MEM_PRIV_H
+#define LWIP_HDR_MEM_PRIV_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/mem.h"
+
+#if MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK
+/* if MEM_OVERFLOW_CHECK or MEMP_OVERFLOW_CHECK is turned on, we reserve some
+ * bytes at the beginning and at the end of each element, initialize them as
+ * 0xcd and check them later.
+ * If MEM(P)_OVERFLOW_CHECK is >= 2, on every call to mem(p)_malloc or mem(p)_free,
+ * every single element in each pool/heap is checked!
+ * This is VERY SLOW but also very helpful.
+ * MEM_SANITY_REGION_BEFORE and MEM_SANITY_REGION_AFTER can be overridden in
+ * lwipopts.h to change the amount reserved for checking. */
+#ifndef MEM_SANITY_REGION_BEFORE
+#define MEM_SANITY_REGION_BEFORE 16
+#endif /* MEM_SANITY_REGION_BEFORE*/
+#if MEM_SANITY_REGION_BEFORE > 0
+#define MEM_SANITY_REGION_BEFORE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SANITY_REGION_BEFORE)
+#else
+#define MEM_SANITY_REGION_BEFORE_ALIGNED 0
+#endif /* MEM_SANITY_REGION_BEFORE*/
+#ifndef MEM_SANITY_REGION_AFTER
+#define MEM_SANITY_REGION_AFTER 16
+#endif /* MEM_SANITY_REGION_AFTER*/
+#if MEM_SANITY_REGION_AFTER > 0
+#define MEM_SANITY_REGION_AFTER_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SANITY_REGION_AFTER)
+#else
+#define MEM_SANITY_REGION_AFTER_ALIGNED 0
+#endif /* MEM_SANITY_REGION_AFTER*/
+
+void mem_overflow_init_raw(void *p, size_t size);
+void mem_overflow_check_raw(void *p, size_t size, const char *descr1, const char *descr2);
+
+#endif /* MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_priv.h
new file mode 100644
index 0000000..1f14cb1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_priv.h
@@ -0,0 +1,161 @@
+/**
+ * @file
+ * memory pools lwIP internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef LWIP_HDR_MEMP_PRIV_H
+#define LWIP_HDR_MEMP_PRIV_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/mem.h"
+#include "lwip/priv/mem_priv.h"
+
+#if MEMP_OVERFLOW_CHECK
+
+
+/* MEMP_SIZE: save space for struct memp and for sanity check */
+#define MEMP_SIZE (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEM_SANITY_REGION_BEFORE_ALIGNED)
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEM_SANITY_REGION_AFTER_ALIGNED)
+
+#else /* MEMP_OVERFLOW_CHECK */
+
+/* No sanity checks
+ * We don't need to preserve the struct memp while not allocated, so we
+ * can save a little space and set MEMP_SIZE to 0.
+ */
+#define MEMP_SIZE 0
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_OVERFLOW_CHECK */
+
+#if !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK
+struct memp {
+ struct memp *next;
+#if MEMP_OVERFLOW_CHECK
+ const char *file;
+ int line;
+#endif /* MEMP_OVERFLOW_CHECK */
+};
+#endif /* !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK */
+
+#if MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS
+/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */
+typedef enum {
+ /* Get the first (via:
+ MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/
+ MEMP_POOL_HELPER_FIRST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START 1
+#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0
+#define LWIP_MALLOC_MEMPOOL_END
+#include "lwip/priv/memp_std.h"
+ ) ,
+ /* Get the last (via:
+ MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */
+ MEMP_POOL_HELPER_LAST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size *
+#define LWIP_MALLOC_MEMPOOL_END 1
+#include "lwip/priv/memp_std.h"
+ )
+} memp_pool_helper_t;
+
+/* The actual start and stop values are here (cast them over)
+ We use this helper type and these defines so we can avoid using const memp_t values */
+#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST)
+#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST)
+#endif /* MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS */
+
+/** Memory pool descriptor */
+struct memp_desc {
+#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY
+ /** Textual description */
+ const char *desc;
+#endif /* LWIP_DEBUG || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY */
+#if MEMP_STATS
+ /** Statistics */
+ struct stats_mem *stats;
+#endif
+
+ /** Element size */
+ u16_t size;
+
+#if !MEMP_MEM_MALLOC
+ /** Number of elements */
+ u16_t num;
+
+ /** Base address */
+ u8_t *base;
+
+ /** First free element of each pool. Elements form a linked list. */
+ struct memp **tab;
+#endif /* MEMP_MEM_MALLOC */
+};
+
+#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY
+#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc),
+#else
+#define DECLARE_LWIP_MEMPOOL_DESC(desc)
+#endif
+
+#if MEMP_STATS
+#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name) static struct stats_mem name;
+#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name) &name,
+#else
+#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name)
+#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name)
+#endif
+
+void memp_init_pool(const struct memp_desc *desc);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_pool_fn(const struct memp_desc* desc, const char* file, const int line);
+#define memp_malloc_pool(d) memp_malloc_pool_fn((d), __FILE__, __LINE__)
+#else
+void *memp_malloc_pool(const struct memp_desc *desc);
+#endif
+void memp_free_pool(const struct memp_desc* desc, void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_std.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_std.h
new file mode 100644
index 0000000..669ad4d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/memp_std.h
@@ -0,0 +1,153 @@
+/**
+ * @file
+ * lwIP internal memory pools (do not use in application code)
+ * This file is deliberately included multiple times: once with empty
+ * definition of LWIP_MEMPOOL() to handle all includes and multiple times
+ * to build up various lists of mem pools.
+ */
+
+/*
+ * SETUP: Make sure we define everything we will need.
+ *
+ * We have create three types of pools:
+ * 1) MEMPOOL - standard pools
+ * 2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c
+ * 3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct
+ *
+ * If the include'r doesn't require any special treatment of each of the types
+ * above, then will declare #2 & #3 to be just standard mempools.
+ */
+#ifndef LWIP_MALLOC_MEMPOOL
+/* This treats "malloc pools" just like any other pool.
+ The pools are a little bigger to provide 'size' as the amount of user data. */
+#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))), "MALLOC_"#size)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL_END
+#endif /* LWIP_MALLOC_MEMPOOL */
+
+#ifndef LWIP_PBUF_MEMPOOL
+/* This treats "pbuf pools" just like any other pool.
+ * Allocates buffers for a pbuf struct AND a payload size */
+#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) + LWIP_MEM_ALIGN_SIZE(payload)), desc)
+#endif /* LWIP_PBUF_MEMPOOL */
+
+
+/*
+ * A list of internal pools used by LWIP.
+ *
+ * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description)
+ * creates a pool name MEMP_pool_name. description is used in stats.c
+ */
+#if LWIP_RAW
+LWIP_MEMPOOL(RAW_PCB, MEMP_NUM_RAW_PCB, sizeof(struct raw_pcb), "RAW_PCB")
+#endif /* LWIP_RAW */
+
+#if LWIP_UDP
+LWIP_MEMPOOL(UDP_PCB, MEMP_NUM_UDP_PCB, sizeof(struct udp_pcb), "UDP_PCB")
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+LWIP_MEMPOOL(TCP_PCB, MEMP_NUM_TCP_PCB, sizeof(struct tcp_pcb), "TCP_PCB")
+LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN, sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN")
+LWIP_MEMPOOL(TCP_SEG, MEMP_NUM_TCP_SEG, sizeof(struct tcp_seg), "TCP_SEG")
+#endif /* LWIP_TCP */
+
+#if LWIP_ALTCP && LWIP_TCP
+LWIP_MEMPOOL(ALTCP_PCB, MEMP_NUM_ALTCP_PCB, sizeof(struct altcp_pcb), "ALTCP_PCB")
+#endif /* LWIP_ALTCP && LWIP_TCP */
+
+#if LWIP_IPV4 && IP_REASSEMBLY
+LWIP_MEMPOOL(REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip_reassdata), "REASSDATA")
+#endif /* LWIP_IPV4 && IP_REASSEMBLY */
+#if (IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG)
+LWIP_MEMPOOL(FRAG_PBUF, MEMP_NUM_FRAG_PBUF, sizeof(struct pbuf_custom_ref),"FRAG_PBUF")
+#endif /* IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF || (LWIP_IPV6 && LWIP_IPV6_FRAG) */
+
+#if LWIP_NETCONN || LWIP_SOCKET
+LWIP_MEMPOOL(NETBUF, MEMP_NUM_NETBUF, sizeof(struct netbuf), "NETBUF")
+LWIP_MEMPOOL(NETCONN, MEMP_NUM_NETCONN, sizeof(struct netconn), "NETCONN")
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(TCPIP_MSG_API, MEMP_NUM_TCPIP_MSG_API, sizeof(struct tcpip_msg), "TCPIP_MSG_API")
+#if LWIP_MPU_COMPATIBLE
+LWIP_MEMPOOL(API_MSG, MEMP_NUM_API_MSG, sizeof(struct api_msg), "API_MSG")
+#if LWIP_DNS
+LWIP_MEMPOOL(DNS_API_MSG, MEMP_NUM_DNS_API_MSG, sizeof(struct dns_api_msg), "DNS_API_MSG")
+#endif
+#if LWIP_SOCKET && !LWIP_TCPIP_CORE_LOCKING
+LWIP_MEMPOOL(SOCKET_SETGETSOCKOPT_DATA, MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA, sizeof(struct lwip_setgetsockopt_data), "SOCKET_SETGETSOCKOPT_DATA")
+#endif
+#if LWIP_SOCKET && (LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL)
+LWIP_MEMPOOL(SELECT_CB, MEMP_NUM_SELECT_CB, sizeof(struct lwip_select_cb), "SELECT_CB")
+#endif /* LWIP_SOCKET && (LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL) */
+#if LWIP_NETIF_API
+LWIP_MEMPOOL(NETIFAPI_MSG, MEMP_NUM_NETIFAPI_MSG, sizeof(struct netifapi_msg), "NETIFAPI_MSG")
+#endif
+#endif /* LWIP_MPU_COMPATIBLE */
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg), "TCPIP_MSG_INPKT")
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+#endif /* NO_SYS==0 */
+
+#if LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING
+LWIP_MEMPOOL(ARP_QUEUE, MEMP_NUM_ARP_QUEUE, sizeof(struct etharp_q_entry), "ARP_QUEUE")
+#endif /* LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING */
+
+#if LWIP_IGMP
+LWIP_MEMPOOL(IGMP_GROUP, MEMP_NUM_IGMP_GROUP, sizeof(struct igmp_group), "IGMP_GROUP")
+#endif /* LWIP_IGMP */
+
+#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM
+LWIP_MEMPOOL(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT")
+#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */
+
+#if LWIP_DNS && LWIP_SOCKET
+LWIP_MEMPOOL(NETDB, MEMP_NUM_NETDB, NETDB_ELEM_SIZE, "NETDB")
+#endif /* LWIP_DNS && LWIP_SOCKET */
+#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+LWIP_MEMPOOL(LOCALHOSTLIST, MEMP_NUM_LOCALHOSTLIST, LOCALHOSTLIST_ELEM_SIZE, "LOCALHOSTLIST")
+#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+#if LWIP_IPV6 && LWIP_ND6_QUEUEING
+LWIP_MEMPOOL(ND6_QUEUE, MEMP_NUM_ND6_QUEUE, sizeof(struct nd6_q_entry), "ND6_QUEUE")
+#endif /* LWIP_IPV6 && LWIP_ND6_QUEUEING */
+
+#if LWIP_IPV6 && LWIP_IPV6_REASS
+LWIP_MEMPOOL(IP6_REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip6_reassdata), "IP6_REASSDATA")
+#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+LWIP_MEMPOOL(MLD6_GROUP, MEMP_NUM_MLD6_GROUP, sizeof(struct mld_group), "MLD6_GROUP")
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+
+/*
+ * A list of pools of pbuf's used by LWIP.
+ *
+ * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description)
+ * creates a pool name MEMP_pool_name. description is used in stats.c
+ * This allocates enough space for the pbuf struct and a payload.
+ * (Example: pbuf_payload_size=0 allocates only size for the struct)
+ */
+LWIP_MEMPOOL(PBUF, MEMP_NUM_PBUF, sizeof(struct pbuf), "PBUF_REF/ROM")
+LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE, PBUF_POOL_BUFSIZE, "PBUF_POOL")
+
+
+/*
+ * Allow for user-defined pools; this must be explicitly set in lwipopts.h
+ * since the default is to NOT look for lwippools.h
+ */
+#if MEMP_USE_CUSTOM_POOLS
+#include "lwippools.h"
+#endif /* MEMP_USE_CUSTOM_POOLS */
+
+/*
+ * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later
+ * (#undef is ignored for something that is not defined)
+ */
+#undef LWIP_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL_START
+#undef LWIP_MALLOC_MEMPOOL_END
+#undef LWIP_PBUF_MEMPOOL
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/nd6_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/nd6_priv.h
new file mode 100644
index 0000000..cc3007d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/nd6_priv.h
@@ -0,0 +1,142 @@
+/**
+ * @file
+ *
+ * Neighbor discovery and stateless address autoconfiguration for IPv6.
+ * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
+ * (Address autoconfiguration).
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+
+#ifndef LWIP_HDR_ND6_PRIV_H
+#define LWIP_HDR_ND6_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_ND6_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+ * defined here to be accessed by memp.h
+ */
+struct nd6_q_entry {
+ struct nd6_q_entry *next;
+ struct pbuf *p;
+};
+#endif /* LWIP_ND6_QUEUEING */
+
+/** Struct for tables. */
+struct nd6_neighbor_cache_entry {
+ ip6_addr_t next_hop_address;
+ struct netif *netif;
+ u8_t lladdr[NETIF_MAX_HWADDR_LEN];
+ /*u32_t pmtu;*/
+#if LWIP_ND6_QUEUEING
+ /** Pointer to queue of pending outgoing packets on this entry. */
+ struct nd6_q_entry *q;
+#else /* LWIP_ND6_QUEUEING */
+ /** Pointer to a single pending outgoing packet on this entry. */
+ struct pbuf *q;
+#endif /* LWIP_ND6_QUEUEING */
+ u8_t state;
+ u8_t isrouter;
+ union {
+ u32_t reachable_time; /* in seconds */
+ u32_t delay_time; /* ticks (ND6_TMR_INTERVAL) */
+ u32_t probes_sent;
+ u32_t stale_time; /* ticks (ND6_TMR_INTERVAL) */
+ } counter;
+};
+
+struct nd6_destination_cache_entry {
+ ip6_addr_t destination_addr;
+ ip6_addr_t next_hop_addr;
+ u16_t pmtu;
+ u32_t age;
+};
+
+struct nd6_prefix_list_entry {
+ ip6_addr_t prefix;
+ struct netif *netif;
+ u32_t invalidation_timer; /* in seconds */
+};
+
+struct nd6_router_list_entry {
+ struct nd6_neighbor_cache_entry *neighbor_entry;
+ u32_t invalidation_timer; /* in seconds */
+ u8_t flags;
+};
+
+enum nd6_neighbor_cache_entry_state {
+ ND6_NO_ENTRY = 0,
+ ND6_INCOMPLETE,
+ ND6_REACHABLE,
+ ND6_STALE,
+ ND6_DELAY,
+ ND6_PROBE
+};
+
+#define ND6_HOPLIM 255 /* maximum hop limit, required in all ND packets */
+
+#define ND6_2HRS 7200 /* two hours, expressed in number of seconds */
+
+/* Router tables. */
+/* @todo make these static? and entries accessible through API? */
+extern struct nd6_neighbor_cache_entry neighbor_cache[];
+extern struct nd6_destination_cache_entry destination_cache[];
+extern struct nd6_prefix_list_entry prefix_list[];
+extern struct nd6_router_list_entry default_router_list[];
+
+/* Default values, can be updated by a RA message. */
+extern u32_t reachable_time;
+extern u32_t retrans_timer;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_ND6_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/raw_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/raw_priv.h
new file mode 100644
index 0000000..d4561d4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/raw_priv.h
@@ -0,0 +1,69 @@
+/**
+ * @file
+ * raw API internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_RAW_PRIV_H
+#define LWIP_HDR_RAW_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/raw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** return codes for raw_input */
+typedef enum raw_input_state
+{
+ RAW_INPUT_NONE = 0, /* pbuf did not match any pcbs */
+ RAW_INPUT_EATEN, /* pbuf handed off and delivered to pcb */
+ RAW_INPUT_DELIVERED /* pbuf only delivered to pcb (pbuf can still be referenced) */
+} raw_input_state_t;
+
+/* The following functions are the lower layer interface to RAW. */
+raw_input_state_t raw_input(struct pbuf *p, struct netif *inp);
+
+void raw_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* LWIP_HDR_RAW_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/sockets_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/sockets_priv.h
new file mode 100644
index 0000000..d8f9904
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/sockets_priv.h
@@ -0,0 +1,175 @@
+/**
+ * @file
+ * Sockets API internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Joel Cunningham
+ *
+ */
+#ifndef LWIP_HDR_SOCKETS_PRIV_H
+#define LWIP_HDR_SOCKETS_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/sockets.h"
+#include "lwip/sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+/** This is overridable for the rare case where more than 255 threads
+ * select on the same socket...
+ */
+#ifndef SELWAIT_T
+#define SELWAIT_T u8_t
+#endif
+
+union lwip_sock_lastdata {
+ struct netbuf *netbuf;
+ struct pbuf *pbuf;
+};
+
+/** Contains all internal pointers and states used for a socket */
+struct lwip_sock {
+ /** sockets currently are built on netconns, each socket has one netconn */
+ struct netconn *conn;
+ /** data that was left from the previous read */
+ union lwip_sock_lastdata lastdata;
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+ /** number of times data was received, set by event_callback(),
+ tested by the receive and select functions */
+ s16_t rcvevent;
+ /** number of times data was ACKed (free send buffer), set by event_callback(),
+ tested by select */
+ u16_t sendevent;
+ /** error happened for this socket, set by event_callback(), tested by select */
+ u16_t errevent;
+ /** counter of how many threads are waiting for this socket using select */
+ SELWAIT_T select_waiting;
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+#if LWIP_NETCONN_FULLDUPLEX
+ /* counter of how many threads are using a struct lwip_sock (not the 'int') */
+ u8_t fd_used;
+ /* status of pending close/delete actions */
+ u8_t fd_free_pending;
+#define LWIP_SOCK_FD_FREE_TCP 1
+#define LWIP_SOCK_FD_FREE_FREE 2
+#endif
+};
+
+#ifndef set_errno
+#define set_errno(err) do { if (err) { errno = (err); } } while(0)
+#endif
+
+#if !LWIP_TCPIP_CORE_LOCKING
+/** Maximum optlen used by setsockopt/getsockopt */
+#define LWIP_SETGETSOCKOPT_MAXOPTLEN LWIP_MAX(16, sizeof(struct ifreq))
+
+/** This struct is used to pass data to the set/getsockopt_internal
+ * functions running in tcpip_thread context (only a void* is allowed) */
+struct lwip_setgetsockopt_data {
+ /** socket index for which to change options */
+ int s;
+ /** level of the option to process */
+ int level;
+ /** name of the option to process */
+ int optname;
+ /** set: value to set the option to
+ * get: value of the option is stored here */
+#if LWIP_MPU_COMPATIBLE
+ u8_t optval[LWIP_SETGETSOCKOPT_MAXOPTLEN];
+#else
+ union {
+ void *p;
+ const void *pc;
+ } optval;
+#endif
+ /** size of *optval */
+ socklen_t optlen;
+ /** if an error occurs, it is temporarily stored here */
+ int err;
+ /** semaphore to wake up the calling task */
+ void* completed_sem;
+};
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+#ifdef __cplusplus
+}
+#endif
+
+struct lwip_sock* lwip_socket_dbg_get_socket(int fd);
+
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define SELECT_SEM_T sys_sem_t*
+#define SELECT_SEM_PTR(sem) (sem)
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define SELECT_SEM_T sys_sem_t
+#define SELECT_SEM_PTR(sem) (&(sem))
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+/** Description for a task waiting in select */
+struct lwip_select_cb {
+ /** Pointer to the next waiting task */
+ struct lwip_select_cb *next;
+ /** Pointer to the previous waiting task */
+ struct lwip_select_cb *prev;
+#if LWIP_SOCKET_SELECT
+ /** readset passed to select */
+ fd_set *readset;
+ /** writeset passed to select */
+ fd_set *writeset;
+ /** unimplemented: exceptset passed to select */
+ fd_set *exceptset;
+#endif /* LWIP_SOCKET_SELECT */
+#if LWIP_SOCKET_POLL
+ /** fds passed to poll; NULL if select */
+ struct pollfd *poll_fds;
+ /** nfds passed to poll; 0 if select */
+ nfds_t poll_nfds;
+#endif /* LWIP_SOCKET_POLL */
+ /** don't signal the same semaphore twice: set to 1 when signalled */
+ int sem_signalled;
+ /** semaphore to wake up a task waiting for select */
+ SELECT_SEM_T sem;
+};
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+
+#endif /* LWIP_SOCKET */
+
+#endif /* LWIP_HDR_SOCKETS_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/tcp_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/tcp_priv.h
new file mode 100644
index 0000000..72f9126
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/tcp_priv.h
@@ -0,0 +1,523 @@
+/**
+ * @file
+ * TCP internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_TCP_PRIV_H
+#define LWIP_HDR_TCP_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/tcp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void tcp_init (void); /* Initialize this module. */
+void tcp_tmr (void); /* Must be called every
+ TCP_TMR_INTERVAL
+ ms. (Typically 250 ms). */
+/* It is also possible to call these two functions at the right
+ intervals (instead of calling tcp_tmr()). */
+void tcp_slowtmr (void);
+void tcp_fasttmr (void);
+
+/* Call this from a netif driver (watch out for threading issues!) that has
+ returned a memory error on transmit and now has free buffers to send more.
+ This iterates all active pcbs that had an error and tries to call
+ tcp_output, so use this with care as it might slow down the system. */
+void tcp_txnow (void);
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void tcp_input (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+struct tcp_pcb * tcp_alloc (u8_t prio);
+void tcp_free (struct tcp_pcb *pcb);
+void tcp_abandon (struct tcp_pcb *pcb, int reset);
+err_t tcp_send_empty_ack(struct tcp_pcb *pcb);
+err_t tcp_rexmit (struct tcp_pcb *pcb);
+err_t tcp_rexmit_rto_prepare(struct tcp_pcb *pcb);
+void tcp_rexmit_rto_commit(struct tcp_pcb *pcb);
+void tcp_rexmit_rto (struct tcp_pcb *pcb);
+void tcp_rexmit_fast (struct tcp_pcb *pcb);
+u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb);
+err_t tcp_process_refused_data(struct tcp_pcb *pcb);
+
+/**
+ * This is the Nagle algorithm: try to combine user data to send as few TCP
+ * segments as possible. Only send if
+ * - no previously transmitted data on the connection remains unacknowledged or
+ * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or
+ * - the only unsent segment is at least pcb->mss bytes long (or there is more
+ * than one unsent segment - with lwIP, this can happen although unsent->len < mss)
+ * - or if we are in fast-retransmit (TF_INFR)
+ */
+#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \
+ ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \
+ (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \
+ ((tpcb)->unsent->len >= (tpcb)->mss))) || \
+ ((tcp_sndbuf(tpcb) == 0) || (tcp_sndqueuelen(tpcb) >= TCP_SND_QUEUELEN)) \
+ ) ? 1 : 0)
+#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK)
+
+
+#define TCP_SEQ_LT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) < 0)
+#define TCP_SEQ_LEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) <= 0)
+#define TCP_SEQ_GT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) > 0)
+#define TCP_SEQ_GEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */
+
+#ifndef TCP_MSL
+#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */
+#endif
+
+/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */
+#ifndef TCP_KEEPIDLE_DEFAULT
+#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */
+#endif
+
+#ifndef TCP_KEEPINTVL_DEFAULT
+#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */
+#endif
+
+#ifndef TCP_KEEPCNT_DEFAULT
+#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */
+#endif
+
+#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */
+
+#define TCP_TCPLEN(seg) ((seg)->len + (((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0) ? 1U : 0U))
+
+/** Flags used on input processing, not on pcb->flags
+*/
+#define TF_RESET (u8_t)0x08U /* Connection was reset. */
+#define TF_CLOSED (u8_t)0x10U /* Connection was successfully closed. */
+#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */
+
+
+#if LWIP_EVENT_API
+
+#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) ret = lwip_tcp_event(arg, (pcb),\
+ LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_RECV, NULL, 0, ERR_OK)
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+ LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret) do { if ((pcb)->state != SYN_RCVD) { \
+ ret = lwip_tcp_event((pcb)->callback_arg, (pcb), LWIP_EVENT_POLL, NULL, 0, ERR_OK); \
+ } else { \
+ ret = ERR_ARG; } } while(0)
+/* For event API, last state SYN_RCVD must be excluded here: the application
+ has not seen this pcb, yet! */
+#define TCP_EVENT_ERR(last_state,errf,arg,err) do { if (last_state != SYN_RCVD) { \
+ lwip_tcp_event((arg), NULL, LWIP_EVENT_ERR, NULL, 0, (err)); } } while(0)
+
+#else /* LWIP_EVENT_API */
+
+#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) \
+ do { \
+ if((lpcb)->accept != NULL) \
+ (ret) = (lpcb)->accept((arg),(pcb),(err)); \
+ else (ret) = ERR_ARG; \
+ } while (0)
+
+#define TCP_EVENT_SENT(pcb,space,ret) \
+ do { \
+ if((pcb)->sent != NULL) \
+ (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \
+ else (ret) = ERR_OK; \
+ } while (0)
+
+#define TCP_EVENT_RECV(pcb,p,err,ret) \
+ do { \
+ if((pcb)->recv != NULL) { \
+ (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\
+ } else { \
+ (ret) = tcp_recv_null(NULL, (pcb), (p), (err)); \
+ } \
+ } while (0)
+
+#define TCP_EVENT_CLOSED(pcb,ret) \
+ do { \
+ if(((pcb)->recv != NULL)) { \
+ (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\
+ } else { \
+ (ret) = ERR_OK; \
+ } \
+ } while (0)
+
+#define TCP_EVENT_CONNECTED(pcb,err,ret) \
+ do { \
+ if((pcb)->connected != NULL) \
+ (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \
+ else (ret) = ERR_OK; \
+ } while (0)
+
+#define TCP_EVENT_POLL(pcb,ret) \
+ do { \
+ if((pcb)->poll != NULL) \
+ (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \
+ else (ret) = ERR_OK; \
+ } while (0)
+
+#define TCP_EVENT_ERR(last_state,errf,arg,err) \
+ do { \
+ LWIP_UNUSED_ARG(last_state); \
+ if((errf) != NULL) \
+ (errf)((arg),(err)); \
+ } while (0)
+
+#endif /* LWIP_EVENT_API */
+
+/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */
+#if TCP_OVERSIZE && defined(LWIP_DEBUG)
+#define TCP_OVERSIZE_DBGCHECK 1
+#else
+#define TCP_OVERSIZE_DBGCHECK 0
+#endif
+
+/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */
+#define TCP_CHECKSUM_ON_COPY (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP)
+
+/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */
+struct tcp_seg {
+ struct tcp_seg *next; /* used when putting segments on a queue */
+ struct pbuf *p; /* buffer containing data + TCP header */
+ u16_t len; /* the TCP length of this segment */
+#if TCP_OVERSIZE_DBGCHECK
+ u16_t oversize_left; /* Extra bytes available at the end of the last
+ pbuf in unsent (used for asserting vs.
+ tcp_pcb.unsent_oversize only) */
+#endif /* TCP_OVERSIZE_DBGCHECK */
+#if TCP_CHECKSUM_ON_COPY
+ u16_t chksum;
+ u8_t chksum_swapped;
+#endif /* TCP_CHECKSUM_ON_COPY */
+ u8_t flags;
+#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option (only used in SYN segments) */
+#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */
+#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is
+ checksummed into 'chksum' */
+#define TF_SEG_OPTS_WND_SCALE (u8_t)0x08U /* Include WND SCALE option (only used in SYN segments) */
+#define TF_SEG_OPTS_SACK_PERM (u8_t)0x10U /* Include SACK Permitted option (only used in SYN segments) */
+ struct tcp_hdr *tcphdr; /* the TCP header */
+};
+
+#define LWIP_TCP_OPT_EOL 0
+#define LWIP_TCP_OPT_NOP 1
+#define LWIP_TCP_OPT_MSS 2
+#define LWIP_TCP_OPT_WS 3
+#define LWIP_TCP_OPT_SACK_PERM 4
+#define LWIP_TCP_OPT_TS 8
+
+#define LWIP_TCP_OPT_LEN_MSS 4
+#if LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_OPT_LEN_TS 10
+#define LWIP_TCP_OPT_LEN_TS_OUT 12 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_TS_OUT 0
+#endif
+#if LWIP_WND_SCALE
+#define LWIP_TCP_OPT_LEN_WS 3
+#define LWIP_TCP_OPT_LEN_WS_OUT 4 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_WS_OUT 0
+#endif
+
+#if LWIP_TCP_SACK_OUT
+#define LWIP_TCP_OPT_LEN_SACK_PERM 2
+#define LWIP_TCP_OPT_LEN_SACK_PERM_OUT 4 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_SACK_PERM_OUT 0
+#endif
+
+#define LWIP_TCP_OPT_LENGTH(flags) \
+ ((flags) & TF_SEG_OPTS_MSS ? LWIP_TCP_OPT_LEN_MSS : 0) + \
+ ((flags) & TF_SEG_OPTS_TS ? LWIP_TCP_OPT_LEN_TS_OUT : 0) + \
+ ((flags) & TF_SEG_OPTS_WND_SCALE ? LWIP_TCP_OPT_LEN_WS_OUT : 0) + \
+ ((flags) & TF_SEG_OPTS_SACK_PERM ? LWIP_TCP_OPT_LEN_SACK_PERM_OUT : 0)
+
+/** This returns a TCP header option for MSS in an u32_t */
+#define TCP_BUILD_MSS_OPTION(mss) lwip_htonl(0x02040000 | ((mss) & 0xFFFF))
+
+#if LWIP_WND_SCALE
+#define TCPWNDSIZE_F U32_F
+#define TCPWND_MAX 0xFFFFFFFFU
+#define TCPWND_CHECK16(x) LWIP_ASSERT("window size > 0xFFFF", (x) <= 0xFFFF)
+#define TCPWND_MIN16(x) ((u16_t)LWIP_MIN((x), 0xFFFF))
+#else /* LWIP_WND_SCALE */
+#define TCPWNDSIZE_F U16_F
+#define TCPWND_MAX 0xFFFFU
+#define TCPWND_CHECK16(x)
+#define TCPWND_MIN16(x) x
+#endif /* LWIP_WND_SCALE */
+
+/* Global variables: */
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+extern u8_t tcp_active_pcbs_changed;
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+ struct tcp_pcb_listen *listen_pcbs;
+ struct tcp_pcb *pcbs;
+};
+extern struct tcp_pcb *tcp_bound_pcbs;
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a
+ state in which they accept or send
+ data. */
+extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */
+
+#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT 3
+#define NUM_TCP_PCB_LISTS 4
+extern struct tcp_pcb ** const tcp_pcb_lists[NUM_TCP_PCB_LISTS];
+
+/* Axioms about the above lists:
+ 1) Every TCP PCB that is not CLOSED is in one of the lists.
+ 2) A PCB is only in one of the lists.
+ 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+ 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+ with a PCB list or removes a PCB from a list, respectively. */
+#ifndef TCP_DEBUG_PCB_LISTS
+#define TCP_DEBUG_PCB_LISTS 0
+#endif
+#if TCP_DEBUG_PCB_LISTS
+#define TCP_REG(pcbs, npcb) do {\
+ struct tcp_pcb *tcp_tmp_pcb; \
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %"U16_F"\n", (void *)(npcb), (npcb)->local_port)); \
+ for (tcp_tmp_pcb = *(pcbs); \
+ tcp_tmp_pcb != NULL; \
+ tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+ LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \
+ } \
+ LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \
+ (npcb)->next = *(pcbs); \
+ LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \
+ *(pcbs) = (npcb); \
+ LWIP_ASSERT("TCP_REG: tcp_pcbs sane", tcp_pcbs_sane()); \
+ tcp_timer_needed(); \
+ } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+ struct tcp_pcb *tcp_tmp_pcb; \
+ LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (void *)(npcb), (void *)(*(pcbs)))); \
+ if(*(pcbs) == (npcb)) { \
+ *(pcbs) = (*pcbs)->next; \
+ } else for (tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+ if(tcp_tmp_pcb->next == (npcb)) { \
+ tcp_tmp_pcb->next = (npcb)->next; \
+ break; \
+ } \
+ } \
+ (npcb)->next = NULL; \
+ LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+ LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (void *)(npcb), (void *)(*(pcbs)))); \
+ } while(0)
+
+#else /* LWIP_DEBUG */
+
+#define TCP_REG(pcbs, npcb) \
+ do { \
+ (npcb)->next = *pcbs; \
+ *(pcbs) = (npcb); \
+ tcp_timer_needed(); \
+ } while (0)
+
+#define TCP_RMV(pcbs, npcb) \
+ do { \
+ if(*(pcbs) == (npcb)) { \
+ (*(pcbs)) = (*pcbs)->next; \
+ } \
+ else { \
+ struct tcp_pcb *tcp_tmp_pcb; \
+ for (tcp_tmp_pcb = *pcbs; \
+ tcp_tmp_pcb != NULL; \
+ tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+ if(tcp_tmp_pcb->next == (npcb)) { \
+ tcp_tmp_pcb->next = (npcb)->next; \
+ break; \
+ } \
+ } \
+ } \
+ (npcb)->next = NULL; \
+ } while(0)
+
+#endif /* LWIP_DEBUG */
+
+#define TCP_REG_ACTIVE(npcb) \
+ do { \
+ TCP_REG(&tcp_active_pcbs, npcb); \
+ tcp_active_pcbs_changed = 1; \
+ } while (0)
+
+#define TCP_RMV_ACTIVE(npcb) \
+ do { \
+ TCP_RMV(&tcp_active_pcbs, npcb); \
+ tcp_active_pcbs_changed = 1; \
+ } while (0)
+
+#define TCP_PCB_REMOVE_ACTIVE(pcb) \
+ do { \
+ tcp_pcb_remove(&tcp_active_pcbs, pcb); \
+ tcp_active_pcbs_changed = 1; \
+ } while (0)
+
+
+/* Internal functions: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+void tcp_segs_free(struct tcp_seg *seg);
+void tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb) \
+ do { \
+ if((pcb)->flags & TF_ACK_DELAY) { \
+ tcp_clear_flags(pcb, TF_ACK_DELAY); \
+ tcp_ack_now(pcb); \
+ } \
+ else { \
+ tcp_set_flags(pcb, TF_ACK_DELAY); \
+ } \
+ } while (0)
+
+#define tcp_ack_now(pcb) \
+ tcp_set_flags(pcb, TF_ACK_NOW)
+
+err_t tcp_send_fin(struct tcp_pcb *pcb);
+err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(const struct tcp_pcb* pcb, u32_t seqno, u32_t ackno,
+ const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
+ u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(struct tcp_pcb *pcb);
+
+err_t tcp_keepalive(struct tcp_pcb *pcb);
+err_t tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split);
+err_t tcp_zero_window_probe(struct tcp_pcb *pcb);
+void tcp_trigger_input_pcb_close(void);
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+u16_t tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif,
+ const ip_addr_t *dest);
+#define tcp_eff_send_mss(sendmss, src, dest) \
+ tcp_eff_send_mss_netif(sendmss, ip_route(src, dest), dest)
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+#if LWIP_CALLBACK_API
+err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+# define tcp_debug_print(tcphdr)
+# define tcp_debug_print_flags(flags)
+# define tcp_debug_print_state(s)
+# define tcp_debug_print_pcbs()
+# define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+/** External function (implemented in timers.c), called when TCP detects
+ * that a timer is needed (i.e. active- or time-wait-pcb found). */
+void tcp_timer_needed(void);
+
+void tcp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
+
+#if TCP_QUEUE_OOSEQ
+void tcp_free_ooseq(struct tcp_pcb *pcb);
+#endif
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+err_t tcp_ext_arg_invoke_callbacks_passive_open(struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCP_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/tcpip_priv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/tcpip_priv.h
new file mode 100644
index 0000000..74be634
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/priv/tcpip_priv.h
@@ -0,0 +1,170 @@
+/**
+ * @file
+ * TCPIP API internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_TCPIP_PRIV_H
+#define LWIP_HDR_TCPIP_PRIV_H
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcpip.h"
+#include "lwip/sys.h"
+#include "lwip/timeouts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pbuf;
+struct netif;
+
+#if LWIP_MPU_COMPATIBLE
+#define API_VAR_REF(name) (*(name))
+#define API_VAR_DECLARE(type, name) type * name
+#define API_VAR_ALLOC_EXT(type, pool, name, errorblock) do { \
+ name = (type *)memp_malloc(pool); \
+ if (name == NULL) { \
+ errorblock; \
+ } \
+ } while(0)
+#define API_VAR_ALLOC(type, pool, name, errorval) API_VAR_ALLOC_EXT(type, pool, name, return errorval)
+#define API_VAR_ALLOC_POOL(type, pool, name, errorval) do { \
+ name = (type *)LWIP_MEMPOOL_ALLOC(pool); \
+ if (name == NULL) { \
+ return errorval; \
+ } \
+ } while(0)
+#define API_VAR_FREE(pool, name) memp_free(pool, name)
+#define API_VAR_FREE_POOL(pool, name) LWIP_MEMPOOL_FREE(pool, name)
+#define API_EXPR_REF(expr) (&(expr))
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define API_EXPR_REF_SEM(expr) (expr)
+#else
+#define API_EXPR_REF_SEM(expr) API_EXPR_REF(expr)
+#endif
+#define API_EXPR_DEREF(expr) expr
+#define API_MSG_M_DEF(m) m
+#define API_MSG_M_DEF_C(t, m) t m
+#else /* LWIP_MPU_COMPATIBLE */
+#define API_VAR_REF(name) name
+#define API_VAR_DECLARE(type, name) type name
+#define API_VAR_ALLOC_EXT(type, pool, name, errorblock)
+#define API_VAR_ALLOC(type, pool, name, errorval)
+#define API_VAR_ALLOC_POOL(type, pool, name, errorval)
+#define API_VAR_FREE(pool, name)
+#define API_VAR_FREE_POOL(pool, name)
+#define API_EXPR_REF(expr) expr
+#define API_EXPR_REF_SEM(expr) API_EXPR_REF(expr)
+#define API_EXPR_DEREF(expr) (*(expr))
+#define API_MSG_M_DEF(m) *m
+#define API_MSG_M_DEF_C(t, m) const t * m
+#endif /* LWIP_MPU_COMPATIBLE */
+
+err_t tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t* sem);
+
+struct tcpip_api_call_data
+{
+#if !LWIP_TCPIP_CORE_LOCKING
+ err_t err;
+#if !LWIP_NETCONN_SEM_PER_THREAD
+ sys_sem_t sem;
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+#else /* !LWIP_TCPIP_CORE_LOCKING */
+ u8_t dummy; /* avoid empty struct :-( */
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+};
+typedef err_t (*tcpip_api_call_fn)(struct tcpip_api_call_data* call);
+err_t tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call);
+
+enum tcpip_msg_type {
+#if !LWIP_TCPIP_CORE_LOCKING
+ TCPIP_MSG_API,
+ TCPIP_MSG_API_CALL,
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+ TCPIP_MSG_INPKT,
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+ TCPIP_MSG_TIMEOUT,
+ TCPIP_MSG_UNTIMEOUT,
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+ TCPIP_MSG_CALLBACK,
+ TCPIP_MSG_CALLBACK_STATIC
+};
+
+struct tcpip_msg {
+ enum tcpip_msg_type type;
+ union {
+#if !LWIP_TCPIP_CORE_LOCKING
+ struct {
+ tcpip_callback_fn function;
+ void* msg;
+ } api_msg;
+ struct {
+ tcpip_api_call_fn function;
+ struct tcpip_api_call_data *arg;
+ sys_sem_t *sem;
+ } api_call;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+ struct {
+ struct pbuf *p;
+ struct netif *netif;
+ netif_input_fn input_fn;
+ } inp;
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+ struct {
+ tcpip_callback_fn function;
+ void *ctx;
+ } cb;
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+ struct {
+ u32_t msecs;
+ sys_timeout_handler h;
+ void *arg;
+ } tmo;
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+ } msg;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* LWIP_HDR_TCPIP_PRIV_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/autoip.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/autoip.h
new file mode 100644
index 0000000..fd3af8a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/autoip.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ * AutoIP protocol definitions
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ */
+
+#ifndef LWIP_HDR_PROT_AUTOIP_H
+#define LWIP_HDR_PROT_AUTOIP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 169.254.0.0 */
+#define AUTOIP_NET 0xA9FE0000
+/* 169.254.1.0 */
+#define AUTOIP_RANGE_START (AUTOIP_NET | 0x0100)
+/* 169.254.254.255 */
+#define AUTOIP_RANGE_END (AUTOIP_NET | 0xFEFF)
+
+/* RFC 3927 Constants */
+#define PROBE_WAIT 1 /* second (initial random delay) */
+#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */
+#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */
+#define PROBE_NUM 3 /* (number of probe packets) */
+#define ANNOUNCE_NUM 2 /* (number of announcement packets) */
+#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */
+#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */
+#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */
+#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */
+#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */
+
+/* AutoIP client states */
+typedef enum {
+ AUTOIP_STATE_OFF = 0,
+ AUTOIP_STATE_PROBING = 1,
+ AUTOIP_STATE_ANNOUNCING = 2,
+ AUTOIP_STATE_BOUND = 3
+} autoip_state_enum_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_AUTOIP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dhcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dhcp.h
new file mode 100644
index 0000000..ab18dca
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dhcp.h
@@ -0,0 +1,178 @@
+/**
+ * @file
+ * DHCP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Leon Woestenberg
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg
+ *
+ */
+#ifndef LWIP_HDR_PROT_DHCP_H
+#define LWIP_HDR_PROT_DHCP_H
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/prot/ip4.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /* DHCP message item offsets and length */
+#define DHCP_CHADDR_LEN 16U
+#define DHCP_SNAME_OFS 44U
+#define DHCP_SNAME_LEN 64U
+#define DHCP_FILE_OFS 108U
+#define DHCP_FILE_LEN 128U
+#define DHCP_MSG_LEN 236U
+#define DHCP_OPTIONS_OFS (DHCP_MSG_LEN + 4U) /* 4 byte: cookie */
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+ PACK_STRUCT_FLD_8(u8_t op);
+ PACK_STRUCT_FLD_8(u8_t htype);
+ PACK_STRUCT_FLD_8(u8_t hlen);
+ PACK_STRUCT_FLD_8(u8_t hops);
+ PACK_STRUCT_FIELD(u32_t xid);
+ PACK_STRUCT_FIELD(u16_t secs);
+ PACK_STRUCT_FIELD(u16_t flags);
+ PACK_STRUCT_FLD_S(ip4_addr_p_t ciaddr);
+ PACK_STRUCT_FLD_S(ip4_addr_p_t yiaddr);
+ PACK_STRUCT_FLD_S(ip4_addr_p_t siaddr);
+ PACK_STRUCT_FLD_S(ip4_addr_p_t giaddr);
+ PACK_STRUCT_FLD_8(u8_t chaddr[DHCP_CHADDR_LEN]);
+ PACK_STRUCT_FLD_8(u8_t sname[DHCP_SNAME_LEN]);
+ PACK_STRUCT_FLD_8(u8_t file[DHCP_FILE_LEN]);
+ PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+# undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+ PACK_STRUCT_FLD_8(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+
+/* DHCP client states */
+typedef enum {
+ DHCP_STATE_OFF = 0,
+ DHCP_STATE_REQUESTING = 1,
+ DHCP_STATE_INIT = 2,
+ DHCP_STATE_REBOOTING = 3,
+ DHCP_STATE_REBINDING = 4,
+ DHCP_STATE_RENEWING = 5,
+ DHCP_STATE_SELECTING = 6,
+ DHCP_STATE_INFORMING = 7,
+ DHCP_STATE_CHECKING = 8,
+ DHCP_STATE_PERMANENT = 9, /* not yet implemented */
+ DHCP_STATE_BOUND = 10,
+ DHCP_STATE_RELEASING = 11, /* not yet implemented */
+ DHCP_STATE_BACKING_OFF = 12
+} dhcp_state_enum_t;
+
+/* DHCP op codes */
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+/* DHCP message types */
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_MAGIC_COOKIE 0x63825363UL
+
+/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */
+
+/* BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_NTP 42
+#define DHCP_OPTION_END 255
+
+/* DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_US 60
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/* possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME 2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_DHCP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dhcp6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dhcp6.h
new file mode 100644
index 0000000..0754c91
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dhcp6.h
@@ -0,0 +1,138 @@
+/**
+ * @file
+ * DHCPv6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_PROT_DHCP6_H
+#define LWIP_HDR_PROT_DHCP6_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DHCP6_CLIENT_PORT 546
+#define DHCP6_SERVER_PORT 547
+
+
+ /* DHCPv6 message item offsets and length */
+#define DHCP6_TRANSACTION_ID_LEN 3
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCPv6 message */
+struct dhcp6_msg
+{
+ PACK_STRUCT_FLD_8(u8_t msgtype);
+ PACK_STRUCT_FLD_8(u8_t transaction_id[DHCP6_TRANSACTION_ID_LEN]);
+ /* options follow */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+
+/* DHCP6 client states */
+typedef enum {
+ DHCP6_STATE_OFF = 0,
+ DHCP6_STATE_STATELESS_IDLE = 1,
+ DHCP6_STATE_REQUESTING_CONFIG = 2
+} dhcp6_state_enum_t;
+
+/* DHCPv6 message types */
+#define DHCP6_SOLICIT 1
+#define DHCP6_ADVERTISE 2
+#define DHCP6_REQUEST 3
+#define DHCP6_CONFIRM 4
+#define DHCP6_RENEW 5
+#define DHCP6_REBIND 6
+#define DHCP6_REPLY 7
+#define DHCP6_RELEASE 8
+#define DHCP6_DECLINE 9
+#define DHCP6_RECONFIGURE 10
+#define DHCP6_INFOREQUEST 11
+#define DHCP6_RELAYFORW 12
+#define DHCP6_RELAYREPL 13
+/* More message types see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */
+
+/** DHCPv6 status codes */
+#define DHCP6_STATUS_SUCCESS 0 /* Success. */
+#define DHCP6_STATUS_UNSPECFAIL 1 /* Failure, reason unspecified; this status code is sent by either a client or a server to indicate a failure not explicitly specified in this document. */
+#define DHCP6_STATUS_NOADDRSAVAIL 2 /* Server has no addresses available to assign to the IA(s). */
+#define DHCP6_STATUS_NOBINDING 3 /* Client record (binding) unavailable. */
+#define DHCP6_STATUS_NOTONLINK 4 /* The prefix for the address is not appropriate for the link to which the client is attached. */
+#define DHCP6_STATUS_USEMULTICAST 5 /* Sent by a server to a client to force the client to send messages to the server using the All_DHCP_Relay_Agents_and_Servers address. */
+/* More status codes see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */
+
+/** DHCPv6 DUID types */
+#define DHCP6_DUID_LLT 1 /* LLT: Link-layer Address Plus Time */
+#define DHCP6_DUID_EN 2 /* EN: Enterprise number */
+#define DHCP6_DUID_LL 3 /* LL: Link-layer Address */
+#define DHCP6_DUID_UUID 4 /* UUID (RFC 6355) */
+
+/* DHCPv6 options */
+#define DHCP6_OPTION_CLIENTID 1
+#define DHCP6_OPTION_SERVERID 2
+#define DHCP6_OPTION_IA_NA 3
+#define DHCP6_OPTION_IA_TA 4
+#define DHCP6_OPTION_IAADDR 5
+#define DHCP6_OPTION_ORO 6
+#define DHCP6_OPTION_PREFERENCE 7
+#define DHCP6_OPTION_ELAPSED_TIME 8
+#define DHCP6_OPTION_RELAY_MSG 9
+#define DHCP6_OPTION_AUTH 11
+#define DHCP6_OPTION_UNICAST 12
+#define DHCP6_OPTION_STATUS_CODE 13
+#define DHCP6_OPTION_RAPID_COMMIT 14
+#define DHCP6_OPTION_USER_CLASS 15
+#define DHCP6_OPTION_VENDOR_CLASS 16
+#define DHCP6_OPTION_VENDOR_OPTS 17
+#define DHCP6_OPTION_INTERFACE_ID 18
+#define DHCP6_OPTION_RECONF_MSG 19
+#define DHCP6_OPTION_RECONF_ACCEPT 20
+/* More options see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */
+#define DHCP6_OPTION_DNS_SERVERS 23 /* RFC 3646 */
+#define DHCP6_OPTION_DOMAIN_LIST 24 /* RFC 3646 */
+#define DHCP6_OPTION_SNTP_SERVERS 31 /* RFC 4075 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_DHCP6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dns.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dns.h
new file mode 100644
index 0000000..94782d6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/dns.h
@@ -0,0 +1,140 @@
+/**
+ * @file
+ * DNS - host name to IP address resolver.
+ */
+
+/*
+ * Port to lwIP from uIP
+ * by Jim Pettinato April 2007
+ *
+ * security fixes and more by Simon Goldschmidt
+ *
+ * uIP version Copyright (c) 2002-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LWIP_HDR_PROT_DNS_H
+#define LWIP_HDR_PROT_DNS_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DNS server port address */
+#ifndef DNS_SERVER_PORT
+#define DNS_SERVER_PORT 53
+#endif
+
+/* DNS field TYPE used for "Resource Records" */
+#define DNS_RRTYPE_A 1 /* a host address */
+#define DNS_RRTYPE_NS 2 /* an authoritative name server */
+#define DNS_RRTYPE_MD 3 /* a mail destination (Obsolete - use MX) */
+#define DNS_RRTYPE_MF 4 /* a mail forwarder (Obsolete - use MX) */
+#define DNS_RRTYPE_CNAME 5 /* the canonical name for an alias */
+#define DNS_RRTYPE_SOA 6 /* marks the start of a zone of authority */
+#define DNS_RRTYPE_MB 7 /* a mailbox domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_MG 8 /* a mail group member (EXPERIMENTAL) */
+#define DNS_RRTYPE_MR 9 /* a mail rename domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_NULL 10 /* a null RR (EXPERIMENTAL) */
+#define DNS_RRTYPE_WKS 11 /* a well known service description */
+#define DNS_RRTYPE_PTR 12 /* a domain name pointer */
+#define DNS_RRTYPE_HINFO 13 /* host information */
+#define DNS_RRTYPE_MINFO 14 /* mailbox or mail list information */
+#define DNS_RRTYPE_MX 15 /* mail exchange */
+#define DNS_RRTYPE_TXT 16 /* text strings */
+#define DNS_RRTYPE_AAAA 28 /* IPv6 address */
+#define DNS_RRTYPE_SRV 33 /* service location */
+#define DNS_RRTYPE_ANY 255 /* any type */
+
+/* DNS field CLASS used for "Resource Records" */
+#define DNS_RRCLASS_IN 1 /* the Internet */
+#define DNS_RRCLASS_CS 2 /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */
+#define DNS_RRCLASS_CH 3 /* the CHAOS class */
+#define DNS_RRCLASS_HS 4 /* Hesiod [Dyer 87] */
+#define DNS_RRCLASS_ANY 255 /* any class */
+#define DNS_RRCLASS_FLUSH 0x800 /* Flush bit */
+
+/* DNS protocol flags */
+#define DNS_FLAG1_RESPONSE 0x80
+#define DNS_FLAG1_OPCODE_STATUS 0x10
+#define DNS_FLAG1_OPCODE_INVERSE 0x08
+#define DNS_FLAG1_OPCODE_STANDARD 0x00
+#define DNS_FLAG1_AUTHORATIVE 0x04
+#define DNS_FLAG1_TRUNC 0x02
+#define DNS_FLAG1_RD 0x01
+#define DNS_FLAG2_RA 0x80
+#define DNS_FLAG2_ERR_MASK 0x0f
+#define DNS_FLAG2_ERR_NONE 0x00
+#define DNS_FLAG2_ERR_NAME 0x03
+
+#define DNS_HDR_GET_OPCODE(hdr) ((((hdr)->flags1) >> 3) & 0xF)
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** DNS message header */
+struct dns_hdr {
+ PACK_STRUCT_FIELD(u16_t id);
+ PACK_STRUCT_FLD_8(u8_t flags1);
+ PACK_STRUCT_FLD_8(u8_t flags2);
+ PACK_STRUCT_FIELD(u16_t numquestions);
+ PACK_STRUCT_FIELD(u16_t numanswers);
+ PACK_STRUCT_FIELD(u16_t numauthrr);
+ PACK_STRUCT_FIELD(u16_t numextrarr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define SIZEOF_DNS_HDR 12
+
+
+/* Multicast DNS definitions */
+
+/** UDP port for multicast DNS queries */
+#ifndef DNS_MQUERY_PORT
+#define DNS_MQUERY_PORT 5353
+#endif
+
+/* IPv4 group for multicast DNS queries: 224.0.0.251 */
+#ifndef DNS_MQUERY_IPV4_GROUP_INIT
+#define DNS_MQUERY_IPV4_GROUP_INIT IPADDR4_INIT_BYTES(224,0,0,251)
+#endif
+
+/* IPv6 group for multicast DNS queries: FF02::FB */
+#ifndef DNS_MQUERY_IPV6_GROUP_INIT
+#define DNS_MQUERY_IPV6_GROUP_INIT IPADDR6_INIT_HOST(0xFF020000,0,0,0xFB)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_DNS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/etharp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/etharp.h
new file mode 100644
index 0000000..4d60f5d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/etharp.h
@@ -0,0 +1,127 @@
+/**
+ * @file
+ * ARP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_ETHARP_H
+#define LWIP_HDR_PROT_ETHARP_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ETHARP_HWADDR_LEN
+#define ETHARP_HWADDR_LEN ETH_HWADDR_LEN
+#endif
+
+/**
+ * struct ip4_addr_wordaligned is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip4_addr_wordaligned {
+ PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** MEMCPY-like copying of IP addresses where addresses are known to be
+ * 16-bit-aligned if the port is correctly configured (so a port could define
+ * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */
+#ifndef IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T
+#define IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t))
+#endif
+
+ /** MEMCPY-like copying of IP addresses where addresses are known to be
+ * 16-bit-aligned if the port is correctly configured (so a port could define
+ * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */
+#ifndef IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T
+#define IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t))
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message, see RFC 826 ("Packet format") */
+struct etharp_hdr {
+ PACK_STRUCT_FIELD(u16_t hwtype);
+ PACK_STRUCT_FIELD(u16_t proto);
+ PACK_STRUCT_FLD_8(u8_t hwlen);
+ PACK_STRUCT_FLD_8(u8_t protolen);
+ PACK_STRUCT_FIELD(u16_t opcode);
+ PACK_STRUCT_FLD_S(struct eth_addr shwaddr);
+ PACK_STRUCT_FLD_S(struct ip4_addr_wordaligned sipaddr);
+ PACK_STRUCT_FLD_S(struct eth_addr dhwaddr);
+ PACK_STRUCT_FLD_S(struct ip4_addr_wordaligned dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ethip_hdr {
+ PACK_STRUCT_FIELD(struct eth_hdr eth);
+ PACK_STRUCT_FIELD(struct ip_hdr ip);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define SIZEOF_ETHARP_HDR 28
+
+/* ARP message types (opcodes) */
+enum etharp_opcode {
+ ARP_REQUEST = 1,
+ ARP_REPLY = 2
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ETHARP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ethernet.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ethernet.h
new file mode 100644
index 0000000..d4c8960
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ethernet.h
@@ -0,0 +1,135 @@
+/**
+ * @file
+ * Ethernet protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_ETHERNET_H
+#define LWIP_HDR_PROT_ETHERNET_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ieee.h"
+#include "xlwipconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if XLWIP_CONFIG_AXI_ETHERNET_ENABLE_1588
+#define IEEE_1588_PAD_SIZE 8
+#else
+#define IEEE_1588_PAD_SIZE 0
+#endif
+
+#ifndef ETH_HWADDR_LEN
+#ifdef ETHARP_HWADDR_LEN
+#define ETH_HWADDR_LEN ETHARP_HWADDR_LEN /* compatibility mode */
+#else
+#define ETH_HWADDR_LEN 6
+#endif
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** An Ethernet MAC address */
+struct eth_addr {
+ PACK_STRUCT_FLD_8(u8_t addr[ETH_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Initialize a struct eth_addr with its 6 bytes (takes care of correct braces) */
+#define ETH_ADDR(b0, b1, b2, b3, b4, b5) {{b0, b1, b2, b3, b4, b5}}
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** Ethernet header */
+struct eth_hdr {
+#if ETH_PAD_SIZE
+ PACK_STRUCT_FLD_8(u8_t padding[ETH_PAD_SIZE]);
+#endif
+#if XLWIP_CONFIG_AXI_ETHERNET_ENABLE_1588
+ PACK_STRUCT_FLD_8(u8_t padding[IEEE_1588_PAD_SIZE]);
+#endif
+ PACK_STRUCT_FLD_S(struct eth_addr dest);
+ PACK_STRUCT_FLD_S(struct eth_addr src);
+ PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE + IEEE_1588_PAD_SIZE)
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** VLAN header inserted between ethernet header and payload
+ * if 'type' in ethernet header is ETHTYPE_VLAN.
+ * See IEEE802.Q */
+struct eth_vlan_hdr {
+ PACK_STRUCT_FIELD(u16_t prio_vid);
+ PACK_STRUCT_FIELD(u16_t tpid);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_VLAN_HDR 4
+#define VLAN_ID(vlan_hdr) (lwip_htons((vlan_hdr)->prio_vid) & 0xFFF)
+
+/** The 24-bit IANA IPv4-multicast OUI is 01-00-5e: */
+#define LL_IP4_MULTICAST_ADDR_0 0x01
+#define LL_IP4_MULTICAST_ADDR_1 0x00
+#define LL_IP4_MULTICAST_ADDR_2 0x5e
+
+/** IPv6 multicast uses this prefix */
+#define LL_IP6_MULTICAST_ADDR_0 0x33
+#define LL_IP6_MULTICAST_ADDR_1 0x33
+
+#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETH_HWADDR_LEN) == 0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ETHERNET_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/iana.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/iana.h
new file mode 100644
index 0000000..32890cc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/iana.h
@@ -0,0 +1,97 @@
+/**
+ * @file
+ * IANA assigned numbers (RFC 1700 and successors)
+ *
+ * @defgroup iana IANA assigned numbers
+ * @ingroup infrastructure
+ */
+
+/*
+ * Copyright (c) 2017 Dirk Ziegelmeier.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier
+ *
+ */
+
+#ifndef LWIP_HDR_PROT_IANA_H
+#define LWIP_HDR_PROT_IANA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup iana
+ * Hardware types
+ */
+enum lwip_iana_hwtype {
+ /** Ethernet */
+ LWIP_IANA_HWTYPE_ETHERNET = 1
+};
+
+/**
+ * @ingroup iana
+ * Port numbers
+ * https://www.iana.org/assignments/service-names-port-numbers/service-names-port-numbers.txt
+ */
+enum lwip_iana_port_number {
+ /** SMTP */
+ LWIP_IANA_PORT_SMTP = 25,
+ /** DHCP server */
+ LWIP_IANA_PORT_DHCP_SERVER = 67,
+ /** DHCP client */
+ LWIP_IANA_PORT_DHCP_CLIENT = 68,
+ /** TFTP */
+ LWIP_IANA_PORT_TFTP = 69,
+ /** HTTP */
+ LWIP_IANA_PORT_HTTP = 80,
+ /** SNTP */
+ LWIP_IANA_PORT_SNTP = 123,
+ /** NETBIOS */
+ LWIP_IANA_PORT_NETBIOS = 137,
+ /** SNMP */
+ LWIP_IANA_PORT_SNMP = 161,
+ /** SNMP traps */
+ LWIP_IANA_PORT_SNMP_TRAP = 162,
+ /** HTTPS */
+ LWIP_IANA_PORT_HTTPS = 443,
+ /** SMTPS */
+ LWIP_IANA_PORT_SMTPS = 465,
+ /** MQTT */
+ LWIP_IANA_PORT_MQTT = 1883,
+ /** MDNS */
+ LWIP_IANA_PORT_MDNS = 5353,
+ /** Secure MQTT */
+ LWIP_IANA_PORT_SECURE_MQTT = 8883
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IANA_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/icmp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/icmp.h
new file mode 100644
index 0000000..7d19385
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/icmp.h
@@ -0,0 +1,91 @@
+/**
+ * @file
+ * ICMP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_ICMP_H
+#define LWIP_HDR_PROT_ICMP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP_ER 0 /* echo reply */
+#define ICMP_DUR 3 /* destination unreachable */
+#define ICMP_SQ 4 /* source quench */
+#define ICMP_RD 5 /* redirect */
+#define ICMP_ECHO 8 /* echo */
+#define ICMP_TE 11 /* time exceeded */
+#define ICMP_PP 12 /* parameter problem */
+#define ICMP_TS 13 /* timestamp */
+#define ICMP_TSR 14 /* timestamp reply */
+#define ICMP_IRQ 15 /* information request */
+#define ICMP_IR 16 /* information reply */
+#define ICMP_AM 17 /* address mask request */
+#define ICMP_AMR 18 /* address mask reply */
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+/** This is the standard ICMP header only that the u32_t data
+ * is split to two u16_t like ICMP echo needs it.
+ * This header is also used for other ICMP types that do not
+ * use the data part.
+ */
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u16_t id);
+ PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/* Compatibility defines, old versions used to combine type and code to an u16_t */
+#define ICMPH_TYPE(hdr) ((hdr)->type)
+#define ICMPH_CODE(hdr) ((hdr)->code)
+#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t))
+#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ICMP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/icmp6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/icmp6.h
new file mode 100644
index 0000000..3461120
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/icmp6.h
@@ -0,0 +1,170 @@
+/**
+ * @file
+ * ICMP6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_ICMP6_H
+#define LWIP_HDR_PROT_ICMP6_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICMP type */
+enum icmp6_type {
+ /** Destination unreachable */
+ ICMP6_TYPE_DUR = 1,
+ /** Packet too big */
+ ICMP6_TYPE_PTB = 2,
+ /** Time exceeded */
+ ICMP6_TYPE_TE = 3,
+ /** Parameter problem */
+ ICMP6_TYPE_PP = 4,
+ /** Private experimentation */
+ ICMP6_TYPE_PE1 = 100,
+ /** Private experimentation */
+ ICMP6_TYPE_PE2 = 101,
+ /** Reserved for expansion of error messages */
+ ICMP6_TYPE_RSV_ERR = 127,
+
+ /** Echo request */
+ ICMP6_TYPE_EREQ = 128,
+ /** Echo reply */
+ ICMP6_TYPE_EREP = 129,
+ /** Multicast listener query */
+ ICMP6_TYPE_MLQ = 130,
+ /** Multicast listener report */
+ ICMP6_TYPE_MLR = 131,
+ /** Multicast listener done */
+ ICMP6_TYPE_MLD = 132,
+ /** Router solicitation */
+ ICMP6_TYPE_RS = 133,
+ /** Router advertisement */
+ ICMP6_TYPE_RA = 134,
+ /** Neighbor solicitation */
+ ICMP6_TYPE_NS = 135,
+ /** Neighbor advertisement */
+ ICMP6_TYPE_NA = 136,
+ /** Redirect */
+ ICMP6_TYPE_RD = 137,
+ /** Multicast router advertisement */
+ ICMP6_TYPE_MRA = 151,
+ /** Multicast router solicitation */
+ ICMP6_TYPE_MRS = 152,
+ /** Multicast router termination */
+ ICMP6_TYPE_MRT = 153,
+ /** Private experimentation */
+ ICMP6_TYPE_PE3 = 200,
+ /** Private experimentation */
+ ICMP6_TYPE_PE4 = 201,
+ /** Reserved for expansion of informational messages */
+ ICMP6_TYPE_RSV_INF = 255
+};
+
+/** ICMP destination unreachable codes */
+enum icmp6_dur_code {
+ /** No route to destination */
+ ICMP6_DUR_NO_ROUTE = 0,
+ /** Communication with destination administratively prohibited */
+ ICMP6_DUR_PROHIBITED = 1,
+ /** Beyond scope of source address */
+ ICMP6_DUR_SCOPE = 2,
+ /** Address unreachable */
+ ICMP6_DUR_ADDRESS = 3,
+ /** Port unreachable */
+ ICMP6_DUR_PORT = 4,
+ /** Source address failed ingress/egress policy */
+ ICMP6_DUR_POLICY = 5,
+ /** Reject route to destination */
+ ICMP6_DUR_REJECT_ROUTE = 6
+};
+
+/** ICMP time exceeded codes */
+enum icmp6_te_code {
+ /** Hop limit exceeded in transit */
+ ICMP6_TE_HL = 0,
+ /** Fragment reassembly time exceeded */
+ ICMP6_TE_FRAG = 1
+};
+
+/** ICMP parameter code */
+enum icmp6_pp_code {
+ /** Erroneous header field encountered */
+ ICMP6_PP_FIELD = 0,
+ /** Unrecognized next header type encountered */
+ ICMP6_PP_HEADER = 1,
+ /** Unrecognized IPv6 option encountered */
+ ICMP6_PP_OPTION = 2
+};
+
+/** This is the standard ICMP6 header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp6_hdr {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u32_t data);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** This is the ICMP6 header adapted for echo req/resp. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp6_echo_hdr {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u16_t id);
+ PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ICMP6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ieee.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ieee.h
new file mode 100644
index 0000000..cd4d2de
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ieee.h
@@ -0,0 +1,91 @@
+/**
+ * @file
+ * IEEE assigned numbers
+ *
+ * @defgroup ieee IEEE assigned numbers
+ * @ingroup infrastructure
+ */
+
+/*
+ * Copyright (c) 2017 Dirk Ziegelmeier.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier
+ *
+ */
+
+#ifndef LWIP_HDR_PROT_IEEE_H
+#define LWIP_HDR_PROT_IEEE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup ieee
+ * A list of often ethtypes (although lwIP does not use all of them).
+ */
+enum lwip_ieee_eth_type {
+ /** Internet protocol v4 */
+ ETHTYPE_IP = 0x0800U,
+ /** Address resolution protocol */
+ ETHTYPE_ARP = 0x0806U,
+ /** Wake on lan */
+ ETHTYPE_WOL = 0x0842U,
+ /** RARP */
+ ETHTYPE_RARP = 0x8035U,
+ /** Virtual local area network */
+ ETHTYPE_VLAN = 0x8100U,
+ /** Internet protocol v6 */
+ ETHTYPE_IPV6 = 0x86DDU,
+ /** PPP Over Ethernet Discovery Stage */
+ ETHTYPE_PPPOEDISC = 0x8863U,
+ /** PPP Over Ethernet Session Stage */
+ ETHTYPE_PPPOE = 0x8864U,
+ /** Jumbo Frames */
+ ETHTYPE_JUMBO = 0x8870U,
+ /** Process field network */
+ ETHTYPE_PROFINET = 0x8892U,
+ /** Ethernet for control automation technology */
+ ETHTYPE_ETHERCAT = 0x88A4U,
+ /** Link layer discovery protocol */
+ ETHTYPE_LLDP = 0x88CCU,
+ /** Serial real-time communication system */
+ ETHTYPE_SERCOS = 0x88CDU,
+ /** Media redundancy protocol */
+ ETHTYPE_MRP = 0x88E3U,
+ /** Precision time protocol */
+ ETHTYPE_PTP = 0x88F7U,
+ /** Q-in-Q, 802.1ad */
+ ETHTYPE_QINQ = 0x9100U
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IEEE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/igmp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/igmp.h
new file mode 100644
index 0000000..46b81a9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/igmp.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ * IGMP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_IGMP_H
+#define LWIP_HDR_PROT_IGMP_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ip4.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * IGMP constants
+ */
+#define IGMP_TTL 1
+#define IGMP_MINLEN 8
+#define ROUTER_ALERT 0x9404U
+#define ROUTER_ALERTLEN 4
+
+/*
+ * IGMP message types, including version number.
+ */
+#define IGMP_MEMB_QUERY 0x11 /* Membership query */
+#define IGMP_V1_MEMB_REPORT 0x12 /* Ver. 1 membership report */
+#define IGMP_V2_MEMB_REPORT 0x16 /* Ver. 2 membership report */
+#define IGMP_LEAVE_GROUP 0x17 /* Leave-group message */
+
+/* Group membership states */
+#define IGMP_GROUP_NON_MEMBER 0
+#define IGMP_GROUP_DELAYING_MEMBER 1
+#define IGMP_GROUP_IDLE_MEMBER 2
+
+/**
+ * IGMP packet format.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct igmp_msg {
+ PACK_STRUCT_FLD_8(u8_t igmp_msgtype);
+ PACK_STRUCT_FLD_8(u8_t igmp_maxresp);
+ PACK_STRUCT_FIELD(u16_t igmp_checksum);
+ PACK_STRUCT_FLD_S(ip4_addr_p_t igmp_group_address);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IGMP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip.h
new file mode 100644
index 0000000..223158f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip.h
@@ -0,0 +1,59 @@
+/**
+ * @file
+ * IP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_IP_H
+#define LWIP_HDR_PROT_IP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_PROTO_ICMP 1
+#define IP_PROTO_IGMP 2
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP 6
+
+/** This operates on a void* by loading the first byte */
+#define IP_HDR_GET_VERSION(ptr) ((*(u8_t*)(ptr)) >> 4)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip4.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip4.h
new file mode 100644
index 0000000..9347461
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip4.h
@@ -0,0 +1,131 @@
+/**
+ * @file
+ * IPv4 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_IP4_H
+#define LWIP_HDR_PROT_IP4_H
+
+#include "lwip/arch.h"
+#include "lwip/ip4_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This is the packed version of ip4_addr_t,
+ used in network headers that are itself packed */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip4_addr_packed {
+ PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+typedef struct ip4_addr_packed ip4_addr_p_t;
+
+/* Size of the IPv4 header. Same as 'sizeof(struct ip_hdr)'. */
+#define IP_HLEN 20
+/* Maximum size of the IPv4 header with options. */
+#define IP_HLEN_MAX 60
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/* The IPv4 header */
+struct ip_hdr {
+ /* version / header length */
+ PACK_STRUCT_FLD_8(u8_t _v_hl);
+ /* type of service */
+ PACK_STRUCT_FLD_8(u8_t _tos);
+ /* total length */
+ PACK_STRUCT_FIELD(u16_t _len);
+ /* identification */
+ PACK_STRUCT_FIELD(u16_t _id);
+ /* fragment offset field */
+ PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000U /* reserved fragment flag */
+#define IP_DF 0x4000U /* don't fragment flag */
+#define IP_MF 0x2000U /* more fragments flag */
+#define IP_OFFMASK 0x1fffU /* mask for fragmenting bits */
+ /* time to live */
+ PACK_STRUCT_FLD_8(u8_t _ttl);
+ /* protocol*/
+ PACK_STRUCT_FLD_8(u8_t _proto);
+ /* checksum */
+ PACK_STRUCT_FIELD(u16_t _chksum);
+ /* source and destination IP addresses */
+ PACK_STRUCT_FLD_S(ip4_addr_p_t src);
+ PACK_STRUCT_FLD_S(ip4_addr_p_t dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/* Macros to get struct ip_hdr fields: */
+#define IPH_V(hdr) ((hdr)->_v_hl >> 4)
+#define IPH_HL(hdr) ((hdr)->_v_hl & 0x0f)
+#define IPH_HL_BYTES(hdr) ((u8_t)(IPH_HL(hdr) * 4))
+#define IPH_TOS(hdr) ((hdr)->_tos)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_OFFSET_BYTES(hdr) ((u16_t)((lwip_ntohs(IPH_OFFSET(hdr)) & IP_OFFMASK) * 8U))
+#define IPH_TTL(hdr) ((hdr)->_ttl)
+#define IPH_PROTO(hdr) ((hdr)->_proto)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+/* Macros to set struct ip_hdr fields: */
+#define IPH_VHL_SET(hdr, v, hl) (hdr)->_v_hl = (u8_t)((((v) << 4) | (hl)))
+#define IPH_TOS_SET(hdr, tos) (hdr)->_tos = (tos)
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl)
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto)
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IP4_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip6.h
new file mode 100644
index 0000000..0f6de45
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/ip6.h
@@ -0,0 +1,233 @@
+/**
+ * @file
+ * IPv6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_IP6_H
+#define LWIP_HDR_PROT_IP6_H
+
+#include "lwip/arch.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This is the packed version of ip6_addr_t,
+ used in network headers that are itself packed */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_addr_packed {
+ PACK_STRUCT_FIELD(u32_t addr[4]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+typedef struct ip6_addr_packed ip6_addr_p_t;
+
+#define IP6_HLEN 40
+
+#define IP6_NEXTH_HOPBYHOP 0
+#define IP6_NEXTH_TCP 6
+#define IP6_NEXTH_UDP 17
+#define IP6_NEXTH_ENCAPS 41
+#define IP6_NEXTH_ROUTING 43
+#define IP6_NEXTH_FRAGMENT 44
+#define IP6_NEXTH_ICMP6 58
+#define IP6_NEXTH_NONE 59
+#define IP6_NEXTH_DESTOPTS 60
+#define IP6_NEXTH_UDPLITE 136
+
+/** The IPv6 header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_hdr {
+ /** version / traffic class / flow label */
+ PACK_STRUCT_FIELD(u32_t _v_tc_fl);
+ /** payload length */
+ PACK_STRUCT_FIELD(u16_t _plen);
+ /** next header */
+ PACK_STRUCT_FLD_8(u8_t _nexth);
+ /** hop limit */
+ PACK_STRUCT_FLD_8(u8_t _hoplim);
+ /** source and destination IP addresses */
+ PACK_STRUCT_FLD_S(ip6_addr_p_t src);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define IP6H_V(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 28) & 0x0f)
+#define IP6H_TC(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 20) & 0xff)
+#define IP6H_FL(hdr) (lwip_ntohl((hdr)->_v_tc_fl) & 0x000fffff)
+#define IP6H_PLEN(hdr) (lwip_ntohs((hdr)->_plen))
+#define IP6H_NEXTH(hdr) ((hdr)->_nexth)
+#define IP6H_NEXTH_P(hdr) ((u8_t *)(hdr) + 6)
+#define IP6H_HOPLIM(hdr) ((hdr)->_hoplim)
+#define IP6H_VTCFL_SET(hdr, v, tc, fl) (hdr)->_v_tc_fl = (lwip_htonl((((u32_t)(v)) << 28) | (((u32_t)(tc)) << 20) | (fl)))
+#define IP6H_PLEN_SET(hdr, plen) (hdr)->_plen = lwip_htons(plen)
+#define IP6H_NEXTH_SET(hdr, nexth) (hdr)->_nexth = (nexth)
+#define IP6H_HOPLIM_SET(hdr, hl) (hdr)->_hoplim = (u8_t)(hl)
+
+/* ipv6 extended options header */
+#define IP6_PAD1_OPTION 0
+#define IP6_PADN_OPTION 1
+#define IP6_ROUTER_ALERT_OPTION 5
+#define IP6_JUMBO_OPTION 194
+#define IP6_HOME_ADDRESS_OPTION 201
+#define IP6_ROUTER_ALERT_DLEN 2
+#define IP6_ROUTER_ALERT_VALUE_MLD 0
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_opt_hdr {
+ /* router alert option type */
+ PACK_STRUCT_FLD_8(u8_t _opt_type);
+ /* router alert option data len */
+ PACK_STRUCT_FLD_8(u8_t _opt_dlen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define IP6_OPT_HLEN 2
+#define IP6_OPT_TYPE_ACTION(hdr) ((((hdr)->_opt_type) >> 6) & 0x3)
+#define IP6_OPT_TYPE_CHANGE(hdr) ((((hdr)->_opt_type) >> 5) & 0x1)
+#define IP6_OPT_TYPE(hdr) ((hdr)->_opt_type)
+#define IP6_OPT_DLEN(hdr) ((hdr)->_opt_dlen)
+
+/* Hop-by-Hop header. */
+#define IP6_HBH_HLEN 2
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_hbh_hdr {
+ /* next header */
+ PACK_STRUCT_FLD_8(u8_t _nexth);
+ /* header length in 8-octet units */
+ PACK_STRUCT_FLD_8(u8_t _hlen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define IP6_HBH_NEXTH(hdr) ((hdr)->_nexth)
+
+/* Destination header. */
+#define IP6_DEST_HLEN 2
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_dest_hdr {
+ /* next header */
+ PACK_STRUCT_FLD_8(u8_t _nexth);
+ /* header length in 8-octet units */
+ PACK_STRUCT_FLD_8(u8_t _hlen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define IP6_DEST_NEXTH(hdr) ((hdr)->_nexth)
+
+/* Routing header */
+#define IP6_ROUT_TYPE2 2
+#define IP6_ROUT_RPL 3
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_rout_hdr {
+ /* next header */
+ PACK_STRUCT_FLD_8(u8_t _nexth);
+ /* reserved */
+ PACK_STRUCT_FLD_8(u8_t _hlen);
+ /* fragment offset */
+ PACK_STRUCT_FIELD(u8_t _routing_type);
+ /* fragmented packet identification */
+ PACK_STRUCT_FIELD(u8_t _segments_left);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define IP6_ROUT_NEXTH(hdr) ((hdr)->_nexth)
+#define IP6_ROUT_TYPE(hdr) ((hdr)->_routing_type)
+#define IP6_ROUT_SEG_LEFT(hdr) ((hdr)->_segments_left)
+
+/* Fragment header. */
+#define IP6_FRAG_HLEN 8
+#define IP6_FRAG_OFFSET_MASK 0xfff8
+#define IP6_FRAG_MORE_FLAG 0x0001
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_frag_hdr {
+ /* next header */
+ PACK_STRUCT_FLD_8(u8_t _nexth);
+ /* reserved */
+ PACK_STRUCT_FLD_8(u8_t reserved);
+ /* fragment offset */
+ PACK_STRUCT_FIELD(u16_t _fragment_offset);
+ /* fragmented packet identification */
+ PACK_STRUCT_FIELD(u32_t _identification);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define IP6_FRAG_NEXTH(hdr) ((hdr)->_nexth)
+#define IP6_FRAG_MBIT(hdr) (lwip_ntohs((hdr)->_fragment_offset) & 0x1)
+#define IP6_FRAG_ID(hdr) (lwip_ntohl((hdr)->_identification))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IP6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/mld6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/mld6.h
new file mode 100644
index 0000000..71f1dcb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/mld6.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ * MLD6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_MLD6_H
+#define LWIP_HDR_PROT_MLD6_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ip6.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MLD6_HBH_HLEN 8
+/** Multicast listener report/query/done message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct mld_header {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u16_t max_resp_delay);
+ PACK_STRUCT_FIELD(u16_t reserved);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t multicast_address);
+ /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_MLD6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/nd6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/nd6.h
new file mode 100644
index 0000000..c270d07
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/nd6.h
@@ -0,0 +1,274 @@
+/**
+ * @file
+ * ND6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_ND6_H
+#define LWIP_HDR_PROT_ND6_H
+
+#include "lwip/arch.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/ip6.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Neighbor solicitation message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ns_header {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u32_t reserved);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+ /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Neighbor advertisement message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct na_header {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FLD_8(u8_t flags);
+ PACK_STRUCT_FLD_8(u8_t reserved[3]);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+ /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+#define ND6_FLAG_ROUTER (0x80)
+#define ND6_FLAG_SOLICITED (0x40)
+#define ND6_FLAG_OVERRIDE (0x20)
+
+/** Router solicitation message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct rs_header {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u32_t reserved);
+ /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Router advertisement message header. */
+#define ND6_RA_FLAG_MANAGED_ADDR_CONFIG (0x80)
+#define ND6_RA_FLAG_OTHER_CONFIG (0x40)
+#define ND6_RA_FLAG_HOME_AGENT (0x20)
+#define ND6_RA_PREFERENCE_MASK (0x18)
+#define ND6_RA_PREFERENCE_HIGH (0x08)
+#define ND6_RA_PREFERENCE_MEDIUM (0x00)
+#define ND6_RA_PREFERENCE_LOW (0x18)
+#define ND6_RA_PREFERENCE_DISABLED (0x10)
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ra_header {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FLD_8(u8_t current_hop_limit);
+ PACK_STRUCT_FLD_8(u8_t flags);
+ PACK_STRUCT_FIELD(u16_t router_lifetime);
+ PACK_STRUCT_FIELD(u32_t reachable_time);
+ PACK_STRUCT_FIELD(u32_t retrans_timer);
+ /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Redirect message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct redirect_header {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u32_t reserved);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t destination_address);
+ /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Link-layer address option. */
+#define ND6_OPTION_TYPE_SOURCE_LLADDR (0x01)
+#define ND6_OPTION_TYPE_TARGET_LLADDR (0x02)
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct lladdr_option {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t length);
+ PACK_STRUCT_FLD_8(u8_t addr[NETIF_MAX_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Prefix information option. */
+#define ND6_OPTION_TYPE_PREFIX_INFO (0x03)
+#define ND6_PREFIX_FLAG_ON_LINK (0x80)
+#define ND6_PREFIX_FLAG_AUTONOMOUS (0x40)
+#define ND6_PREFIX_FLAG_ROUTER_ADDRESS (0x20)
+#define ND6_PREFIX_FLAG_SITE_PREFIX (0x10)
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct prefix_option {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t length);
+ PACK_STRUCT_FLD_8(u8_t prefix_length);
+ PACK_STRUCT_FLD_8(u8_t flags);
+ PACK_STRUCT_FIELD(u32_t valid_lifetime);
+ PACK_STRUCT_FIELD(u32_t preferred_lifetime);
+ PACK_STRUCT_FLD_8(u8_t reserved2[3]);
+ PACK_STRUCT_FLD_8(u8_t site_prefix_length);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Redirected header option. */
+#define ND6_OPTION_TYPE_REDIR_HDR (0x04)
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct redirected_header_option {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t length);
+ PACK_STRUCT_FLD_8(u8_t reserved[6]);
+ /* Portion of redirected packet follows. */
+ /* PACK_STRUCT_FLD_8(u8_t redirected[8]); */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** MTU option. */
+#define ND6_OPTION_TYPE_MTU (0x05)
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct mtu_option {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t length);
+ PACK_STRUCT_FIELD(u16_t reserved);
+ PACK_STRUCT_FIELD(u32_t mtu);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Route information option. */
+#define ND6_OPTION_TYPE_ROUTE_INFO (24)
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct route_option {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t length);
+ PACK_STRUCT_FLD_8(u8_t prefix_length);
+ PACK_STRUCT_FLD_8(u8_t preference);
+ PACK_STRUCT_FIELD(u32_t route_lifetime);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/** Recursive DNS Server Option. */
+#define ND6_OPTION_TYPE_RDNSS (25)
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct rdnss_option {
+ PACK_STRUCT_FLD_8(u8_t type);
+ PACK_STRUCT_FLD_8(u8_t length);
+ PACK_STRUCT_FIELD(u16_t reserved);
+ PACK_STRUCT_FIELD(u32_t lifetime);
+ PACK_STRUCT_FLD_S(ip6_addr_p_t rdnss_address[1]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_RDNSS_OPTION_BASE 8 /* size without addresses */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ND6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/tcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/tcp.h
new file mode 100644
index 0000000..c1d7de1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/tcp.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * TCP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_TCP_H
+#define LWIP_HDR_PROT_TCP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+/* Fields are (of course) in network byte order.
+ * Some fields are converted to host byte order in tcp_input().
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+ PACK_STRUCT_FIELD(u16_t src);
+ PACK_STRUCT_FIELD(u16_t dest);
+ PACK_STRUCT_FIELD(u32_t seqno);
+ PACK_STRUCT_FIELD(u32_t ackno);
+ PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+ PACK_STRUCT_FIELD(u16_t wnd);
+ PACK_STRUCT_FIELD(u16_t chksum);
+ PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/* TCP header flags bits */
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+/* Valid TCP header flags */
+#define TCP_FLAGS 0x3fU
+
+#define TCP_MAX_OPTION_BYTES 40
+
+#define TCPH_HDRLEN(phdr) ((u16_t)(lwip_ntohs((phdr)->_hdrlen_rsvd_flags) >> 12))
+#define TCPH_HDRLEN_BYTES(phdr) ((u8_t)(TCPH_HDRLEN(phdr) << 2))
+#define TCPH_FLAGS(phdr) ((u8_t)((lwip_ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)))
+
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = lwip_htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS(~TCP_FLAGS)) | lwip_htons(flags))
+#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = (u16_t)(lwip_htons((u16_t)((len) << 12) | (flags)))
+
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | lwip_htons(flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags & ~lwip_htons(flags))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_TCP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/udp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/udp.h
new file mode 100644
index 0000000..664f19a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/prot/udp.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ * UDP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_PROT_UDP_H
+#define LWIP_HDR_PROT_UDP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_HLEN 8
+
+/* Fields are (of course) in network byte order. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct udp_hdr {
+ PACK_STRUCT_FIELD(u16_t src);
+ PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */
+ PACK_STRUCT_FIELD(u16_t len);
+ PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_UDP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/raw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/raw.h
new file mode 100644
index 0000000..b129bd3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/raw.h
@@ -0,0 +1,143 @@
+/**
+ * @file
+ * raw API (to be used from TCPIP thread)\n
+ * See also @ref raw_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_RAW_H
+#define LWIP_HDR_RAW_H
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/def.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RAW_FLAGS_CONNECTED 0x01U
+#define RAW_FLAGS_HDRINCL 0x02U
+#define RAW_FLAGS_MULTICAST_LOOP 0x04U
+
+struct raw_pcb;
+
+/** Function prototype for raw pcb receive callback functions.
+ * @param arg user supplied argument (raw_pcb.recv_arg)
+ * @param pcb the raw_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @return 1 if the packet was 'eaten' (aka. deleted),
+ * 0 if the packet lives on
+ * If returning 1, the callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ */
+typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *addr);
+
+/** the RAW protocol control block */
+struct raw_pcb {
+ /* Common members of all PCB types */
+ IP_PCB;
+
+ struct raw_pcb *next;
+
+ u8_t protocol;
+ u8_t flags;
+
+#if LWIP_MULTICAST_TX_OPTIONS
+ /** outgoing network interface for multicast packets, by interface index (if nonzero) */
+ u8_t mcast_ifindex;
+ /** TTL for outgoing multicast packets */
+ u8_t mcast_ttl;
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+ /** receive callback function */
+ raw_recv_fn recv;
+ /* user-supplied argument for the recv callback */
+ void *recv_arg;
+#if LWIP_IPV6
+ /* fields for handling checksum computations as per RFC3542. */
+ u16_t chksum_offset;
+ u8_t chksum_reqd;
+#endif
+};
+
+/* The following functions is the application layer interface to the
+ RAW code. */
+struct raw_pcb * raw_new (u8_t proto);
+struct raw_pcb * raw_new_ip_type(u8_t type, u8_t proto);
+void raw_remove (struct raw_pcb *pcb);
+err_t raw_bind (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
+void raw_bind_netif (struct raw_pcb *pcb, const struct netif *netif);
+err_t raw_connect (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
+void raw_disconnect (struct raw_pcb *pcb);
+
+err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr);
+err_t raw_sendto_if_src(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, struct netif *netif, const ip_addr_t *src_ip);
+err_t raw_send (struct raw_pcb *pcb, struct pbuf *p);
+
+void raw_recv (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg);
+
+#define raw_flags(pcb) ((pcb)->flags)
+#define raw_setflags(pcb,f) ((pcb)->flags = (f))
+
+#define raw_set_flags(pcb, set_flags) do { (pcb)->flags = (u8_t)((pcb)->flags | (set_flags)); } while(0)
+#define raw_clear_flags(pcb, clr_flags) do { (pcb)->flags = (u8_t)((pcb)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define raw_is_flag_set(pcb, flag) (((pcb)->flags & (flag)) != 0)
+
+#define raw_init() /* Compatibility define, no init needed. */
+
+/* for compatibility with older implementation */
+#define raw_new_ip6(proto) raw_new_ip_type(IPADDR_TYPE_V6, proto)
+
+#if LWIP_MULTICAST_TX_OPTIONS
+#define raw_set_multicast_netif_index(pcb, idx) ((pcb)->mcast_ifindex = (idx))
+#define raw_get_multicast_netif_index(pcb) ((pcb)->mcast_ifindex)
+#define raw_set_multicast_ttl(pcb, value) ((pcb)->mcast_ttl = (value))
+#define raw_get_multicast_ttl(pcb) ((pcb)->mcast_ttl)
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* LWIP_HDR_RAW_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sio.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sio.h
new file mode 100644
index 0000000..7643e19
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sio.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#ifndef SIO_H
+#define SIO_H
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If you want to define sio_fd_t elsewhere or differently,
+ define this in your cc.h file. */
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+/* The following functions can be defined to something else in your cc.h file
+ or be implemented in your custom sio.c file. */
+
+#ifndef sio_open
+/**
+ * Opens a serial device for communication.
+ *
+ * @param devnum device number
+ * @return handle to serial device if successful, NULL otherwise
+ */
+sio_fd_t sio_open(u8_t devnum);
+#endif
+
+#ifndef sio_send
+/**
+ * Sends a single character to the serial device.
+ *
+ * @param c character to send
+ * @param fd serial device handle
+ *
+ * @note This function will block until the character can be sent.
+ */
+void sio_send(u8_t c, sio_fd_t fd);
+#endif
+
+#ifndef sio_recv
+/**
+ * Receives a single character from the serial device.
+ *
+ * @param fd serial device handle
+ *
+ * @note This function will block until a character is received.
+ */
+u8_t sio_recv(sio_fd_t fd);
+#endif
+
+#ifndef sio_read
+/**
+ * Reads from the serial device.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received - may be 0 if aborted by sio_read_abort
+ *
+ * @note This function will block until data can be received. The blocking
+ * can be cancelled by calling sio_read_abort().
+ */
+u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_tryread
+/**
+ * Tries to read from the serial device. Same as sio_read but returns
+ * immediately if no data is available and never blocks.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received
+ */
+u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_write
+/**
+ * Writes to the serial device.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data to send
+ * @param len length (in bytes) of data to send
+ * @return number of bytes actually sent
+ *
+ * @note This function will block until all data can be sent.
+ */
+u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_read_abort
+/**
+ * Aborts a blocking sio_read() call.
+ *
+ * @param fd serial device handle
+ */
+void sio_read_abort(sio_fd_t fd);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SIO_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/snmp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/snmp.h
new file mode 100644
index 0000000..8704d0b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/snmp.h
@@ -0,0 +1,213 @@
+/**
+ * @file
+ * SNMP support API for implementing netifs and statitics for MIB2
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier
+ *
+ */
+#ifndef LWIP_HDR_SNMP_H
+#define LWIP_HDR_SNMP_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct udp_pcb;
+struct netif;
+
+/**
+ * @defgroup netif_mib2 MIB2 statistics
+ * @ingroup netif
+ */
+
+/* MIB2 statistics functions */
+#if MIB2_STATS /* don't build if not configured for use in lwipopts.h */
+/**
+ * @ingroup netif_mib2
+ * @see RFC1213, "MIB-II, 6. Definitions"
+ */
+enum snmp_ifType {
+ snmp_ifType_other=1, /* none of the following */
+ snmp_ifType_regular1822,
+ snmp_ifType_hdh1822,
+ snmp_ifType_ddn_x25,
+ snmp_ifType_rfc877_x25,
+ snmp_ifType_ethernet_csmacd,
+ snmp_ifType_iso88023_csmacd,
+ snmp_ifType_iso88024_tokenBus,
+ snmp_ifType_iso88025_tokenRing,
+ snmp_ifType_iso88026_man,
+ snmp_ifType_starLan,
+ snmp_ifType_proteon_10Mbit,
+ snmp_ifType_proteon_80Mbit,
+ snmp_ifType_hyperchannel,
+ snmp_ifType_fddi,
+ snmp_ifType_lapb,
+ snmp_ifType_sdlc,
+ snmp_ifType_ds1, /* T-1 */
+ snmp_ifType_e1, /* european equiv. of T-1 */
+ snmp_ifType_basicISDN,
+ snmp_ifType_primaryISDN, /* proprietary serial */
+ snmp_ifType_propPointToPointSerial,
+ snmp_ifType_ppp,
+ snmp_ifType_softwareLoopback,
+ snmp_ifType_eon, /* CLNP over IP [11] */
+ snmp_ifType_ethernet_3Mbit,
+ snmp_ifType_nsip, /* XNS over IP */
+ snmp_ifType_slip, /* generic SLIP */
+ snmp_ifType_ultra, /* ULTRA technologies */
+ snmp_ifType_ds3, /* T-3 */
+ snmp_ifType_sip, /* SMDS */
+ snmp_ifType_frame_relay
+};
+
+/** This macro has a precision of ~49 days because sys_now returns u32_t. \#define your own if you want ~490 days. */
+#ifndef MIB2_COPY_SYSUPTIME_TO
+#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) (*(ptrToVal) = (sys_now() / 10))
+#endif
+
+/**
+ * @ingroup netif_mib2
+ * Increment stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs)
+ */
+#define MIB2_STATS_NETIF_INC(n, x) do { ++(n)->mib2_counters.x; } while(0)
+/**
+ * @ingroup netif_mib2
+ * Add value to stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs)
+ */
+#define MIB2_STATS_NETIF_ADD(n, x, val) do { (n)->mib2_counters.x += (val); } while(0)
+
+/**
+ * @ingroup netif_mib2
+ * Init MIB2 statistic counters in netif
+ * @param netif Netif to init
+ * @param type one of enum @ref snmp_ifType
+ * @param speed your link speed here (units: bits per second)
+ */
+#define MIB2_INIT_NETIF(netif, type, speed) do { \
+ (netif)->link_type = (type); \
+ (netif)->link_speed = (speed);\
+ (netif)->ts = 0; \
+ (netif)->mib2_counters.ifinoctets = 0; \
+ (netif)->mib2_counters.ifinucastpkts = 0; \
+ (netif)->mib2_counters.ifinnucastpkts = 0; \
+ (netif)->mib2_counters.ifindiscards = 0; \
+ (netif)->mib2_counters.ifinerrors = 0; \
+ (netif)->mib2_counters.ifinunknownprotos = 0; \
+ (netif)->mib2_counters.ifoutoctets = 0; \
+ (netif)->mib2_counters.ifoutucastpkts = 0; \
+ (netif)->mib2_counters.ifoutnucastpkts = 0; \
+ (netif)->mib2_counters.ifoutdiscards = 0; \
+ (netif)->mib2_counters.ifouterrors = 0; } while(0)
+#else /* MIB2_STATS */
+#ifndef MIB2_COPY_SYSUPTIME_TO
+#define MIB2_COPY_SYSUPTIME_TO(ptrToVal)
+#endif
+#define MIB2_INIT_NETIF(netif, type, speed)
+#define MIB2_STATS_NETIF_INC(n, x)
+#define MIB2_STATS_NETIF_ADD(n, x, val)
+#endif /* MIB2_STATS */
+
+/* LWIP MIB2 callbacks */
+#if LWIP_MIB2_CALLBACKS /* don't build if not configured for use in lwipopts.h */
+/* network interface */
+void mib2_netif_added(struct netif *ni);
+void mib2_netif_removed(struct netif *ni);
+
+#if LWIP_IPV4 && LWIP_ARP
+/* ARP (for atTable and ipNetToMediaTable) */
+void mib2_add_arp_entry(struct netif *ni, ip4_addr_t *ip);
+void mib2_remove_arp_entry(struct netif *ni, ip4_addr_t *ip);
+#else /* LWIP_IPV4 && LWIP_ARP */
+#define mib2_add_arp_entry(ni,ip)
+#define mib2_remove_arp_entry(ni,ip)
+#endif /* LWIP_IPV4 && LWIP_ARP */
+
+/* IP */
+#if LWIP_IPV4
+void mib2_add_ip4(struct netif *ni);
+void mib2_remove_ip4(struct netif *ni);
+void mib2_add_route_ip4(u8_t dflt, struct netif *ni);
+void mib2_remove_route_ip4(u8_t dflt, struct netif *ni);
+#endif /* LWIP_IPV4 */
+
+/* UDP */
+#if LWIP_UDP
+void mib2_udp_bind(struct udp_pcb *pcb);
+void mib2_udp_unbind(struct udp_pcb *pcb);
+#endif /* LWIP_UDP */
+
+#else /* LWIP_MIB2_CALLBACKS */
+/* LWIP_MIB2_CALLBACKS support not available */
+/* define everything to be empty */
+
+/* network interface */
+#define mib2_netif_added(ni)
+#define mib2_netif_removed(ni)
+
+/* ARP */
+#define mib2_add_arp_entry(ni,ip)
+#define mib2_remove_arp_entry(ni,ip)
+
+/* IP */
+#define mib2_add_ip4(ni)
+#define mib2_remove_ip4(ni)
+#define mib2_add_route_ip4(dflt, ni)
+#define mib2_remove_route_ip4(dflt, ni)
+
+/* UDP */
+#define mib2_udp_bind(pcb)
+#define mib2_udp_unbind(pcb)
+#endif /* LWIP_MIB2_CALLBACKS */
+
+/* for source-code compatibility reasons only, can be removed (not used internally) */
+#define NETIF_INIT_SNMP MIB2_INIT_NETIF
+#define snmp_add_ifinoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifinoctets, value)
+#define snmp_inc_ifinucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifinucastpkts)
+#define snmp_inc_ifinnucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifinnucastpkts)
+#define snmp_inc_ifindiscards(ni) MIB2_STATS_NETIF_INC(ni, ifindiscards)
+#define snmp_inc_ifinerrors(ni) MIB2_STATS_NETIF_INC(ni, ifinerrors)
+#define snmp_inc_ifinunknownprotos(ni) MIB2_STATS_NETIF_INC(ni, ifinunknownprotos)
+#define snmp_add_ifoutoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifoutoctets, value)
+#define snmp_inc_ifoutucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifoutucastpkts)
+#define snmp_inc_ifoutnucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifoutnucastpkts)
+#define snmp_inc_ifoutdiscards(ni) MIB2_STATS_NETIF_INC(ni, ifoutdiscards)
+#define snmp_inc_ifouterrors(ni) MIB2_STATS_NETIF_INC(ni, ifouterrors)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_SNMP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sockets.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sockets.h
new file mode 100644
index 0000000..37b9528
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sockets.h
@@ -0,0 +1,693 @@
+/**
+ * @file
+ * Socket API (to be used from non-TCPIP threads)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+
+#ifndef LWIP_HDR_SOCKETS_H
+#define LWIP_HDR_SOCKETS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/err.h"
+#include "lwip/inet.h"
+#include "lwip/errno.h"
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If your port already typedef's sa_family_t, define SA_FAMILY_T_DEFINED
+ to prevent this code from redefining it. */
+#if !defined(sa_family_t) && !defined(SA_FAMILY_T_DEFINED)
+typedef u8_t sa_family_t;
+#endif
+/* If your port already typedef's in_port_t, define IN_PORT_T_DEFINED
+ to prevent this code from redefining it. */
+#if !defined(in_port_t) && !defined(IN_PORT_T_DEFINED)
+typedef u16_t in_port_t;
+#endif
+
+#if LWIP_IPV4
+/* members are in network byte order */
+struct sockaddr_in {
+ u8_t sin_len;
+ sa_family_t sin_family;
+ in_port_t sin_port;
+ struct in_addr sin_addr;
+#define SIN_ZERO_LEN 8
+ char sin_zero[SIN_ZERO_LEN];
+};
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+struct sockaddr_in6 {
+ u8_t sin6_len; /* length of this structure */
+ sa_family_t sin6_family; /* AF_INET6 */
+ in_port_t sin6_port; /* Transport layer port # */
+ u32_t sin6_flowinfo; /* IPv6 flow information */
+ struct in6_addr sin6_addr; /* IPv6 address */
+ u32_t sin6_scope_id; /* Set of interfaces for scope */
+};
+#endif /* LWIP_IPV6 */
+
+struct sockaddr {
+ u8_t sa_len;
+ sa_family_t sa_family;
+ char sa_data[14];
+};
+
+struct sockaddr_storage {
+ u8_t s2_len;
+ sa_family_t ss_family;
+ char s2_data1[2];
+ u32_t s2_data2[3];
+#if LWIP_IPV6
+ u32_t s2_data3[3];
+#endif /* LWIP_IPV6 */
+};
+
+/* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED
+ to prevent this code from redefining it. */
+#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED)
+typedef u32_t socklen_t;
+#endif
+
+#if !defined IOV_MAX
+#define IOV_MAX 0xFFFF
+#elif IOV_MAX > 0xFFFF
+#error "IOV_MAX larger than supported by LwIP"
+#endif /* IOV_MAX */
+
+#if !defined(iovec)
+struct iovec {
+ void *iov_base;
+ size_t iov_len;
+};
+#endif
+
+struct msghdr {
+ void *msg_name;
+ socklen_t msg_namelen;
+ struct iovec *msg_iov;
+ int msg_iovlen;
+ void *msg_control;
+ socklen_t msg_controllen;
+ int msg_flags;
+};
+
+/* struct msghdr->msg_flags bit field values */
+#define MSG_TRUNC 0x04
+#define MSG_CTRUNC 0x08
+
+/* RFC 3542, Section 20: Ancillary Data */
+struct cmsghdr {
+ socklen_t cmsg_len; /* number of bytes, including header */
+ int cmsg_level; /* originating protocol */
+ int cmsg_type; /* protocol-specific type */
+};
+/* Data section follows header and possible padding, typically referred to as
+ unsigned char cmsg_data[]; */
+
+/* cmsg header/data alignment. NOTE: we align to native word size (double word
+size on 16-bit arch) so structures are not placed at an unaligned address.
+16-bit arch needs double word to ensure 32-bit alignment because socklen_t
+could be 32 bits. If we ever have cmsg data with a 64-bit variable, alignment
+will need to increase long long */
+#define ALIGN_H(size) (((size) + sizeof(long) - 1U) & ~(sizeof(long)-1U))
+#define ALIGN_D(size) ALIGN_H(size)
+
+#define CMSG_FIRSTHDR(mhdr) \
+ ((mhdr)->msg_controllen >= sizeof(struct cmsghdr) ? \
+ (struct cmsghdr *)(mhdr)->msg_control : \
+ (struct cmsghdr *)NULL)
+
+#define CMSG_NXTHDR(mhdr, cmsg) \
+ (((cmsg) == NULL) ? CMSG_FIRSTHDR(mhdr) : \
+ (((u8_t *)(cmsg) + ALIGN_H((cmsg)->cmsg_len) \
+ + ALIGN_D(sizeof(struct cmsghdr)) > \
+ (u8_t *)((mhdr)->msg_control) + (mhdr)->msg_controllen) ? \
+ (struct cmsghdr *)NULL : \
+ (struct cmsghdr *)((void*)((u8_t *)(cmsg) + \
+ ALIGN_H((cmsg)->cmsg_len)))))
+
+#define CMSG_DATA(cmsg) ((void*)((u8_t *)(cmsg) + \
+ ALIGN_D(sizeof(struct cmsghdr))))
+
+#define CMSG_SPACE(length) (ALIGN_D(sizeof(struct cmsghdr)) + \
+ ALIGN_H(length))
+
+#define CMSG_LEN(length) (ALIGN_D(sizeof(struct cmsghdr)) + \
+ length)
+
+/* Set socket options argument */
+#define IFNAMSIZ NETIF_NAMESIZE
+struct ifreq {
+ char ifr_name[IFNAMSIZ]; /* Interface name */
+};
+
+/* Socket protocol types (TCP/UDP/RAW) */
+#define SOCK_STREAM 1
+#define SOCK_DGRAM 2
+#define SOCK_RAW 3
+
+/*
+ * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c)
+ */
+#define SO_REUSEADDR 0x0004 /* Allow local address reuse */
+#define SO_KEEPALIVE 0x0008 /* keep connections alive */
+#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */
+#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */
+#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */
+#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */
+#define SO_LINGER 0x0080 /* linger on close if data present */
+#define SO_DONTLINGER ((int)(~SO_LINGER))
+#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */
+#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */
+#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */
+#define SO_RCVBUF 0x1002 /* receive buffer size */
+#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */
+#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */
+#define SO_SNDTIMEO 0x1005 /* send timeout */
+#define SO_RCVTIMEO 0x1006 /* receive timeout */
+#define SO_ERROR 0x1007 /* get error status and clear */
+#define SO_TYPE 0x1008 /* get socket type */
+#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */
+#define SO_NO_CHECK 0x100a /* don't create UDP checksum */
+#define SO_BINDTODEVICE 0x100b /* bind to device */
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+ int l_onoff; /* option on/off */
+ int l_linger; /* linger time in seconds */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define SOL_SOCKET 0xfff /* options for socket level */
+
+
+#define AF_UNSPEC 0
+#define AF_INET 2
+#if LWIP_IPV6
+#define AF_INET6 10
+#else /* LWIP_IPV6 */
+#define AF_INET6 AF_UNSPEC
+#endif /* LWIP_IPV6 */
+#define PF_INET AF_INET
+#define PF_INET6 AF_INET6
+#define PF_UNSPEC AF_UNSPEC
+
+#define IPPROTO_IP 0
+#define IPPROTO_ICMP 1
+#define IPPROTO_TCP 6
+#define IPPROTO_UDP 17
+#if LWIP_IPV6
+#define IPPROTO_IPV6 41
+#define IPPROTO_ICMPV6 58
+#endif /* LWIP_IPV6 */
+#define IPPROTO_UDPLITE 136
+#define IPPROTO_RAW 255
+
+/* Flags we can use with send and recv. */
+#define MSG_PEEK 0x01 /* Peeks at an incoming message */
+#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
+#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
+#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */
+#define MSG_MORE 0x10 /* Sender will send more */
+#define MSG_NOSIGNAL 0x20 /* Uninmplemented: Requests not to send the SIGPIPE signal if an attempt to send is made on a stream-oriented socket that is no longer connected. */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS 1
+#define IP_TTL 2
+#define IP_PKTINFO 8
+
+#if LWIP_TCP
+/*
+ * Options for level IPPROTO_TCP
+ */
+#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */
+#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */
+#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */
+#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */
+#endif /* LWIP_TCP */
+
+#if LWIP_IPV6
+/*
+ * Options for level IPPROTO_IPV6
+ */
+#define IPV6_CHECKSUM 7 /* RFC3542: calculate and insert the ICMPv6 checksum for raw sockets. */
+#define IPV6_V6ONLY 27 /* RFC3493: boolean control to restrict AF_INET6 sockets to IPv6 communications only. */
+#endif /* LWIP_IPV6 */
+
+#if LWIP_UDP && LWIP_UDPLITE
+/*
+ * Options for level IPPROTO_UDPLITE
+ */
+#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
+#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+
+
+#if LWIP_MULTICAST_TX_OPTIONS
+/*
+ * Options and types for UDP multicast traffic handling
+ */
+#define IP_MULTICAST_TTL 5
+#define IP_MULTICAST_IF 6
+#define IP_MULTICAST_LOOP 7
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if LWIP_IGMP
+/*
+ * Options and types related to multicast membership
+ */
+#define IP_ADD_MEMBERSHIP 3
+#define IP_DROP_MEMBERSHIP 4
+
+typedef struct ip_mreq {
+ struct in_addr imr_multiaddr; /* IP multicast address of group */
+ struct in_addr imr_interface; /* local IP address of interface */
+} ip_mreq;
+#endif /* LWIP_IGMP */
+
+#if LWIP_IPV4
+struct in_pktinfo {
+ unsigned int ipi_ifindex; /* Interface index */
+ struct in_addr ipi_addr; /* Destination (from header) address */
+};
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6_MLD
+/*
+ * Options and types related to IPv6 multicast membership
+ */
+#define IPV6_JOIN_GROUP 12
+#define IPV6_ADD_MEMBERSHIP IPV6_JOIN_GROUP
+#define IPV6_LEAVE_GROUP 13
+#define IPV6_DROP_MEMBERSHIP IPV6_LEAVE_GROUP
+
+typedef struct ipv6_mreq {
+ struct in6_addr ipv6mr_multiaddr; /* IPv6 multicast addr */
+ unsigned int ipv6mr_interface; /* interface index, or 0 */
+} ipv6_mreq;
+#endif /* LWIP_IPV6_MLD */
+
+/*
+ * The Type of Service provides an indication of the abstract
+ * parameters of the quality of service desired. These parameters are
+ * to be used to guide the selection of the actual service parameters
+ * when transmitting a datagram through a particular network. Several
+ * networks offer service precedence, which somehow treats high
+ * precedence traffic as more important than other traffic (generally
+ * by accepting only traffic above a certain precedence at time of high
+ * load). The major choice is a three way tradeoff between low-delay,
+ * high-reliability, and high-throughput.
+ * The use of the Delay, Throughput, and Reliability indications may
+ * increase the cost (in some sense) of the service. In many networks
+ * better performance for one of these parameters is coupled with worse
+ * performance on another. Except for very unusual cases at most two
+ * of these three indications should be set.
+ */
+#define IPTOS_TOS_MASK 0x1E
+#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY 0x10
+#define IPTOS_THROUGHPUT 0x08
+#define IPTOS_RELIABILITY 0x04
+#define IPTOS_LOWCOST 0x02
+#define IPTOS_MINCOST IPTOS_LOWCOST
+
+/*
+ * The Network Control precedence designation is intended to be used
+ * within a network only. The actual use and control of that
+ * designation is up to each network. The Internetwork Control
+ * designation is intended for use by gateway control originators only.
+ * If the actual use of these precedence designations is of concern to
+ * a particular network, it is the responsibility of that network to
+ * control the access to, and use of, those precedence designations.
+ */
+#define IPTOS_PREC_MASK 0xe0
+#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL 0xe0
+#define IPTOS_PREC_INTERNETCONTROL 0xc0
+#define IPTOS_PREC_CRITIC_ECP 0xa0
+#define IPTOS_PREC_FLASHOVERRIDE 0x80
+#define IPTOS_PREC_FLASH 0x60
+#define IPTOS_PREC_IMMEDIATE 0x40
+#define IPTOS_PREC_PRIORITY 0x20
+#define IPTOS_PREC_ROUTINE 0x00
+
+
+/*
+ * Commands for ioctlsocket(), taken from the BSD file fcntl.h.
+ * lwip_ioctl only supports FIONREAD and FIONBIO, for now
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word. The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */
+#define IOC_VOID 0x20000000UL /* no parameters */
+#define IOC_OUT 0x40000000UL /* copy out parameters */
+#define IOC_IN 0x80000000UL /* copy in parameters */
+#define IOC_INOUT (IOC_IN|IOC_OUT)
+ /* 0x20000000 distinguishes new &
+ old ioctl's */
+#define _IO(x,y) ((long)(IOC_VOID|((x)<<8)|(y)))
+
+#define _IOR(x,y,t) ((long)(IOC_OUT|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)))
+
+#define _IOW(x,y,t) ((long)(IOC_IN|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)))
+#endif /* !defined(FIONREAD) || !defined(FIONBIO) */
+
+#ifndef FIONREAD
+#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls: unimplemented */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */
+#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */
+#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */
+#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */
+#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */
+#endif
+
+/* commands for fnctl */
+#ifndef F_GETFL
+#define F_GETFL 3
+#endif
+#ifndef F_SETFL
+#define F_SETFL 4
+#endif
+
+/* File status flags and file access modes for fnctl,
+ these are bits in an int. */
+#ifndef O_NONBLOCK
+#define O_NONBLOCK 1 /* nonblocking I/O */
+#endif
+#ifndef O_NDELAY
+#define O_NDELAY O_NONBLOCK /* same as O_NONBLOCK, for compatibility */
+#endif
+#ifndef O_RDONLY
+#define O_RDONLY 2
+#endif
+#ifndef O_WRONLY
+#define O_WRONLY 4
+#endif
+#ifndef O_RDWR
+#define O_RDWR (O_RDONLY|O_WRONLY)
+#endif
+
+#ifndef SHUT_RD
+ #define SHUT_RD 0
+ #define SHUT_WR 1
+ #define SHUT_RDWR 2
+#endif
+
+/* FD_SET used for lwip_select */
+#ifndef FD_SET
+#undef FD_SETSIZE
+/* Make FD_SETSIZE match NUM_SOCKETS in socket.c */
+#define FD_SETSIZE MEMP_NUM_NETCONN
+#define LWIP_SELECT_MAXNFDS (FD_SETSIZE + LWIP_SOCKET_OFFSET)
+#define FDSETSAFESET(n, code) do { \
+ if (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0)) { \
+ code; }} while(0)
+#define FDSETSAFEGET(n, code) (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0) ?\
+ (code) : 0)
+#define FD_SET(n, p) FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] = (u8_t)((p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] | (1 << (((n)-LWIP_SOCKET_OFFSET) & 7))))
+#define FD_CLR(n, p) FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] = (u8_t)((p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] & ~(1 << (((n)-LWIP_SOCKET_OFFSET) & 7))))
+#define FD_ISSET(n,p) FDSETSAFEGET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] & (1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
+#define FD_ZERO(p) memset((void*)(p), 0, sizeof(*(p)))
+
+typedef struct fd_set
+{
+ unsigned char fd_bits [(FD_SETSIZE+7)/8];
+} fd_set;
+
+#elif FD_SETSIZE < (LWIP_SOCKET_OFFSET + MEMP_NUM_NETCONN)
+#error "external FD_SETSIZE too small for number of sockets"
+#else
+#define LWIP_SELECT_MAXNFDS FD_SETSIZE
+#endif /* FD_SET */
+
+/* poll-related defines and types */
+/* @todo: find a better way to guard the definition of these defines and types if already defined */
+#if !defined(POLLIN) && !defined(POLLOUT)
+#define POLLIN 0x1
+#define POLLOUT 0x2
+#define POLLERR 0x4
+#define POLLNVAL 0x8
+/* Below values are unimplemented */
+#define POLLRDNORM 0x10
+#define POLLRDBAND 0x20
+#define POLLPRI 0x40
+#define POLLWRNORM 0x80
+#define POLLWRBAND 0x100
+#define POLLHUP 0x200
+typedef unsigned int nfds_t;
+struct pollfd
+{
+ int fd;
+ short events;
+ short revents;
+};
+#endif
+
+/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided
+ * by your system, set this to 0 and include in cc.h */
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+struct timeval {
+ long tv_sec; /* seconds */
+ long tv_usec; /* and microseconds */
+};
+#endif /* LWIP_TIMEVAL_PRIVATE */
+
+#define lwip_socket_init() /* Compatibility define, no init needed. */
+void lwip_socket_thread_init(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */
+void lwip_socket_thread_cleanup(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */
+
+#if LWIP_COMPAT_SOCKETS == 2
+/* This helps code parsers/code completion by not having the COMPAT functions as defines */
+#define lwip_accept accept
+#define lwip_bind bind
+#define lwip_shutdown shutdown
+#define lwip_getpeername getpeername
+#define lwip_getsockname getsockname
+#define lwip_setsockopt setsockopt
+#define lwip_getsockopt getsockopt
+#define lwip_close closesocket
+#define lwip_connect connect
+#define lwip_listen listen
+#define lwip_recv recv
+#define lwip_recvmsg recvmsg
+#define lwip_recvfrom recvfrom
+#define lwip_send send
+#define lwip_sendmsg sendmsg
+#define lwip_sendto sendto
+#define lwip_socket socket
+#if LWIP_SOCKET_SELECT
+#define lwip_select select
+#endif
+#if LWIP_SOCKET_POLL
+#define lwip_poll poll
+#endif
+#define lwip_ioctl ioctlsocket
+#define lwip_inet_ntop inet_ntop
+#define lwip_inet_pton inet_pton
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define lwip_read read
+#define lwip_readv readv
+#define lwip_write write
+#define lwip_writev writev
+#undef lwip_close
+#define lwip_close close
+#define closesocket(s) close(s)
+int fcntl(int s, int cmd, ...);
+#undef lwip_ioctl
+#define lwip_ioctl ioctl
+#define ioctlsocket ioctl
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+#endif /* LWIP_COMPAT_SOCKETS == 2 */
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+ int lwip_close(int s);
+int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+ssize_t lwip_recv(int s, void *mem, size_t len, int flags);
+ssize_t lwip_read(int s, void *mem, size_t len);
+ssize_t lwip_readv(int s, const struct iovec *iov, int iovcnt);
+ssize_t lwip_recvfrom(int s, void *mem, size_t len, int flags,
+ struct sockaddr *from, socklen_t *fromlen);
+ssize_t lwip_recvmsg(int s, struct msghdr *message, int flags);
+ssize_t lwip_sendto(int s, const void *data, size_t size, int flags,
+ const struct sockaddr *to, socklen_t tolen);
+ssize_t lwip_send(int s, const void *dataptr, size_t size, int flags);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ssize_t lwip_send_blocking(int s, const void *dataptr, size_t size, int flags);
+ssize_t lwip_sendto_blocking(int s, const void *data, size_t size, int flags,
+ const struct sockaddr *to, socklen_t tolen);
+#endif
+ssize_t lwip_sendmsg(int s, const struct msghdr *message, int flags);
+int lwip_socket(int domain, int type, int protocol);
+ssize_t lwip_write(int s, const void *dataptr, size_t size);
+ssize_t lwip_writev(int s, const struct iovec *iov, int iovcnt);
+#if LWIP_SOCKET_SELECT
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+ struct timeval *timeout);
+#endif
+#if LWIP_SOCKET_POLL
+int lwip_poll(struct pollfd *fds, nfds_t nfds, int timeout);
+#endif
+int lwip_ioctl(int s, long cmd, void *argp);
+int lwip_fcntl(int s, int cmd, int val);
+const char *lwip_inet_ntop(int af, const void *src, char *dst, socklen_t size);
+int lwip_inet_pton(int af, const char *src, void *dst);
+
+#if LWIP_COMPAT_SOCKETS
+#if LWIP_COMPAT_SOCKETS != 2
+/** @ingroup socket */
+#define accept(s,addr,addrlen) lwip_accept(s,addr,addrlen)
+/** @ingroup socket */
+#define bind(s,name,namelen) lwip_bind(s,name,namelen)
+/** @ingroup socket */
+#define shutdown(s,how) lwip_shutdown(s,how)
+/** @ingroup socket */
+#define getpeername(s,name,namelen) lwip_getpeername(s,name,namelen)
+/** @ingroup socket */
+#define getsockname(s,name,namelen) lwip_getsockname(s,name,namelen)
+/** @ingroup socket */
+#define setsockopt(s,level,optname,opval,optlen) lwip_setsockopt(s,level,optname,opval,optlen)
+/** @ingroup socket */
+#define getsockopt(s,level,optname,opval,optlen) lwip_getsockopt(s,level,optname,opval,optlen)
+/** @ingroup socket */
+#define closesocket(s) lwip_close(s)
+/** @ingroup socket */
+#define connect(s,name,namelen) lwip_connect(s,name,namelen)
+/** @ingroup socket */
+#define listen(s,backlog) lwip_listen(s,backlog)
+/** @ingroup socket */
+#define recv(s,mem,len,flags) lwip_recv(s,mem,len,flags)
+/** @ingroup socket */
+#define recvmsg(s,message,flags) lwip_recvmsg(s,message,flags)
+/** @ingroup socket */
+#define recvfrom(s,mem,len,flags,from,fromlen) lwip_recvfrom(s,mem,len,flags,from,fromlen)
+/** @ingroup socket */
+#define send(s,dataptr,size,flags) lwip_send(s,dataptr,size,flags)
+/** @ingroup socket */
+#define sendmsg(s,message,flags) lwip_sendmsg(s,message,flags)
+/** @ingroup socket */
+#define sendto(s,dataptr,size,flags,to,tolen) lwip_sendto(s,dataptr,size,flags,to,tolen)
+/** @ingroup socket */
+#define socket(domain,type,protocol) lwip_socket(domain,type,protocol)
+#if LWIP_SOCKET_SELECT
+/** @ingroup socket */
+#define select(maxfdp1,readset,writeset,exceptset,timeout) lwip_select(maxfdp1,readset,writeset,exceptset,timeout)
+#endif
+#if LWIP_SOCKET_POLL
+/** @ingroup socket */
+#define poll(fds,nfds,timeout) lwip_poll(fds,nfds,timeout)
+#endif
+/** @ingroup socket */
+#define ioctlsocket(s,cmd,argp) lwip_ioctl(s,cmd,argp)
+/** @ingroup socket */
+#define inet_ntop(af,src,dst,size) lwip_inet_ntop(af,src,dst,size)
+/** @ingroup socket */
+#define inet_pton(af,src,dst) lwip_inet_pton(af,src,dst)
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+/** @ingroup socket */
+#define read(s,mem,len) lwip_read(s,mem,len)
+/** @ingroup socket */
+#define readv(s,iov,iovcnt) lwip_readv(s,iov,iovcnt)
+/** @ingroup socket */
+#define write(s,dataptr,len) lwip_write(s,dataptr,len)
+/** @ingroup socket */
+#define writev(s,iov,iovcnt) lwip_writev(s,iov,iovcnt)
+/** @ingroup socket */
+#define close(s) lwip_close(s)
+/** @ingroup socket */
+#define fcntl(s,cmd,val) lwip_fcntl(s,cmd,val)
+/** @ingroup socket */
+#define ioctl(s,cmd,argp) lwip_ioctl(s,cmd,argp)
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+#endif /* LWIP_COMPAT_SOCKETS != 2 */
+
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* LWIP_HDR_SOCKETS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/stats.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/stats.h
new file mode 100644
index 0000000..b570dba
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/stats.h
@@ -0,0 +1,491 @@
+/**
+ * @file
+ * Statistics API (to be used from TCPIP thread)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_STATS_H
+#define LWIP_HDR_STATS_H
+
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_LARGE
+#define LWIP_STATS_LARGE 0
+#endif
+
+#if LWIP_STATS_LARGE
+#define STAT_COUNTER u32_t
+#define STAT_COUNTER_F U32_F
+#else
+#define STAT_COUNTER u16_t
+#define STAT_COUNTER_F U16_F
+#endif
+
+/** Protocol related stats */
+struct stats_proto {
+ STAT_COUNTER xmit; /* Transmitted packets. */
+ STAT_COUNTER recv; /* Received packets. */
+ STAT_COUNTER fw; /* Forwarded packets. */
+ STAT_COUNTER drop; /* Dropped packets. */
+ STAT_COUNTER chkerr; /* Checksum error. */
+ STAT_COUNTER lenerr; /* Invalid length error. */
+ STAT_COUNTER memerr; /* Out of memory error. */
+ STAT_COUNTER rterr; /* Routing error. */
+ STAT_COUNTER proterr; /* Protocol error. */
+ STAT_COUNTER opterr; /* Error in options. */
+ STAT_COUNTER err; /* Misc error. */
+ STAT_COUNTER cachehit;
+};
+
+/** IGMP stats */
+struct stats_igmp {
+ STAT_COUNTER xmit; /* Transmitted packets. */
+ STAT_COUNTER recv; /* Received packets. */
+ STAT_COUNTER drop; /* Dropped packets. */
+ STAT_COUNTER chkerr; /* Checksum error. */
+ STAT_COUNTER lenerr; /* Invalid length error. */
+ STAT_COUNTER memerr; /* Out of memory error. */
+ STAT_COUNTER proterr; /* Protocol error. */
+ STAT_COUNTER rx_v1; /* Received v1 frames. */
+ STAT_COUNTER rx_group; /* Received group-specific queries. */
+ STAT_COUNTER rx_general; /* Received general queries. */
+ STAT_COUNTER rx_report; /* Received reports. */
+ STAT_COUNTER tx_join; /* Sent joins. */
+ STAT_COUNTER tx_leave; /* Sent leaves. */
+ STAT_COUNTER tx_report; /* Sent reports. */
+};
+
+/** Memory stats */
+struct stats_mem {
+#if defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY
+ const char *name;
+#endif /* defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY */
+ STAT_COUNTER err;
+ mem_size_t avail;
+ mem_size_t used;
+ mem_size_t max;
+ STAT_COUNTER illegal;
+};
+
+/** System element stats */
+struct stats_syselem {
+ STAT_COUNTER used;
+ STAT_COUNTER max;
+ STAT_COUNTER err;
+};
+
+/** System stats */
+struct stats_sys {
+ struct stats_syselem sem;
+ struct stats_syselem mutex;
+ struct stats_syselem mbox;
+};
+
+/** SNMP MIB2 stats */
+struct stats_mib2 {
+ /* IP */
+ u32_t ipinhdrerrors;
+ u32_t ipinaddrerrors;
+ u32_t ipinunknownprotos;
+ u32_t ipindiscards;
+ u32_t ipindelivers;
+ u32_t ipoutrequests;
+ u32_t ipoutdiscards;
+ u32_t ipoutnoroutes;
+ u32_t ipreasmoks;
+ u32_t ipreasmfails;
+ u32_t ipfragoks;
+ u32_t ipfragfails;
+ u32_t ipfragcreates;
+ u32_t ipreasmreqds;
+ u32_t ipforwdatagrams;
+ u32_t ipinreceives;
+
+ /* TCP */
+ u32_t tcpactiveopens;
+ u32_t tcppassiveopens;
+ u32_t tcpattemptfails;
+ u32_t tcpestabresets;
+ u32_t tcpoutsegs;
+ u32_t tcpretranssegs;
+ u32_t tcpinsegs;
+ u32_t tcpinerrs;
+ u32_t tcpoutrsts;
+
+ /* UDP */
+ u32_t udpindatagrams;
+ u32_t udpnoports;
+ u32_t udpinerrors;
+ u32_t udpoutdatagrams;
+
+ /* ICMP */
+ u32_t icmpinmsgs;
+ u32_t icmpinerrors;
+ u32_t icmpindestunreachs;
+ u32_t icmpintimeexcds;
+ u32_t icmpinparmprobs;
+ u32_t icmpinsrcquenchs;
+ u32_t icmpinredirects;
+ u32_t icmpinechos;
+ u32_t icmpinechoreps;
+ u32_t icmpintimestamps;
+ u32_t icmpintimestampreps;
+ u32_t icmpinaddrmasks;
+ u32_t icmpinaddrmaskreps;
+ u32_t icmpoutmsgs;
+ u32_t icmpouterrors;
+ u32_t icmpoutdestunreachs;
+ u32_t icmpouttimeexcds;
+ u32_t icmpoutechos; /* can be incremented by user application ('ping') */
+ u32_t icmpoutechoreps;
+};
+
+/**
+ * @ingroup netif_mib2
+ * SNMP MIB2 interface stats
+ */
+struct stats_mib2_netif_ctrs {
+ /** The total number of octets received on the interface, including framing characters */
+ u32_t ifinoctets;
+ /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were
+ * not addressed to a multicast or broadcast address at this sub-layer */
+ u32_t ifinucastpkts;
+ /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were
+ * addressed to a multicast or broadcast address at this sub-layer */
+ u32_t ifinnucastpkts;
+ /** The number of inbound packets which were chosen to be discarded even though no errors had
+ * been detected to prevent their being deliverable to a higher-layer protocol. One possible
+ * reason for discarding such a packet could be to free up buffer space */
+ u32_t ifindiscards;
+ /** For packet-oriented interfaces, the number of inbound packets that contained errors
+ * preventing them from being deliverable to a higher-layer protocol. For character-
+ * oriented or fixed-length interfaces, the number of inbound transmission units that
+ * contained errors preventing them from being deliverable to a higher-layer protocol. */
+ u32_t ifinerrors;
+ /** For packet-oriented interfaces, the number of packets received via the interface which
+ * were discarded because of an unknown or unsupported protocol. For character-oriented
+ * or fixed-length interfaces that support protocol multiplexing the number of transmission
+ * units received via the interface which were discarded because of an unknown or unsupported
+ * protocol. For any interface that does not support protocol multiplexing, this counter will
+ * always be 0 */
+ u32_t ifinunknownprotos;
+ /** The total number of octets transmitted out of the interface, including framing characters. */
+ u32_t ifoutoctets;
+ /** The total number of packets that higher-level protocols requested be transmitted, and
+ * which were not addressed to a multicast or broadcast address at this sub-layer, including
+ * those that were discarded or not sent. */
+ u32_t ifoutucastpkts;
+ /** The total number of packets that higher-level protocols requested be transmitted, and which
+ * were addressed to a multicast or broadcast address at this sub-layer, including
+ * those that were discarded or not sent. */
+ u32_t ifoutnucastpkts;
+ /** The number of outbound packets which were chosen to be discarded even though no errors had
+ * been detected to prevent their being transmitted. One possible reason for discarding
+ * such a packet could be to free up buffer space. */
+ u32_t ifoutdiscards;
+ /** For packet-oriented interfaces, the number of outbound packets that could not be transmitted
+ * because of errors. For character-oriented or fixed-length interfaces, the number of outbound
+ * transmission units that could not be transmitted because of errors. */
+ u32_t ifouterrors;
+};
+
+/** lwIP stats container */
+struct stats_ {
+#if LINK_STATS
+ /** Link level */
+ struct stats_proto link;
+#endif
+#if ETHARP_STATS
+ /** ARP */
+ struct stats_proto etharp;
+#endif
+#if IPFRAG_STATS
+ /** Fragmentation */
+ struct stats_proto ip_frag;
+#endif
+#if IP_STATS
+ /** IP */
+ struct stats_proto ip;
+#endif
+#if ICMP_STATS
+ /** ICMP */
+ struct stats_proto icmp;
+#endif
+#if IGMP_STATS
+ /** IGMP */
+ struct stats_igmp igmp;
+#endif
+#if UDP_STATS
+ /** UDP */
+ struct stats_proto udp;
+#endif
+#if TCP_STATS
+ /** TCP */
+ struct stats_proto tcp;
+#endif
+#if MEM_STATS
+ /** Heap */
+ struct stats_mem mem;
+#endif
+#if MEMP_STATS
+ /** Internal memory pools */
+ struct stats_mem *memp[MEMP_MAX];
+#endif
+#if SYS_STATS
+ /** System */
+ struct stats_sys sys;
+#endif
+#if IP6_STATS
+ /** IPv6 */
+ struct stats_proto ip6;
+#endif
+#if ICMP6_STATS
+ /** ICMP6 */
+ struct stats_proto icmp6;
+#endif
+#if IP6_FRAG_STATS
+ /** IPv6 fragmentation */
+ struct stats_proto ip6_frag;
+#endif
+#if MLD6_STATS
+ /** Multicast listener discovery */
+ struct stats_igmp mld6;
+#endif
+#if ND6_STATS
+ /** Neighbor discovery */
+ struct stats_proto nd6;
+#endif
+#if MIB2_STATS
+ /** SNMP MIB2 */
+ struct stats_mib2 mib2;
+#endif
+};
+
+/** Global variable containing lwIP internal statistics. Add this to your debugger's watchlist. */
+extern struct stats_ lwip_stats;
+
+/** Init statistics */
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#define STATS_DEC(x) --lwip_stats.x
+#define STATS_INC_USED(x, y, type) do { lwip_stats.x.used = (type)(lwip_stats.x.used + y); \
+ if (lwip_stats.x.max < lwip_stats.x.used) { \
+ lwip_stats.x.max = lwip_stats.x.used; \
+ } \
+ } while(0)
+#define STATS_GET(x) lwip_stats.x
+#else /* LWIP_STATS */
+#define stats_init()
+#define STATS_INC(x)
+#define STATS_DEC(x)
+#define STATS_INC_USED(x, y, type)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP")
+#else
+#define TCP_STATS_INC(x)
+#define TCP_STATS_DISPLAY()
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP")
+#else
+#define UDP_STATS_INC(x)
+#define UDP_STATS_DISPLAY()
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP")
+#else
+#define ICMP_STATS_INC(x)
+#define ICMP_STATS_DISPLAY()
+#endif
+
+#if IGMP_STATS
+#define IGMP_STATS_INC(x) STATS_INC(x)
+#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp, "IGMP")
+#else
+#define IGMP_STATS_INC(x)
+#define IGMP_STATS_DISPLAY()
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP")
+#else
+#define IP_STATS_INC(x)
+#define IP_STATS_DISPLAY()
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG")
+#else
+#define IPFRAG_STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY()
+#endif
+
+#if ETHARP_STATS
+#define ETHARP_STATS_INC(x) STATS_INC(x)
+#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP")
+#else
+#define ETHARP_STATS_INC(x)
+#define ETHARP_STATS_DISPLAY()
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK")
+#else
+#define LINK_STATS_INC(x)
+#define LINK_STATS_DISPLAY()
+#endif
+
+#if MEM_STATS
+#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y
+#define MEM_STATS_INC(x) STATS_INC(mem.x)
+#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y, mem_size_t)
+#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x = (mem_size_t)((lwip_stats.mem.x) - (y))
+#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP")
+#else
+#define MEM_STATS_AVAIL(x, y)
+#define MEM_STATS_INC(x)
+#define MEM_STATS_INC_USED(x, y)
+#define MEM_STATS_DEC_USED(x, y)
+#define MEM_STATS_DISPLAY()
+#endif
+
+ #if MEMP_STATS
+#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i]->x)
+#define MEMP_STATS_DISPLAY(i) stats_display_memp(lwip_stats.memp[i], i)
+#define MEMP_STATS_GET(x, i) STATS_GET(memp[i]->x)
+ #else
+#define MEMP_STATS_DEC(x, i)
+#define MEMP_STATS_DISPLAY(i)
+#define MEMP_STATS_GET(x, i) 0
+#endif
+
+#if SYS_STATS
+#define SYS_STATS_INC(x) STATS_INC(sys.x)
+#define SYS_STATS_DEC(x) STATS_DEC(sys.x)
+#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1, STAT_COUNTER)
+#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys)
+#else
+#define SYS_STATS_INC(x)
+#define SYS_STATS_DEC(x)
+#define SYS_STATS_INC_USED(x)
+#define SYS_STATS_DISPLAY()
+#endif
+
+#if IP6_STATS
+#define IP6_STATS_INC(x) STATS_INC(x)
+#define IP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6, "IPv6")
+#else
+#define IP6_STATS_INC(x)
+#define IP6_STATS_DISPLAY()
+#endif
+
+#if ICMP6_STATS
+#define ICMP6_STATS_INC(x) STATS_INC(x)
+#define ICMP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp6, "ICMPv6")
+#else
+#define ICMP6_STATS_INC(x)
+#define ICMP6_STATS_DISPLAY()
+#endif
+
+#if IP6_FRAG_STATS
+#define IP6_FRAG_STATS_INC(x) STATS_INC(x)
+#define IP6_FRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6_frag, "IPv6 FRAG")
+#else
+#define IP6_FRAG_STATS_INC(x)
+#define IP6_FRAG_STATS_DISPLAY()
+#endif
+
+#if MLD6_STATS
+#define MLD6_STATS_INC(x) STATS_INC(x)
+#define MLD6_STATS_DISPLAY() stats_display_igmp(&lwip_stats.mld6, "MLDv1")
+#else
+#define MLD6_STATS_INC(x)
+#define MLD6_STATS_DISPLAY()
+#endif
+
+#if ND6_STATS
+#define ND6_STATS_INC(x) STATS_INC(x)
+#define ND6_STATS_DISPLAY() stats_display_proto(&lwip_stats.nd6, "ND")
+#else
+#define ND6_STATS_INC(x)
+#define ND6_STATS_DISPLAY()
+#endif
+
+#if MIB2_STATS
+#define MIB2_STATS_INC(x) STATS_INC(x)
+#else
+#define MIB2_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+void stats_display_proto(struct stats_proto *proto, const char *name);
+void stats_display_igmp(struct stats_igmp *igmp, const char *name);
+void stats_display_mem(struct stats_mem *mem, const char *name);
+void stats_display_memp(struct stats_mem *mem, int index);
+void stats_display_sys(struct stats_sys *sys);
+#else /* LWIP_STATS_DISPLAY */
+#define stats_display()
+#define stats_display_proto(proto, name)
+#define stats_display_igmp(igmp, name)
+#define stats_display_mem(mem, name)
+#define stats_display_memp(mem, index)
+#define stats_display_sys(sys)
+#endif /* LWIP_STATS_DISPLAY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_STATS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sys.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sys.h
new file mode 100644
index 0000000..eefa8f3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/sys.h
@@ -0,0 +1,578 @@
+/**
+ * @file
+ * OS abstraction layer
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ */
+
+#ifndef LWIP_HDR_SYS_H
+#define LWIP_HDR_SYS_H
+
+#include "lwip/opt.h"
+#if defined (__arm__) || defined (__aarch64__)
+#include "xpseudo_asm.h"
+#include "xil_exception.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+ definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mutex_t;
+typedef u8_t sys_mbox_t;
+typedef u32_t sys_prot_t;
+
+#define sys_sem_new(s, c) ERR_OK
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_arch_sem_wait(s,t)
+#define sys_sem_free(s)
+#define sys_sem_valid(s) 0
+#define sys_sem_valid_val(s) 0
+#define sys_sem_set_invalid(s)
+#define sys_sem_set_invalid_val(s)
+#define sys_mutex_new(mu) ERR_OK
+#define sys_mutex_lock(mu)
+#define sys_mutex_unlock(mu)
+#define sys_mutex_free(mu)
+#define sys_mutex_valid(mu) 0
+#define sys_mutex_set_invalid(mu)
+#define sys_mbox_new(m, s) ERR_OK
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_tryfetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_trypost(m,d)
+#define sys_mbox_free(m)
+#define sys_mbox_valid(m)
+#define sys_mbox_valid_val(m)
+#define sys_mbox_set_invalid(m)
+#define sys_mbox_set_invalid_val(m)
+
+#define sys_thread_new(n,t,a,s,p)
+
+#define sys_msleep(t)
+
+#else /* NO_SYS */
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffffUL
+
+/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate.
+ * For now we use the same magic value, but we allow this to change in future.
+ */
+#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT
+
+#include "lwip/err.h"
+#include "arch/sys_arch.h"
+
+/** Function prototype for thread functions */
+typedef void (*lwip_thread_fn)(void *arg);
+
+/* Function prototypes for functions to be implemented by platform ports
+ (in sys_arch.c) */
+
+/* Mutex functions: */
+
+/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores
+ should be used instead */
+#ifndef LWIP_COMPAT_MUTEX
+#define LWIP_COMPAT_MUTEX 0
+#endif
+
+#if LWIP_COMPAT_MUTEX
+/* for old ports that don't have mutexes: define them to binary semaphores */
+#define sys_mutex_t sys_sem_t
+#define sys_mutex_new(mutex) sys_sem_new(mutex, 1)
+#define sys_mutex_lock(mutex) sys_sem_wait(mutex)
+#define sys_mutex_unlock(mutex) sys_sem_signal(mutex)
+#define sys_mutex_free(mutex) sys_sem_free(mutex)
+#define sys_mutex_valid(mutex) sys_sem_valid(mutex)
+#define sys_mutex_set_invalid(mutex) sys_sem_set_invalid(mutex)
+
+#else /* LWIP_COMPAT_MUTEX */
+
+/**
+ * @ingroup sys_mutex
+ * Create a new mutex.
+ * Note that mutexes are expected to not be taken recursively by the lwIP code,
+ * so both implementation types (recursive or non-recursive) should work.
+ * The mutex is allocated to the memory that 'mutex'
+ * points to (which can be both a pointer or the actual OS structure).
+ * If the mutex has been created, ERR_OK should be returned. Returning any
+ * other error will provide a hint what went wrong, but except for assertions,
+ * no real error handling is implemented.
+ *
+ * @param mutex pointer to the mutex to create
+ * @return ERR_OK if successful, another err_t otherwise
+ */
+err_t sys_mutex_new(sys_mutex_t *mutex);
+/**
+ * @ingroup sys_mutex
+ * Blocks the thread until the mutex can be grabbed.
+ * @param mutex the mutex to lock
+ */
+void sys_mutex_lock(sys_mutex_t *mutex);
+/**
+ * @ingroup sys_mutex
+ * Releases the mutex previously locked through 'sys_mutex_lock()'.
+ * @param mutex the mutex to unlock
+ */
+void sys_mutex_unlock(sys_mutex_t *mutex);
+/**
+ * @ingroup sys_mutex
+ * Deallocates a mutex.
+ * @param mutex the mutex to delete
+ */
+void sys_mutex_free(sys_mutex_t *mutex);
+#ifndef sys_mutex_valid
+/**
+ * @ingroup sys_mutex
+ * Returns 1 if the mutes is valid, 0 if it is not valid.
+ * When using pointers, a simple way is to check the pointer for != NULL.
+ * When directly using OS structures, implementing this may be more complex.
+ * This may also be a define, in which case the function is not prototyped.
+ */
+int sys_mutex_valid(sys_mutex_t *mutex);
+#endif
+#ifndef sys_mutex_set_invalid
+/**
+ * @ingroup sys_mutex
+ * Invalidate a mutex so that sys_mutex_valid() returns 0.
+ * ATTENTION: This does NOT mean that the mutex shall be deallocated:
+ * sys_mutex_free() is always called before calling this function!
+ * This may also be a define, in which case the function is not prototyped.
+ */
+void sys_mutex_set_invalid(sys_mutex_t *mutex);
+#endif
+#endif /* LWIP_COMPAT_MUTEX */
+
+/* Semaphore functions: */
+
+/**
+ * @ingroup sys_sem
+ * Create a new semaphore
+ * Creates a new semaphore. The semaphore is allocated to the memory that 'sem'
+ * points to (which can be both a pointer or the actual OS structure).
+ * The "count" argument specifies the initial state of the semaphore (which is
+ * either 0 or 1).
+ * If the semaphore has been created, ERR_OK should be returned. Returning any
+ * other error will provide a hint what went wrong, but except for assertions,
+ * no real error handling is implemented.
+ *
+ * @param sem pointer to the semaphore to create
+ * @param count initial count of the semaphore
+ * @return ERR_OK if successful, another err_t otherwise
+ */
+err_t sys_sem_new(sys_sem_t *sem, u8_t count);
+/**
+ * @ingroup sys_sem
+ * Signals a semaphore
+ * @param sem the semaphore to signal
+ */
+void sys_sem_signal(sys_sem_t *sem);
+/**
+ * @ingroup sys_sem
+ * Blocks the thread while waiting for the semaphore to be signaled. If the
+ * "timeout" argument is non-zero, the thread should only be blocked for the
+ * specified time (measured in milliseconds). If the "timeout" argument is zero,
+ * the thread should be blocked until the semaphore is signalled.
+ *
+ * The return value is SYS_ARCH_TIMEOUT if the semaphore wasn't signaled within
+ * the specified time or any other value if it was signaled (with or without
+ * waiting).
+ * Notice that lwIP implements a function with a similar name,
+ * sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+ *
+ * @param sem the semaphore to wait for
+ * @param timeout timeout in milliseconds to wait (0 = wait forever)
+ * @return SYS_ARCH_TIMEOUT on timeout, any other value on success
+ */
+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout);
+/**
+ * @ingroup sys_sem
+ * Deallocates a semaphore.
+ * @param sem semaphore to delete
+ */
+void sys_sem_free(sys_sem_t *sem);
+/** Wait for a semaphore - forever/no timeout */
+#define sys_sem_wait(sem) sys_arch_sem_wait(sem, 0)
+#ifndef sys_sem_valid
+/**
+ * @ingroup sys_sem
+ * Returns 1 if the semaphore is valid, 0 if it is not valid.
+ * When using pointers, a simple way is to check the pointer for != NULL.
+ * When directly using OS structures, implementing this may be more complex.
+ * This may also be a define, in which case the function is not prototyped.
+ */
+int sys_sem_valid(sys_sem_t *sem);
+#endif
+#ifndef sys_sem_set_invalid
+/**
+ * @ingroup sys_sem
+ * Invalidate a semaphore so that sys_sem_valid() returns 0.
+ * ATTENTION: This does NOT mean that the semaphore shall be deallocated:
+ * sys_sem_free() is always called before calling this function!
+ * This may also be a define, in which case the function is not prototyped.
+ */
+void sys_sem_set_invalid(sys_sem_t *sem);
+#endif
+#ifndef sys_sem_valid_val
+/**
+ * Same as sys_sem_valid() but taking a value, not a pointer
+ */
+#define sys_sem_valid_val(sem) sys_sem_valid(&(sem))
+#endif
+#ifndef sys_sem_set_invalid_val
+/**
+ * Same as sys_sem_set_invalid() but taking a value, not a pointer
+ */
+#define sys_sem_set_invalid_val(sem) sys_sem_set_invalid(&(sem))
+#endif
+
+#ifndef sys_msleep
+/**
+ * @ingroup sys_misc
+ * Sleep for specified number of ms
+ */
+void sys_msleep(u32_t ms); /* only has a (close to) 1 ms resolution. */
+#endif
+
+/* Mailbox functions. */
+
+/**
+ * @ingroup sys_mbox
+ * Creates an empty mailbox for maximum "size" elements. Elements stored
+ * in mailboxes are pointers. You have to define macros "_MBOX_SIZE"
+ * in your lwipopts.h, or ignore this parameter in your implementation
+ * and use a default size.
+ * If the mailbox has been created, ERR_OK should be returned. Returning any
+ * other error will provide a hint what went wrong, but except for assertions,
+ * no real error handling is implemented.
+ *
+ * @param mbox pointer to the mbox to create
+ * @param size (minimum) number of messages in this mbox
+ * @return ERR_OK if successful, another err_t otherwise
+ */
+err_t sys_mbox_new(sys_mbox_t *mbox, int size);
+/**
+ * @ingroup sys_mbox
+ * Post a message to an mbox - may not fail
+ * -> blocks if full, only to be used from tasks NOT from ISR!
+ *
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL)
+ */
+void sys_mbox_post(sys_mbox_t *mbox, void *msg);
+/**
+ * @ingroup sys_mbox
+ * Try to post a message to an mbox - may fail if full.
+ * Can be used from ISR (if the sys arch layer allows this).
+ * Returns ERR_MEM if it is full, else, ERR_OK if the "msg" is posted.
+ *
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL)
+ */
+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg);
+/**
+ * @ingroup sys_mbox
+ * Try to post a message to an mbox - may fail if full.
+ * To be be used from ISR.
+ * Returns ERR_MEM if it is full, else, ERR_OK if the "msg" is posted.
+ *
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL)
+ */
+err_t sys_mbox_trypost_fromisr(sys_mbox_t *mbox, void *msg);
+/**
+ * @ingroup sys_mbox
+ * Blocks the thread until a message arrives in the mailbox, but does
+ * not block the thread longer than "timeout" milliseconds (similar to
+ * the sys_arch_sem_wait() function). If "timeout" is 0, the thread should
+ * be blocked until a message arrives. The "msg" argument is a result
+ * parameter that is set by the function (i.e., by doing "*msg =
+ * ptr"). The "msg" parameter maybe NULL to indicate that the message
+ * should be dropped.
+ * The return values are the same as for the sys_arch_sem_wait() function:
+ * SYS_ARCH_TIMEOUT if there was a timeout, any other value if a messages
+ * is received.
+ *
+ * Note that a function with a similar name, sys_mbox_fetch(), is
+ * implemented by lwIP.
+ *
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @param timeout maximum time (in milliseconds) to wait for a message (0 = wait forever)
+ * @return SYS_ARCH_TIMEOUT on timeout, any other value if a message has been received
+ */
+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout);
+/* Allow port to override with a macro, e.g. special timeout for sys_arch_mbox_fetch() */
+#ifndef sys_arch_mbox_tryfetch
+/**
+ * @ingroup sys_mbox
+ * This is similar to sys_arch_mbox_fetch, however if a message is not
+ * present in the mailbox, it immediately returns with the code
+ * SYS_MBOX_EMPTY. On success 0 is returned.
+ * To allow for efficient implementations, this can be defined as a
+ * function-like macro in sys_arch.h instead of a normal function. For
+ * example, a naive implementation could be:
+ * \#define sys_arch_mbox_tryfetch(mbox,msg) sys_arch_mbox_fetch(mbox,msg,1)
+ * although this would introduce unnecessary delays.
+ *
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @return 0 (milliseconds) if a message has been received
+ * or SYS_MBOX_EMPTY if the mailbox is empty
+ */
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg);
+#endif
+/**
+ * For now, we map straight to sys_arch implementation.
+ */
+#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg)
+/**
+ * @ingroup sys_mbox
+ * Deallocates a mailbox. If there are messages still present in the
+ * mailbox when the mailbox is deallocated, it is an indication of a
+ * programming error in lwIP and the developer should be notified.
+ *
+ * @param mbox mbox to delete
+ */
+void sys_mbox_free(sys_mbox_t *mbox);
+#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0)
+#ifndef sys_mbox_valid
+/**
+ * @ingroup sys_mbox
+ * Returns 1 if the mailbox is valid, 0 if it is not valid.
+ * When using pointers, a simple way is to check the pointer for != NULL.
+ * When directly using OS structures, implementing this may be more complex.
+ * This may also be a define, in which case the function is not prototyped.
+ */
+int sys_mbox_valid(sys_mbox_t *mbox);
+#endif
+#ifndef sys_mbox_set_invalid
+/**
+ * @ingroup sys_mbox
+ * Invalidate a mailbox so that sys_mbox_valid() returns 0.
+ * ATTENTION: This does NOT mean that the mailbox shall be deallocated:
+ * sys_mbox_free() is always called before calling this function!
+ * This may also be a define, in which case the function is not prototyped.
+ */
+void sys_mbox_set_invalid(sys_mbox_t *mbox);
+#endif
+#ifndef sys_mbox_valid_val
+/**
+ * Same as sys_mbox_valid() but taking a value, not a pointer
+ */
+#define sys_mbox_valid_val(mbox) sys_mbox_valid(&(mbox))
+#endif
+#ifndef sys_mbox_set_invalid_val
+/**
+ * Same as sys_mbox_set_invalid() but taking a value, not a pointer
+ */
+#define sys_mbox_set_invalid_val(mbox) sys_mbox_set_invalid(&(mbox))
+#endif
+
+
+/**
+ * @ingroup sys_misc
+ * The only thread function:
+ * Starts a new thread named "name" with priority "prio" that will begin its
+ * execution in the function "thread()". The "arg" argument will be passed as an
+ * argument to the thread() function. The stack size to used for this thread is
+ * the "stacksize" parameter. The id of the new thread is returned. Both the id
+ * and the priority are system dependent.
+ * ATTENTION: although this function returns a value, it MUST NOT FAIL (ports have to assert this!)
+ *
+ * @param name human-readable name for the thread (used for debugging purposes)
+ * @param thread thread-function
+ * @param arg parameter passed to 'thread'
+ * @param stacksize stack size in bytes for the new thread (may be ignored by ports)
+ * @param prio priority of the new thread (may be ignored by ports) */
+sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio);
+
+#endif /* NO_SYS */
+
+/**
+ * @ingroup sys_misc
+ * sys_init() must be called before anything else.
+ * Initialize the sys_arch layer.
+ */
+void sys_init(void);
+
+#ifndef sys_jiffies
+/**
+ * Ticks/jiffies since power up.
+ */
+u32_t sys_jiffies(void);
+#endif
+
+/**
+ * @ingroup sys_time
+ * Returns the current time in milliseconds,
+ * may be the same as sys_jiffies or at least based on it.
+ * Don't care for wraparound, this is only used for time diffs.
+ * Not implementing this function means you cannot use some modules (e.g. TCP
+ * timestamps, internal timeouts for NO_SYS==1).
+ */
+u32_t sys_now(void);
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+ In some implementations they can provide a more light-weight protection
+ mechanism than using semaphores. Otherwise semaphores can be used for
+ implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/**
+ * @ingroup sys_prot
+ * SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/**
+ * @ingroup sys_prot
+ * SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#ifdef __MICROBLAZE__
+#define SYS_ARCH_PROTECT(lev) lev = mfmsr(); \
+ mtmsr(lev & ~0x2)
+#endif
+
+#if defined (__arm__) || defined (__aarch64__)
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+#endif
+/**
+ * @ingroup sys_prot
+ * SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex. This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#ifdef __MICROBLAZE__
+#define SYS_ARCH_UNPROTECT(lev) mtmsr(lev)
+#endif
+
+#if defined (__arm__) || defined (__aarch64__)
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+#endif
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+/*
+ * Macros to set/get and increase/decrease variables in a thread-safe way.
+ * Use these for accessing variable that are used from more than one thread.
+ */
+
+#ifndef SYS_ARCH_INC
+#define SYS_ARCH_INC(var, val) do { \
+ SYS_ARCH_DECL_PROTECT(old_level); \
+ SYS_ARCH_PROTECT(old_level); \
+ var += val; \
+ SYS_ARCH_UNPROTECT(old_level); \
+ } while(0)
+#endif /* SYS_ARCH_INC */
+
+#ifndef SYS_ARCH_DEC
+#define SYS_ARCH_DEC(var, val) do { \
+ SYS_ARCH_DECL_PROTECT(old_level); \
+ SYS_ARCH_PROTECT(old_level); \
+ var -= val; \
+ SYS_ARCH_UNPROTECT(old_level); \
+ } while(0)
+#endif /* SYS_ARCH_DEC */
+
+#ifndef SYS_ARCH_GET
+#define SYS_ARCH_GET(var, ret) do { \
+ SYS_ARCH_DECL_PROTECT(old_level); \
+ SYS_ARCH_PROTECT(old_level); \
+ ret = var; \
+ SYS_ARCH_UNPROTECT(old_level); \
+ } while(0)
+#endif /* SYS_ARCH_GET */
+
+#ifndef SYS_ARCH_SET
+#define SYS_ARCH_SET(var, val) do { \
+ SYS_ARCH_DECL_PROTECT(old_level); \
+ SYS_ARCH_PROTECT(old_level); \
+ var = val; \
+ SYS_ARCH_UNPROTECT(old_level); \
+ } while(0)
+#endif /* SYS_ARCH_SET */
+
+#ifndef SYS_ARCH_LOCKED
+#define SYS_ARCH_LOCKED(code) do { \
+ SYS_ARCH_DECL_PROTECT(old_level); \
+ SYS_ARCH_PROTECT(old_level); \
+ code; \
+ SYS_ARCH_UNPROTECT(old_level); \
+ } while(0)
+#endif /* SYS_ARCH_LOCKED */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_SYS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcp.h
new file mode 100644
index 0000000..daf7599
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcp.h
@@ -0,0 +1,500 @@
+/**
+ * @file
+ * TCP API (to be used from TCPIP thread)\n
+ * See also @ref tcp_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_TCP_H
+#define LWIP_HDR_TCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcpbase.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tcp_pcb;
+struct tcp_pcb_listen;
+
+/** Function prototype for tcp accept callback functions. Called when a new
+ * connection can be accepted on a listening pcb.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param newpcb The new connection pcb
+ * @param err An error code if there has been an error accepting.
+ * Only return ERR_ABRT if you have called tcp_abort from within the
+ * callback function!
+ */
+typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+/** Function prototype for tcp receive callback functions. Called when data has
+ * been received.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which received data
+ * @param p The received data (or NULL when the connection has been closed!)
+ * @param err An error code if there has been an error receiving
+ * Only return ERR_ABRT if you have called tcp_abort from within the
+ * callback function!
+ */
+typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb,
+ struct pbuf *p, err_t err);
+
+/** Function prototype for tcp sent callback functions. Called when sent data has
+ * been acknowledged by the remote side. Use it to free corresponding resources.
+ * This also means that the pcb has now space available to send new data.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb for which data has been acknowledged
+ * @param len The amount of bytes acknowledged
+ * @return ERR_OK: try to send some data by calling tcp_output
+ * Only return ERR_ABRT if you have called tcp_abort from within the
+ * callback function!
+ */
+typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb,
+ u16_t len);
+
+/** Function prototype for tcp poll callback functions. Called periodically as
+ * specified by @see tcp_poll.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb tcp pcb
+ * @return ERR_OK: try to send some data by calling tcp_output
+ * Only return ERR_ABRT if you have called tcp_abort from within the
+ * callback function!
+ */
+typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb);
+
+/** Function prototype for tcp error callback functions. Called when the pcb
+ * receives a RST or is unexpectedly closed for any other reason.
+ *
+ * @note The corresponding pcb is already freed when this callback is called!
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param err Error code to indicate why the pcb has been closed
+ * ERR_ABRT: aborted through tcp_abort or by a TCP timer
+ * ERR_RST: the connection was reset by the remote host
+ */
+typedef void (*tcp_err_fn)(void *arg, err_t err);
+
+/** Function prototype for tcp connected callback functions. Called when a pcb
+ * is connected to the remote side after initiating a connection attempt by
+ * calling tcp_connect().
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which is connected
+ * @param err An unused error code, always ERR_OK currently ;-) @todo!
+ * Only return ERR_ABRT if you have called tcp_abort from within the
+ * callback function!
+ *
+ * @note When a connection attempt fails, the error callback is currently called!
+ */
+typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err);
+
+#if LWIP_WND_SCALE
+#define RCV_WND_SCALE(pcb, wnd) (((wnd) >> (pcb)->rcv_scale))
+#define SND_WND_SCALE(pcb, wnd) (((wnd) << (pcb)->snd_scale))
+#define TCPWND16(x) ((u16_t)LWIP_MIN((x), 0xFFFF))
+#define TCP_WND_MAX(pcb) ((tcpwnd_size_t)(((pcb)->flags & TF_WND_SCALE) ? TCP_WND : TCPWND16(TCP_WND)))
+#else
+#define RCV_WND_SCALE(pcb, wnd) (wnd)
+#define SND_WND_SCALE(pcb, wnd) (wnd)
+#define TCPWND16(x) (x)
+#define TCP_WND_MAX(pcb) TCP_WND
+#endif
+/* Increments a tcpwnd_size_t and holds at max value rather than rollover */
+#define TCP_WND_INC(wnd, inc) do { \
+ if ((tcpwnd_size_t)(wnd + inc) >= wnd) { \
+ wnd = (tcpwnd_size_t)(wnd + inc); \
+ } else { \
+ wnd = (tcpwnd_size_t)-1; \
+ } \
+ } while(0)
+
+#if LWIP_TCP_SACK_OUT
+/** SACK ranges to include in ACK packets.
+ * SACK entry is invalid if left==right. */
+struct tcp_sack_range {
+ /** Left edge of the SACK: the first acknowledged sequence number. */
+ u32_t left;
+ /** Right edge of the SACK: the last acknowledged sequence number +1 (so first NOT acknowledged). */
+ u32_t right;
+};
+#endif /* LWIP_TCP_SACK_OUT */
+
+/** Function prototype for deallocation of arguments. Called *just before* the
+ * pcb is freed, so don't expect to be able to do anything with this pcb!
+ *
+ * @param id ext arg id (allocated via @ref tcp_ext_arg_alloc_id)
+ * @param data pointer to the data (set via @ref tcp_ext_arg_set before)
+ */
+typedef void (*tcp_extarg_callback_pcb_destroyed_fn)(u8_t id, void *data);
+
+/** Function prototype to transition arguments from a listening pcb to an accepted pcb
+ *
+ * @param id ext arg id (allocated via @ref tcp_ext_arg_alloc_id)
+ * @param lpcb the listening pcb accepting a connection
+ * @param cpcb the newly allocated connection pcb
+ * @return ERR_OK if OK, any error if connection should be dropped
+ */
+typedef err_t (*tcp_extarg_callback_passive_open_fn)(u8_t id, struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb);
+
+/** A table of callback functions that is invoked for ext arguments */
+struct tcp_ext_arg_callbacks {
+ /** @ref tcp_extarg_callback_pcb_destroyed_fn */
+ tcp_extarg_callback_pcb_destroyed_fn destroy;
+ /** @ref tcp_extarg_callback_passive_open_fn */
+ tcp_extarg_callback_passive_open_fn passive_open;
+};
+
+#define LWIP_TCP_PCB_NUM_EXT_ARG_ID_INVALID 0xFF
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+/* This is the structure for ext args in tcp pcbs (used as array) */
+struct tcp_pcb_ext_args {
+ const struct tcp_ext_arg_callbacks *callbacks;
+ void *data;
+};
+/* This is a helper define to prevent zero size arrays if disabled */
+#define TCP_PCB_EXTARGS struct tcp_pcb_ext_args ext_args[LWIP_TCP_PCB_NUM_EXT_ARGS];
+#else
+#define TCP_PCB_EXTARGS
+#endif
+
+typedef u16_t tcpflags_t;
+#define TCP_ALLFLAGS 0xffffU
+
+/**
+ * members common to struct tcp_pcb and struct tcp_listen_pcb
+ */
+#define TCP_PCB_COMMON(type) \
+ type *next; /* for the linked list */ \
+ void *callback_arg; \
+ TCP_PCB_EXTARGS \
+ enum tcp_state state; /* TCP state */ \
+ u8_t prio; \
+ /* ports are in host byte order */ \
+ u16_t local_port
+
+
+/** the TCP protocol control block for listening pcbs */
+struct tcp_pcb_listen {
+/** Common members of all PCB types */
+ IP_PCB;
+/** Protocol specific PCB members */
+ TCP_PCB_COMMON(struct tcp_pcb_listen);
+
+#if LWIP_CALLBACK_API
+ /* Function to call when a listener has been connected. */
+ tcp_accept_fn accept;
+#endif /* LWIP_CALLBACK_API */
+
+#if TCP_LISTEN_BACKLOG
+ u8_t backlog;
+ u8_t accepts_pending;
+#endif /* TCP_LISTEN_BACKLOG */
+};
+
+
+/** the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+ IP_PCB;
+/** protocol specific PCB members */
+ TCP_PCB_COMMON(struct tcp_pcb);
+
+ /* ports are in host byte order */
+ u16_t remote_port;
+
+ tcpflags_t flags;
+#define TF_ACK_DELAY 0x01U /* Delayed ACK. */
+#define TF_ACK_NOW 0x02U /* Immediate ACK. */
+#define TF_INFR 0x04U /* In fast recovery. */
+#define TF_CLOSEPEND 0x08U /* If this is set, tcp_close failed to enqueue the FIN (retried in tcp_tmr) */
+#define TF_RXCLOSED 0x10U /* rx closed by tcp_shutdown */
+#define TF_FIN 0x20U /* Connection was closed locally (FIN segment enqueued). */
+#define TF_NODELAY 0x40U /* Disable Nagle algorithm */
+#define TF_NAGLEMEMERR 0x80U /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */
+#if LWIP_WND_SCALE
+#define TF_WND_SCALE 0x0100U /* Window Scale option enabled */
+#endif
+#if TCP_LISTEN_BACKLOG
+#define TF_BACKLOGPEND 0x0200U /* If this is set, a connection pcb has increased the backlog on its listener */
+#endif
+#if LWIP_TCP_TIMESTAMPS
+#define TF_TIMESTAMP 0x0400U /* Timestamp option enabled */
+#endif
+#define TF_RTO 0x0800U /* RTO timer has fired, in-flight data moved to unsent and being retransmitted */
+#if LWIP_TCP_SACK_OUT
+#define TF_SACK 0x1000U /* Selective ACKs enabled */
+#endif
+
+ /* the rest of the fields are in host byte order
+ as we have to do some math with them */
+
+ /* Timers */
+ u8_t polltmr, pollinterval;
+ u8_t last_timer;
+ u32_t tmr;
+
+ /* receiver variables */
+ u32_t rcv_nxt; /* next seqno expected */
+ tcpwnd_size_t rcv_wnd; /* receiver window available */
+ tcpwnd_size_t rcv_ann_wnd; /* receiver window to announce */
+ u32_t rcv_ann_right_edge; /* announced right edge of window */
+
+#if LWIP_TCP_SACK_OUT
+ /* SACK ranges to include in ACK packets (entry is invalid if left==right) */
+ struct tcp_sack_range rcv_sacks[LWIP_TCP_MAX_SACK_NUM];
+#define LWIP_TCP_SACK_VALID(pcb, idx) ((pcb)->rcv_sacks[idx].left != (pcb)->rcv_sacks[idx].right)
+#endif /* LWIP_TCP_SACK_OUT */
+
+ /* Retransmission timer. */
+ s16_t rtime;
+
+ u16_t mss; /* maximum segment size */
+
+ /* RTT (round trip time) estimation variables */
+ u32_t rttest; /* RTT estimate in 500ms ticks */
+ u32_t rtseq; /* sequence number being timed */
+ s16_t sa, sv; /* @see "Congestion Avoidance and Control" by Van Jacobson and Karels */
+
+ s16_t rto; /* retransmission time-out (in ticks of TCP_SLOW_INTERVAL) */
+ u8_t nrtx; /* number of retransmissions */
+
+ /* fast retransmit/recovery */
+ u8_t dupacks;
+ u32_t lastack; /* Highest acknowledged seqno. */
+
+ /* congestion avoidance/control variables */
+ tcpwnd_size_t cwnd;
+ tcpwnd_size_t ssthresh;
+
+ /* first byte following last rto byte */
+ u32_t rto_end;
+
+ /* sender variables */
+ u32_t snd_nxt; /* next new seqno to be sent */
+ u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last
+ window update. */
+ u32_t snd_lbb; /* Sequence number of next byte to be buffered. */
+ tcpwnd_size_t snd_wnd; /* sender window */
+ tcpwnd_size_t snd_wnd_max; /* the maximum sender window announced by the remote host */
+
+ tcpwnd_size_t snd_buf; /* Available buffer space for sending (in bytes). */
+#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3)
+ u16_t snd_queuelen; /* Number of pbufs currently in the send buffer. */
+
+#if TCP_OVERSIZE
+ /* Extra bytes available at the end of the last pbuf in unsent. */
+ u16_t unsent_oversize;
+#endif /* TCP_OVERSIZE */
+
+ tcpwnd_size_t bytes_acked;
+
+ /* These are ordered by sequence number: */
+ struct tcp_seg *unsent; /* Unsent (queued) segments. */
+ struct tcp_seg *unacked; /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ
+ struct tcp_seg *ooseq; /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+ struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */
+
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+ struct tcp_pcb_listen* listener;
+#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
+
+#if LWIP_CALLBACK_API
+ /* Function to be called when more send buffer space is available. */
+ tcp_sent_fn sent;
+ /* Function to be called when (in-sequence) data has arrived. */
+ tcp_recv_fn recv;
+ /* Function to be called when a connection has been set up. */
+ tcp_connected_fn connected;
+ /* Function which is called periodically. */
+ tcp_poll_fn poll;
+ /* Function to be called whenever a fatal error occurs. */
+ tcp_err_fn errf;
+#endif /* LWIP_CALLBACK_API */
+
+#if LWIP_TCP_TIMESTAMPS
+ u32_t ts_lastacksent;
+ u32_t ts_recent;
+#endif /* LWIP_TCP_TIMESTAMPS */
+
+ /* idle time before KEEPALIVE is sent */
+ u32_t keep_idle;
+#if LWIP_TCP_KEEPALIVE
+ u32_t keep_intvl;
+ u32_t keep_cnt;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+ /* Persist timer counter */
+ u8_t persist_cnt;
+ /* Persist timer back-off */
+ u8_t persist_backoff;
+ /* Number of persist probes */
+ u8_t persist_probe;
+
+ /* KEEPALIVE counter */
+ u8_t keep_cnt_sent;
+
+#if LWIP_WND_SCALE
+ u8_t snd_scale;
+ u8_t rcv_scale;
+#endif
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+ LWIP_EVENT_ACCEPT,
+ LWIP_EVENT_SENT,
+ LWIP_EVENT_RECV,
+ LWIP_EVENT_CONNECTED,
+ LWIP_EVENT_POLL,
+ LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+ enum lwip_event,
+ struct pbuf *p,
+ u16_t size,
+ err_t err);
+
+#endif /* LWIP_EVENT_API */
+
+/* Application program's interface: */
+struct tcp_pcb * tcp_new (void);
+struct tcp_pcb * tcp_new_ip_type (u8_t type);
+
+void tcp_arg (struct tcp_pcb *pcb, void *arg);
+#if LWIP_CALLBACK_API
+void tcp_recv (struct tcp_pcb *pcb, tcp_recv_fn recv);
+void tcp_sent (struct tcp_pcb *pcb, tcp_sent_fn sent);
+void tcp_err (struct tcp_pcb *pcb, tcp_err_fn err);
+void tcp_accept (struct tcp_pcb *pcb, tcp_accept_fn accept);
+#endif /* LWIP_CALLBACK_API */
+void tcp_poll (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval);
+
+#define tcp_set_flags(pcb, set_flags) do { (pcb)->flags = (tcpflags_t)((pcb)->flags | (set_flags)); } while(0)
+#define tcp_clear_flags(pcb, clr_flags) do { (pcb)->flags = (tcpflags_t)((pcb)->flags & (tcpflags_t)(~(clr_flags) & TCP_ALLFLAGS)); } while(0)
+#define tcp_is_flag_set(pcb, flag) (((pcb)->flags & (flag)) != 0)
+
+#if LWIP_TCP_TIMESTAMPS
+#define tcp_mss(pcb) (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12) : (pcb)->mss)
+#else /* LWIP_TCP_TIMESTAMPS */
+/** @ingroup tcp_raw */
+#define tcp_mss(pcb) ((pcb)->mss)
+#endif /* LWIP_TCP_TIMESTAMPS */
+/** @ingroup tcp_raw */
+#define tcp_sndbuf(pcb) (TCPWND16((pcb)->snd_buf))
+/** @ingroup tcp_raw */
+#define tcp_sndqueuelen(pcb) ((pcb)->snd_queuelen)
+/** @ingroup tcp_raw */
+#define tcp_nagle_disable(pcb) tcp_set_flags(pcb, TF_NODELAY)
+/** @ingroup tcp_raw */
+#define tcp_nagle_enable(pcb) tcp_clear_flags(pcb, TF_NODELAY)
+/** @ingroup tcp_raw */
+#define tcp_nagle_disabled(pcb) tcp_is_flag_set(pcb, TF_NODELAY)
+
+#if TCP_LISTEN_BACKLOG
+#define tcp_backlog_set(pcb, new_backlog) do { \
+ LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", (pcb)->state == LISTEN); \
+ ((struct tcp_pcb_listen *)(pcb))->backlog = ((new_backlog) ? (new_backlog) : 1); } while(0)
+void tcp_backlog_delayed(struct tcp_pcb* pcb);
+void tcp_backlog_accepted(struct tcp_pcb* pcb);
+#else /* TCP_LISTEN_BACKLOG */
+#define tcp_backlog_set(pcb, new_backlog)
+#define tcp_backlog_delayed(pcb)
+#define tcp_backlog_accepted(pcb)
+#endif /* TCP_LISTEN_BACKLOG */
+#define tcp_accepted(pcb) do { LWIP_UNUSED_ARG(pcb); } while(0) /* compatibility define, not needed any more */
+
+void tcp_recved (struct tcp_pcb *pcb, u16_t len);
+err_t tcp_bind (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
+ u16_t port);
+void tcp_bind_netif(struct tcp_pcb *pcb, const struct netif *netif);
+err_t tcp_connect (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
+ u16_t port, tcp_connected_fn connected);
+
+struct tcp_pcb * tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err);
+struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog);
+/** @ingroup tcp_raw */
+#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG)
+
+void tcp_abort (struct tcp_pcb *pcb);
+err_t tcp_close (struct tcp_pcb *pcb);
+err_t tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx);
+
+err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+ u8_t apiflags);
+
+void tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+err_t tcp_output (struct tcp_pcb *pcb);
+
+err_t tcp_tcp_get_tcp_addrinfo(struct tcp_pcb *pcb, int local, ip_addr_t *addr, u16_t *port);
+
+#define tcp_dbg_get_tcp_state(pcb) ((pcb)->state)
+
+/* for compatibility with older implementation */
+#define tcp_new_ip6() tcp_new_ip_type(IPADDR_TYPE_V6)
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+u8_t tcp_ext_arg_alloc_id(void);
+void tcp_ext_arg_set_callbacks(struct tcp_pcb *pcb, uint8_t id, const struct tcp_ext_arg_callbacks * const callbacks);
+void tcp_ext_arg_set(struct tcp_pcb *pcb, uint8_t id, void *arg);
+void *tcp_ext_arg_get(const struct tcp_pcb *pcb, uint8_t id);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcpbase.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcpbase.h
new file mode 100644
index 0000000..0023074
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcpbase.h
@@ -0,0 +1,88 @@
+/**
+ * @file
+ * Base TCP API definitions shared by TCP and ALTCP\n
+ * See also @ref tcp_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_TCPBASE_H
+#define LWIP_HDR_TCPBASE_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if LWIP_WND_SCALE
+typedef u32_t tcpwnd_size_t;
+#else
+typedef u16_t tcpwnd_size_t;
+#endif
+
+enum tcp_state {
+ CLOSED = 0,
+ LISTEN = 1,
+ SYN_SENT = 2,
+ SYN_RCVD = 3,
+ ESTABLISHED = 4,
+ FIN_WAIT_1 = 5,
+ FIN_WAIT_2 = 6,
+ CLOSE_WAIT = 7,
+ CLOSING = 8,
+ LAST_ACK = 9,
+ TIME_WAIT = 10
+};
+/* ATTENTION: this depends on state number ordering! */
+#define TCP_STATE_IS_CLOSING(state) ((state) >= FIN_WAIT_1)
+
+/* Flags for "apiflags" parameter in tcp_write */
+#define TCP_WRITE_FLAG_COPY 0x01
+#define TCP_WRITE_FLAG_MORE 0x02
+
+#define TCP_PRIO_MIN 1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX 127
+
+const char* tcp_debug_state_str(enum tcp_state s);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCPBASE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcpip.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcpip.h
new file mode 100644
index 0000000..0b8880a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/tcpip.h
@@ -0,0 +1,113 @@
+/**
+ * @file
+ * Functions to sync with TCPIP thread
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_TCPIP_H
+#define LWIP_HDR_TCPIP_H
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/timeouts.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+extern sys_mutex_t lock_tcpip_core;
+#if !defined LOCK_TCPIP_CORE || defined __DOXYGEN__
+/** Lock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */
+#define LOCK_TCPIP_CORE() sys_mutex_lock(&lock_tcpip_core)
+/** Unlock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */
+#define UNLOCK_TCPIP_CORE() sys_mutex_unlock(&lock_tcpip_core)
+#endif /* LOCK_TCPIP_CORE */
+#else /* LWIP_TCPIP_CORE_LOCKING */
+#define LOCK_TCPIP_CORE()
+#define UNLOCK_TCPIP_CORE()
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+struct pbuf;
+struct netif;
+
+/** Function prototype for the init_done function passed to tcpip_init */
+typedef void (*tcpip_init_done_fn)(void *arg);
+/** Function prototype for functions passed to tcpip_callback() */
+typedef void (*tcpip_callback_fn)(void *ctx);
+
+/* Forward declarations */
+struct tcpip_callback_msg;
+
+void tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg);
+
+err_t tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn);
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+
+err_t tcpip_try_callback(tcpip_callback_fn function, void *ctx);
+err_t tcpip_callback(tcpip_callback_fn function, void *ctx);
+/** @ingroup lwip_os
+ * @deprecated use tcpip_try_callback() or tcpip_callback() instead
+ */
+#define tcpip_callback_with_block(function, ctx, block) ((block != 0)? tcpip_callback(function, ctx) : tcpip_try_callback(function, ctx))
+
+struct tcpip_callback_msg* tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx);
+void tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg);
+err_t tcpip_callbackmsg_trycallback(struct tcpip_callback_msg* msg);
+err_t tcpip_callbackmsg_trycallback_fromisr(struct tcpip_callback_msg* msg);
+
+/* free pbufs or heap memory from another context without blocking */
+err_t pbuf_free_callback(struct pbuf *p);
+err_t mem_free_callback(void *m);
+
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+err_t tcpip_untimeout(sys_timeout_handler h, void *arg);
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+
+#ifdef TCPIP_THREAD_TEST
+int tcpip_thread_poll_one(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* LWIP_HDR_TCPIP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/timeouts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/timeouts.h
new file mode 100644
index 0000000..b601f9e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/timeouts.h
@@ -0,0 +1,128 @@
+/**
+ * @file
+ * Timer implementations
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ * Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_TIMEOUTS_H
+#define LWIP_HDR_TIMEOUTS_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#if !NO_SYS
+#include "lwip/sys.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef LWIP_DEBUG_TIMERNAMES
+#ifdef LWIP_DEBUG
+#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG
+#else /* LWIP_DEBUG */
+#define LWIP_DEBUG_TIMERNAMES 0
+#endif /* LWIP_DEBUG*/
+#endif
+
+/** Returned by sys_timeouts_sleeptime() to indicate there is no timer, so we
+ * can sleep forever.
+ */
+#define SYS_TIMEOUTS_SLEEPTIME_INFINITE 0xFFFFFFFF
+
+/** Function prototype for a stack-internal timer function that has to be
+ * called at a defined interval */
+typedef void (* lwip_cyclic_timer_handler)(void);
+
+/** This struct contains information about a stack-internal timer function
+ that has to be called at a defined interval */
+struct lwip_cyclic_timer {
+ u32_t interval_ms;
+ lwip_cyclic_timer_handler handler;
+#if LWIP_DEBUG_TIMERNAMES
+ const char* handler_name;
+#endif /* LWIP_DEBUG_TIMERNAMES */
+};
+
+/** This array contains all stack-internal cyclic timers. To get the number of
+ * timers, use lwip_num_cyclic_timers */
+extern const struct lwip_cyclic_timer lwip_cyclic_timers[];
+/** Array size of lwip_cyclic_timers[] */
+extern const int lwip_num_cyclic_timers;
+
+#if LWIP_TIMERS
+
+/** Function prototype for a timeout callback function. Register such a function
+ * using sys_timeout().
+ *
+ * @param arg Additional argument to pass to the function - set up by sys_timeout()
+ */
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeo {
+ struct sys_timeo *next;
+ u32_t time;
+ sys_timeout_handler h;
+ void *arg;
+#if LWIP_DEBUG_TIMERNAMES
+ const char* handler_name;
+#endif /* LWIP_DEBUG_TIMERNAMES */
+};
+
+void sys_timeouts_init(void);
+
+#if LWIP_DEBUG_TIMERNAMES
+void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name);
+#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler)
+#else /* LWIP_DEBUG_TIMERNAMES */
+void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg);
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+void sys_untimeout(sys_timeout_handler handler, void *arg);
+void sys_restart_timeouts(void);
+void sys_check_timeouts(void);
+u32_t sys_timeouts_sleeptime(void);
+
+#if LWIP_TESTMODE
+struct sys_timeo** sys_timeouts_get_next_timeout(void);
+void lwip_cyclic_timer(void *arg);
+#endif
+
+#endif /* LWIP_TIMERS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_TIMEOUTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/udp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/udp.h
new file mode 100644
index 0000000..9a4a2e6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwip/udp.h
@@ -0,0 +1,209 @@
+/**
+ * @file
+ * UDP API (to be used from TCPIP thread)\n
+ * See also @ref udp_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_UDP_H
+#define LWIP_HDR_UDP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE 0x02U
+#define UDP_FLAGS_CONNECTED 0x04U
+#define UDP_FLAGS_MULTICAST_LOOP 0x08U
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+#define UDP_FLAGS_BLOCK_TX_TILL_COMPLETE 0x10U
+#endif
+
+struct udp_pcb;
+
+/** Function prototype for udp pcb receive callback functions
+ * addr and port are in same byte order as in the pcb
+ * The callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ *
+ * ATTENTION: Be aware that 'addr' might point into the pbuf 'p' so freeing this pbuf
+ * can make 'addr' invalid, too.
+ *
+ * @param arg user supplied argument (udp_pcb.recv_arg)
+ * @param pcb the udp_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @param port the remote port from which the packet was received
+ */
+typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *addr, u16_t port);
+
+/** the UDP protocol control block */
+struct udp_pcb {
+/** Common members of all PCB types */
+ IP_PCB;
+
+/* Protocol specific PCB members */
+
+ struct udp_pcb *next;
+
+ u8_t flags;
+ /** ports are in host byte order */
+ u16_t local_port, remote_port;
+
+#if LWIP_MULTICAST_TX_OPTIONS
+#if LWIP_IPV4
+ /** outgoing network interface for multicast packets, by IPv4 address (if not 'any') */
+ ip4_addr_t mcast_ip4;
+#endif /* LWIP_IPV4 */
+ /** outgoing network interface for multicast packets, by interface index (if nonzero) */
+ u8_t mcast_ifindex;
+ /** TTL for outgoing multicast packets */
+ u8_t mcast_ttl;
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if LWIP_UDPLITE
+ /** used for UDP_LITE only */
+ u16_t chksum_len_rx, chksum_len_tx;
+#endif /* LWIP_UDPLITE */
+
+ /** receive callback function */
+ udp_recv_fn recv;
+ /** user-supplied argument for the recv callback */
+ void *recv_arg;
+};
+/* udp_pcbs export for external reference (e.g. SNMP agent) */
+extern struct udp_pcb *udp_pcbs;
+
+/* The following functions is the application layer interface to the
+ UDP code. */
+struct udp_pcb * udp_new (void);
+struct udp_pcb * udp_new_ip_type(u8_t type);
+void udp_remove (struct udp_pcb *pcb);
+err_t udp_bind (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
+ u16_t port);
+void udp_bind_netif (struct udp_pcb *pcb, const struct netif* netif);
+err_t udp_connect (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
+ u16_t port);
+void udp_disconnect (struct udp_pcb *pcb);
+void udp_recv (struct udp_pcb *pcb, udp_recv_fn recv,
+ void *recv_arg);
+err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *dst_ip, u16_t dst_port,
+ struct netif *netif);
+err_t udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *dst_ip, u16_t dst_port,
+ struct netif *netif, const ip_addr_t *src_ip);
+err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *dst_ip, u16_t dst_port);
+err_t udp_send (struct udp_pcb *pcb, struct pbuf *p);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE && NO_SYS
+err_t udp_send_blocking(struct udp_pcb *pcb, struct pbuf *p);
+err_t udp_sendto_blocking(struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *dst_ip, u16_t dst_port);
+#endif
+
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+err_t udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *dst_ip, u16_t dst_port,
+ struct netif *netif, u8_t have_chksum,
+ u16_t chksum);
+err_t udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *dst_ip, u16_t dst_port,
+ u8_t have_chksum, u16_t chksum);
+err_t udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p,
+ u8_t have_chksum, u16_t chksum);
+err_t udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p,
+ const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif,
+ u8_t have_chksum, u16_t chksum, const ip_addr_t *src_ip);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE && NO_SYS
+err_t udp_send_chksum_blocking(struct udp_pcb *pcb, struct pbuf *p,
+ u8_t have_chksum, u16_t chksum);
+err_t udp_sendto_chksum_blocking(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip,
+ u16_t dst_port, u8_t have_chksum, u16_t chksum);
+#endif
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+
+#define udp_flags(pcb) ((pcb)->flags)
+#define udp_setflags(pcb, f) ((pcb)->flags = (f))
+
+#define udp_set_flags(pcb, set_flags) do { (pcb)->flags = (u8_t)((pcb)->flags | (set_flags)); } while(0)
+#define udp_clear_flags(pcb, clr_flags) do { (pcb)->flags = (u8_t)((pcb)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define udp_is_flag_set(pcb, flag) (((pcb)->flags & (flag)) != 0)
+
+/* The following functions are the lower layer interface to UDP. */
+void udp_input (struct pbuf *p, struct netif *inp);
+
+void udp_init (void);
+
+/* for compatibility with older implementation */
+#define udp_new_ip6() udp_new_ip_type(IPADDR_TYPE_V6)
+
+#if LWIP_MULTICAST_TX_OPTIONS
+#if LWIP_IPV4
+#define udp_set_multicast_netif_addr(pcb, ip4addr) ip4_addr_copy((pcb)->mcast_ip4, *(ip4addr))
+#define udp_get_multicast_netif_addr(pcb) (&(pcb)->mcast_ip4)
+#endif /* LWIP_IPV4 */
+#define udp_set_multicast_netif_index(pcb, idx) ((pcb)->mcast_ifindex = (idx))
+#define udp_get_multicast_netif_index(pcb) ((pcb)->mcast_ifindex)
+#define udp_set_multicast_ttl(pcb, value) ((pcb)->mcast_ttl = (value))
+#define udp_get_multicast_ttl(pcb) ((pcb)->mcast_ttl)
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+
+void udp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_UDP */
+
+#endif /* LWIP_HDR_UDP_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwipopts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwipopts.h
new file mode 100644
index 0000000..560f7bb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/lwipopts.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef __LWIPOPTS_H_
+#define __LWIPOPTS_H_
+
+#ifndef PROCESSOR_LITTLE_ENDIAN
+#define PROCESSOR_LITTLE_ENDIAN
+#endif
+
+#define SYS_LIGHTWEIGHT_PROT 1
+
+#define NO_SYS 1
+#define LWIP_SOCKET 0
+#define LWIP_COMPAT_SOCKETS 0
+#define LWIP_NETCONN 0
+
+#define NO_SYS_NO_TIMERS 1
+
+#define LWIP_TCP_KEEPALIVE 0
+
+#define MEM_ALIGNMENT 64
+#define MEM_SIZE 131072
+#define MEMP_NUM_PBUF 16
+#define MEMP_NUM_UDP_PCB 4
+#define MEMP_NUM_TCP_PCB 32
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+#define MEMP_NUM_TCP_SEG 256
+#define MEMP_NUM_SYS_TIMEOUT 8
+#define MEMP_NUM_NETBUF 8
+#define MEMP_NUM_NETCONN 16
+#define MEMP_NUM_TCPIP_MSG_API 16
+#define MEMP_NUM_TCPIP_MSG_INPKT 64
+
+#define MEMP_NUM_SYS_TIMEOUT 8
+#define PBUF_POOL_SIZE 2048
+#define PBUF_POOL_BUFSIZE 1700
+#define PBUF_LINK_HLEN 16
+
+#define ARP_TABLE_SIZE 10
+#define ARP_QUEUEING 1
+
+#define ICMP_TTL 255
+
+#define IP_OPTIONS 0
+#define IP_FORWARD 0
+#define IP_REASSEMBLY 1
+#define IP_FRAG 1
+#define IP_REASS_MAX_PBUFS 128
+#define IP_FRAG_MAX_MTU 1500
+#define IP_DEFAULT_TTL 255
+#define LWIP_CHKSUM_ALGORITHM 3
+
+#define LWIP_UDP 1
+#define UDP_TTL 255
+#define LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE 0
+
+#define LWIP_TCP 1
+#define TCP_MSS 1460
+#define TCP_SND_BUF 8192
+#define TCP_WND 2048
+#define TCP_TTL 255
+#define TCP_MAXRTX 12
+#define TCP_SYNMAXRTX 4
+#define TCP_QUEUE_OOSEQ 1
+#define TCP_SND_QUEUELEN 16 * TCP_SND_BUF/TCP_MSS
+#define CHECKSUM_GEN_TCP 0
+#define CHECKSUM_GEN_UDP 0
+#define CHECKSUM_GEN_IP 0
+#define CHECKSUM_CHECK_TCP 0
+#define CHECKSUM_CHECK_UDP 0
+#define CHECKSUM_CHECK_IP 0
+#define LWIP_FULL_CSUM_OFFLOAD_RX 1
+#define LWIP_FULL_CSUM_OFFLOAD_TX 1
+
+#define MEMP_SEPARATE_POOLS 1
+#define MEMP_NUM_FRAG_PBUF 256
+#define IP_OPTIONS_ALLOWED 0
+#define TCP_OVERSIZE TCP_MSS
+
+#define LWIP_DHCP 1
+#define DHCP_DOES_ARP_CHECK 1
+
+#define CONFIG_LINKSPEED_AUTODETECT 1
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
new file mode 100644
index 0000000..807dda3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char byte;
+typedef short half;
+typedef int word;
+typedef unsigned char ubyte;
+typedef unsigned short uhalf;
+typedef unsigned int uword;
+typedef ubyte boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/bridgeif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/bridgeif.h
new file mode 100644
index 0000000..f4f8cf1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/bridgeif.h
@@ -0,0 +1,127 @@
+/**
+ * @file
+ * lwIP netif implementing an IEEE 802.1D MAC Bridge
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_NETIF_BRIDGEIF_H
+#define LWIP_HDR_NETIF_BRIDGEIF_H
+
+#include "netif/bridgeif_opts.h"
+
+#include "lwip/err.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netif;
+
+#if (BRIDGEIF_MAX_PORTS < 0) || (BRIDGEIF_MAX_PORTS >= 64)
+#error BRIDGEIF_MAX_PORTS must be [1..63]
+#elif BRIDGEIF_MAX_PORTS < 8
+typedef u8_t bridgeif_portmask_t;
+#elif BRIDGEIF_MAX_PORTS < 16
+typedef u16_t bridgeif_portmask_t;
+#elif BRIDGEIF_MAX_PORTS < 32
+typedef u32_t bridgeif_portmask_t;
+#elif BRIDGEIF_MAX_PORTS < 64
+typedef u64_t bridgeif_portmask_t;
+#endif
+
+#define BR_FLOOD ((bridgeif_portmask_t)-1)
+
+/** @ingroup bridgeif
+ * Initialisation data for @ref bridgeif_init.
+ * An instance of this type must be passed as parameter 'state' to @ref netif_add
+ * when the bridge is added.
+ */
+typedef struct bridgeif_initdata_s {
+ /** MAC address of the bridge (cannot use the netif's addresses) */
+ struct eth_addr ethaddr;
+ /** Maximum number of ports in the bridge (ports are stored in an array, this
+ influences memory allocated for netif->state of the bridge netif). */
+ u8_t max_ports;
+ /** Maximum number of dynamic/learning entries in the bridge's forwarding database.
+ In the default implementation, this controls memory consumption only. */
+ u16_t max_fdb_dynamic_entries;
+ /** Maximum number of static forwarding entries. Influences memory consumption! */
+ u16_t max_fdb_static_entries;
+} bridgeif_initdata_t;
+
+/** @ingroup bridgeif
+ * Use this for constant initialization of a bridgeif_initdat_t
+ * (ethaddr must be passed as ETH_ADDR())
+ */
+#define BRIDGEIF_INITDATA1(max_ports, max_fdb_dynamic_entries, max_fdb_static_entries, ethaddr) {ethaddr, max_ports, max_fdb_dynamic_entries, max_fdb_static_entries}
+/** @ingroup bridgeif
+ * Use this for constant initialization of a bridgeif_initdat_t
+ * (each byte of ethaddr must be passed)
+ */
+#define BRIDGEIF_INITDATA2(max_ports, max_fdb_dynamic_entries, max_fdb_static_entries, e0, e1, e2, e3, e4, e5) {{e0, e1, e2, e3, e4, e5}, max_ports, max_fdb_dynamic_entries, max_fdb_static_entries}
+
+err_t bridgeif_init(struct netif *netif);
+err_t bridgeif_add_port(struct netif *bridgeif, struct netif *portif);
+err_t bridgeif_fdb_add(struct netif *bridgeif, const struct eth_addr *addr, bridgeif_portmask_t ports);
+err_t bridgeif_fdb_remove(struct netif *bridgeif, const struct eth_addr *addr);
+
+/* FDB interface, can be replaced by own implementation */
+void bridgeif_fdb_update_src(void *fdb_ptr, struct eth_addr *src_addr, u8_t port_idx);
+bridgeif_portmask_t bridgeif_fdb_get_dst_ports(void *fdb_ptr, struct eth_addr *dst_addr);
+void* bridgeif_fdb_init(u16_t max_fdb_entries);
+
+#if BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT
+#ifndef BRIDGEIF_DECL_PROTECT
+/* define bridgeif protection to sys_arch_protect... */
+#include "lwip/sys.h"
+#define BRIDGEIF_DECL_PROTECT(lev) SYS_ARCH_DECL_PROTECT(lev)
+#define BRIDGEIF_READ_PROTECT(lev) SYS_ARCH_PROTECT(lev)
+#define BRIDGEIF_READ_UNPROTECT(lev) SYS_ARCH_UNPROTECT(lev)
+#define BRIDGEIF_WRITE_PROTECT(lev)
+#define BRIDGEIF_WRITE_UNPROTECT(lev)
+#endif
+#else /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */
+#include "lwip/tcpip.h"
+#define BRIDGEIF_DECL_PROTECT(lev)
+#define BRIDGEIF_READ_PROTECT(lev)
+#define BRIDGEIF_READ_UNPROTECT(lev)
+#define BRIDGEIF_WRITE_PROTECT(lev)
+#define BRIDGEIF_WRITE_UNPROTECT(lev)
+#endif /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_BRIDGEIF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/bridgeif_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/bridgeif_opts.h
new file mode 100644
index 0000000..b85c301
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/bridgeif_opts.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ * lwIP netif implementing an IEEE 802.1D MAC Bridge
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_BRIDGEIF_OPTS_H
+#define LWIP_HDR_NETIF_BRIDGEIF_OPTS_H
+
+#include "lwip/opt.h"
+
+/**
+ * @defgroup bridgeif_opts Options
+ * @ingroup bridgeif
+ * @{
+ */
+
+/** BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT==1: set port netif's 'input' function
+ * to call directly into bridgeif code and on top of that, directly call into
+ * the selected forwarding port's 'linkoutput' function.
+ * This means that the bridgeif input/output path is protected from concurrent access
+ * but as well, *all* bridge port netif's drivers must correctly handle concurrent access!
+ * == 0: get into tcpip_thread for every input packet (no multithreading)
+ * ATTENTION: as ==0 relies on tcpip.h, the default depends on NO_SYS setting
+ */
+#ifndef BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT
+#define BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT NO_SYS
+#endif
+
+/** BRIDGEIF_MAX_PORTS: this is used to create a typedef used for forwarding
+ * bit-fields: the number of bits required is this + 1 (for the internal/cpu port)
+ * (63 is the maximum, resulting in an u64_t for the bit mask)
+ * ATTENTION: this controls the maximum number of the implementation only!
+ * The max. number of ports per bridge must still be passed via netif_add parameter!
+ */
+#ifndef BRIDGEIF_MAX_PORTS
+#define BRIDGEIF_MAX_PORTS 7
+#endif
+
+/** BRIDGEIF_DEBUG: Enable generic debugging in bridgeif.c. */
+#ifndef BRIDGEIF_DEBUG
+#define BRIDGEIF_DEBUG LWIP_DBG_OFF
+#endif
+
+/** BRIDGEIF_DEBUG: Enable FDB debugging in bridgeif.c. */
+#ifndef BRIDGEIF_FDB_DEBUG
+#define BRIDGEIF_FDB_DEBUG LWIP_DBG_OFF
+#endif
+
+/** BRIDGEIF_DEBUG: Enable forwarding debugging in bridgeif.c. */
+#ifndef BRIDGEIF_FW_DEBUG
+#define BRIDGEIF_FW_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_NETIF_BRIDGEIF_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/etharp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/etharp.h
new file mode 100644
index 0000000..b536fd2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/etharp.h
@@ -0,0 +1,3 @@
+/* ARP has been moved to core/ipv4, provide this #include for compatibility only */
+#include "lwip/etharp.h"
+#include "netif/ethernet.h"
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ethernet.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ethernet.h
new file mode 100644
index 0000000..49649cb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ethernet.h
@@ -0,0 +1,77 @@
+/**
+ * @file
+ * Ethernet input function - handles INCOMING ethernet level traffic
+ * To be used in most low-level netif implementations
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_ETHERNET_H
+#define LWIP_HDR_NETIF_ETHERNET_H
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_ARP || LWIP_ETHERNET
+
+/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type)
+ * to a filter function that returns the correct netif when using multiple
+ * netifs on one hardware interface where the netif's low-level receive
+ * routine cannot decide for the correct netif (e.g. when mapping multiple
+ * IP addresses to one hardware interface).
+ */
+#ifndef LWIP_ARP_FILTER_NETIF
+#define LWIP_ARP_FILTER_NETIF 0
+#endif
+
+err_t ethernet_input(struct pbuf *p, struct netif *netif);
+err_t ethernet_output(struct netif* netif, struct pbuf* p, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);
+
+extern const struct eth_addr ethbroadcast, ethzero;
+
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_ETHERNET_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ieee802154.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ieee802154.h
new file mode 100644
index 0000000..54e019f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ieee802154.h
@@ -0,0 +1,112 @@
+/**
+ * @file
+ * Definitions for IEEE 802.15.4 MAC frames
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_NETIF_IEEE802154_H
+#define LWIP_HDR_NETIF_IEEE802154_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** General MAC frame format
+ * This shows the full featured header, mainly for documentation.
+ * Some fields are omitted or shortened to achieve frame compression.
+ */
+struct ieee_802154_hdr {
+ /** See IEEE_802154_FC_* defines */
+ PACK_STRUCT_FIELD(u16_t frame_control);
+ /** Sequence number is omitted if IEEE_802154_FC_SEQNO_SUPPR is set in frame_control */
+ PACK_STRUCT_FLD_8(u8_t sequence_number);
+ /** Destination PAN ID is omitted if Destination Addressing Mode is 0 */
+ PACK_STRUCT_FIELD(u16_t destination_pan_id);
+ /** Destination Address is omitted if Destination Addressing Mode is 0 */
+ PACK_STRUCT_FLD_8(u8_t destination_address[8]);
+ /** Source PAN ID is omitted if Source Addressing Mode is 0
+ or if IEEE_802154_FC_PANID_COMPR is set in frame control*/
+ PACK_STRUCT_FIELD(u16_t source_pan_id);
+ /** Source Address is omitted if Source Addressing Mode is 0 */
+ PACK_STRUCT_FLD_8(u8_t source_address[8]);
+ /* The rest is variable */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+/* Addressing modes (2 bits) */
+#define IEEE_802154_ADDR_MODE_NO_ADDR 0x00 /* PAN ID and address fields are not present */
+#define IEEE_802154_ADDR_MODE_RESERVED 0x01 /* Reserved */
+#define IEEE_802154_ADDR_MODE_SHORT 0x02 /* Address field contains a short address (16 bit) */
+#define IEEE_802154_ADDR_MODE_EXT 0x03 /* Address field contains an extended address (64 bit) */
+
+/* IEEE 802.15.4 Frame Control definitions (2 bytes; see IEEE 802.15.4-2015 ch. 7.2.1) */
+#define IEEE_802154_FC_FT_MASK 0x0007 /* bits 0..2: Frame Type */
+#define IEEE_802154_FC_FT_BEACON 0x00
+#define IEEE_802154_FC_FT_DATA 0x01
+#define IEEE_802154_FC_FT_ACK 0x02
+#define IEEE_802154_FC_FT_MAC_CMD 0x03
+#define IEEE_802154_FC_FT_RESERVED 0x04
+#define IEEE_802154_FC_FT_MULTIPURPOSE 0x05
+#define IEEE_802154_FC_FT_FRAG 0x06
+#define IEEE_802154_FC_FT_EXT 0x07
+#define IEEE_802154_FC_SEC_EN 0x0008 /* bit 3: Security Enabled */
+#define IEEE_802154_FC_FRAME_PEND 0x0010 /* bit 4: Frame Pending */
+#define IEEE_802154_FC_ACK_REQ 0x0020 /* bit 5: AR (ACK required) */
+#define IEEE_802154_FC_PANID_COMPR 0x0040 /* bit 6: PAN ID Compression (src and dst are equal, src PAN ID omitted) */
+#define IEEE_802154_FC_RESERVED 0x0080
+#define IEEE_802154_FC_SEQNO_SUPPR 0x0100 /* bit 8: Sequence Number Suppression */
+#define IEEE_802154_FC_IE_PRESENT 0x0200 /* bit 9: IE Present */
+#define IEEE_802154_FC_DST_ADDR_MODE_MASK 0x0c00 /* bits 10..11: Destination Addressing Mode */
+#define IEEE_802154_FC_DST_ADDR_MODE_NO_ADDR (IEEE_802154_ADDR_MODE_NO_ADDR << 10)
+#define IEEE_802154_FC_DST_ADDR_MODE_SHORT (IEEE_802154_ADDR_MODE_SHORT << 10)
+#define IEEE_802154_FC_DST_ADDR_MODE_EXT (IEEE_802154_ADDR_MODE_EXT << 10)
+#define IEEE_802154_FC_FRAME_VERSION_MASK 0x3000 /* bits 12..13: Frame Version */
+#define IEEE_802154_FC_FRAME_VERSION_GET(x) (((x) & IEEE_802154_FC_FRAME_VERSION_MASK) >> 12)
+#define IEEE_802154_FC_SRC_ADDR_MODE_MASK 0xc000 /* bits 14..15: Source Addressing Mode */
+#define IEEE_802154_FC_SRC_ADDR_MODE_SHORT (IEEE_802154_ADDR_MODE_SHORT << 14)
+#define IEEE_802154_FC_SRC_ADDR_MODE_EXT (IEEE_802154_ADDR_MODE_EXT << 14)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_IEEE802154_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6.h
new file mode 100644
index 0000000..ecff24b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_H
+#define LWIP_HDR_LOWPAN6_H
+
+#include "netif/lowpan6_opts.h"
+
+#if LWIP_IPV6
+
+#include "netif/lowpan6_common.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** 1 second period for reassembly */
+#define LOWPAN6_TMR_INTERVAL 1000
+
+void lowpan6_tmr(void);
+
+err_t lowpan6_set_context(u8_t idx, const ip6_addr_t * context);
+err_t lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low);
+
+#if LWIP_IPV4
+err_t lowpan4_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
+#endif /* LWIP_IPV4 */
+err_t lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+err_t lowpan6_input(struct pbuf * p, struct netif *netif);
+err_t lowpan6_if_init(struct netif *netif);
+
+/* pan_id in network byte order. */
+err_t lowpan6_set_pan_id(u16_t pan_id);
+
+u16_t lowpan6_calc_crc(const void *buf, u16_t len);
+
+#if !NO_SYS
+err_t tcpip_6lowpan_input(struct pbuf *p, struct netif *inp);
+#endif /* !NO_SYS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_LOWPAN6_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_ble.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_ble.h
new file mode 100644
index 0000000..5190e7b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_ble.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ * 6LowPAN over BLE for IPv6 (RFC7668).
+ */
+
+/*
+ * Copyright (c) 2017 Benjamin Aigner
+ * Copyright (c) 2015 Inico Technologies Ltd. , Author: Ivan Delamer
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Benjamin Aigner
+ *
+ * Based on the original 6lowpan implementation of lwIP ( @see 6lowpan.c)
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_BLE_H
+#define LWIP_HDR_LOWPAN6_BLE_H
+
+#include "netif/lowpan6_opts.h"
+
+#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/lowpan6_common.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t rfc7668_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+err_t rfc7668_input(struct pbuf * p, struct netif *netif);
+err_t rfc7668_set_local_addr_eui64(struct netif *netif, const u8_t *local_addr, size_t local_addr_len);
+err_t rfc7668_set_local_addr_mac48(struct netif *netif, const u8_t *local_addr, size_t local_addr_len, int is_public_addr);
+err_t rfc7668_set_peer_addr_eui64(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len);
+err_t rfc7668_set_peer_addr_mac48(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len, int is_public_addr);
+err_t rfc7668_set_context(u8_t index, const ip6_addr_t * context);
+err_t rfc7668_if_init(struct netif *netif);
+
+#if !NO_SYS
+err_t tcpip_rfc7668_input(struct pbuf *p, struct netif *inp);
+#endif
+
+void ble_addr_to_eui64(uint8_t *dst, const uint8_t *src, int public_addr);
+void eui64_to_ble_addr(uint8_t *dst, const uint8_t *src);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_LOWPAN6_BLE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_common.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_common.h
new file mode 100644
index 0000000..0dc13ab
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_common.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * Common 6LowPAN routines for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_COMMON_H
+#define LWIP_HDR_LOWPAN6_COMMON_H
+
+#include "netif/lowpan6_opts.h"
+
+#if LWIP_IPV6 /* don't build if IPv6 is disabled in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Helper define for a link layer address, which can be encoded as 0, 2 or 8 bytes */
+struct lowpan6_link_addr {
+ /* encoded length of the address */
+ u8_t addr_len;
+ /* address bytes */
+ u8_t addr[8];
+};
+
+s8_t lowpan6_get_address_mode(const ip6_addr_t *ip6addr, const struct lowpan6_link_addr *mac_addr);
+
+#if LWIP_6LOWPAN_IPHC
+err_t lowpan6_compress_headers(struct netif *netif, u8_t *inbuf, size_t inbuf_size, u8_t *outbuf, size_t outbuf_size,
+ u8_t *lowpan6_header_len_out, u8_t *hidden_header_len_out, ip6_addr_t *lowpan6_contexts,
+ const struct lowpan6_link_addr *src, const struct lowpan6_link_addr *dst);
+struct pbuf *lowpan6_decompress(struct pbuf *p, u16_t datagram_size, ip6_addr_t *lowpan6_contexts,
+ struct lowpan6_link_addr *src, struct lowpan6_link_addr *dest);
+#endif /* LWIP_6LOWPAN_IPHC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_LOWPAN6_COMMON_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_opts.h
new file mode 100644
index 0000000..32e5c5e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/lowpan6_opts.h
@@ -0,0 +1,122 @@
+/**
+ * @file
+ * 6LowPAN options list
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ *
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_OPTS_H
+#define LWIP_HDR_LOWPAN6_OPTS_H
+
+#include "lwip/opt.h"
+
+/** LWIP_6LOWPAN_NUM_CONTEXTS: define the number of compression
+ * contexts per netif type
+ */
+#ifndef LWIP_6LOWPAN_NUM_CONTEXTS
+#define LWIP_6LOWPAN_NUM_CONTEXTS 10
+#endif
+
+/** LWIP_6LOWPAN_INFER_SHORT_ADDRESS: set this to 0 to disable creating
+ * short addresses for matching addresses (debug only)
+ */
+#ifndef LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+#define LWIP_6LOWPAN_INFER_SHORT_ADDRESS 1
+#endif
+
+/** LWIP_6LOWPAN_IPHC: set this to 0 to disable IP header compression as per
+ * RFC 6282 (which is mandatory for BLE)
+ */
+#ifndef LWIP_6LOWPAN_IPHC
+#define LWIP_6LOWPAN_IPHC 1
+#endif
+
+/** Set this to 1 if your IEEE 802.15.4 interface can calculate and check the
+ * CRC in hardware. This means TX packets get 2 zero bytes added on transmission
+ * which are to be filled with the CRC.
+ */
+#ifndef LWIP_6LOWPAN_802154_HW_CRC
+#define LWIP_6LOWPAN_802154_HW_CRC 0
+#endif
+
+/** If LWIP_6LOWPAN_802154_HW_CRC==0, this can override the default slow
+ * implementation of the CRC used for 6LoWPAN over IEEE 802.15.4 (which uses
+ * a shift register).
+ */
+#ifndef LWIP_6LOWPAN_CALC_CRC
+#define LWIP_6LOWPAN_CALC_CRC(buf, len) lowpan6_calc_crc(buf, len)
+#endif
+
+/** Debug level for 6LoWPAN in general */
+#ifndef LWIP_LOWPAN6_DEBUG
+#define LWIP_LOWPAN6_DEBUG LWIP_DBG_OFF
+#endif
+
+/** Debug level for 6LoWPAN over IEEE 802.15.4 */
+#ifndef LWIP_LOWPAN6_802154_DEBUG
+#define LWIP_LOWPAN6_802154_DEBUG LWIP_DBG_OFF
+#endif
+
+/** LWIP_LOWPAN6_IP_COMPRESSED_DEBUG: enable compressed IP frame
+ * output debugging
+ */
+#ifndef LWIP_LOWPAN6_IP_COMPRESSED_DEBUG
+#define LWIP_LOWPAN6_IP_COMPRESSED_DEBUG LWIP_DBG_OFF
+#endif
+
+/** LWIP_LOWPAN6_DECOMPRESSION_DEBUG: enable decompression debug output
+ */
+#ifndef LWIP_LOWPAN6_DECOMPRESSION_DEBUG
+#define LWIP_LOWPAN6_DECOMPRESSION_DEBUG LWIP_DBG_OFF
+#endif
+
+/** LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG: enable decompressed IP frame
+ * output debugging */
+#ifndef LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG
+#define LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG LWIP_DBG_OFF
+#endif
+
+/** LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS:
+ * Currently, the linux kernel driver for 6lowpan sets/clears a bit in
+ * the address, depending on the BD address (either public or not).
+ * Might not be RFC7668 conform, so you may select to do that (=1) or
+ * not (=0) */
+#ifndef LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS
+#define LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS 1
+#endif
+
+
+#endif /* LWIP_HDR_LOWPAN6_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ccp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ccp.h
new file mode 100644
index 0000000..b228522
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ccp.h
@@ -0,0 +1,164 @@
+/*
+ * ccp.h - Definitions for PPP Compression Control Protocol.
+ *
+ * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Paul Mackerras
+ * ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ccp.h,v 1.12 2004/11/04 10:02:26 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CCP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CCP_H
+#define CCP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CCP codes.
+ */
+
+#define CCP_CONFREQ 1
+#define CCP_CONFACK 2
+#define CCP_TERMREQ 5
+#define CCP_TERMACK 6
+#define CCP_RESETREQ 14
+#define CCP_RESETACK 15
+
+/*
+ * Max # bytes for a CCP option
+ */
+
+#define CCP_MAX_OPTION_LENGTH 32
+
+/*
+ * Parts of a CCP packet.
+ */
+
+#define CCP_CODE(dp) ((dp)[0])
+#define CCP_ID(dp) ((dp)[1])
+#define CCP_LENGTH(dp) (((dp)[2] << 8) + (dp)[3])
+#define CCP_HDRLEN 4
+
+#define CCP_OPT_CODE(dp) ((dp)[0])
+#define CCP_OPT_LENGTH(dp) ((dp)[1])
+#define CCP_OPT_MINLEN 2
+
+#if BSDCOMPRESS_SUPPORT
+/*
+ * Definitions for BSD-Compress.
+ */
+
+#define CI_BSD_COMPRESS 21 /* config. option for BSD-Compress */
+#define CILEN_BSD_COMPRESS 3 /* length of config. option */
+
+/* Macros for handling the 3rd byte of the BSD-Compress config option. */
+#define BSD_NBITS(x) ((x) & 0x1F) /* number of bits requested */
+#define BSD_VERSION(x) ((x) >> 5) /* version of option format */
+#define BSD_CURRENT_VERSION 1 /* current version number */
+#define BSD_MAKE_OPT(v, n) (((v) << 5) | (n))
+
+#define BSD_MIN_BITS 9 /* smallest code size supported */
+#define BSD_MAX_BITS 15 /* largest code size supported */
+#endif /* BSDCOMPRESS_SUPPORT */
+
+#if DEFLATE_SUPPORT
+/*
+ * Definitions for Deflate.
+ */
+
+#define CI_DEFLATE 26 /* config option for Deflate */
+#define CI_DEFLATE_DRAFT 24 /* value used in original draft RFC */
+#define CILEN_DEFLATE 4 /* length of its config option */
+
+#define DEFLATE_MIN_SIZE 9
+#define DEFLATE_MAX_SIZE 15
+#define DEFLATE_METHOD_VAL 8
+#define DEFLATE_SIZE(x) (((x) >> 4) + 8)
+#define DEFLATE_METHOD(x) ((x) & 0x0F)
+#define DEFLATE_MAKE_OPT(w) ((((w) - 8) << 4) + DEFLATE_METHOD_VAL)
+#define DEFLATE_CHK_SEQUENCE 0
+#endif /* DEFLATE_SUPPORT */
+
+#if MPPE_SUPPORT
+/*
+ * Definitions for MPPE.
+ */
+
+#define CI_MPPE 18 /* config option for MPPE */
+#define CILEN_MPPE 6 /* length of config option */
+#endif /* MPPE_SUPPORT */
+
+#if PREDICTOR_SUPPORT
+/*
+ * Definitions for other, as yet unsupported, compression methods.
+ */
+
+#define CI_PREDICTOR_1 1 /* config option for Predictor-1 */
+#define CILEN_PREDICTOR_1 2 /* length of its config option */
+#define CI_PREDICTOR_2 2 /* config option for Predictor-2 */
+#define CILEN_PREDICTOR_2 2 /* length of its config option */
+#endif /* PREDICTOR_SUPPORT */
+
+typedef struct ccp_options {
+#if DEFLATE_SUPPORT
+ unsigned int deflate :1; /* do Deflate? */
+ unsigned int deflate_correct :1; /* use correct code for deflate? */
+ unsigned int deflate_draft :1; /* use draft RFC code for deflate? */
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+ unsigned int bsd_compress :1; /* do BSD Compress? */
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+ unsigned int predictor_1 :1; /* do Predictor-1? */
+ unsigned int predictor_2 :1; /* do Predictor-2? */
+#endif /* PREDICTOR_SUPPORT */
+
+#if MPPE_SUPPORT
+ u8_t mppe; /* MPPE bitfield */
+#endif /* MPPE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+ u_short bsd_bits; /* # bits/code for BSD Compress */
+#endif /* BSDCOMPRESS_SUPPORT */
+#if DEFLATE_SUPPORT
+ u_short deflate_size; /* lg(window size) for Deflate */
+#endif /* DEFLATE_SUPPORT */
+ u8_t method; /* code for chosen compression method */
+} ccp_options;
+
+extern const struct protent ccp_protent;
+
+void ccp_resetrequest(ppp_pcb *pcb); /* Issue a reset-request. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CCP_H */
+#endif /* PPP_SUPPORT && CCP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap-md5.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap-md5.h
new file mode 100644
index 0000000..eb0269f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap-md5.h
@@ -0,0 +1,36 @@
+/*
+ * chap-md5.h - New CHAP/MD5 implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Paul Mackerras
+ * ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+extern const struct chap_digest_type md5_digest;
+
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap-new.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap-new.h
new file mode 100644
index 0000000..2d8cd9c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap-new.h
@@ -0,0 +1,200 @@
+/*
+ * chap-new.c - New CHAP implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Paul Mackerras
+ * ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CHAP packets begin with a standard header with code, id, len (2 bytes).
+ */
+#define CHAP_HDRLEN 4
+
+/*
+ * Values for the code field.
+ */
+#define CHAP_CHALLENGE 1
+#define CHAP_RESPONSE 2
+#define CHAP_SUCCESS 3
+#define CHAP_FAILURE 4
+
+/*
+ * CHAP digest codes.
+ */
+#define CHAP_MD5 5
+#if MSCHAP_SUPPORT
+#define CHAP_MICROSOFT 0x80
+#define CHAP_MICROSOFT_V2 0x81
+#endif /* MSCHAP_SUPPORT */
+
+/*
+ * Semi-arbitrary limits on challenge and response fields.
+ */
+#define MAX_CHALLENGE_LEN 64
+#define MAX_RESPONSE_LEN 64
+
+/*
+ * These limits apply to challenge and response packets we send.
+ * The +4 is the +1 that we actually need rounded up.
+ */
+#define CHAL_MAX_PKTLEN (PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_CHALLENGE_LEN + MAXNAMELEN)
+#define RESP_MAX_PKTLEN (PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_RESPONSE_LEN + MAXNAMELEN)
+
+/* bitmask of supported algorithms */
+#if MSCHAP_SUPPORT
+#define MDTYPE_MICROSOFT_V2 0x1
+#define MDTYPE_MICROSOFT 0x2
+#endif /* MSCHAP_SUPPORT */
+#define MDTYPE_MD5 0x4
+#define MDTYPE_NONE 0
+
+#if MSCHAP_SUPPORT
+/* Return the digest alg. ID for the most preferred digest type. */
+#define CHAP_DIGEST(mdtype) \
+ ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
+ ((mdtype) & MDTYPE_MICROSOFT_V2)? CHAP_MICROSOFT_V2: \
+ ((mdtype) & MDTYPE_MICROSOFT)? CHAP_MICROSOFT: \
+ 0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_DIGEST(mdtype) \
+ ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
+ 0
+#endif /* MSCHAP_SUPPORT */
+
+/* Return the bit flag (lsb set) for our most preferred digest type. */
+#define CHAP_MDTYPE(mdtype) ((mdtype) ^ ((mdtype) - 1)) & (mdtype)
+
+/* Return the bit flag for a given digest algorithm ID. */
+#if MSCHAP_SUPPORT
+#define CHAP_MDTYPE_D(digest) \
+ ((digest) == CHAP_MICROSOFT_V2)? MDTYPE_MICROSOFT_V2: \
+ ((digest) == CHAP_MICROSOFT)? MDTYPE_MICROSOFT: \
+ ((digest) == CHAP_MD5)? MDTYPE_MD5: \
+ 0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_MDTYPE_D(digest) \
+ ((digest) == CHAP_MD5)? MDTYPE_MD5: \
+ 0
+#endif /* MSCHAP_SUPPORT */
+
+/* Can we do the requested digest? */
+#if MSCHAP_SUPPORT
+#define CHAP_CANDIGEST(mdtype, digest) \
+ ((digest) == CHAP_MICROSOFT_V2)? (mdtype) & MDTYPE_MICROSOFT_V2: \
+ ((digest) == CHAP_MICROSOFT)? (mdtype) & MDTYPE_MICROSOFT: \
+ ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
+ 0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_CANDIGEST(mdtype, digest) \
+ ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
+ 0
+#endif /* MSCHAP_SUPPORT */
+
+/*
+ * The code for each digest type has to supply one of these.
+ */
+struct chap_digest_type {
+ int code;
+
+#if PPP_SERVER
+ /*
+ * Note: challenge and response arguments below are formatted as
+ * a length byte followed by the actual challenge/response data.
+ */
+ void (*generate_challenge)(ppp_pcb *pcb, unsigned char *challenge);
+ int (*verify_response)(ppp_pcb *pcb, int id, const char *name,
+ const unsigned char *secret, int secret_len,
+ const unsigned char *challenge, const unsigned char *response,
+ char *message, int message_space);
+#endif /* PPP_SERVER */
+ void (*make_response)(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name,
+ const unsigned char *challenge, const char *secret, int secret_len,
+ unsigned char *priv);
+ int (*check_success)(ppp_pcb *pcb, unsigned char *pkt, int len, unsigned char *priv);
+ void (*handle_failure)(ppp_pcb *pcb, unsigned char *pkt, int len);
+};
+
+/*
+ * Each interface is described by chap structure.
+ */
+#if CHAP_SUPPORT
+typedef struct chap_client_state {
+ u8_t flags;
+ const char *name;
+ const struct chap_digest_type *digest;
+ unsigned char priv[64]; /* private area for digest's use */
+} chap_client_state;
+
+#if PPP_SERVER
+typedef struct chap_server_state {
+ u8_t flags;
+ u8_t id;
+ const char *name;
+ const struct chap_digest_type *digest;
+ int challenge_xmits;
+ int challenge_pktlen;
+ unsigned char challenge[CHAL_MAX_PKTLEN];
+} chap_server_state;
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPORT */
+
+#if 0 /* UNUSED */
+/* Hook for a plugin to validate CHAP challenge */
+extern int (*chap_verify_hook)(char *name, char *ourname, int id,
+ const struct chap_digest_type *digest,
+ unsigned char *challenge, unsigned char *response,
+ char *message, int message_space);
+#endif /* UNUSED */
+
+#if PPP_SERVER
+/* Called by authentication code to start authenticating the peer. */
+extern void chap_auth_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
+#endif /* PPP_SERVER */
+
+/* Called by auth. code to start authenticating us to the peer. */
+extern void chap_auth_with_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
+
+/* Represents the CHAP protocol to the main pppd code */
+extern const struct protent chap_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CHAP_H */
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap_ms.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap_ms.h
new file mode 100644
index 0000000..0795291
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/chap_ms.h
@@ -0,0 +1,44 @@
+/*
+ * chap_ms.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: chap_ms.h,v 1.13 2004/11/15 22:13:26 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CHAPMS_INCLUDE
+#define CHAPMS_INCLUDE
+
+extern const struct chap_digest_type chapms_digest;
+extern const struct chap_digest_type chapms2_digest;
+
+#endif /* CHAPMS_INCLUDE */
+
+#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/eap.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/eap.h
new file mode 100644
index 0000000..3ee9aaf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/eap.h
@@ -0,0 +1,169 @@
+/*
+ * eap.h - Extensible Authentication Protocol for PPP (RFC 2284)
+ *
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ *
+ * Non-exclusive rights to redistribute, modify, translate, and use
+ * this software in source and binary forms, in whole or in part, is
+ * hereby granted, provided that the above copyright notice is
+ * duplicated in any source form, and that neither the name of the
+ * copyright holder nor the author is used to endorse or promote
+ * products derived from this software.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Original version by James Carlson
+ *
+ * $Id: eap.h,v 1.2 2003/06/11 23:56:26 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && EAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_EAP_H
+#define PPP_EAP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define EAP_HEADERLEN 4
+
+
+/* EAP message codes. */
+#define EAP_REQUEST 1
+#define EAP_RESPONSE 2
+#define EAP_SUCCESS 3
+#define EAP_FAILURE 4
+
+/* EAP types */
+#define EAPT_IDENTITY 1
+#define EAPT_NOTIFICATION 2
+#define EAPT_NAK 3 /* (response only) */
+#define EAPT_MD5CHAP 4
+#define EAPT_OTP 5 /* One-Time Password; RFC 1938 */
+#define EAPT_TOKEN 6 /* Generic Token Card */
+/* 7 and 8 are unassigned. */
+#define EAPT_RSA 9 /* RSA Public Key Authentication */
+#define EAPT_DSS 10 /* DSS Unilateral */
+#define EAPT_KEA 11 /* KEA */
+#define EAPT_KEA_VALIDATE 12 /* KEA-VALIDATE */
+#define EAPT_TLS 13 /* EAP-TLS */
+#define EAPT_DEFENDER 14 /* Defender Token (AXENT) */
+#define EAPT_W2K 15 /* Windows 2000 EAP */
+#define EAPT_ARCOT 16 /* Arcot Systems */
+#define EAPT_CISCOWIRELESS 17 /* Cisco Wireless */
+#define EAPT_NOKIACARD 18 /* Nokia IP smart card */
+#define EAPT_SRP 19 /* Secure Remote Password */
+/* 20 is deprecated */
+
+/* EAP SRP-SHA1 Subtypes */
+#define EAPSRP_CHALLENGE 1 /* Request 1 - Challenge */
+#define EAPSRP_CKEY 1 /* Response 1 - Client Key */
+#define EAPSRP_SKEY 2 /* Request 2 - Server Key */
+#define EAPSRP_CVALIDATOR 2 /* Response 2 - Client Validator */
+#define EAPSRP_SVALIDATOR 3 /* Request 3 - Server Validator */
+#define EAPSRP_ACK 3 /* Response 3 - final ack */
+#define EAPSRP_LWRECHALLENGE 4 /* Req/resp 4 - Lightweight rechal */
+
+#define SRPVAL_EBIT 0x00000001 /* Use shared key for ECP */
+
+#define SRP_PSEUDO_ID "pseudo_"
+#define SRP_PSEUDO_LEN 7
+
+#define MD5_SIGNATURE_SIZE 16
+#define EAP_MIN_CHALLENGE_LENGTH 17
+#define EAP_MAX_CHALLENGE_LENGTH 24
+#define EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH 3 /* 2^3-1 = 7, 17+7 = 24 */
+
+#define EAP_STATES \
+ "Initial", "Pending", "Closed", "Listen", "Identify", \
+ "SRP1", "SRP2", "SRP3", "MD5Chall", "Open", "SRP4", "BadAuth"
+
+#define eap_client_active(pcb) ((pcb)->eap.es_client.ea_state == eapListen)
+#if PPP_SERVER
+#define eap_server_active(pcb) \
+ ((pcb)->eap.es_server.ea_state >= eapIdentify && \
+ (pcb)->eap.es_server.ea_state <= eapMD5Chall)
+#endif /* PPP_SERVER */
+
+/*
+ * Complete EAP state for one PPP session.
+ */
+enum eap_state_code {
+ eapInitial = 0, /* No EAP authentication yet requested */
+ eapPending, /* Waiting for LCP (no timer) */
+ eapClosed, /* Authentication not in use */
+ eapListen, /* Client ready (and timer running) */
+ eapIdentify, /* EAP Identify sent */
+ eapSRP1, /* Sent EAP SRP-SHA1 Subtype 1 */
+ eapSRP2, /* Sent EAP SRP-SHA1 Subtype 2 */
+ eapSRP3, /* Sent EAP SRP-SHA1 Subtype 3 */
+ eapMD5Chall, /* Sent MD5-Challenge */
+ eapOpen, /* Completed authentication */
+ eapSRP4, /* Sent EAP SRP-SHA1 Subtype 4 */
+ eapBadAuth /* Failed authentication */
+};
+
+struct eap_auth {
+ const char *ea_name; /* Our name */
+ char ea_peer[MAXNAMELEN +1]; /* Peer's name */
+ void *ea_session; /* Authentication library linkage */
+ u_char *ea_skey; /* Shared encryption key */
+ u_short ea_namelen; /* Length of our name */
+ u_short ea_peerlen; /* Length of peer's name */
+ enum eap_state_code ea_state;
+ u_char ea_id; /* Current id */
+ u_char ea_requests; /* Number of Requests sent/received */
+ u_char ea_responses; /* Number of Responses */
+ u_char ea_type; /* One of EAPT_* */
+ u32_t ea_keyflags; /* SRP shared key usage flags */
+};
+
+#ifndef EAP_MAX_CHALLENGE_LENGTH
+#define EAP_MAX_CHALLENGE_LENGTH 24
+#endif
+typedef struct eap_state {
+ struct eap_auth es_client; /* Client (authenticatee) data */
+#if PPP_SERVER
+ struct eap_auth es_server; /* Server (authenticator) data */
+#endif /* PPP_SERVER */
+ int es_savedtime; /* Saved timeout */
+ int es_rechallenge; /* EAP rechallenge interval */
+ int es_lwrechallenge; /* SRP lightweight rechallenge inter */
+ u8_t es_usepseudo; /* Use SRP Pseudonym if offered one */
+ int es_usedpseudo; /* Set if we already sent PN */
+ int es_challen; /* Length of challenge string */
+ u_char es_challenge[EAP_MAX_CHALLENGE_LENGTH];
+} eap_state;
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to ppp_opts.h */
+#define EAP_DEFTIMEOUT 3 /* Timeout (seconds) for rexmit */
+#define EAP_DEFTRANSMITS 10 /* max # times to transmit */
+#define EAP_DEFREQTIME 20 /* Time to wait for peer request */
+#define EAP_DEFALLOWREQ 20 /* max # times to accept requests */
+#endif /* moved to ppp_opts.h */
+
+void eap_authwithpeer(ppp_pcb *pcb, const char *localname);
+void eap_authpeer(ppp_pcb *pcb, const char *localname);
+
+extern const struct protent eap_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPP_EAP_H */
+
+#endif /* PPP_SUPPORT && EAP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ecp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ecp.h
new file mode 100644
index 0000000..d8808c3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ecp.h
@@ -0,0 +1,62 @@
+/*
+ * ecp.h - Definitions for PPP Encryption Control Protocol.
+ *
+ * Copyright (c) 2002 Google, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ecp.h,v 1.2 2003/01/10 07:12:36 fcusack Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && ECP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef ECP_H
+#define ECP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct ecp_options {
+ bool required; /* Is ECP required? */
+ unsigned enctype; /* Encryption type */
+} ecp_options;
+
+extern fsm ecp_fsm[];
+extern ecp_options ecp_wantoptions[];
+extern ecp_options ecp_gotoptions[];
+extern ecp_options ecp_allowoptions[];
+extern ecp_options ecp_hisoptions[];
+
+extern const struct protent ecp_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ECP_H */
+#endif /* PPP_SUPPORT && ECP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/eui64.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/eui64.h
new file mode 100644
index 0000000..5adeb48
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/eui64.h
@@ -0,0 +1,102 @@
+/*
+ * eui64.h - EUI64 routines for IPv6CP.
+ *
+ * Copyright (c) 1999 Tommi Komulainen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Tommi Komulainen
+ * ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: eui64.h,v 1.6 2002/12/04 23:03:32 paulus Exp $
+*/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef EUI64_H
+#define EUI64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * @todo:
+ *
+ * Maybe this should be done by processing struct in6_addr directly...
+ */
+typedef union
+{
+ u8_t e8[8];
+ u16_t e16[4];
+ u32_t e32[2];
+} eui64_t;
+
+#define eui64_iszero(e) (((e).e32[0] | (e).e32[1]) == 0)
+#define eui64_equals(e, o) (((e).e32[0] == (o).e32[0]) && \
+ ((e).e32[1] == (o).e32[1]))
+#define eui64_zero(e) (e).e32[0] = (e).e32[1] = 0;
+
+#define eui64_copy(s, d) memcpy(&(d), &(s), sizeof(eui64_t))
+
+#define eui64_magic(e) do { \
+ (e).e32[0] = magic(); \
+ (e).e32[1] = magic(); \
+ (e).e8[0] &= ~2; \
+ } while (0)
+#define eui64_magic_nz(x) do { \
+ eui64_magic(x); \
+ } while (eui64_iszero(x))
+#define eui64_magic_ne(x, y) do { \
+ eui64_magic(x); \
+ } while (eui64_equals(x, y))
+
+#define eui64_get(ll, cp) do { \
+ eui64_copy((*cp), (ll)); \
+ (cp) += sizeof(eui64_t); \
+ } while (0)
+
+#define eui64_put(ll, cp) do { \
+ eui64_copy((ll), (*cp)); \
+ (cp) += sizeof(eui64_t); \
+ } while (0)
+
+#define eui64_set32(e, l) do { \
+ (e).e32[0] = 0; \
+ (e).e32[1] = lwip_htonl(l); \
+ } while (0)
+#define eui64_setlo32(e, l) eui64_set32(e, l)
+
+char *eui64_ntoa(eui64_t); /* Returns ascii representation of id */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EUI64_H */
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/fsm.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/fsm.h
new file mode 100644
index 0000000..8dec700
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/fsm.h
@@ -0,0 +1,182 @@
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission. For permission or any legal
+ * details, please contact
+ * Office of Technology Transfer
+ * Carnegie Mellon University
+ * 5000 Forbes Avenue
+ * Pittsburgh, PA 15213-3890
+ * (412) 268-4387, fax: (412) 268-7395
+ * tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Computing Services
+ * at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: fsm.h,v 1.10 2004/11/13 02:28:15 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef FSM_H
+#define FSM_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define HEADERLEN 4
+
+
+/*
+ * CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ 1 /* Configuration Request */
+#define CONFACK 2 /* Configuration Ack */
+#define CONFNAK 3 /* Configuration Nak */
+#define CONFREJ 4 /* Configuration Reject */
+#define TERMREQ 5 /* Termination Request */
+#define TERMACK 6 /* Termination Ack */
+#define CODEREJ 7 /* Code Reject */
+
+
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+ ppp_pcb *pcb; /* PPP Interface */
+ const struct fsm_callbacks *callbacks; /* Callback routines */
+ const char *term_reason; /* Reason for closing protocol */
+ u8_t seen_ack; /* Have received valid Ack/Nak/Rej to Req */
+ /* -- This is our only flag, we might use u_int :1 if we have more flags */
+ u16_t protocol; /* Data Link Layer Protocol field value */
+ u8_t state; /* State */
+ u8_t flags; /* Contains option bits */
+ u8_t id; /* Current id */
+ u8_t reqid; /* Current request id */
+ u8_t retransmits; /* Number of retransmissions left */
+ u8_t nakloops; /* Number of nak loops since last ack */
+ u8_t rnakloops; /* Number of naks received */
+ u8_t maxnakloops; /* Maximum number of nak loops tolerated
+ (necessary because IPCP require a custom large max nak loops value) */
+ u8_t term_reason_len; /* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+ void (*resetci) /* Reset our Configuration Information */
+ (fsm *);
+ int (*cilen) /* Length of our Configuration Information */
+ (fsm *);
+ void (*addci) /* Add our Configuration Information */
+ (fsm *, u_char *, int *);
+ int (*ackci) /* ACK our Configuration Information */
+ (fsm *, u_char *, int);
+ int (*nakci) /* NAK our Configuration Information */
+ (fsm *, u_char *, int, int);
+ int (*rejci) /* Reject our Configuration Information */
+ (fsm *, u_char *, int);
+ int (*reqci) /* Request peer's Configuration Information */
+ (fsm *, u_char *, int *, int);
+ void (*up) /* Called when fsm reaches PPP_FSM_OPENED state */
+ (fsm *);
+ void (*down) /* Called when fsm leaves PPP_FSM_OPENED state */
+ (fsm *);
+ void (*starting) /* Called when we want the lower layer */
+ (fsm *);
+ void (*finished) /* Called when we don't want the lower layer */
+ (fsm *);
+ void (*protreject) /* Called when Protocol-Reject received */
+ (int);
+ void (*retransmit) /* Retransmission is necessary */
+ (fsm *);
+ int (*extcode) /* Called when unknown code received */
+ (fsm *, int, int, u_char *, int);
+ const char *proto_name; /* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*
+ * Link states.
+ */
+#define PPP_FSM_INITIAL 0 /* Down, hasn't been opened */
+#define PPP_FSM_STARTING 1 /* Down, been opened */
+#define PPP_FSM_CLOSED 2 /* Up, hasn't been opened */
+#define PPP_FSM_STOPPED 3 /* Open, waiting for down event */
+#define PPP_FSM_CLOSING 4 /* Terminating the connection, not open */
+#define PPP_FSM_STOPPING 5 /* Terminating, but open */
+#define PPP_FSM_REQSENT 6 /* We've sent a Config Request */
+#define PPP_FSM_ACKRCVD 7 /* We've received a Config Ack */
+#define PPP_FSM_ACKSENT 8 /* We've sent a Config Ack */
+#define PPP_FSM_OPENED 9 /* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE 1 /* Don't die if we don't get a response */
+#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT 4 /* Wait for peer to speak first */
+
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to ppp_opts.h */
+#define DEFTIMEOUT 3 /* Timeout time in seconds */
+#define DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */
+#define DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */
+#define DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */
+#endif /* moved to ppp_opts.h */
+
+
+/*
+ * Prototypes
+ */
+void fsm_init(fsm *f);
+void fsm_lowerup(fsm *f);
+void fsm_lowerdown(fsm *f);
+void fsm_open(fsm *f);
+void fsm_close(fsm *f, const char *reason);
+void fsm_input(fsm *f, u_char *inpacket, int l);
+void fsm_protreject(fsm *f);
+void fsm_sdata(fsm *f, u_char code, u_char id, const u_char *data, int datalen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FSM_H */
+#endif /* PPP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ipcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ipcp.h
new file mode 100644
index 0000000..5590dec
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ipcp.h
@@ -0,0 +1,134 @@
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission. For permission or any legal
+ * details, please contact
+ * Office of Technology Transfer
+ * Carnegie Mellon University
+ * 5000 Forbes Avenue
+ * Pittsburgh, PA 15213-3890
+ * (412) 268-4387, fax: (412) 268-7395
+ * tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Computing Services
+ * at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ipcp.h,v 1.14 2002/12/04 23:03:32 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV4_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Options.
+ */
+#define CI_ADDRS 1 /* IP Addresses */
+#if VJ_SUPPORT
+#define CI_COMPRESSTYPE 2 /* Compression Type */
+#endif /* VJ_SUPPORT */
+#define CI_ADDR 3
+
+#if LWIP_DNS
+#define CI_MS_DNS1 129 /* Primary DNS value */
+#define CI_MS_DNS2 131 /* Secondary DNS value */
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+#define CI_MS_WINS1 130 /* Primary WINS value */
+#define CI_MS_WINS2 132 /* Secondary WINS value */
+#endif /* UNUSED - WINS */
+
+#if VJ_SUPPORT
+#define MAX_STATES 16 /* from slcompress.h */
+
+#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */
+ /* maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */
+ /* compression option*/
+#endif /* VJ_SUPPORT */
+
+typedef struct ipcp_options {
+ unsigned int neg_addr :1; /* Negotiate IP Address? */
+ unsigned int old_addrs :1; /* Use old (IP-Addresses) option? */
+ unsigned int req_addr :1; /* Ask peer to send IP address? */
+#if 0 /* UNUSED */
+ unsigned int default_route :1; /* Assign default route through interface? */
+ unsigned int replace_default_route :1; /* Replace default route through interface? */
+#endif /* UNUSED */
+#if 0 /* UNUSED - PROXY ARP */
+ unsigned int proxy_arp :1; /* Make proxy ARP entry for peer? */
+#endif /* UNUSED - PROXY ARP */
+#if VJ_SUPPORT
+ unsigned int neg_vj :1; /* Van Jacobson Compression? */
+ unsigned int old_vj :1; /* use old (short) form of VJ option? */
+ unsigned int cflag :1;
+#endif /* VJ_SUPPORT */
+ unsigned int accept_local :1; /* accept peer's value for ouraddr */
+ unsigned int accept_remote :1; /* accept peer's value for hisaddr */
+#if LWIP_DNS
+ unsigned int req_dns1 :1; /* Ask peer to send primary DNS address? */
+ unsigned int req_dns2 :1; /* Ask peer to send secondary DNS address? */
+#endif /* LWIP_DNS */
+
+ u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */
+#if LWIP_DNS
+ u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+ u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */
+#endif /* UNUSED - WINS */
+
+#if VJ_SUPPORT
+ u16_t vj_protocol; /* protocol value to use in VJ option */
+ u8_t maxslotindex; /* values for RFC1332 VJ compression neg. */
+#endif /* VJ_SUPPORT */
+} ipcp_options;
+
+#if 0 /* UNUSED, already defined by lwIP */
+char *ip_ntoa (u32_t);
+#endif /* UNUSED, already defined by lwIP */
+
+extern const struct protent ipcp_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IPCP_H */
+#endif /* PPP_SUPPORT && PPP_IPV4_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ipv6cp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ipv6cp.h
new file mode 100644
index 0000000..e668c74
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ipv6cp.h
@@ -0,0 +1,191 @@
+/*
+ * ipv6cp.h - PPP IPV6 Control Protocol.
+ *
+ * Copyright (c) 1999 Tommi Komulainen. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Tommi Komulainen
+ * ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/* Original version, based on RFC2023 :
+
+ Copyright (c) 1995, 1996, 1997 Francis.Dupont@inria.fr, INRIA Rocquencourt,
+ Alain.Durand@imag.fr, IMAG,
+ Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+ Copyright (c) 1998, 1999 Francis.Dupont@inria.fr, GIE DYADE,
+ Alain.Durand@imag.fr, IMAG,
+ Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+ Ce travail a été fait au sein du GIE DYADE (Groupement d'Intérêt
+ Économique ayant pour membres BULL S.A. et l'INRIA).
+
+ Ce logiciel informatique est disponible aux conditions
+ usuelles dans la recherche, c'est-à-dire qu'il peut
+ être utilisé, copié, modifié, distribué à l'unique
+ condition que ce texte soit conservé afin que
+ l'origine de ce logiciel soit reconnue.
+
+ Le nom de l'Institut National de Recherche en Informatique
+ et en Automatique (INRIA), de l'IMAG, ou d'une personne morale
+ ou physique ayant participé à l'élaboration de ce logiciel ne peut
+ être utilisé sans son accord préalable explicite.
+
+ Ce logiciel est fourni tel quel sans aucune garantie,
+ support ou responsabilité d'aucune sorte.
+ Ce logiciel est dérivé de sources d'origine
+ "University of California at Berkeley" et
+ "Digital Equipment Corporation" couvertes par des copyrights.
+
+ L'Institut d'Informatique et de Mathématiques Appliquées de Grenoble (IMAG)
+ est une fédération d'unités mixtes de recherche du CNRS, de l'Institut National
+ Polytechnique de Grenoble et de l'Université Joseph Fourier regroupant
+ sept laboratoires dont le laboratoire Logiciels, Systèmes, Réseaux (LSR).
+
+ This work has been done in the context of GIE DYADE (joint R & D venture
+ between BULL S.A. and INRIA).
+
+ This software is available with usual "research" terms
+ with the aim of retain credits of the software.
+ Permission to use, copy, modify and distribute this software for any
+ purpose and without fee is hereby granted, provided that the above
+ copyright notice and this permission notice appear in all copies,
+ and the name of INRIA, IMAG, or any contributor not be used in advertising
+ or publicity pertaining to this material without the prior explicit
+ permission. The software is provided "as is" without any
+ warranties, support or liabilities of any kind.
+ This software is derived from source code from
+ "University of California at Berkeley" and
+ "Digital Equipment Corporation" protected by copyrights.
+
+ Grenoble's Institute of Computer Science and Applied Mathematics (IMAG)
+ is a federation of seven research units funded by the CNRS, National
+ Polytechnic Institute of Grenoble and University Joseph Fourier.
+ The research unit in Software, Systems, Networks (LSR) is member of IMAG.
+*/
+
+/*
+ * Derived from :
+ *
+ *
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission. For permission or any legal
+ * details, please contact
+ * Office of Technology Transfer
+ * Carnegie Mellon University
+ * 5000 Forbes Avenue
+ * Pittsburgh, PA 15213-3890
+ * (412) 268-4387, fax: (412) 268-7395
+ * tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Computing Services
+ * at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ipv6cp.h,v 1.7 2002/12/04 23:03:32 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef IPV6CP_H
+#define IPV6CP_H
+
+#include "eui64.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Options.
+ */
+#define CI_IFACEID 1 /* Interface Identifier */
+#ifdef IPV6CP_COMP
+#define CI_COMPRESSTYPE 2 /* Compression Type */
+#endif /* IPV6CP_COMP */
+
+/* No compression types yet defined.
+ *#define IPV6CP_COMP 0x004f
+ */
+typedef struct ipv6cp_options {
+ unsigned int neg_ifaceid :1; /* Negotiate interface identifier? */
+ unsigned int req_ifaceid :1; /* Ask peer to send interface identifier? */
+ unsigned int accept_local :1; /* accept peer's value for iface id? */
+ unsigned int opt_local :1; /* ourtoken set by option */
+ unsigned int opt_remote :1; /* histoken set by option */
+ unsigned int use_ip :1; /* use IP as interface identifier */
+#if 0
+ unsigned int use_persistent :1; /* use uniquely persistent value for address */
+#endif
+#ifdef IPV6CP_COMP
+ unsigned int neg_vj :1; /* Van Jacobson Compression? */
+#endif /* IPV6CP_COMP */
+
+#ifdef IPV6CP_COMP
+ u_short vj_protocol; /* protocol value to use in VJ option */
+#endif /* IPV6CP_COMP */
+ eui64_t ourid, hisid; /* Interface identifiers */
+} ipv6cp_options;
+
+extern const struct protent ipv6cp_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IPV6CP_H */
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/lcp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/lcp.h
new file mode 100644
index 0000000..18ad1cb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/lcp.h
@@ -0,0 +1,179 @@
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission. For permission or any legal
+ * details, please contact
+ * Office of Technology Transfer
+ * Carnegie Mellon University
+ * 5000 Forbes Avenue
+ * Pittsburgh, PA 15213-3890
+ * (412) 268-4387, fax: (412) 268-7395
+ * tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Computing Services
+ * at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: lcp.h,v 1.20 2004/11/14 22:53:42 carlsonj Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef LCP_H
+#define LCP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Options.
+ */
+#define CI_VENDOR 0 /* Vendor Specific */
+#define CI_MRU 1 /* Maximum Receive Unit */
+#define CI_ASYNCMAP 2 /* Async Control Character Map */
+#define CI_AUTHTYPE 3 /* Authentication Type */
+#define CI_QUALITY 4 /* Quality Protocol */
+#define CI_MAGICNUMBER 5 /* Magic Number */
+#define CI_PCOMPRESSION 7 /* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */
+#define CI_FCSALTERN 9 /* FCS-Alternatives */
+#define CI_SDP 10 /* Self-Describing-Pad */
+#define CI_NUMBERED 11 /* Numbered-Mode */
+#define CI_CALLBACK 13 /* callback */
+#define CI_MRRU 17 /* max reconstructed receive unit; multilink */
+#define CI_SSNHF 18 /* short sequence numbers for multilink */
+#define CI_EPDISC 19 /* endpoint discriminator */
+#define CI_MPPLUS 22 /* Multi-Link-Plus-Procedure */
+#define CI_LDISC 23 /* Link-Discriminator */
+#define CI_LCPAUTH 24 /* LCP Authentication */
+#define CI_COBS 25 /* Consistent Overhead Byte Stuffing */
+#define CI_PREFELIS 26 /* Prefix Elision */
+#define CI_MPHDRFMT 27 /* MP Header Format */
+#define CI_I18N 28 /* Internationalization */
+#define CI_SDL 29 /* Simple Data Link */
+
+/*
+ * LCP-specific packet types (code numbers).
+ */
+#define PROTREJ 8 /* Protocol Reject */
+#define ECHOREQ 9 /* Echo Request */
+#define ECHOREP 10 /* Echo Reply */
+#define DISCREQ 11 /* Discard Request */
+#define IDENTIF 12 /* Identification */
+#define TIMEREM 13 /* Time Remaining */
+
+/* Value used as data for CI_CALLBACK option */
+#define CBCP_OPT 6 /* Use callback control protocol */
+
+#if 0 /* moved to ppp_opts.h */
+#define DEFMRU 1500 /* Try for this */
+#define MINMRU 128 /* No MRUs below this */
+#define MAXMRU 16384 /* Normally limit MRU to this */
+#endif /* moved to ppp_opts.h */
+
+/* An endpoint discriminator, used with multilink. */
+#define MAX_ENDP_LEN 20 /* maximum length of discriminator value */
+struct epdisc {
+ unsigned char class_; /* -- The word "class" is reserved in C++. */
+ unsigned char length;
+ unsigned char value[MAX_ENDP_LEN];
+};
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+ unsigned int passive :1; /* Don't die if we don't get a response */
+ unsigned int silent :1; /* Wait for the other end to start first */
+#if 0 /* UNUSED */
+ unsigned int restart :1; /* Restart vs. exit after close */
+#endif /* UNUSED */
+ unsigned int neg_mru :1; /* Negotiate the MRU? */
+ unsigned int neg_asyncmap :1; /* Negotiate the async map? */
+#if PAP_SUPPORT
+ unsigned int neg_upap :1; /* Ask for UPAP authentication? */
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+ unsigned int neg_chap :1; /* Ask for CHAP authentication? */
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+ unsigned int neg_eap :1; /* Ask for EAP authentication? */
+#endif /* EAP_SUPPORT */
+ unsigned int neg_magicnumber :1; /* Ask for magic number? */
+ unsigned int neg_pcompression :1; /* HDLC Protocol Field Compression? */
+ unsigned int neg_accompression :1; /* HDLC Address/Control Field Compression? */
+#if LQR_SUPPORT
+ unsigned int neg_lqr :1; /* Negotiate use of Link Quality Reports */
+#endif /* LQR_SUPPORT */
+ unsigned int neg_cbcp :1; /* Negotiate use of CBCP */
+#ifdef HAVE_MULTILINK
+ unsigned int neg_mrru :1; /* negotiate multilink MRRU */
+#endif /* HAVE_MULTILINK */
+ unsigned int neg_ssnhf :1; /* negotiate short sequence numbers */
+ unsigned int neg_endpoint :1; /* negotiate endpoint discriminator */
+
+ u16_t mru; /* Value of MRU */
+#ifdef HAVE_MULTILINK
+ u16_t mrru; /* Value of MRRU, and multilink enable */
+#endif /* MULTILINK */
+#if CHAP_SUPPORT
+ u8_t chap_mdtype; /* which MD types (hashing algorithm) */
+#endif /* CHAP_SUPPORT */
+ u32_t asyncmap; /* Value of async map */
+ u32_t magicnumber;
+ u8_t numloops; /* Number of loops during magic number neg. */
+#if LQR_SUPPORT
+ u32_t lqr_period; /* Reporting period for LQR 1/100ths second */
+#endif /* LQR_SUPPORT */
+ struct epdisc endpoint; /* endpoint discriminator */
+} lcp_options;
+
+void lcp_open(ppp_pcb *pcb);
+void lcp_close(ppp_pcb *pcb, const char *reason);
+void lcp_lowerup(ppp_pcb *pcb);
+void lcp_lowerdown(ppp_pcb *pcb);
+void lcp_sprotrej(ppp_pcb *pcb, u_char *p, int len); /* send protocol reject */
+
+extern const struct protent lcp_protent;
+
+#if 0 /* moved to ppp_opts.h */
+/* Default number of times we receive our magic number from the peer
+ before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL 10
+#endif /* moved to ppp_opts.h */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LCP_H */
+#endif /* PPP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/magic.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/magic.h
new file mode 100644
index 0000000..12a002c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/magic.h
@@ -0,0 +1,130 @@
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission. For permission or any legal
+ * details, please contact
+ * Office of Technology Transfer
+ * Carnegie Mellon University
+ * 5000 Forbes Avenue
+ * Pittsburgh, PA 15213-3890
+ * (412) 268-4387, fax: (412) 268-7395
+ * tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Computing Services
+ * at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: magic.h,v 1.5 2003/06/11 23:56:26 paulus Exp $
+ */
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher
+* Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+* Extracted from avos.
+*****************************************************************************/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/*
+ * Initialize the random number generator.
+ */
+void magic_init(void);
+
+/*
+ * Randomize our random seed value. To be called for truly random events
+ * such as user operations and network traffic.
+ */
+void magic_randomize(void);
+
+/*
+ * Return a new random number.
+ */
+u32_t magic(void); /* Returns the next magic number */
+
+/*
+ * Fill buffer with random bytes
+ *
+ * Use the random pool to generate random data. This degrades to pseudo
+ * random when used faster than randomness is supplied using magic_churnrand().
+ * Thus it's important to make sure that the results of this are not
+ * published directly because one could predict the next result to at
+ * least some degree. Also, it's important to get a good seed before
+ * the first use.
+ */
+void magic_random_bytes(unsigned char *buf, u32_t buf_len);
+
+/*
+ * Return a new random number between 0 and (2^pow)-1 included.
+ */
+u32_t magic_pow(u8_t pow);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MAGIC_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/mppe.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/mppe.h
new file mode 100644
index 0000000..5de1128
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/mppe.h
@@ -0,0 +1,181 @@
+/*
+ * mppe.h - Definitions for MPPE
+ *
+ * Copyright (c) 2008 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Paul Mackerras
+ * ".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && MPPE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef MPPE_H
+#define MPPE_H
+
+#include "netif/ppp/pppcrypt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MPPE_PAD 4 /* MPPE growth per frame */
+#define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */
+
+/* option bits for ccp_options.mppe */
+#define MPPE_OPT_40 0x01 /* 40 bit */
+#define MPPE_OPT_128 0x02 /* 128 bit */
+#define MPPE_OPT_STATEFUL 0x04 /* stateful mode */
+/* unsupported opts */
+#define MPPE_OPT_56 0x08 /* 56 bit */
+#define MPPE_OPT_MPPC 0x10 /* MPPC compression */
+#define MPPE_OPT_D 0x20 /* Unknown */
+#define MPPE_OPT_UNSUPPORTED (MPPE_OPT_56|MPPE_OPT_MPPC|MPPE_OPT_D)
+#define MPPE_OPT_UNKNOWN 0x40 /* Bits !defined in RFC 3078 were set */
+
+/*
+ * This is not nice ... the alternative is a bitfield struct though.
+ * And unfortunately, we cannot share the same bits for the option
+ * names above since C and H are the same bit. We could do a u_int32
+ * but then we have to do a lwip_htonl() all the time and/or we still need
+ * to know which octet is which.
+ */
+#define MPPE_C_BIT 0x01 /* MPPC */
+#define MPPE_D_BIT 0x10 /* Obsolete, usage unknown */
+#define MPPE_L_BIT 0x20 /* 40-bit */
+#define MPPE_S_BIT 0x40 /* 128-bit */
+#define MPPE_M_BIT 0x80 /* 56-bit, not supported */
+#define MPPE_H_BIT 0x01 /* Stateless (in a different byte) */
+
+/* Does not include H bit; used for least significant octet only. */
+#define MPPE_ALL_BITS (MPPE_D_BIT|MPPE_L_BIT|MPPE_S_BIT|MPPE_M_BIT|MPPE_H_BIT)
+
+/* Build a CI from mppe opts (see RFC 3078) */
+#define MPPE_OPTS_TO_CI(opts, ci) \
+ do { \
+ u_char *ptr = ci; /* u_char[4] */ \
+ \
+ /* H bit */ \
+ if (opts & MPPE_OPT_STATEFUL) \
+ *ptr++ = 0x0; \
+ else \
+ *ptr++ = MPPE_H_BIT; \
+ *ptr++ = 0; \
+ *ptr++ = 0; \
+ \
+ /* S,L bits */ \
+ *ptr = 0; \
+ if (opts & MPPE_OPT_128) \
+ *ptr |= MPPE_S_BIT; \
+ if (opts & MPPE_OPT_40) \
+ *ptr |= MPPE_L_BIT; \
+ /* M,D,C bits not supported */ \
+ } while (/* CONSTCOND */ 0)
+
+/* The reverse of the above */
+#define MPPE_CI_TO_OPTS(ci, opts) \
+ do { \
+ const u_char *ptr = ci; /* u_char[4] */ \
+ \
+ opts = 0; \
+ \
+ /* H bit */ \
+ if (!(ptr[0] & MPPE_H_BIT)) \
+ opts |= MPPE_OPT_STATEFUL; \
+ \
+ /* S,L bits */ \
+ if (ptr[3] & MPPE_S_BIT) \
+ opts |= MPPE_OPT_128; \
+ if (ptr[3] & MPPE_L_BIT) \
+ opts |= MPPE_OPT_40; \
+ \
+ /* M,D,C bits */ \
+ if (ptr[3] & MPPE_M_BIT) \
+ opts |= MPPE_OPT_56; \
+ if (ptr[3] & MPPE_D_BIT) \
+ opts |= MPPE_OPT_D; \
+ if (ptr[3] & MPPE_C_BIT) \
+ opts |= MPPE_OPT_MPPC; \
+ \
+ /* Other bits */ \
+ if (ptr[0] & ~MPPE_H_BIT) \
+ opts |= MPPE_OPT_UNKNOWN; \
+ if (ptr[1] || ptr[2]) \
+ opts |= MPPE_OPT_UNKNOWN; \
+ if (ptr[3] & ~MPPE_ALL_BITS) \
+ opts |= MPPE_OPT_UNKNOWN; \
+ } while (/* CONSTCOND */ 0)
+
+/* Shared MPPE padding between MSCHAP and MPPE */
+#define SHA1_PAD_SIZE 40
+
+static const u8_t mppe_sha1_pad1[SHA1_PAD_SIZE] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+static const u8_t mppe_sha1_pad2[SHA1_PAD_SIZE] = {
+ 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+ 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+ 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+ 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2
+};
+
+/*
+ * State for an MPPE (de)compressor.
+ */
+typedef struct ppp_mppe_state {
+ lwip_arc4_context arc4;
+ u8_t master_key[MPPE_MAX_KEY_LEN];
+ u8_t session_key[MPPE_MAX_KEY_LEN];
+ u8_t keylen; /* key length in bytes */
+ /* NB: 128-bit == 16, 40-bit == 8!
+ * If we want to support 56-bit, the unit has to change to bits
+ */
+ u8_t bits; /* MPPE control bits */
+ u16_t ccount; /* 12-bit coherency count (seqno) */
+ u16_t sanity_errors; /* take down LCP if too many */
+ unsigned int stateful :1; /* stateful mode flag */
+ unsigned int discard :1; /* stateful mode packet loss flag */
+} ppp_mppe_state;
+
+void mppe_set_key(ppp_pcb *pcb, ppp_mppe_state *state, u8_t *key);
+void mppe_init(ppp_pcb *pcb, ppp_mppe_state *state, u8_t options);
+void mppe_comp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
+err_t mppe_compress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb, u16_t protocol);
+void mppe_decomp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
+err_t mppe_decompress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MPPE_H */
+#endif /* PPP_SUPPORT && MPPE_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/arc4.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/arc4.h
new file mode 100644
index 0000000..91b08e6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/arc4.h
@@ -0,0 +1,81 @@
+/**
+ * \file arc4.h
+ *
+ * Based on XySSL: Copyright (C) 2006-2008 Christophe Devine
+ *
+ * Copyright (C) 2009 Paul Bakker
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_ARC4
+
+#ifndef LWIP_INCLUDED_POLARSSL_ARC4_H
+#define LWIP_INCLUDED_POLARSSL_ARC4_H
+
+/**
+ * \brief ARC4 context structure
+ */
+typedef struct
+{
+ int x; /*!< permutation index */
+ int y; /*!< permutation index */
+ unsigned char m[256]; /*!< permutation table */
+}
+arc4_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ARC4 key schedule
+ *
+ * \param ctx ARC4 context to be initialized
+ * \param key the secret key
+ * \param keylen length of the key
+ */
+void arc4_setup( arc4_context *ctx, unsigned char *key, int keylen );
+
+/**
+ * \brief ARC4 cipher function
+ *
+ * \param ctx ARC4 context
+ * \param buf buffer to be processed
+ * \param buflen amount of data in buf
+ */
+void arc4_crypt( arc4_context *ctx, unsigned char *buf, int buflen );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/des.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/des.h
new file mode 100644
index 0000000..5e3a085
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/des.h
@@ -0,0 +1,92 @@
+/**
+ * \file des.h
+ *
+ * Based on XySSL: Copyright (C) 2006-2008 Christophe Devine
+ *
+ * Copyright (C) 2009 Paul Bakker
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_DES
+
+#ifndef LWIP_INCLUDED_POLARSSL_DES_H
+#define LWIP_INCLUDED_POLARSSL_DES_H
+
+#define DES_ENCRYPT 1
+#define DES_DECRYPT 0
+
+/**
+ * \brief DES context structure
+ */
+typedef struct
+{
+ int mode; /*!< encrypt/decrypt */
+ unsigned long sk[32]; /*!< DES subkeys */
+}
+des_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief DES key schedule (56-bit, encryption)
+ *
+ * \param ctx DES context to be initialized
+ * \param key 8-byte secret key
+ */
+void des_setkey_enc( des_context *ctx, unsigned char key[8] );
+
+/**
+ * \brief DES key schedule (56-bit, decryption)
+ *
+ * \param ctx DES context to be initialized
+ * \param key 8-byte secret key
+ */
+void des_setkey_dec( des_context *ctx, unsigned char key[8] );
+
+/**
+ * \brief DES-ECB block encryption/decryption
+ *
+ * \param ctx DES context
+ * \param input 64-bit input block
+ * \param output 64-bit output block
+ */
+void des_crypt_ecb( des_context *ctx,
+ const unsigned char input[8],
+ unsigned char output[8] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_DES_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_DES */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md4.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md4.h
new file mode 100644
index 0000000..a4aa1dc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md4.h
@@ -0,0 +1,97 @@
+/**
+ * \file md4.h
+ *
+ * Based on XySSL: Copyright (C) 2006-2008 Christophe Devine
+ *
+ * Copyright (C) 2009 Paul Bakker
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_MD4
+
+#ifndef LWIP_INCLUDED_POLARSSL_MD4_H
+#define LWIP_INCLUDED_POLARSSL_MD4_H
+
+/**
+ * \brief MD4 context structure
+ */
+typedef struct
+{
+ unsigned long total[2]; /*!< number of bytes processed */
+ unsigned long state[4]; /*!< intermediate digest state */
+ unsigned char buffer[64]; /*!< data block being processed */
+}
+md4_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief MD4 context setup
+ *
+ * \param ctx context to be initialized
+ */
+void md4_starts( md4_context *ctx );
+
+/**
+ * \brief MD4 process buffer
+ *
+ * \param ctx MD4 context
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ */
+void md4_update( md4_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief MD4 final digest
+ *
+ * \param ctx MD4 context
+ * \param output MD4 checksum result
+ */
+void md4_finish( md4_context *ctx, unsigned char output[16] );
+
+/**
+ * \brief Output = MD4( input buffer )
+ *
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ * \param output MD4 checksum result
+ */
+void md4( unsigned char *input, int ilen, unsigned char output[16] );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD4_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md5.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md5.h
new file mode 100644
index 0000000..4d7b04d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md5.h
@@ -0,0 +1,96 @@
+/**
+ * \file md5.h
+ *
+ * Based on XySSL: Copyright (C) 2006-2008 Christophe Devine
+ *
+ * Copyright (C) 2009 Paul Bakker
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_MD5
+
+#ifndef LWIP_INCLUDED_POLARSSL_MD5_H
+#define LWIP_INCLUDED_POLARSSL_MD5_H
+
+/**
+ * \brief MD5 context structure
+ */
+typedef struct
+{
+ unsigned long total[2]; /*!< number of bytes processed */
+ unsigned long state[4]; /*!< intermediate digest state */
+ unsigned char buffer[64]; /*!< data block being processed */
+}
+md5_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief MD5 context setup
+ *
+ * \param ctx context to be initialized
+ */
+void md5_starts( md5_context *ctx );
+
+/**
+ * \brief MD5 process buffer
+ *
+ * \param ctx MD5 context
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ */
+void md5_update( md5_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief MD5 final digest
+ *
+ * \param ctx MD5 context
+ * \param output MD5 checksum result
+ */
+void md5_finish( md5_context *ctx, unsigned char output[16] );
+
+/**
+ * \brief Output = MD5( input buffer )
+ *
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ * \param output MD5 checksum result
+ */
+void md5( unsigned char *input, int ilen, unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD5_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/sha1.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/sha1.h
new file mode 100644
index 0000000..d8f347c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/sha1.h
@@ -0,0 +1,96 @@
+/**
+ * \file sha1.h
+ *
+ * Based on XySSL: Copyright (C) 2006-2008 Christophe Devine
+ *
+ * Copyright (C) 2009 Paul Bakker
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_SHA1
+
+#ifndef LWIP_INCLUDED_POLARSSL_SHA1_H
+#define LWIP_INCLUDED_POLARSSL_SHA1_H
+
+/**
+ * \brief SHA-1 context structure
+ */
+typedef struct
+{
+ unsigned long total[2]; /*!< number of bytes processed */
+ unsigned long state[5]; /*!< intermediate digest state */
+ unsigned char buffer[64]; /*!< data block being processed */
+}
+sha1_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief SHA-1 context setup
+ *
+ * \param ctx context to be initialized
+ */
+void sha1_starts( sha1_context *ctx );
+
+/**
+ * \brief SHA-1 process buffer
+ *
+ * \param ctx SHA-1 context
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ */
+void sha1_update( sha1_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief SHA-1 final digest
+ *
+ * \param ctx SHA-1 context
+ * \param output SHA-1 checksum result
+ */
+void sha1_finish( sha1_context *ctx, unsigned char output[20] );
+
+/**
+ * \brief Output = SHA-1( input buffer )
+ *
+ * \param input buffer holding the data
+ * \param ilen length of the input data
+ * \param output SHA-1 checksum result
+ */
+void sha1( unsigned char *input, int ilen, unsigned char output[20] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp.h
new file mode 100644
index 0000000..26ba7a3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp.h
@@ -0,0 +1,698 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher
+* Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+* Original derived from BSD codes.
+*****************************************************************************/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/netif.h"
+#include "lwip/sys.h"
+#include "lwip/timeouts.h"
+#if PPP_IPV6_SUPPORT
+#include "lwip/ip6_addr.h"
+#endif /* PPP_IPV6_SUPPORT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Disable non-working or rarely used PPP feature, so rarely that we don't want to bloat ppp_opts.h with them */
+#ifndef PPP_OPTIONS
+#define PPP_OPTIONS 0
+#endif
+
+#ifndef PPP_NOTIFY
+#define PPP_NOTIFY 0
+#endif
+
+#ifndef PPP_REMOTENAME
+#define PPP_REMOTENAME 0
+#endif
+
+#ifndef PPP_IDLETIMELIMIT
+#define PPP_IDLETIMELIMIT 0
+#endif
+
+#ifndef PPP_LCP_ADAPTIVE
+#define PPP_LCP_ADAPTIVE 0
+#endif
+
+#ifndef PPP_MAXCONNECT
+#define PPP_MAXCONNECT 0
+#endif
+
+#ifndef PPP_ALLOWED_ADDRS
+#define PPP_ALLOWED_ADDRS 0
+#endif
+
+#ifndef PPP_PROTOCOLNAME
+#define PPP_PROTOCOLNAME 0
+#endif
+
+#ifndef PPP_STATS_SUPPORT
+#define PPP_STATS_SUPPORT 0
+#endif
+
+#ifndef DEFLATE_SUPPORT
+#define DEFLATE_SUPPORT 0
+#endif
+
+#ifndef BSDCOMPRESS_SUPPORT
+#define BSDCOMPRESS_SUPPORT 0
+#endif
+
+#ifndef PREDICTOR_SUPPORT
+#define PREDICTOR_SUPPORT 0
+#endif
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN 4 /* octets for standard ppp header */
+#define PPP_FCSLEN 2 /* octets for FCS */
+
+/*
+ * Values for phase.
+ */
+#define PPP_PHASE_DEAD 0
+#define PPP_PHASE_MASTER 1
+#define PPP_PHASE_HOLDOFF 2
+#define PPP_PHASE_INITIALIZE 3
+#define PPP_PHASE_SERIALCONN 4
+#define PPP_PHASE_DORMANT 5
+#define PPP_PHASE_ESTABLISH 6
+#define PPP_PHASE_AUTHENTICATE 7
+#define PPP_PHASE_CALLBACK 8
+#define PPP_PHASE_NETWORK 9
+#define PPP_PHASE_RUNNING 10
+#define PPP_PHASE_TERMINATE 11
+#define PPP_PHASE_DISCONNECT 12
+
+/* Error codes. */
+#define PPPERR_NONE 0 /* No error. */
+#define PPPERR_PARAM 1 /* Invalid parameter. */
+#define PPPERR_OPEN 2 /* Unable to open PPP session. */
+#define PPPERR_DEVICE 3 /* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC 4 /* Unable to allocate resources. */
+#define PPPERR_USER 5 /* User interrupt. */
+#define PPPERR_CONNECT 6 /* Connection lost. */
+#define PPPERR_AUTHFAIL 7 /* Failed authentication challenge. */
+#define PPPERR_PROTOCOL 8 /* Failed to meet protocol. */
+#define PPPERR_PEERDEAD 9 /* Connection timeout */
+#define PPPERR_IDLETIMEOUT 10 /* Idle Timeout */
+#define PPPERR_CONNECTTIME 11 /* Max connect time reached */
+#define PPPERR_LOOPBACK 12 /* Loopback detected */
+
+/* Whether auth support is enabled at all */
+#define PPP_AUTH_SUPPORT (PAP_SUPPORT || CHAP_SUPPORT || EAP_SUPPORT)
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Other headers require ppp_pcb definition for prototypes, but ppp_pcb
+ * require some structure definition from other headers as well, we are
+ * fixing the dependency loop here by declaring the ppp_pcb type then
+ * by including headers containing necessary struct definition for ppp_pcb
+ */
+typedef struct ppp_pcb_s ppp_pcb;
+
+/* Type definitions for BSD code. */
+#ifndef __u_char_defined
+typedef unsigned long u_long;
+typedef unsigned int u_int;
+typedef unsigned short u_short;
+typedef unsigned char u_char;
+#endif
+
+#include "fsm.h"
+#include "lcp.h"
+#if CCP_SUPPORT
+#include "ccp.h"
+#endif /* CCP_SUPPORT */
+#if MPPE_SUPPORT
+#include "mppe.h"
+#endif /* MPPE_SUPPORT */
+#if PPP_IPV4_SUPPORT
+#include "ipcp.h"
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+#include "ipv6cp.h"
+#endif /* PPP_IPV6_SUPPORT */
+#if PAP_SUPPORT
+#include "upap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "chap-new.h"
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#include "eap.h"
+#endif /* EAP_SUPPORT */
+#if VJ_SUPPORT
+#include "vj.h"
+#endif /* VJ_SUPPORT */
+
+/* Link status callback function prototype */
+typedef void (*ppp_link_status_cb_fn)(ppp_pcb *pcb, int err_code, void *ctx);
+
+/*
+ * PPP configuration.
+ */
+typedef struct ppp_settings_s {
+
+#if PPP_SERVER && PPP_AUTH_SUPPORT
+ unsigned int auth_required :1; /* Peer is required to authenticate */
+ unsigned int null_login :1; /* Username of "" and a password of "" are acceptable */
+#endif /* PPP_SERVER && PPP_AUTH_SUPPORT */
+#if PPP_REMOTENAME
+ unsigned int explicit_remote :1; /* remote_name specified with remotename opt */
+#endif /* PPP_REMOTENAME */
+#if PAP_SUPPORT
+ unsigned int refuse_pap :1; /* Don't proceed auth. with PAP */
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+ unsigned int refuse_chap :1; /* Don't proceed auth. with CHAP */
+#endif /* CHAP_SUPPORT */
+#if MSCHAP_SUPPORT
+ unsigned int refuse_mschap :1; /* Don't proceed auth. with MS-CHAP */
+ unsigned int refuse_mschap_v2 :1; /* Don't proceed auth. with MS-CHAPv2 */
+#endif /* MSCHAP_SUPPORT */
+#if EAP_SUPPORT
+ unsigned int refuse_eap :1; /* Don't proceed auth. with EAP */
+#endif /* EAP_SUPPORT */
+#if LWIP_DNS
+ unsigned int usepeerdns :1; /* Ask peer for DNS adds */
+#endif /* LWIP_DNS */
+ unsigned int persist :1; /* Persist mode, always try to open the connection */
+#if PRINTPKT_SUPPORT
+ unsigned int hide_password :1; /* Hide password in dumped packets */
+#endif /* PRINTPKT_SUPPORT */
+ unsigned int noremoteip :1; /* Let him have no IP address */
+ unsigned int lax_recv :1; /* accept control chars in asyncmap */
+ unsigned int noendpoint :1; /* don't send/accept endpoint discriminator */
+#if PPP_LCP_ADAPTIVE
+ unsigned int lcp_echo_adaptive :1; /* request echo only if the link was idle */
+#endif /* PPP_LCP_ADAPTIVE */
+#if MPPE_SUPPORT
+ unsigned int require_mppe :1; /* Require MPPE (Microsoft Point to Point Encryption) */
+ unsigned int refuse_mppe_40 :1; /* Allow MPPE 40-bit mode? */
+ unsigned int refuse_mppe_128 :1; /* Allow MPPE 128-bit mode? */
+ unsigned int refuse_mppe_stateful :1; /* Allow MPPE stateful mode? */
+#endif /* MPPE_SUPPORT */
+
+ u16_t listen_time; /* time to listen first (ms), waiting for peer to send LCP packet */
+
+#if PPP_IDLETIMELIMIT
+ u16_t idle_time_limit; /* Disconnect if idle for this many seconds */
+#endif /* PPP_IDLETIMELIMIT */
+#if PPP_MAXCONNECT
+ u32_t maxconnect; /* Maximum connect time (seconds) */
+#endif /* PPP_MAXCONNECT */
+
+#if PPP_AUTH_SUPPORT
+ /* auth data */
+ const char *user; /* Username for PAP */
+ const char *passwd; /* Password for PAP, secret for CHAP */
+#if PPP_REMOTENAME
+ char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */
+#endif /* PPP_REMOTENAME */
+
+#if PAP_SUPPORT
+ u8_t pap_timeout_time; /* Timeout (seconds) for auth-req retrans. */
+ u8_t pap_max_transmits; /* Number of auth-reqs sent */
+#if PPP_SERVER
+ u8_t pap_req_timeout; /* Time to wait for auth-req from peer */
+#endif /* PPP_SERVER */
+#endif /* PAP_SUPPPORT */
+
+#if CHAP_SUPPORT
+ u8_t chap_timeout_time; /* Timeout (seconds) for retransmitting req */
+ u8_t chap_max_transmits; /* max # times to send challenge */
+#if PPP_SERVER
+ u8_t chap_rechallenge_time; /* Time to wait for auth-req from peer */
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPPORT */
+
+#if EAP_SUPPORT
+ u8_t eap_req_time; /* Time to wait (for retransmit/fail) */
+ u8_t eap_allow_req; /* Max Requests allowed */
+#if PPP_SERVER
+ u8_t eap_timeout_time; /* Time to wait (for retransmit/fail) */
+ u8_t eap_max_transmits; /* Max Requests allowed */
+#endif /* PPP_SERVER */
+#endif /* EAP_SUPPORT */
+
+#endif /* PPP_AUTH_SUPPORT */
+
+ u8_t fsm_timeout_time; /* Timeout time in seconds */
+ u8_t fsm_max_conf_req_transmits; /* Maximum Configure-Request transmissions */
+ u8_t fsm_max_term_transmits; /* Maximum Terminate-Request transmissions */
+ u8_t fsm_max_nak_loops; /* Maximum number of nak loops tolerated */
+
+ u8_t lcp_loopbackfail; /* Number of times we receive our magic number from the peer
+ before deciding the link is looped-back. */
+ u8_t lcp_echo_interval; /* Interval between LCP echo-requests */
+ u8_t lcp_echo_fails; /* Tolerance to unanswered echo-requests */
+
+} ppp_settings;
+
+#if PPP_SERVER
+struct ppp_addrs {
+#if PPP_IPV4_SUPPORT
+ ip4_addr_t our_ipaddr, his_ipaddr, netmask;
+#if LWIP_DNS
+ ip4_addr_t dns1, dns2;
+#endif /* LWIP_DNS */
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+ ip6_addr_t our6_ipaddr, his6_ipaddr;
+#endif /* PPP_IPV6_SUPPORT */
+};
+#endif /* PPP_SERVER */
+
+/*
+ * PPP interface control block.
+ */
+struct ppp_pcb_s {
+ ppp_settings settings;
+ const struct link_callbacks *link_cb;
+ void *link_ctx_cb;
+ void (*link_status_cb)(ppp_pcb *pcb, int err_code, void *ctx); /* Status change callback */
+#if PPP_NOTIFY_PHASE
+ void (*notify_phase_cb)(ppp_pcb *pcb, u8_t phase, void *ctx); /* Notify phase callback */
+#endif /* PPP_NOTIFY_PHASE */
+ void *ctx_cb; /* Callbacks optional pointer */
+ struct netif *netif; /* PPP interface */
+ u8_t phase; /* where the link is at */
+ u8_t err_code; /* Code indicating why interface is down. */
+
+ /* flags */
+#if PPP_IPV4_SUPPORT
+ unsigned int ask_for_local :1; /* request our address from peer */
+ unsigned int ipcp_is_open :1; /* haven't called np_finished() */
+ unsigned int ipcp_is_up :1; /* have called ipcp_up() */
+ unsigned int if4_up :1; /* True when the IPv4 interface is up. */
+#if 0 /* UNUSED - PROXY ARP */
+ unsigned int proxy_arp_set :1; /* Have created proxy arp entry */
+#endif /* UNUSED - PROXY ARP */
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+ unsigned int ipv6cp_is_up :1; /* have called ip6cp_up() */
+ unsigned int if6_up :1; /* True when the IPv6 interface is up. */
+#endif /* PPP_IPV6_SUPPORT */
+ unsigned int lcp_echo_timer_running :1; /* set if a timer is running */
+#if VJ_SUPPORT
+ unsigned int vj_enabled :1; /* Flag indicating VJ compression enabled. */
+#endif /* VJ_SUPPORT */
+#if CCP_SUPPORT
+ unsigned int ccp_all_rejected :1; /* we rejected all peer's options */
+#endif /* CCP_SUPPORT */
+#if MPPE_SUPPORT
+ unsigned int mppe_keys_set :1; /* Have the MPPE keys been set? */
+#endif /* MPPE_SUPPORT */
+
+#if PPP_AUTH_SUPPORT
+ /* auth data */
+#if PPP_SERVER && defined(HAVE_MULTILINK)
+ char peer_authname[MAXNAMELEN + 1]; /* The name by which the peer authenticated itself to us. */
+#endif /* PPP_SERVER && defined(HAVE_MULTILINK) */
+ u16_t auth_pending; /* Records which authentication operations haven't completed yet. */
+ u16_t auth_done; /* Records which authentication operations have been completed. */
+
+#if PAP_SUPPORT
+ upap_state upap; /* PAP data */
+#endif /* PAP_SUPPORT */
+
+#if CHAP_SUPPORT
+ chap_client_state chap_client; /* CHAP client data */
+#if PPP_SERVER
+ chap_server_state chap_server; /* CHAP server data */
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPORT */
+
+#if EAP_SUPPORT
+ eap_state eap; /* EAP data */
+#endif /* EAP_SUPPORT */
+#endif /* PPP_AUTH_SUPPORT */
+
+ fsm lcp_fsm; /* LCP fsm structure */
+ lcp_options lcp_wantoptions; /* Options that we want to request */
+ lcp_options lcp_gotoptions; /* Options that peer ack'd */
+ lcp_options lcp_allowoptions; /* Options we allow peer to request */
+ lcp_options lcp_hisoptions; /* Options that we ack'd */
+ u16_t peer_mru; /* currently negotiated peer MRU */
+ u8_t lcp_echos_pending; /* Number of outstanding echo msgs */
+ u8_t lcp_echo_number; /* ID number of next echo frame */
+
+ u8_t num_np_open; /* Number of network protocols which we have opened. */
+ u8_t num_np_up; /* Number of network protocols which have come up. */
+
+#if VJ_SUPPORT
+ struct vjcompress vj_comp; /* Van Jacobson compression header. */
+#endif /* VJ_SUPPORT */
+
+#if CCP_SUPPORT
+ fsm ccp_fsm; /* CCP fsm structure */
+ ccp_options ccp_wantoptions; /* what to request the peer to use */
+ ccp_options ccp_gotoptions; /* what the peer agreed to do */
+ ccp_options ccp_allowoptions; /* what we'll agree to do */
+ ccp_options ccp_hisoptions; /* what we agreed to do */
+ u8_t ccp_localstate; /* Local state (mainly for handling reset-reqs and reset-acks). */
+ u8_t ccp_receive_method; /* Method chosen on receive path */
+ u8_t ccp_transmit_method; /* Method chosen on transmit path */
+#if MPPE_SUPPORT
+ ppp_mppe_state mppe_comp; /* MPPE "compressor" structure */
+ ppp_mppe_state mppe_decomp; /* MPPE "decompressor" structure */
+#endif /* MPPE_SUPPORT */
+#endif /* CCP_SUPPORT */
+
+#if PPP_IPV4_SUPPORT
+ fsm ipcp_fsm; /* IPCP fsm structure */
+ ipcp_options ipcp_wantoptions; /* Options that we want to request */
+ ipcp_options ipcp_gotoptions; /* Options that peer ack'd */
+ ipcp_options ipcp_allowoptions; /* Options we allow peer to request */
+ ipcp_options ipcp_hisoptions; /* Options that we ack'd */
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+ fsm ipv6cp_fsm; /* IPV6CP fsm structure */
+ ipv6cp_options ipv6cp_wantoptions; /* Options that we want to request */
+ ipv6cp_options ipv6cp_gotoptions; /* Options that peer ack'd */
+ ipv6cp_options ipv6cp_allowoptions; /* Options we allow peer to request */
+ ipv6cp_options ipv6cp_hisoptions; /* Options that we ack'd */
+#endif /* PPP_IPV6_SUPPORT */
+};
+
+/************************
+ *** PUBLIC FUNCTIONS ***
+ ************************/
+
+/*
+ * WARNING: For multi-threads environment, all ppp_set_* functions most
+ * only be called while the PPP is in the dead phase (i.e. disconnected).
+ */
+
+#if PPP_AUTH_SUPPORT
+/*
+ * Set PPP authentication.
+ *
+ * Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets"). It is not anticipated that a particular
+ * named user would be authenticated by multiple methods. This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP). If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name. If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ * Default is none auth type, unset (NULL) user and passwd.
+ */
+#define PPPAUTHTYPE_NONE 0x00
+#define PPPAUTHTYPE_PAP 0x01
+#define PPPAUTHTYPE_CHAP 0x02
+#define PPPAUTHTYPE_MSCHAP 0x04
+#define PPPAUTHTYPE_MSCHAP_V2 0x08
+#define PPPAUTHTYPE_EAP 0x10
+#define PPPAUTHTYPE_ANY 0xff
+void ppp_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd);
+
+/*
+ * If set, peer is required to authenticate. This is mostly necessary for PPP server support.
+ *
+ * Default is false.
+ */
+#define ppp_set_auth_required(ppp, boolval) (ppp->settings.auth_required = boolval)
+#endif /* PPP_AUTH_SUPPORT */
+
+#if PPP_IPV4_SUPPORT
+/*
+ * Set PPP interface "our" and "his" IPv4 addresses. This is mostly necessary for PPP server
+ * support but it can also be used on a PPP link where each side choose its own IP address.
+ *
+ * Default is unset (0.0.0.0).
+ */
+#define ppp_set_ipcp_ouraddr(ppp, addr) do { ppp->ipcp_wantoptions.ouraddr = ip4_addr_get_u32(addr); \
+ ppp->ask_for_local = ppp->ipcp_wantoptions.ouraddr != 0; } while(0)
+#define ppp_set_ipcp_hisaddr(ppp, addr) (ppp->ipcp_wantoptions.hisaddr = ip4_addr_get_u32(addr))
+#if LWIP_DNS
+/*
+ * Set DNS server addresses that are sent if the peer asks for them. This is mostly necessary
+ * for PPP server support.
+ *
+ * Default is unset (0.0.0.0).
+ */
+#define ppp_set_ipcp_dnsaddr(ppp, index, addr) (ppp->ipcp_allowoptions.dnsaddr[index] = ip4_addr_get_u32(addr))
+
+/*
+ * If set, we ask the peer for up to 2 DNS server addresses. Received DNS server addresses are
+ * registered using the dns_setserver() function.
+ *
+ * Default is false.
+ */
+#define ppp_set_usepeerdns(ppp, boolval) (ppp->settings.usepeerdns = boolval)
+#endif /* LWIP_DNS */
+#endif /* PPP_IPV4_SUPPORT */
+
+#if MPPE_SUPPORT
+/* Disable MPPE (Microsoft Point to Point Encryption). This parameter is exclusive. */
+#define PPP_MPPE_DISABLE 0x00
+/* Require the use of MPPE (Microsoft Point to Point Encryption). */
+#define PPP_MPPE_ENABLE 0x01
+/* Allow MPPE to use stateful mode. Stateless mode is still attempted first. */
+#define PPP_MPPE_ALLOW_STATEFUL 0x02
+/* Refuse the use of MPPE with 40-bit encryption. Conflict with PPP_MPPE_REFUSE_128. */
+#define PPP_MPPE_REFUSE_40 0x04
+/* Refuse the use of MPPE with 128-bit encryption. Conflict with PPP_MPPE_REFUSE_40. */
+#define PPP_MPPE_REFUSE_128 0x08
+/*
+ * Set MPPE configuration
+ *
+ * Default is disabled.
+ */
+void ppp_set_mppe(ppp_pcb *pcb, u8_t flags);
+#endif /* MPPE_SUPPORT */
+
+/*
+ * Wait for up to intval milliseconds for a valid PPP packet from the peer.
+ * At the end of this time, or when a valid PPP packet is received from the
+ * peer, we commence negotiation by sending our first LCP packet.
+ *
+ * Default is 0.
+ */
+#define ppp_set_listen_time(ppp, intval) (ppp->settings.listen_time = intval)
+
+/*
+ * If set, we will attempt to initiate a connection but if no reply is received from
+ * the peer, we will then just wait passively for a valid LCP packet from the peer.
+ *
+ * Default is false.
+ */
+#define ppp_set_passive(ppp, boolval) (ppp->lcp_wantoptions.passive = boolval)
+
+/*
+ * If set, we will not transmit LCP packets to initiate a connection until a valid
+ * LCP packet is received from the peer. This is what we usually call the server mode.
+ *
+ * Default is false.
+ */
+#define ppp_set_silent(ppp, boolval) (ppp->lcp_wantoptions.silent = boolval)
+
+/*
+ * If set, enable protocol field compression negotiation in both the receive and
+ * the transmit direction.
+ *
+ * Default is true.
+ */
+#define ppp_set_neg_pcomp(ppp, boolval) (ppp->lcp_wantoptions.neg_pcompression = \
+ ppp->lcp_allowoptions.neg_pcompression = boolval)
+
+/*
+ * If set, enable Address/Control compression in both the receive and the transmit
+ * direction.
+ *
+ * Default is true.
+ */
+#define ppp_set_neg_accomp(ppp, boolval) (ppp->lcp_wantoptions.neg_accompression = \
+ ppp->lcp_allowoptions.neg_accompression = boolval)
+
+/*
+ * If set, enable asyncmap negotiation. Otherwise forcing all control characters to
+ * be escaped for both the transmit and the receive direction.
+ *
+ * Default is true.
+ */
+#define ppp_set_neg_asyncmap(ppp, boolval) (ppp->lcp_wantoptions.neg_asyncmap = \
+ ppp->lcp_allowoptions.neg_asyncmap = boolval)
+
+/*
+ * This option sets the Async-Control-Character-Map (ACCM) for this end of the link.
+ * The ACCM is a set of 32 bits, one for each of the ASCII control characters with
+ * values from 0 to 31, where a 1 bit indicates that the corresponding control
+ * character should not be used in PPP packets sent to this system. The map is
+ * an unsigned 32 bits integer where the least significant bit (00000001) represents
+ * character 0 and the most significant bit (80000000) represents character 31.
+ * We will then ask the peer to send these characters as a 2-byte escape sequence.
+ *
+ * Default is 0.
+ */
+#define ppp_set_asyncmap(ppp, intval) (ppp->lcp_wantoptions.asyncmap = intval)
+
+/*
+ * Set a PPP interface as the default network interface
+ * (used to output all packets for which no specific route is found).
+ */
+#define ppp_set_default(ppp) netif_set_default(ppp->netif)
+
+#if PPP_NOTIFY_PHASE
+/*
+ * Set a PPP notify phase callback.
+ *
+ * This can be used for example to set a LED pattern depending on the
+ * current phase of the PPP session.
+ */
+typedef void (*ppp_notify_phase_cb_fn)(ppp_pcb *pcb, u8_t phase, void *ctx);
+void ppp_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
+#endif /* PPP_NOTIFY_PHASE */
+
+/*
+ * Initiate a PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * Holdoff is the time to wait (in seconds) before initiating
+ * the connection.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_connect(ppp_pcb *pcb, u16_t holdoff);
+
+#if PPP_SERVER
+/*
+ * Listen for an incoming PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_listen(ppp_pcb *pcb);
+#endif /* PPP_SERVER */
+
+/*
+ * Initiate the end of a PPP connection.
+ * Any outstanding packets in the queues are dropped.
+ *
+ * Setting nocarrier to 1 close the PPP connection without initiating the
+ * shutdown procedure. Always using nocarrier = 0 is still recommended,
+ * this is going to take a little longer time if your link is down, but
+ * is a safer choice for the PPP state machine.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_close(ppp_pcb *pcb, u8_t nocarrier);
+
+/*
+ * Release the control block.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * You must use ppp_close() before if you wish to terminate
+ * an established PPP session.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_free(ppp_pcb *pcb);
+
+/*
+ * PPP IOCTL commands.
+ *
+ * Get the up status - 0 for down, non-zero for up. The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 0
+
+/*
+ * Get the PPP error code. The argument must point to an int.
+ * Returns a PPPERR_* value.
+ */
+#define PPPCTLG_ERRCODE 1
+
+/*
+ * Get the fd associated with a PPP over serial
+ */
+#define PPPCTLG_FD 2
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
+
+/* Get the PPP netif interface */
+#define ppp_netif(ppp) (ppp->netif)
+
+/* Set an lwIP-style status-callback for the selected PPP device */
+#define ppp_set_netif_statuscallback(ppp, status_cb) \
+ netif_set_status_callback(ppp->netif, status_cb);
+
+/* Set an lwIP-style link-callback for the selected PPP device */
+#define ppp_set_netif_linkcallback(ppp, link_cb) \
+ netif_set_link_callback(ppp->netif, link_cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPP_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp_impl.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp_impl.h
new file mode 100644
index 0000000..51ee422
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp_impl.h
@@ -0,0 +1,722 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher
+* Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+* Original derived from BSD codes.
+*****************************************************************************/
+#ifndef LWIP_HDR_PPP_IMPL_H
+#define LWIP_HDR_PPP_IMPL_H
+
+#include "netif/ppp/ppp_opts.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifdef PPP_INCLUDE_SETTINGS_HEADER
+#include "ppp_settings.h"
+#endif
+
+#include /* formats */
+#include
+#include
+#include /* strtol() */
+
+#include "lwip/netif.h"
+#include "lwip/def.h"
+#include "lwip/timeouts.h"
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Memory used for control packets.
+ *
+ * PPP_CTRL_PBUF_MAX_SIZE is the amount of memory we allocate when we
+ * cannot figure out how much we are going to use before filling the buffer.
+ */
+#if PPP_USE_PBUF_RAM
+#define PPP_CTRL_PBUF_TYPE PBUF_RAM
+#define PPP_CTRL_PBUF_MAX_SIZE 512
+#else /* PPP_USE_PBUF_RAM */
+#define PPP_CTRL_PBUF_TYPE PBUF_POOL
+#define PPP_CTRL_PBUF_MAX_SIZE PBUF_POOL_BUFSIZE
+#endif /* PPP_USE_PBUF_RAM */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p) (((u_char *)(p))[0])
+#define PPP_CONTROL(p) (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */
+#define PPP_UI 0x03 /* Unnumbered Information */
+#define PPP_FLAG 0x7e /* Flag Sequence */
+#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */
+#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP 0x21 /* Internet Protocol */
+#if 0 /* UNUSED */
+#define PPP_AT 0x29 /* AppleTalk Protocol */
+#define PPP_IPX 0x2b /* IPX protocol */
+#endif /* UNUSED */
+#if VJ_SUPPORT
+#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */
+#endif /* VJ_SUPPORT */
+#if PPP_IPV6_SUPPORT
+#define PPP_IPV6 0x57 /* Internet Protocol Version 6 */
+#endif /* PPP_IPV6_SUPPORT */
+#if CCP_SUPPORT
+#define PPP_COMP 0xfd /* compressed packet */
+#endif /* CCP_SUPPORT */
+#define PPP_IPCP 0x8021 /* IP Control Protocol */
+#if 0 /* UNUSED */
+#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */
+#define PPP_IPXCP 0x802b /* IPX Control Protocol */
+#endif /* UNUSED */
+#if PPP_IPV6_SUPPORT
+#define PPP_IPV6CP 0x8057 /* IPv6 Control Protocol */
+#endif /* PPP_IPV6_SUPPORT */
+#if CCP_SUPPORT
+#define PPP_CCP 0x80fd /* Compression Control Protocol */
+#endif /* CCP_SUPPORT */
+#if ECP_SUPPORT
+#define PPP_ECP 0x8053 /* Encryption Control Protocol */
+#endif /* ECP_SUPPORT */
+#define PPP_LCP 0xc021 /* Link Control Protocol */
+#if PAP_SUPPORT
+#define PPP_PAP 0xc023 /* Password Authentication Protocol */
+#endif /* PAP_SUPPORT */
+#if LQR_SUPPORT
+#define PPP_LQR 0xc025 /* Link Quality Report protocol */
+#endif /* LQR_SUPPORT */
+#if CHAP_SUPPORT
+#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */
+#endif /* CHAP_SUPPORT */
+#if CBCP_SUPPORT
+#define PPP_CBCP 0xc029 /* Callback Control Protocol */
+#endif /* CBCP_SUPPORT */
+#if EAP_SUPPORT
+#define PPP_EAP 0xc227 /* Extensible Authentication Protocol */
+#endif /* EAP_SUPPORT */
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular lower link level protocol.
+ */
+struct link_callbacks {
+ /* Start a connection (e.g. Initiate discovery phase) */
+ void (*connect) (ppp_pcb *pcb, void *ctx);
+#if PPP_SERVER
+ /* Listen for an incoming connection (Passive mode) */
+ void (*listen) (ppp_pcb *pcb, void *ctx);
+#endif /* PPP_SERVER */
+ /* End a connection (i.e. initiate disconnect phase) */
+ void (*disconnect) (ppp_pcb *pcb, void *ctx);
+ /* Free lower protocol control block */
+ err_t (*free) (ppp_pcb *pcb, void *ctx);
+ /* Write a pbuf to a ppp link, only used from PPP functions to send PPP packets. */
+ err_t (*write)(ppp_pcb *pcb, void *ctx, struct pbuf *p);
+ /* Send a packet from lwIP core (IPv4 or IPv6) */
+ err_t (*netif_output)(ppp_pcb *pcb, void *ctx, struct pbuf *p, u_short protocol);
+ /* configure the transmit-side characteristics of the PPP interface */
+ void (*send_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
+ /* confire the receive-side characteristics of the PPP interface */
+ void (*recv_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
+};
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+ NPMODE_PASS, /* pass the packet through */
+ NPMODE_DROP, /* silently drop the packet */
+ NPMODE_ERROR, /* return an error */
+ NPMODE_QUEUE /* save it up for later. */
+};
+
+/*
+ * Statistics.
+ */
+#if PPP_STATS_SUPPORT
+struct pppstat {
+ unsigned int ppp_ibytes; /* bytes received */
+ unsigned int ppp_ipackets; /* packets received */
+ unsigned int ppp_ierrors; /* receive errors */
+ unsigned int ppp_obytes; /* bytes sent */
+ unsigned int ppp_opackets; /* packets sent */
+ unsigned int ppp_oerrors; /* transmit errors */
+};
+
+#if VJ_SUPPORT
+struct vjstat {
+ unsigned int vjs_packets; /* outbound packets */
+ unsigned int vjs_compressed; /* outbound compressed packets */
+ unsigned int vjs_searches; /* searches for connection state */
+ unsigned int vjs_misses; /* times couldn't find conn. state */
+ unsigned int vjs_uncompressedin; /* inbound uncompressed packets */
+ unsigned int vjs_compressedin; /* inbound compressed packets */
+ unsigned int vjs_errorin; /* inbound unknown type packets */
+ unsigned int vjs_tossed; /* inbound packets tossed because of error */
+};
+#endif /* VJ_SUPPORT */
+
+struct ppp_stats {
+ struct pppstat p; /* basic PPP statistics */
+#if VJ_SUPPORT
+ struct vjstat vj; /* VJ header compression statistics */
+#endif /* VJ_SUPPORT */
+};
+
+#if CCP_SUPPORT
+struct compstat {
+ unsigned int unc_bytes; /* total uncompressed bytes */
+ unsigned int unc_packets; /* total uncompressed packets */
+ unsigned int comp_bytes; /* compressed bytes */
+ unsigned int comp_packets; /* compressed packets */
+ unsigned int inc_bytes; /* incompressible bytes */
+ unsigned int inc_packets; /* incompressible packets */
+ unsigned int ratio; /* recent compression ratio << 8 */
+};
+
+struct ppp_comp_stats {
+ struct compstat c; /* packet compression statistics */
+ struct compstat d; /* packet decompression statistics */
+};
+#endif /* CCP_SUPPORT */
+
+#endif /* PPP_STATS_SUPPORT */
+
+#if PPP_IDLETIMELIMIT
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+ time_t xmit_idle; /* time since last NP packet sent */
+ time_t recv_idle; /* time since last NP packet received */
+};
+#endif /* PPP_IDLETIMELIMIT */
+
+/* values for epdisc.class */
+#define EPD_NULL 0 /* null discriminator, no data */
+#define EPD_LOCAL 1
+#define EPD_IP 2
+#define EPD_MAC 3
+#define EPD_MAGIC 4
+#define EPD_PHONENUM 5
+
+/*
+ * Global variables.
+ */
+#ifdef HAVE_MULTILINK
+extern u8_t multilink; /* enable multilink operation */
+extern u8_t doing_multilink;
+extern u8_t multilink_master;
+extern u8_t bundle_eof;
+extern u8_t bundle_terminating;
+#endif
+
+#ifdef MAXOCTETS
+extern unsigned int maxoctets; /* Maximum octetes per session (in bytes) */
+extern int maxoctets_dir; /* Direction :
+ 0 - in+out (default)
+ 1 - in
+ 2 - out
+ 3 - max(in,out) */
+extern int maxoctets_timeout; /* Timeout for check of octets limit */
+#define PPP_OCTETS_DIRECTION_SUM 0
+#define PPP_OCTETS_DIRECTION_IN 1
+#define PPP_OCTETS_DIRECTION_OUT 2
+#define PPP_OCTETS_DIRECTION_MAXOVERAL 3
+/* same as previous, but little different on RADIUS side */
+#define PPP_OCTETS_DIRECTION_MAXSESSION 4
+#endif
+
+/* Data input may be used by CCP and ECP, remove this entry
+ * from struct protent to save some flash
+ */
+#define PPP_DATAINPUT 0
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+ u_short protocol; /* PPP protocol number */
+ /* Initialization procedure */
+ void (*init) (ppp_pcb *pcb);
+ /* Process a received packet */
+ void (*input) (ppp_pcb *pcb, u_char *pkt, int len);
+ /* Process a received protocol-reject */
+ void (*protrej) (ppp_pcb *pcb);
+ /* Lower layer has come up */
+ void (*lowerup) (ppp_pcb *pcb);
+ /* Lower layer has gone down */
+ void (*lowerdown) (ppp_pcb *pcb);
+ /* Open the protocol */
+ void (*open) (ppp_pcb *pcb);
+ /* Close the protocol */
+ void (*close) (ppp_pcb *pcb, const char *reason);
+#if PRINTPKT_SUPPORT
+ /* Print a packet in readable form */
+ int (*printpkt) (const u_char *pkt, int len,
+ void (*printer) (void *, const char *, ...),
+ void *arg);
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+ /* Process a received data packet */
+ void (*datainput) (ppp_pcb *pcb, u_char *pkt, int len);
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+ const char *name; /* Text name of protocol */
+ const char *data_name; /* Text name of corresponding data protocol */
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+ option_t *options; /* List of command-line options */
+ /* Check requested options, assign defaults */
+ void (*check_options) (void);
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+ /* Configure interface for demand-dial */
+ int (*demand_conf) (int unit);
+ /* Say whether to bring up link for this pkt */
+ int (*active_pkt) (u_char *pkt, int len);
+#endif /* DEMAND_SUPPORT */
+};
+
+/* Table of pointers to supported protocols */
+extern const struct protent* const protocols[];
+
+
+/* Values for auth_pending, auth_done */
+#if PAP_SUPPORT
+#define PAP_WITHPEER 0x1
+#define PAP_PEER 0x2
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#define CHAP_WITHPEER 0x4
+#define CHAP_PEER 0x8
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#define EAP_WITHPEER 0x10
+#define EAP_PEER 0x20
+#endif /* EAP_SUPPORT */
+
+/* Values for auth_done only */
+#if CHAP_SUPPORT
+#define CHAP_MD5_WITHPEER 0x40
+#define CHAP_MD5_PEER 0x80
+#if MSCHAP_SUPPORT
+#define CHAP_MS_SHIFT 8 /* LSB position for MS auths */
+#define CHAP_MS_WITHPEER 0x100
+#define CHAP_MS_PEER 0x200
+#define CHAP_MS2_WITHPEER 0x400
+#define CHAP_MS2_PEER 0x800
+#endif /* MSCHAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+
+/* Supported CHAP protocols */
+#if CHAP_SUPPORT
+
+#if MSCHAP_SUPPORT
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MICROSOFT_V2 | MDTYPE_MICROSOFT | MDTYPE_MD5)
+#else /* MSCHAP_SUPPORT */
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MD5)
+#endif /* MSCHAP_SUPPORT */
+
+#else /* CHAP_SUPPORT */
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_NONE)
+#endif /* CHAP_SUPPORT */
+
+#if PPP_STATS_SUPPORT
+/*
+ * PPP statistics structure
+ */
+struct pppd_stats {
+ unsigned int bytes_in;
+ unsigned int bytes_out;
+ unsigned int pkts_in;
+ unsigned int pkts_out;
+};
+#endif /* PPP_STATS_SUPPORT */
+
+
+/*
+ * PPP private functions
+ */
+
+
+/*
+ * Functions called from lwIP core.
+ */
+
+/* initialize the PPP subsystem */
+int ppp_init(void);
+
+/*
+ * Functions called from PPP link protocols.
+ */
+
+/* Create a new PPP control block */
+ppp_pcb *ppp_new(struct netif *pppif, const struct link_callbacks *callbacks, void *link_ctx_cb,
+ ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+/* Initiate LCP open request */
+void ppp_start(ppp_pcb *pcb);
+
+/* Called when link failed to setup */
+void ppp_link_failed(ppp_pcb *pcb);
+
+/* Called when link is normally down (i.e. it was asked to end) */
+void ppp_link_end(ppp_pcb *pcb);
+
+/* function called to process input packet */
+void ppp_input(ppp_pcb *pcb, struct pbuf *pb);
+
+
+/*
+ * Functions called by PPP protocols.
+ */
+
+/* function called by all PPP subsystems to send packets */
+err_t ppp_write(ppp_pcb *pcb, struct pbuf *p);
+
+/* functions called by auth.c link_terminated() */
+void ppp_link_terminated(ppp_pcb *pcb);
+
+void new_phase(ppp_pcb *pcb, int p);
+
+int ppp_send_config(ppp_pcb *pcb, int mtu, u32_t accm, int pcomp, int accomp);
+int ppp_recv_config(ppp_pcb *pcb, int mru, u32_t accm, int pcomp, int accomp);
+
+#if PPP_IPV4_SUPPORT
+int sifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr, u32_t netmask);
+int cifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr);
+#if 0 /* UNUSED - PROXY ARP */
+int sifproxyarp(ppp_pcb *pcb, u32_t his_adr);
+int cifproxyarp(ppp_pcb *pcb, u32_t his_adr);
+#endif /* UNUSED - PROXY ARP */
+#if LWIP_DNS
+int sdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
+int cdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
+#endif /* LWIP_DNS */
+#if VJ_SUPPORT
+int sifvjcomp(ppp_pcb *pcb, int vjcomp, int cidcomp, int maxcid);
+#endif /* VJ_SUPPORT */
+int sifup(ppp_pcb *pcb);
+int sifdown (ppp_pcb *pcb);
+u32_t get_mask(u32_t addr);
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+int sif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
+int cif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
+int sif6up(ppp_pcb *pcb);
+int sif6down (ppp_pcb *pcb);
+#endif /* PPP_IPV6_SUPPORT */
+
+#if DEMAND_SUPPORT
+int sifnpmode(ppp_pcb *pcb, int proto, enum NPmode mode);
+#endif /* DEMAND_SUPPORt */
+
+void netif_set_mtu(ppp_pcb *pcb, int mtu);
+int netif_get_mtu(ppp_pcb *pcb);
+
+#if CCP_SUPPORT
+#if 0 /* unused */
+int ccp_test(ppp_pcb *pcb, u_char *opt_ptr, int opt_len, int for_transmit);
+#endif /* unused */
+void ccp_set(ppp_pcb *pcb, u8_t isopen, u8_t isup, u8_t receive_method, u8_t transmit_method);
+void ccp_reset_comp(ppp_pcb *pcb);
+void ccp_reset_decomp(ppp_pcb *pcb);
+#if 0 /* unused */
+int ccp_fatal_error(ppp_pcb *pcb);
+#endif /* unused */
+#endif /* CCP_SUPPORT */
+
+#if PPP_IDLETIMELIMIT
+int get_idle_time(ppp_pcb *pcb, struct ppp_idle *ip);
+#endif /* PPP_IDLETIMELIMIT */
+
+#if DEMAND_SUPPORT
+int get_loop_output(void);
+#endif /* DEMAND_SUPPORT */
+
+/* Optional protocol names list, to make our messages a little more informative. */
+#if PPP_PROTOCOLNAME
+const char * protocol_name(int proto);
+#endif /* PPP_PROTOCOLNAME */
+
+/* Optional stats support, to get some statistics on the PPP interface */
+#if PPP_STATS_SUPPORT
+void print_link_stats(void); /* Print stats, if available */
+void reset_link_stats(int u); /* Reset (init) stats when link goes up */
+void update_link_stats(int u); /* Get stats at link termination */
+#endif /* PPP_STATS_SUPPORT */
+
+
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+ (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+ *(cp)++ = (u_char) (c); \
+}
+#define GETSHORT(s, cp) { \
+ (s) = *(cp)++ << 8; \
+ (s) |= *(cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+ *(cp)++ = (u_char) ((s) >> 8); \
+ *(cp)++ = (u_char) (s); \
+}
+#define GETLONG(l, cp) { \
+ (l) = *(cp)++ << 8; \
+ (l) |= *(cp)++; (l) <<= 8; \
+ (l) |= *(cp)++; (l) <<= 8; \
+ (l) |= *(cp)++; \
+}
+#define PUTLONG(l, cp) { \
+ *(cp)++ = (u_char) ((l) >> 24); \
+ *(cp)++ = (u_char) ((l) >> 16); \
+ *(cp)++ = (u_char) ((l) >> 8); \
+ *(cp)++ = (u_char) (l); \
+}
+
+#define INCPTR(n, cp) ((cp) += (n))
+#define DECPTR(n, cp) ((cp) -= (n))
+
+/*
+ * System dependent definitions for user-level 4.3BSD UNIX implementation.
+ */
+#define TIMEOUT(f, a, t) do { sys_untimeout((f), (a)); sys_timeout((t)*1000, (f), (a)); } while(0)
+#define TIMEOUTMS(f, a, t) do { sys_untimeout((f), (a)); sys_timeout((t), (f), (a)); } while(0)
+#define UNTIMEOUT(f, a) sys_untimeout((f), (a))
+
+#define BZERO(s, n) memset(s, 0, n)
+#define BCMP(s1, s2, l) memcmp(s1, s2, l)
+
+#define PRINTMSG(m, l) { ppp_info("Remote message: %0.*v", l, m); }
+
+/*
+ * MAKEHEADER - Add Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+ PUTCHAR(PPP_ALLSTATIONS, p); \
+ PUTCHAR(PPP_UI, p); \
+ PUTSHORT(t, p); }
+
+/* Procedures exported from auth.c */
+void link_required(ppp_pcb *pcb); /* we are starting to use the link */
+void link_terminated(ppp_pcb *pcb); /* we are finished with the link */
+void link_down(ppp_pcb *pcb); /* the LCP layer has left the Opened state */
+void upper_layers_down(ppp_pcb *pcb); /* take all NCPs down */
+void link_established(ppp_pcb *pcb); /* the link is up; authenticate now */
+void start_networks(ppp_pcb *pcb); /* start all the network control protos */
+void continue_networks(ppp_pcb *pcb); /* start network [ip, etc] control protos */
+#if PPP_AUTH_SUPPORT
+#if PPP_SERVER
+int auth_check_passwd(ppp_pcb *pcb, char *auser, int userlen, char *apasswd, int passwdlen, const char **msg, int *msglen);
+ /* check the user name and passwd against configuration */
+void auth_peer_fail(ppp_pcb *pcb, int protocol);
+ /* peer failed to authenticate itself */
+void auth_peer_success(ppp_pcb *pcb, int protocol, int prot_flavor, const char *name, int namelen);
+ /* peer successfully authenticated itself */
+#endif /* PPP_SERVER */
+void auth_withpeer_fail(ppp_pcb *pcb, int protocol);
+ /* we failed to authenticate ourselves */
+void auth_withpeer_success(ppp_pcb *pcb, int protocol, int prot_flavor);
+ /* we successfully authenticated ourselves */
+#endif /* PPP_AUTH_SUPPORT */
+void np_up(ppp_pcb *pcb, int proto); /* a network protocol has come up */
+void np_down(ppp_pcb *pcb, int proto); /* a network protocol has gone down */
+void np_finished(ppp_pcb *pcb, int proto); /* a network protocol no longer needs link */
+#if PPP_AUTH_SUPPORT
+int get_secret(ppp_pcb *pcb, const char *client, const char *server, char *secret, int *secret_len, int am_server);
+ /* get "secret" for chap */
+#endif /* PPP_AUTH_SUPPORT */
+
+/* Procedures exported from ipcp.c */
+/* int parse_dotted_ip (char *, u32_t *); */
+
+/* Procedures exported from demand.c */
+#if DEMAND_SUPPORT
+void demand_conf (void); /* config interface(s) for demand-dial */
+void demand_block (void); /* set all NPs to queue up packets */
+void demand_unblock (void); /* set all NPs to pass packets */
+void demand_discard (void); /* set all NPs to discard packets */
+void demand_rexmit (int, u32_t); /* retransmit saved frames for an NP*/
+int loop_chars (unsigned char *, int); /* process chars from loopback */
+int loop_frame (unsigned char *, int); /* should we bring link up? */
+#endif /* DEMAND_SUPPORT */
+
+/* Procedures exported from multilink.c */
+#ifdef HAVE_MULTILINK
+void mp_check_options (void); /* Check multilink-related options */
+int mp_join_bundle (void); /* join our link to an appropriate bundle */
+void mp_exit_bundle (void); /* have disconnected our link from bundle */
+void mp_bundle_terminated (void);
+char *epdisc_to_str (struct epdisc *); /* string from endpoint discrim. */
+int str_to_epdisc (struct epdisc *, char *); /* endpt disc. from str */
+#else
+#define mp_bundle_terminated() /* nothing */
+#define mp_exit_bundle() /* nothing */
+#define doing_multilink 0
+#define multilink_master 0
+#endif
+
+/* Procedures exported from utils.c. */
+void ppp_print_string(const u_char *p, int len, void (*printer) (void *, const char *, ...), void *arg); /* Format a string for output */
+int ppp_slprintf(char *buf, int buflen, const char *fmt, ...); /* sprintf++ */
+int ppp_vslprintf(char *buf, int buflen, const char *fmt, va_list args); /* vsprintf++ */
+size_t ppp_strlcpy(char *dest, const char *src, size_t len); /* safe strcpy */
+size_t ppp_strlcat(char *dest, const char *src, size_t len); /* safe strncpy */
+void ppp_dbglog(const char *fmt, ...); /* log a debug message */
+void ppp_info(const char *fmt, ...); /* log an informational message */
+void ppp_notice(const char *fmt, ...); /* log a notice-level message */
+void ppp_warn(const char *fmt, ...); /* log a warning message */
+void ppp_error(const char *fmt, ...); /* log an error message */
+void ppp_fatal(const char *fmt, ...); /* log an error message and die(1) */
+#if PRINTPKT_SUPPORT
+void ppp_dump_packet(ppp_pcb *pcb, const char *tag, unsigned char *p, int len);
+ /* dump packet to debug log if interesting */
+#endif /* PRINTPKT_SUPPORT */
+
+/*
+ * Number of necessary timers analysis.
+ *
+ * PPP use at least one timer per each of its protocol, but not all protocols are
+ * active at the same time, thus the number of necessary timeouts is actually
+ * lower than enabled protocols. Here is the actual necessary timeouts based
+ * on code analysis.
+ *
+ * Note that many features analysed here are not working at all and are only
+ * there for a comprehensive analysis of necessary timers in order to prevent
+ * having to redo that each time we add a feature.
+ *
+ * Timer list
+ *
+ * | holdoff timeout
+ * | low level protocol timeout (PPPoE or PPPoL2P)
+ * | LCP delayed UP
+ * | LCP retransmit (FSM)
+ * | LCP Echo timer
+ * .| PAP or CHAP or EAP authentication
+ * . | ECP retransmit (FSM)
+ * . | CCP retransmit (FSM) when MPPE is enabled
+ * . | CCP retransmit (FSM) when MPPE is NOT enabled
+ * . | IPCP retransmit (FSM)
+ * . .| IP6CP retransmit (FSM)
+ * . . | Idle time limit
+ * . . | Max connect time
+ * . . | Max octets
+ * . . | CCP RACK timeout
+ * . . .
+ * PPP_PHASE_DEAD
+ * PPP_PHASE_HOLDOFF
+ * | . . .
+ * PPP_PHASE_INITIALIZE
+ * | . . .
+ * PPP_PHASE_ESTABLISH
+ * | . . .
+ * |. . .
+ * | . .
+ * PPP_PHASE_AUTHENTICATE
+ * | . .
+ * || . .
+ * PPP_PHASE_NETWORK
+ * | || . .
+ * | ||| .
+ * PPP_PHASE_RUNNING
+ * | .|||||
+ * | . ||||
+ * PPP_PHASE_TERMINATE
+ * | . ||||
+ * PPP_PHASE_NETWORK
+ * |. .
+ * PPP_PHASE_ESTABLISH
+ * PPP_PHASE_DISCONNECT
+ * PPP_PHASE_DEAD
+ *
+ * Alright, PPP basic retransmission and LCP Echo consume one timer.
+ * 1
+ *
+ * If authentication is enabled one timer is necessary during authentication.
+ * 1 + PPP_AUTH_SUPPORT
+ *
+ * If ECP is enabled one timer is necessary before IPCP and/or IP6CP, one more
+ * is necessary if CCP is enabled (only with MPPE support but we don't care much
+ * up to this detail level).
+ * 1 + ECP_SUPPORT + CCP_SUPPORT
+ *
+ * If CCP is enabled it might consume a timer during IPCP or IP6CP, thus
+ * we might use IPCP, IP6CP and CCP timers simultaneously.
+ * 1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT
+ *
+ * When entering running phase, IPCP or IP6CP is still running. If idle time limit
+ * is enabled one more timer is necessary. Same for max connect time and max
+ * octets features. Furthermore CCP RACK might be used past this point.
+ * 1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS + CCP_SUPPORT
+ *
+ * IPv4 or IPv6 must be enabled, therefore we don't need to take care the authentication
+ * and the CCP + ECP case, thus reducing overall complexity.
+ * 1 + LWIP_MAX(PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT, PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS + CCP_SUPPORT)
+ *
+ * We don't support PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS features
+ * and adding those defines to ppp_opts.h just for having the value always
+ * defined to 0 isn't worth it.
+ * 1 + LWIP_MAX(PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT, PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + CCP_SUPPORT)
+ *
+ * Thus, the following is enough for now.
+ * 1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPP_SUPPORT */
+#endif /* LWIP_HDR_PPP_IMPL_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp_opts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp_opts.h
new file mode 100644
index 0000000..6702bec
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/ppp_opts.h
@@ -0,0 +1,610 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef LWIP_PPP_OPTS_H
+#define LWIP_PPP_OPTS_H
+
+#include "lwip/opt.h"
+
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT 0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT 0
+#endif
+
+/**
+ * PPPOL2TP_SUPPORT==1: Enable PPP Over L2TP
+ */
+#ifndef PPPOL2TP_SUPPORT
+#define PPPOL2TP_SUPPORT 0
+#endif
+
+/**
+ * PPPOL2TP_AUTH_SUPPORT==1: Enable PPP Over L2TP Auth (enable MD5 support)
+ */
+#ifndef PPPOL2TP_AUTH_SUPPORT
+#define PPPOL2TP_AUTH_SUPPORT PPPOL2TP_SUPPORT
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT PPP_SUPPORT
+#endif
+
+/**
+ * LWIP_PPP_API==1: Enable PPP API (in pppapi.c)
+ */
+#ifndef LWIP_PPP_API
+#define LWIP_PPP_API (PPP_SUPPORT && (NO_SYS == 0))
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * MEMP_NUM_PPP_PCB: the number of simultaneously active PPP
+ * connections (requires the PPP_SUPPORT option)
+ */
+#ifndef MEMP_NUM_PPP_PCB
+#define MEMP_NUM_PPP_PCB 1
+#endif
+
+/**
+ * PPP_NUM_TIMEOUTS_PER_PCB: the number of sys_timeouts running in parallel per
+ * ppp_pcb. See the detailed explanation at the end of ppp_impl.h about simultaneous
+ * timers analysis.
+ */
+#ifndef PPP_NUM_TIMEOUTS_PER_PCB
+#define PPP_NUM_TIMEOUTS_PER_PCB (1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT)
+#endif
+
+/* The number of sys_timeouts required for the PPP module */
+#define PPP_NUM_TIMEOUTS (PPP_SUPPORT * PPP_NUM_TIMEOUTS_PER_PCB * MEMP_NUM_PPP_PCB)
+
+/**
+ * MEMP_NUM_PPPOS_INTERFACES: the number of concurrently active PPPoS
+ * interfaces (only used with PPPOS_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOS_INTERFACES
+#define MEMP_NUM_PPPOS_INTERFACES MEMP_NUM_PPP_PCB
+#endif
+
+/**
+ * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE
+ * interfaces (only used with PPPOE_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOE_INTERFACES
+#define MEMP_NUM_PPPOE_INTERFACES 1
+#endif
+
+/**
+ * MEMP_NUM_PPPOL2TP_INTERFACES: the number of concurrently active PPPoL2TP
+ * interfaces (only used with PPPOL2TP_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOL2TP_INTERFACES
+#define MEMP_NUM_PPPOL2TP_INTERFACES 1
+#endif
+
+/**
+ * MEMP_NUM_PPP_API_MSG: Number of concurrent PPP API messages (in pppapi.c)
+ */
+#ifndef MEMP_NUM_PPP_API_MSG
+#define MEMP_NUM_PPP_API_MSG 5
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_INPROC_IRQ_SAFE==1 call pppos_input() using tcpip_callback().
+ *
+ * Please read the "PPPoS input path" chapter in the PPP documentation about this option.
+ */
+#ifndef PPP_INPROC_IRQ_SAFE
+#define PPP_INPROC_IRQ_SAFE 0
+#endif
+
+/**
+ * PRINTPKT_SUPPORT==1: Enable PPP print packet support
+ *
+ * Mandatory for debugging, it displays exchanged packet content in debug trace.
+ */
+#ifndef PRINTPKT_SUPPORT
+#define PRINTPKT_SUPPORT 0
+#endif
+
+/**
+ * PPP_IPV4_SUPPORT==1: Enable PPP IPv4 support
+ */
+#ifndef PPP_IPV4_SUPPORT
+#define PPP_IPV4_SUPPORT (LWIP_IPV4)
+#endif
+
+/**
+ * PPP_IPV6_SUPPORT==1: Enable PPP IPv6 support
+ */
+#ifndef PPP_IPV6_SUPPORT
+#define PPP_IPV6_SUPPORT (LWIP_IPV6)
+#endif
+
+/**
+ * PPP_NOTIFY_PHASE==1: Support PPP notify phase support
+ *
+ * PPP notify phase support allows you to set a callback which is
+ * called on change of the internal PPP state machine.
+ *
+ * This can be used for example to set a LED pattern depending on the
+ * current phase of the PPP session.
+ */
+#ifndef PPP_NOTIFY_PHASE
+#define PPP_NOTIFY_PHASE 0
+#endif
+
+/**
+ * pbuf_type PPP is using for LCP, PAP, CHAP, EAP, CCP, IPCP and IP6CP packets.
+ *
+ * Memory allocated must be single buffered for PPP to works, it requires pbuf
+ * that are not going to be chained when allocated. This requires setting
+ * PBUF_POOL_BUFSIZE to at least 512 bytes, which is quite huge for small systems.
+ *
+ * Setting PPP_USE_PBUF_RAM to 1 makes PPP use memory from heap where continuous
+ * buffers are required, allowing you to use a smaller PBUF_POOL_BUFSIZE.
+ */
+#ifndef PPP_USE_PBUF_RAM
+#define PPP_USE_PBUF_RAM 0
+#endif
+
+/**
+ * PPP_FCS_TABLE: Keep a 256*2 byte table to speed up FCS calculation for PPPoS
+ */
+#ifndef PPP_FCS_TABLE
+#define PPP_FCS_TABLE 1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT 0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT 0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP.
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT 0
+#endif
+#if MSCHAP_SUPPORT
+/* MSCHAP requires CHAP support */
+#undef CHAP_SUPPORT
+#define CHAP_SUPPORT 1
+#endif /* MSCHAP_SUPPORT */
+
+/**
+ * EAP_SUPPORT==1: Support EAP.
+ */
+#ifndef EAP_SUPPORT
+#define EAP_SUPPORT 0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP.
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT 0
+#endif
+
+/**
+ * MPPE_SUPPORT==1: Support MPPE.
+ */
+#ifndef MPPE_SUPPORT
+#define MPPE_SUPPORT 0
+#endif
+#if MPPE_SUPPORT
+/* MPPE requires CCP support */
+#undef CCP_SUPPORT
+#define CCP_SUPPORT 1
+/* MPPE requires MSCHAP support */
+#undef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT 1
+/* MSCHAP requires CHAP support */
+#undef CHAP_SUPPORT
+#define CHAP_SUPPORT 1
+#endif /* MPPE_SUPPORT */
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT 0
+#endif
+
+/**
+ * ECP_SUPPORT==1: Support ECP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef ECP_SUPPORT
+#define ECP_SUPPORT 0
+#endif
+
+/**
+ * DEMAND_SUPPORT==1: Support dial on demand. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef DEMAND_SUPPORT
+#define DEMAND_SUPPORT 0
+#endif
+
+/**
+ * LQR_SUPPORT==1: Support Link Quality Report. Do nothing except exchanging some LCP packets.
+ */
+#ifndef LQR_SUPPORT
+#define LQR_SUPPORT 0
+#endif
+
+/**
+ * PPP_SERVER==1: Enable PPP server support (waiting for incoming PPP session).
+ *
+ * Currently only supported for PPPoS.
+ */
+#ifndef PPP_SERVER
+#define PPP_SERVER 0
+#endif
+
+#if PPP_SERVER
+/*
+ * PPP_OUR_NAME: Our name for authentication purposes
+ */
+#ifndef PPP_OUR_NAME
+#define PPP_OUR_NAME "lwIP"
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT 1
+#endif
+/* VJ compression is only supported for TCP over IPv4 over PPPoS. */
+#if !PPPOS_SUPPORT || !PPP_IPV4_SUPPORT || !LWIP_TCP
+#undef VJ_SUPPORT
+#define VJ_SUPPORT 0
+#endif /* !PPPOS_SUPPORT */
+
+/**
+ * PPP_MD5_RANDM==1: Use MD5 for better randomness.
+ * Enabled by default if CHAP, EAP, or L2TP AUTH support is enabled.
+ */
+#ifndef PPP_MD5_RANDM
+#define PPP_MD5_RANDM (CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT)
+#endif
+
+/**
+ * PolarSSL embedded library
+ *
+ *
+ * lwIP contains some files fetched from the latest BSD release of
+ * the PolarSSL project (PolarSSL 0.10.1-bsd) for ciphers and encryption
+ * methods we need for lwIP PPP support.
+ *
+ * The PolarSSL files were cleaned to contain only the necessary struct
+ * fields and functions needed for lwIP.
+ *
+ * The PolarSSL API was not changed at all, so if you are already using
+ * PolarSSL you can choose to skip the compilation of the included PolarSSL
+ * library into lwIP.
+ *
+ * If you are not using the embedded copy you must include external
+ * libraries into your arch/cc.h port file.
+ *
+ * Beware of the stack requirements which can be a lot larger if you are not
+ * using our cleaned PolarSSL library.
+ */
+
+/**
+ * LWIP_USE_EXTERNAL_POLARSSL: Use external PolarSSL library
+ */
+#ifndef LWIP_USE_EXTERNAL_POLARSSL
+#define LWIP_USE_EXTERNAL_POLARSSL 0
+#endif
+
+/**
+ * LWIP_USE_EXTERNAL_MBEDTLS: Use external mbed TLS library
+ */
+#ifndef LWIP_USE_EXTERNAL_MBEDTLS
+#define LWIP_USE_EXTERNAL_MBEDTLS 0
+#endif
+
+/*
+ * PPP Timeouts
+ */
+
+/**
+ * FSM_DEFTIMEOUT: Timeout time in seconds
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT 6
+#endif
+
+/**
+ * FSM_DEFMAXTERMREQS: Maximum Terminate-Request transmissions
+ */
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS 2
+#endif
+
+/**
+ * FSM_DEFMAXCONFREQS: Maximum Configure-Request transmissions
+ */
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS 10
+#endif
+
+/**
+ * FSM_DEFMAXNAKLOOPS: Maximum number of nak loops
+ */
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS 5
+#endif
+
+/**
+ * UPAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
+ */
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT 6
+#endif
+
+/**
+ * UPAP_DEFTRANSMITS: Maximum number of auth-reqs to send
+ */
+#ifndef UPAP_DEFTRANSMITS
+#define UPAP_DEFTRANSMITS 10
+#endif
+
+#if PPP_SERVER
+/**
+ * UPAP_DEFREQTIME: Time to wait for auth-req from peer
+ */
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME 30
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * CHAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
+ */
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT 6
+#endif
+
+/**
+ * CHAP_DEFTRANSMITS: max # times to send challenge
+ */
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS 10
+#endif
+
+#if PPP_SERVER
+/**
+ * CHAP_DEFRECHALLENGETIME: If this option is > 0, rechallenge the peer every n seconds
+ */
+#ifndef CHAP_DEFRECHALLENGETIME
+#define CHAP_DEFRECHALLENGETIME 0
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * EAP_DEFREQTIME: Time to wait for peer request
+ */
+#ifndef EAP_DEFREQTIME
+#define EAP_DEFREQTIME 6
+#endif
+
+/**
+ * EAP_DEFALLOWREQ: max # times to accept requests
+ */
+#ifndef EAP_DEFALLOWREQ
+#define EAP_DEFALLOWREQ 10
+#endif
+
+#if PPP_SERVER
+/**
+ * EAP_DEFTIMEOUT: Timeout (seconds) for rexmit
+ */
+#ifndef EAP_DEFTIMEOUT
+#define EAP_DEFTIMEOUT 6
+#endif
+
+/**
+ * EAP_DEFTRANSMITS: max # times to transmit
+ */
+#ifndef EAP_DEFTRANSMITS
+#define EAP_DEFTRANSMITS 10
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * LCP_DEFLOOPBACKFAIL: Default number of times we receive our magic number from the peer
+ * before deciding the link is looped-back.
+ */
+#ifndef LCP_DEFLOOPBACKFAIL
+#define LCP_DEFLOOPBACKFAIL 10
+#endif
+
+/**
+ * LCP_ECHOINTERVAL: Interval in seconds between keepalive echo requests, 0 to disable.
+ */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL 0
+#endif
+
+/**
+ * LCP_MAXECHOFAILS: Number of unanswered echo requests before failure.
+ */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS 3
+#endif
+
+/**
+ * PPP_MAXIDLEFLAG: Max Xmit idle time (in ms) before resend flag char.
+ */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG 100
+#endif
+
+/**
+ * PPP Packet sizes
+ */
+
+/**
+ * PPP_MRU: Default MRU
+ */
+#ifndef PPP_MRU
+#define PPP_MRU 1500
+#endif
+
+/**
+ * PPP_DEFMRU: Default MRU to try
+ */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU 1500
+#endif
+
+/**
+ * PPP_MAXMRU: Normally limit MRU to this (pppd default = 16384)
+ */
+#ifndef PPP_MAXMRU
+#define PPP_MAXMRU 1500
+#endif
+
+/**
+ * PPP_MINMRU: No MRUs below this
+ */
+#ifndef PPP_MINMRU
+#define PPP_MINMRU 128
+#endif
+
+/**
+ * PPPOL2TP_DEFMRU: Default MTU and MRU for L2TP
+ * Default = 1500 - PPPoE(6) - PPP Protocol(2) - IPv4 header(20) - UDP Header(8)
+ * - L2TP Header(6) - HDLC Header(2) - PPP Protocol(2) - MPPE Header(2) - PPP Protocol(2)
+ */
+#if PPPOL2TP_SUPPORT
+#ifndef PPPOL2TP_DEFMRU
+#define PPPOL2TP_DEFMRU 1450
+#endif
+#endif /* PPPOL2TP_SUPPORT */
+
+/**
+ * MAXNAMELEN: max length of hostname or name for auth
+ */
+#ifndef MAXNAMELEN
+#define MAXNAMELEN 256
+#endif
+
+/**
+ * MAXSECRETLEN: max length of password or secret
+ */
+#ifndef MAXSECRETLEN
+#define MAXSECRETLEN 256
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Build triggers for embedded PolarSSL
+ */
+#if !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS
+
+/* CHAP, EAP, L2TP AUTH and MD5 Random require MD5 support */
+#if CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM
+#define LWIP_INCLUDED_POLARSSL_MD5 1
+#endif /* CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM */
+
+#if MSCHAP_SUPPORT
+
+/* MSCHAP require MD4 support */
+#define LWIP_INCLUDED_POLARSSL_MD4 1
+/* MSCHAP require SHA1 support */
+#define LWIP_INCLUDED_POLARSSL_SHA1 1
+/* MSCHAP require DES support */
+#define LWIP_INCLUDED_POLARSSL_DES 1
+
+/* MS-CHAP support is required for MPPE */
+#if MPPE_SUPPORT
+/* MPPE require ARC4 support */
+#define LWIP_INCLUDED_POLARSSL_ARC4 1
+#endif /* MPPE_SUPPORT */
+
+#endif /* MSCHAP_SUPPORT */
+
+#endif /* !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS */
+
+/* Default value if unset */
+#ifndef LWIP_INCLUDED_POLARSSL_MD4
+#define LWIP_INCLUDED_POLARSSL_MD4 0
+#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
+#ifndef LWIP_INCLUDED_POLARSSL_MD5
+#define LWIP_INCLUDED_POLARSSL_MD5 0
+#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
+#ifndef LWIP_INCLUDED_POLARSSL_SHA1
+#define LWIP_INCLUDED_POLARSSL_SHA1 0
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
+#ifndef LWIP_INCLUDED_POLARSSL_DES
+#define LWIP_INCLUDED_POLARSSL_DES 0
+#endif /* LWIP_INCLUDED_POLARSSL_DES */
+#ifndef LWIP_INCLUDED_POLARSSL_ARC4
+#define LWIP_INCLUDED_POLARSSL_ARC4 0
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
+
+#endif /* PPP_SUPPORT */
+
+/* Default value if unset */
+#ifndef PPP_NUM_TIMEOUTS
+#define PPP_NUM_TIMEOUTS 0
+#endif /* PPP_NUM_TIMEOUTS */
+
+#endif /* LWIP_PPP_OPTS_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppapi.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppapi.h
new file mode 100644
index 0000000..913d93f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppapi.h
@@ -0,0 +1,137 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef LWIP_PPPAPI_H
+#define LWIP_PPPAPI_H
+
+#include "netif/ppp/ppp_opts.h"
+
+#if LWIP_PPP_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "netif/ppp/ppp.h"
+#if PPPOS_SUPPORT
+#include "netif/ppp/pppos.h"
+#endif /* PPPOS_SUPPORT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pppapi_msg_msg {
+ ppp_pcb *ppp;
+ union {
+#if PPP_NOTIFY_PHASE
+ struct {
+ ppp_notify_phase_cb_fn notify_phase_cb;
+ } setnotifyphasecb;
+#endif /* PPP_NOTIFY_PHASE */
+#if PPPOS_SUPPORT
+ struct {
+ struct netif *pppif;
+ pppos_output_cb_fn output_cb;
+ ppp_link_status_cb_fn link_status_cb;
+ void *ctx_cb;
+ } serialcreate;
+#endif /* PPPOS_SUPPORT */
+#if PPPOE_SUPPORT
+ struct {
+ struct netif *pppif;
+ struct netif *ethif;
+ const char *service_name;
+ const char *concentrator_name;
+ ppp_link_status_cb_fn link_status_cb;
+ void *ctx_cb;
+ } ethernetcreate;
+#endif /* PPPOE_SUPPORT */
+#if PPPOL2TP_SUPPORT
+ struct {
+ struct netif *pppif;
+ struct netif *netif;
+ API_MSG_M_DEF_C(ip_addr_t, ipaddr);
+ u16_t port;
+#if PPPOL2TP_AUTH_SUPPORT
+ const u8_t *secret;
+ u8_t secret_len;
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+ ppp_link_status_cb_fn link_status_cb;
+ void *ctx_cb;
+ } l2tpcreate;
+#endif /* PPPOL2TP_SUPPORT */
+ struct {
+ u16_t holdoff;
+ } connect;
+ struct {
+ u8_t nocarrier;
+ } close;
+ struct {
+ u8_t cmd;
+ void *arg;
+ } ioctl;
+ } msg;
+};
+
+struct pppapi_msg {
+ struct tcpip_api_call_data call;
+ struct pppapi_msg_msg msg;
+};
+
+/* API for application */
+err_t pppapi_set_default(ppp_pcb *pcb);
+#if PPP_NOTIFY_PHASE
+err_t pppapi_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
+#endif /* PPP_NOTIFY_PHASE */
+#if PPPOS_SUPPORT
+ppp_pcb *pppapi_pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+#endif /* PPPOS_SUPPORT */
+#if PPPOE_SUPPORT
+ppp_pcb *pppapi_pppoe_create(struct netif *pppif, struct netif *ethif, const char *service_name,
+ const char *concentrator_name, ppp_link_status_cb_fn link_status_cb,
+ void *ctx_cb);
+#endif /* PPPOE_SUPPORT */
+#if PPPOL2TP_SUPPORT
+ppp_pcb *pppapi_pppol2tp_create(struct netif *pppif, struct netif *netif, ip_addr_t *ipaddr, u16_t port,
+ const u8_t *secret, u8_t secret_len,
+ ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+#endif /* PPPOL2TP_SUPPORT */
+err_t pppapi_connect(ppp_pcb *pcb, u16_t holdoff);
+#if PPP_SERVER
+err_t pppapi_listen(ppp_pcb *pcb);
+#endif /* PPP_SERVER */
+err_t pppapi_close(ppp_pcb *pcb, u8_t nocarrier);
+err_t pppapi_free(ppp_pcb *pcb);
+err_t pppapi_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_PPP_API */
+
+#endif /* LWIP_PPPAPI_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppcrypt.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppcrypt.h
new file mode 100644
index 0000000..c0230bb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppcrypt.h
@@ -0,0 +1,144 @@
+/*
+ * pppcrypt.c - PPP/DES linkage for MS-CHAP and EAP SRP-SHA1
+ *
+ * Extracted from chap_ms.c by James Carlson.
+ *
+ * Copyright (c) 1995 Eric Rosenquist. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/* This header file is included in all PPP modules needing hashes and/or ciphers */
+
+#ifndef PPPCRYPT_H
+#define PPPCRYPT_H
+
+/*
+ * If included PolarSSL copy is not used, user is expected to include
+ * external libraries in arch/cc.h (which is included by lwip/arch.h).
+ */
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Map hashes and ciphers functions to PolarSSL
+ */
+#if !LWIP_USE_EXTERNAL_MBEDTLS
+
+#include "netif/ppp/polarssl/md4.h"
+#define lwip_md4_context md4_context
+#define lwip_md4_init(context)
+#define lwip_md4_starts md4_starts
+#define lwip_md4_update md4_update
+#define lwip_md4_finish md4_finish
+#define lwip_md4_free(context)
+
+#include "netif/ppp/polarssl/md5.h"
+#define lwip_md5_context md5_context
+#define lwip_md5_init(context)
+#define lwip_md5_starts md5_starts
+#define lwip_md5_update md5_update
+#define lwip_md5_finish md5_finish
+#define lwip_md5_free(context)
+
+#include "netif/ppp/polarssl/sha1.h"
+#define lwip_sha1_context sha1_context
+#define lwip_sha1_init(context)
+#define lwip_sha1_starts sha1_starts
+#define lwip_sha1_update sha1_update
+#define lwip_sha1_finish sha1_finish
+#define lwip_sha1_free(context)
+
+#include "netif/ppp/polarssl/des.h"
+#define lwip_des_context des_context
+#define lwip_des_init(context)
+#define lwip_des_setkey_enc des_setkey_enc
+#define lwip_des_crypt_ecb des_crypt_ecb
+#define lwip_des_free(context)
+
+#include "netif/ppp/polarssl/arc4.h"
+#define lwip_arc4_context arc4_context
+#define lwip_arc4_init(context)
+#define lwip_arc4_setup arc4_setup
+#define lwip_arc4_crypt arc4_crypt
+#define lwip_arc4_free(context)
+
+#endif /* !LWIP_USE_EXTERNAL_MBEDTLS */
+
+/*
+ * Map hashes and ciphers functions to mbed TLS
+ */
+#if LWIP_USE_EXTERNAL_MBEDTLS
+
+#define lwip_md4_context mbedtls_md4_context
+#define lwip_md4_init mbedtls_md4_init
+#define lwip_md4_starts mbedtls_md4_starts
+#define lwip_md4_update mbedtls_md4_update
+#define lwip_md4_finish mbedtls_md4_finish
+#define lwip_md4_free mbedtls_md4_free
+
+#define lwip_md5_context mbedtls_md5_context
+#define lwip_md5_init mbedtls_md5_init
+#define lwip_md5_starts mbedtls_md5_starts
+#define lwip_md5_update mbedtls_md5_update
+#define lwip_md5_finish mbedtls_md5_finish
+#define lwip_md5_free mbedtls_md5_free
+
+#define lwip_sha1_context mbedtls_sha1_context
+#define lwip_sha1_init mbedtls_sha1_init
+#define lwip_sha1_starts mbedtls_sha1_starts
+#define lwip_sha1_update mbedtls_sha1_update
+#define lwip_sha1_finish mbedtls_sha1_finish
+#define lwip_sha1_free mbedtls_sha1_free
+
+#define lwip_des_context mbedtls_des_context
+#define lwip_des_init mbedtls_des_init
+#define lwip_des_setkey_enc mbedtls_des_setkey_enc
+#define lwip_des_crypt_ecb mbedtls_des_crypt_ecb
+#define lwip_des_free mbedtls_des_free
+
+#define lwip_arc4_context mbedtls_arc4_context
+#define lwip_arc4_init mbedtls_arc4_init
+#define lwip_arc4_setup mbedtls_arc4_setup
+#define lwip_arc4_crypt(context, buffer, length) mbedtls_arc4_crypt(context, length, buffer, buffer)
+#define lwip_arc4_free mbedtls_arc4_free
+
+#endif /* LWIP_USE_EXTERNAL_MBEDTLS */
+
+void pppcrypt_56_to_64_bit_key(u_char *key, u_char *des_key);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPCRYPT_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppdebug.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppdebug.h
new file mode 100644
index 0000000..5e6741b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppdebug.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher
+* Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+* Original.
+*
+*****************************************************************************
+*/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Trace levels. */
+#define LOG_CRITICAL (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_ERR (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_NOTICE (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_WARNING (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_INFO (PPP_DEBUG)
+#define LOG_DETAIL (PPP_DEBUG)
+#define LOG_DEBUG (PPP_DEBUG)
+
+#if PPP_DEBUG
+
+#define MAINDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define SYSDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define FSMDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define LCPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define IPCPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define IPV6CPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define UPAPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define CHAPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define PPPDEBUG(a, b) LWIP_DEBUGF(a, b)
+
+#else /* PPP_DEBUG */
+
+#define MAINDEBUG(a)
+#define SYSDEBUG(a)
+#define FSMDEBUG(a)
+#define LCPDEBUG(a)
+#define IPCPDEBUG(a)
+#define IPV6CPDEBUG(a)
+#define UPAPDEBUG(a)
+#define CHAPDEBUG(a)
+#define PPPDEBUG(a, b)
+
+#endif /* PPP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPDEBUG_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppoe.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppoe.h
new file mode 100644
index 0000000..c96eb78
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppoe.h
@@ -0,0 +1,187 @@
+/*****************************************************************************
+* pppoe.h - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher
+* Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_OE_H
+#define PPP_OE_H
+
+#include "ppp.h"
+#include "lwip/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoehdr {
+ PACK_STRUCT_FLD_8(u8_t vertype);
+ PACK_STRUCT_FLD_8(u8_t code);
+ PACK_STRUCT_FIELD(u16_t session);
+ PACK_STRUCT_FIELD(u16_t plen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoetag {
+ PACK_STRUCT_FIELD(u16_t tag);
+ PACK_STRUCT_FIELD(u16_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+# include "arch/epstruct.h"
+#endif
+
+
+#define PPPOE_STATE_INITIAL 0
+#define PPPOE_STATE_PADI_SENT 1
+#define PPPOE_STATE_PADR_SENT 2
+#define PPPOE_STATE_SESSION 3
+/* passive */
+#define PPPOE_STATE_PADO_SENT 1
+
+#define PPPOE_HEADERLEN sizeof(struct pppoehdr)
+#define PPPOE_VERTYPE 0x11 /* VER=1, TYPE = 1 */
+
+#define PPPOE_TAG_EOL 0x0000 /* end of list */
+#define PPPOE_TAG_SNAME 0x0101 /* service name */
+#define PPPOE_TAG_ACNAME 0x0102 /* access concentrator name */
+#define PPPOE_TAG_HUNIQUE 0x0103 /* host unique */
+#define PPPOE_TAG_ACCOOKIE 0x0104 /* AC cookie */
+#define PPPOE_TAG_VENDOR 0x0105 /* vendor specific */
+#define PPPOE_TAG_RELAYSID 0x0110 /* relay session id */
+#define PPPOE_TAG_SNAME_ERR 0x0201 /* service name error */
+#define PPPOE_TAG_ACSYS_ERR 0x0202 /* AC system error */
+#define PPPOE_TAG_GENERIC_ERR 0x0203 /* gerneric error */
+
+#define PPPOE_CODE_PADI 0x09 /* Active Discovery Initiation */
+#define PPPOE_CODE_PADO 0x07 /* Active Discovery Offer */
+#define PPPOE_CODE_PADR 0x19 /* Active Discovery Request */
+#define PPPOE_CODE_PADS 0x65 /* Active Discovery Session confirmation */
+#define PPPOE_CODE_PADT 0xA7 /* Active Discovery Terminate */
+
+#ifndef PPPOE_MAX_AC_COOKIE_LEN
+#define PPPOE_MAX_AC_COOKIE_LEN 64
+#endif
+
+struct pppoe_softc {
+ struct pppoe_softc *next;
+ struct netif *sc_ethif; /* ethernet interface we are using */
+ ppp_pcb *pcb; /* PPP PCB */
+
+ struct eth_addr sc_dest; /* hardware address of concentrator */
+ u16_t sc_session; /* PPPoE session id */
+ u8_t sc_state; /* discovery phase or session connected */
+
+#ifdef PPPOE_TODO
+ u8_t *sc_service_name; /* if != NULL: requested name of service */
+ u8_t *sc_concentrator_name; /* if != NULL: requested concentrator id */
+#endif /* PPPOE_TODO */
+ u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */
+ u8_t sc_ac_cookie_len; /* length of cookie data */
+#ifdef PPPOE_SERVER
+ u8_t *sc_hunique; /* content of host unique we must echo back */
+ u8_t sc_hunique_len; /* length of host unique */
+#endif
+ u8_t sc_padi_retried; /* number of PADI retries already done */
+ u8_t sc_padr_retried; /* number of PADR retries already done */
+};
+
+
+#define pppoe_init() /* compatibility define, no initialization needed */
+
+ppp_pcb *pppoe_create(struct netif *pppif,
+ struct netif *ethif,
+ const char *service_name, const char *concentrator_name,
+ ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+/*
+ * Functions called from lwIP
+ * DO NOT CALL FROM lwIP USER APPLICATION.
+ */
+void pppoe_disc_input(struct netif *netif, struct pbuf *p);
+void pppoe_data_input(struct netif *netif, struct pbuf *p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPP_OE_H */
+
+#endif /* PPP_SUPPORT && PPPOE_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppol2tp.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppol2tp.h
new file mode 100644
index 0000000..1221ca1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppol2tp.h
@@ -0,0 +1,209 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Layer 2 Tunneling Protocol header file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOL2TP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPOL2TP_H
+#define PPPOL2TP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Timeout */
+#define PPPOL2TP_CONTROL_TIMEOUT (5*1000) /* base for quick timeout calculation */
+#define PPPOL2TP_SLOW_RETRY (60*1000) /* persistent retry interval */
+
+#define PPPOL2TP_MAXSCCRQ 4 /* retry SCCRQ four times (quickly) */
+#define PPPOL2TP_MAXICRQ 4 /* retry IRCQ four times */
+#define PPPOL2TP_MAXICCN 4 /* retry ICCN four times */
+
+/* L2TP header flags */
+#define PPPOL2TP_HEADERFLAG_CONTROL 0x8000
+#define PPPOL2TP_HEADERFLAG_LENGTH 0x4000
+#define PPPOL2TP_HEADERFLAG_SEQUENCE 0x0800
+#define PPPOL2TP_HEADERFLAG_OFFSET 0x0200
+#define PPPOL2TP_HEADERFLAG_PRIORITY 0x0100
+#define PPPOL2TP_HEADERFLAG_VERSION 0x0002
+
+/* Mandatory bits for control: Control, Length, Sequence, Version 2 */
+#define PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY (PPPOL2TP_HEADERFLAG_CONTROL|PPPOL2TP_HEADERFLAG_LENGTH|PPPOL2TP_HEADERFLAG_SEQUENCE|PPPOL2TP_HEADERFLAG_VERSION)
+/* Forbidden bits for control: Offset, Priority */
+#define PPPOL2TP_HEADERFLAG_CONTROL_FORBIDDEN (PPPOL2TP_HEADERFLAG_OFFSET|PPPOL2TP_HEADERFLAG_PRIORITY)
+
+/* Mandatory bits for data: Version 2 */
+#define PPPOL2TP_HEADERFLAG_DATA_MANDATORY (PPPOL2TP_HEADERFLAG_VERSION)
+
+/* AVP (Attribute Value Pair) header */
+#define PPPOL2TP_AVPHEADERFLAG_MANDATORY 0x8000
+#define PPPOL2TP_AVPHEADERFLAG_HIDDEN 0x4000
+#define PPPOL2TP_AVPHEADERFLAG_LENGTHMASK 0x03ff
+
+/* -- AVP - Message type */
+#define PPPOL2TP_AVPTYPE_MESSAGE 0 /* Message type */
+
+/* Control Connection Management */
+#define PPPOL2TP_MESSAGETYPE_SCCRQ 1 /* Start Control Connection Request */
+#define PPPOL2TP_MESSAGETYPE_SCCRP 2 /* Start Control Connection Reply */
+#define PPPOL2TP_MESSAGETYPE_SCCCN 3 /* Start Control Connection Connected */
+#define PPPOL2TP_MESSAGETYPE_STOPCCN 4 /* Stop Control Connection Notification */
+#define PPPOL2TP_MESSAGETYPE_HELLO 6 /* Hello */
+/* Call Management */
+#define PPPOL2TP_MESSAGETYPE_OCRQ 7 /* Outgoing Call Request */
+#define PPPOL2TP_MESSAGETYPE_OCRP 8 /* Outgoing Call Reply */
+#define PPPOL2TP_MESSAGETYPE_OCCN 9 /* Outgoing Call Connected */
+#define PPPOL2TP_MESSAGETYPE_ICRQ 10 /* Incoming Call Request */
+#define PPPOL2TP_MESSAGETYPE_ICRP 11 /* Incoming Call Reply */
+#define PPPOL2TP_MESSAGETYPE_ICCN 12 /* Incoming Call Connected */
+#define PPPOL2TP_MESSAGETYPE_CDN 14 /* Call Disconnect Notify */
+/* Error reporting */
+#define PPPOL2TP_MESSAGETYPE_WEN 15 /* WAN Error Notify */
+/* PPP Session Control */
+#define PPPOL2TP_MESSAGETYPE_SLI 16 /* Set Link Info */
+
+/* -- AVP - Result code */
+#define PPPOL2TP_AVPTYPE_RESULTCODE 1 /* Result code */
+#define PPPOL2TP_RESULTCODE 1 /* General request to clear control connection */
+
+/* -- AVP - Protocol version (!= L2TP Header version) */
+#define PPPOL2TP_AVPTYPE_VERSION 2
+#define PPPOL2TP_VERSION 0x0100 /* L2TP Protocol version 1, revision 0 */
+
+/* -- AVP - Framing capabilities */
+#define PPPOL2TP_AVPTYPE_FRAMINGCAPABILITIES 3 /* Bearer capabilities */
+#define PPPOL2TP_FRAMINGCAPABILITIES 0x00000003 /* Async + Sync framing */
+
+/* -- AVP - Bearer capabilities */
+#define PPPOL2TP_AVPTYPE_BEARERCAPABILITIES 4 /* Bearer capabilities */
+#define PPPOL2TP_BEARERCAPABILITIES 0x00000003 /* Analog + Digital Access */
+
+/* -- AVP - Tie breaker */
+#define PPPOL2TP_AVPTYPE_TIEBREAKER 5
+
+/* -- AVP - Host name */
+#define PPPOL2TP_AVPTYPE_HOSTNAME 7 /* Host name */
+#define PPPOL2TP_HOSTNAME "lwIP" /* FIXME: make it configurable */
+
+/* -- AVP - Vendor name */
+#define PPPOL2TP_AVPTYPE_VENDORNAME 8 /* Vendor name */
+#define PPPOL2TP_VENDORNAME "lwIP" /* FIXME: make it configurable */
+
+/* -- AVP - Assign tunnel ID */
+#define PPPOL2TP_AVPTYPE_TUNNELID 9 /* Assign Tunnel ID */
+
+/* -- AVP - Receive window size */
+#define PPPOL2TP_AVPTYPE_RECEIVEWINDOWSIZE 10 /* Receive window size */
+#define PPPOL2TP_RECEIVEWINDOWSIZE 8 /* FIXME: make it configurable */
+
+/* -- AVP - Challenge */
+#define PPPOL2TP_AVPTYPE_CHALLENGE 11 /* Challenge */
+
+/* -- AVP - Cause code */
+#define PPPOL2TP_AVPTYPE_CAUSECODE 12 /* Cause code*/
+
+/* -- AVP - Challenge response */
+#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE 13 /* Challenge response */
+#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE_SIZE 16
+
+/* -- AVP - Assign session ID */
+#define PPPOL2TP_AVPTYPE_SESSIONID 14 /* Assign Session ID */
+
+/* -- AVP - Call serial number */
+#define PPPOL2TP_AVPTYPE_CALLSERIALNUMBER 15 /* Call Serial Number */
+
+/* -- AVP - Framing type */
+#define PPPOL2TP_AVPTYPE_FRAMINGTYPE 19 /* Framing Type */
+#define PPPOL2TP_FRAMINGTYPE 0x00000001 /* Sync framing */
+
+/* -- AVP - TX Connect Speed */
+#define PPPOL2TP_AVPTYPE_TXCONNECTSPEED 24 /* TX Connect Speed */
+#define PPPOL2TP_TXCONNECTSPEED 100000000 /* Connect speed: 100 Mbits/s */
+
+/* L2TP Session state */
+#define PPPOL2TP_STATE_INITIAL 0
+#define PPPOL2TP_STATE_SCCRQ_SENT 1
+#define PPPOL2TP_STATE_ICRQ_SENT 2
+#define PPPOL2TP_STATE_ICCN_SENT 3
+#define PPPOL2TP_STATE_DATA 4
+
+#define PPPOL2TP_OUTPUT_DATA_HEADER_LEN 6 /* Our data header len */
+
+/*
+ * PPPoL2TP interface control block.
+ */
+typedef struct pppol2tp_pcb_s pppol2tp_pcb;
+struct pppol2tp_pcb_s {
+ ppp_pcb *ppp; /* PPP PCB */
+ u8_t phase; /* L2TP phase */
+ struct udp_pcb *udp; /* UDP L2TP Socket */
+ struct netif *netif; /* Output interface, used as a default route */
+ ip_addr_t remote_ip; /* LNS IP Address */
+ u16_t remote_port; /* LNS port */
+#if PPPOL2TP_AUTH_SUPPORT
+ const u8_t *secret; /* Secret string */
+ u8_t secret_len; /* Secret string length */
+ u8_t secret_rv[16]; /* Random vector */
+ u8_t challenge_hash[16]; /* Challenge response */
+ u8_t send_challenge; /* Boolean whether the next sent packet should contains a challenge response */
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+ u16_t tunnel_port; /* Tunnel port */
+ u16_t our_ns; /* NS to peer */
+ u16_t peer_nr; /* NR from peer */
+ u16_t peer_ns; /* Expected NS from peer */
+ u16_t source_tunnel_id; /* Tunnel ID assigned by peer */
+ u16_t remote_tunnel_id; /* Tunnel ID assigned to peer */
+ u16_t source_session_id; /* Session ID assigned by peer */
+ u16_t remote_session_id; /* Session ID assigned to peer */
+
+ u8_t sccrq_retried; /* number of SCCRQ retries already done */
+ u8_t icrq_retried; /* number of ICRQ retries already done */
+ u8_t iccn_retried; /* number of ICCN retries already done */
+};
+
+
+/* Create a new L2TP session. */
+ppp_pcb *pppol2tp_create(struct netif *pppif,
+ struct netif *netif, const ip_addr_t *ipaddr, u16_t port,
+ const u8_t *secret, u8_t secret_len,
+ ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPOL2TP_H */
+#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppos.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppos.h
new file mode 100644
index 0000000..380a965
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/pppos.h
@@ -0,0 +1,126 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Serial header file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOS_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPOS_H
+#define PPPOS_H
+
+#include "lwip/sys.h"
+
+#include "ppp.h"
+#include "vj.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* PPP packet parser states. Current state indicates operation yet to be
+ * completed. */
+enum {
+ PDIDLE = 0, /* Idle state - waiting. */
+ PDSTART, /* Process start flag. */
+ PDADDRESS, /* Process address field. */
+ PDCONTROL, /* Process control field. */
+ PDPROTOCOL1, /* Process protocol field 1. */
+ PDPROTOCOL2, /* Process protocol field 2. */
+ PDDATA /* Process data byte. */
+};
+
+/* PPPoS serial output callback function prototype */
+typedef u32_t (*pppos_output_cb_fn)(ppp_pcb *pcb, u8_t *data, u32_t len, void *ctx);
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u8_t ext_accm[32];
+
+/*
+ * PPPoS interface control block.
+ */
+typedef struct pppos_pcb_s pppos_pcb;
+struct pppos_pcb_s {
+ /* -- below are data that will NOT be cleared between two sessions */
+ ppp_pcb *ppp; /* PPP PCB */
+ pppos_output_cb_fn output_cb; /* PPP serial output callback */
+
+ /* -- below are data that will be cleared between two sessions
+ *
+ * last_xmit must be the first member of cleared members, because it is
+ * used to know which part must not be cleared.
+ */
+ u32_t last_xmit; /* Time of last transmission. */
+ ext_accm out_accm; /* Async-Ctl-Char-Map for output. */
+
+ /* flags */
+ unsigned int open :1; /* Set if PPPoS is open */
+ unsigned int pcomp :1; /* Does peer accept protocol compression? */
+ unsigned int accomp :1; /* Does peer accept addr/ctl compression? */
+
+ /* PPPoS rx */
+ ext_accm in_accm; /* Async-Ctl-Char-Map for input. */
+ struct pbuf *in_head, *in_tail; /* The input packet. */
+ u16_t in_protocol; /* The input protocol code. */
+ u16_t in_fcs; /* Input Frame Check Sequence value. */
+ u8_t in_state; /* The input process state. */
+ u8_t in_escaped; /* Escape next character. */
+};
+
+/* Create a new PPPoS session. */
+ppp_pcb *pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb,
+ ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
+/* Pass received raw characters to PPPoS to be decoded through lwIP TCPIP thread. */
+err_t pppos_input_tcpip(ppp_pcb *ppp, u8_t *s, int l);
+#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
+
+/* PPP over Serial: this is the input function to be called for received data. */
+void pppos_input(ppp_pcb *ppp, u8_t* data, int len);
+
+
+/*
+ * Functions called from lwIP
+ * DO NOT CALL FROM lwIP USER APPLICATION.
+ */
+#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
+err_t pppos_input_sys(struct pbuf *p, struct netif *inp);
+#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPOS_H */
+#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/upap.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/upap.h
new file mode 100644
index 0000000..540d981
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/upap.h
@@ -0,0 +1,131 @@
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ * endorse or promote products derived from this software without
+ * prior written permission. For permission or any legal
+ * details, please contact
+ * Office of Technology Transfer
+ * Carnegie Mellon University
+ * 5000 Forbes Avenue
+ * Pittsburgh, PA 15213-3890
+ * (412) 268-4387, fax: (412) 268-7395
+ * tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ * acknowledgment:
+ * "This product includes software developed by Computing Services
+ * at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: upap.h,v 1.8 2002/12/04 23:03:33 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef UPAP_H
+#define UPAP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN 4
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ 1 /* Authenticate-Request */
+#define UPAP_AUTHACK 2 /* Authenticate-Ack */
+#define UPAP_AUTHNAK 3 /* Authenticate-Nak */
+
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL 0 /* Connection down */
+#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */
+#define UPAPCS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN 4 /* We've received an Ack */
+#define UPAPCS_BADAUTH 5 /* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL 0 /* Connection down */
+#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */
+#define UPAPSS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */
+#define UPAPSS_OPEN 4 /* We've sent an Ack */
+#define UPAPSS_BADAUTH 5 /* We've sent a Nak */
+
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to ppp_opts.h */
+#define UPAP_DEFTIMEOUT 3 /* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */
+#endif /* moved to ppp_opts.h */
+
+/*
+ * Each interface is described by upap structure.
+ */
+#if PAP_SUPPORT
+typedef struct upap_state {
+ const char *us_user; /* User */
+ u8_t us_userlen; /* User length */
+ const char *us_passwd; /* Password */
+ u8_t us_passwdlen; /* Password length */
+ u8_t us_clientstate; /* Client state */
+#if PPP_SERVER
+ u8_t us_serverstate; /* Server state */
+#endif /* PPP_SERVER */
+ u8_t us_id; /* Current id */
+ u8_t us_transmits; /* Number of auth-reqs sent */
+} upap_state;
+#endif /* PAP_SUPPORT */
+
+
+void upap_authwithpeer(ppp_pcb *pcb, const char *user, const char *password);
+#if PPP_SERVER
+void upap_authpeer(ppp_pcb *pcb);
+#endif /* PPP_SERVER */
+
+extern const struct protent pap_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UPAP_H */
+#endif /* PPP_SUPPORT && PAP_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/vj.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/vj.h
new file mode 100644
index 0000000..77d9976
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/ppp/vj.h
@@ -0,0 +1,169 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.7 2010/02/22 17:52:09 goldsimon Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley. The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && VJ_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "lwip/ip.h"
+#include "lwip/priv/tcp_priv.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_SLOTS 16 /* must be > 2 and < 256 */
+#define MAX_HDR 128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits). The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet. The next two octets are the TCP checksum
+ * from the original datagram. The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ *
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID. (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.) Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0. (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type. There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows. Top
+ * three bits are actual packet type. For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP 0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP 0x80
+#define TYPE_ERROR 0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C 0x40 /* flag bits for what changed in a packet */
+#define NEW_I 0x20
+#define NEW_S 0x08
+#define NEW_A 0x04
+#define NEW_W 0x02
+#define NEW_U 0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire. This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+ struct cstate *cs_next; /* next most recently used state (xmit only) */
+ u16_t cs_hlen; /* size of hdr (receive only) */
+ u8_t cs_id; /* connection # associated with this state */
+ u8_t cs_filler;
+ union {
+ char csu_hdr[MAX_HDR];
+ struct ip_hdr csu_ip; /* ip/tcp hdr from most recent packet */
+ } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+ u32_t vjs_packets; /* outbound packets */
+ u32_t vjs_compressed; /* outbound compressed packets */
+ u32_t vjs_searches; /* searches for connection state */
+ u32_t vjs_misses; /* times couldn't find conn. state */
+ u32_t vjs_uncompressedin; /* inbound uncompressed packets */
+ u32_t vjs_compressedin; /* inbound compressed packets */
+ u32_t vjs_errorin; /* inbound unknown type packets */
+ u32_t vjs_tossed; /* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+ struct cstate *last_cs; /* most recently used tstate */
+ u8_t last_recv; /* last rcvd conn. id */
+ u8_t last_xmit; /* last sent conn. id */
+ u16_t flags;
+ u8_t maxSlotIndex;
+ u8_t compressSlot; /* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+ struct vjstat stats;
+#endif
+ struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
+ struct cstate rstate[MAX_SLOTS]; /* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
+
+extern void vj_compress_init (struct vjcompress *comp);
+extern u8_t vj_compress_tcp (struct vjcompress *comp, struct pbuf **pb);
+extern void vj_uncompress_err (struct vjcompress *comp);
+extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int vj_uncompress_tcp (struct pbuf **nb, struct vjcompress *comp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* VJ_H */
+
+#endif /* PPP_SUPPORT && VJ_SUPPORT */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/slipif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/slipif.h
new file mode 100644
index 0000000..46d2010
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/slipif.h
@@ -0,0 +1,86 @@
+/**
+ * @file
+ *
+ * SLIP netif API
+ */
+
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef LWIP_HDR_NETIF_SLIPIF_H
+#define LWIP_HDR_NETIF_SLIPIF_H
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+
+/** Set this to 1 to start a thread that blocks reading on the serial line
+ * (using sio_read()).
+ */
+#ifndef SLIP_USE_RX_THREAD
+#define SLIP_USE_RX_THREAD !NO_SYS
+#endif
+
+/** Set this to 1 to enable functions to pass in RX bytes from ISR context.
+ * If enabled, slipif_received_byte[s]() process incoming bytes and put assembled
+ * packets on a queue, which is fed into lwIP from slipif_poll().
+ * If disabled, slipif_poll() polls the serial line (using sio_tryread()).
+ */
+#ifndef SLIP_RX_FROM_ISR
+#define SLIP_RX_FROM_ISR 0
+#endif
+
+/** Set this to 1 (default for SLIP_RX_FROM_ISR) to queue incoming packets
+ * received by slipif_received_byte[s]() as long as PBUF_POOL pbufs are available.
+ * If disabled, packets will be dropped if more than one packet is received.
+ */
+#ifndef SLIP_RX_QUEUE
+#define SLIP_RX_QUEUE SLIP_RX_FROM_ISR
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t slipif_init(struct netif * netif);
+void slipif_poll(struct netif *netif);
+#if SLIP_RX_FROM_ISR
+void slipif_process_rxqueue(struct netif *netif);
+void slipif_received_byte(struct netif *netif, u8_t data);
+void slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len);
+#endif /* SLIP_RX_FROM_ISR */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_SLIPIF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xadapter.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xadapter.h
new file mode 100644
index 0000000..4d32b7f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xadapter.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2007 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XADAPTER_H_
+#define __XADAPTER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwipopts.h"
+
+#if !NO_SYS
+#include "lwip/sys.h"
+#endif
+
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#include "netif/xtopology.h"
+
+struct xemac_s {
+ enum xemac_types type;
+ int topology_index;
+ void *state;
+#if !NO_SYS
+ sys_sem_t sem_rx_data_available;
+#if defined(__arm__) && !defined(ARMR5)
+ TimerHandle_t xTimer;
+#endif
+#endif
+};
+
+enum ethernet_link_status {
+ ETH_LINK_UNDEFINED = 0,
+ ETH_LINK_UP,
+ ETH_LINK_DOWN,
+ ETH_LINK_NEGOTIATING
+};
+
+void eth_link_detect(struct netif *netif);
+void lwip_raw_init();
+int xemacif_input(struct netif *netif);
+void xemacif_input_thread(struct netif *netif);
+struct netif * xemac_add(struct netif *netif,
+ ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
+ unsigned char *mac_ethernet_address,
+ UINTPTR mac_baseaddr);
+#if defined (__arm__) || defined (__aarch64__)
+void xemacpsif_resetrx_on_no_rxdata(struct netif *netif);
+#endif
+
+/* global lwip debug variable used for debugging */
+extern int lwip_runtime_debug;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xaxiemacif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xaxiemacif.h
new file mode 100644
index 0000000..3a25466
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xaxiemacif.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2010 - 2020 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XAXIEMACIF_H__
+#define __NETIF_XAXIEMACIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xlwipconfig.h"
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "netif/xadapter.h"
+
+#include "xparameters.h"
+#include "xstatus.h"
+
+#include "xaxiethernet.h"
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+#include "xllfifo.h"
+#elif XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+#include "xmcdma.h"
+#else
+#include "xaxidma.h"
+#include "xaxidma_hw.h"
+#endif
+
+#include "netif/xpqueue.h"
+#include "xlwipconfig.h"
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#define AXIDMA_TX_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define AXIDMA_RX_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define AXIETH_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define TRIG_TYPE_RISING_EDGE_SENSITIVE 0x3
+
+#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
+#endif
+
+void xaxiemacif_setmac(u32_t index, u8_t *addr);
+u8_t* xaxiemacif_getmac(u32_t index);
+err_t xaxiemacif_init(struct netif *netif);
+int xaxiemacif_input(struct netif *netif);
+
+unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp);
+void enable_sgmii_clock(XAxiEthernet *xaxiemacp);
+unsigned configure_IEEE_phy_speed(XAxiEthernet *xaxiemacp, unsigned speed);
+unsigned phy_setup_axiemac (XAxiEthernet *xaxiemacp);
+
+/* xaxiemacif_hw.c */
+void xaxiemac_error_handler(XAxiEthernet * Temac);
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular temac instance
+ */
+typedef struct {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+ XLlFifo axififo;
+#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA)
+ XMcdma aximcdma;
+#else
+ XAxiDma axidma;
+#endif
+ XAxiEthernet axi_ethernet;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+
+ /* pointers to memory holding buffer descriptors (used only with SDMA) */
+ void *rx_bdspace;
+ void *tx_bdspace;
+} xaxiemacif_s;
+
+extern xaxiemacif_s xaxiemacif;
+
+#ifndef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+s32_t is_tx_space_available(xaxiemacif_s *emac);
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+s32_t process_sent_bds(XMcdma_ChanCtrl *Tx_Chan);
+#else
+s32_t process_sent_bds(XAxiDma_BdRing *txring);
+#endif
+#endif
+
+/* xaxiemacif_dma.c/xaxiemacif_mcdma.c */
+#ifndef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+XStatus init_axi_mcdma(struct xemac_s *xemac);
+XStatus axi_mcdma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p);
+#else
+XStatus init_axi_dma(struct xemac_s *xemac);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+XStatus axidma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p,
+ u32_t block_till_tx_complete, u32_t *to_block_index);
+#else
+XStatus axidma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p);
+#endif
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XAXIEMACIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xemacliteif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xemacliteif.h
new file mode 100644
index 0000000..c083660
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xemacliteif.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XEMACLITEIF_H__
+#define __NETIF_XEMACLITEIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "netif/xpqueue.h"
+#include "xemaclite.h"
+#include "xemaclite_i.h"
+#include "xstatus.h"
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular emaclite instance
+ */
+typedef struct {
+ XEmacLite *instance;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+} xemacliteif_s;
+
+void xemacliteif_setmac(u32_t index, u8_t *addr);
+u8_t* xemacliteif_getmac(u32_t index);
+err_t xemacliteif_init(struct netif *netif);
+int xemacliteif_input(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XEMACLITEIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xemacpsif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xemacpsif.h
new file mode 100644
index 0000000..f108920
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xemacpsif.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XEMACPSIF_H__
+#define __NETIF_XEMACPSIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xlwipconfig.h"
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "lwip/sys.h"
+#include "netif/xadapter.h"
+
+#include "xstatus.h"
+#include "sleep.h"
+#include "xparameters.h"
+#include "xparameters_ps.h" /* defines XPAR values */
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xil_cache.h"
+#include "xil_printf.h"
+#include "xscugic.h"
+#include "xemacps.h" /* defines XEmacPs API */
+
+#include "netif/xpqueue.h"
+#include "xlwipconfig.h"
+
+#if defined (__aarch64__) && (EL1_NONSECURE == 1)
+#include "xil_smc.h"
+#endif
+
+#define ZYNQ_EMACPS_0_BASEADDR 0xE000B000
+#define ZYNQ_EMACPS_1_BASEADDR 0xE000C000
+
+#define ZYNQMP_EMACPS_0_BASEADDR 0xFF0B0000
+#define ZYNQMP_EMACPS_1_BASEADDR 0xFF0C0000
+#define ZYNQMP_EMACPS_2_BASEADDR 0xFF0D0000
+#define ZYNQMP_EMACPS_3_BASEADDR 0xFF0E0000
+
+#define CRL_APB_GEM0_REF_CTRL 0xFF5E0050
+#define CRL_APB_GEM1_REF_CTRL 0xFF5E0054
+#define CRL_APB_GEM2_REF_CTRL 0xFF5E0058
+#define CRL_APB_GEM3_REF_CTRL 0xFF5E005C
+
+#define CRL_APB_GEM_DIV0_MASK 0x00003F00
+#define CRL_APB_GEM_DIV0_SHIFT 8
+#define CRL_APB_GEM_DIV1_MASK 0x003F0000
+#define CRL_APB_GEM_DIV1_SHIFT 16
+
+#define VERSAL_EMACPS_0_BASEADDR 0xFF0C0000
+#define VERSAL_EMACPS_1_BASEADDR 0xFF0D0000
+
+#define VERSAL_CRL_GEM0_REF_CTRL 0xFF5E0118
+#define VERSAL_CRL_GEM1_REF_CTRL 0xFF5E011C
+
+#define VERSAL_CRL_GEM_DIV_MASK 0x0003FF00
+#define VERSAL_CRL_APB_GEM_DIV_SHIFT 8
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (__MICROBLAZE__)
+#if defined (USE_JUMBO_FRAMES)
+#define ZYNQMP_USE_JUMBO
+#endif
+#endif
+
+#define GEM_VERSION_ZYNQMP 7
+#define GEM_VERSION_VERSAL 0x107
+
+#define MAX_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE)
+
+void xemacpsif_setmac(u32_t index, u8_t *addr);
+u8_t* xemacpsif_getmac(u32_t index);
+err_t xemacpsif_init(struct netif *netif);
+s32_t xemacpsif_input(struct netif *netif);
+
+/* xaxiemacif_hw.c */
+void xemacps_error_handler(XEmacPs * Temac);
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular temac instance
+ */
+typedef struct {
+ XEmacPs emacps;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+
+ /* pointers to memory holding buffer descriptors (used only with SDMA) */
+ void *rx_bdspace;
+ void *tx_bdspace;
+
+ unsigned int last_rx_frms_cntr;
+
+} xemacpsif_s;
+
+extern xemacpsif_s xemacpsif;
+
+s32_t is_tx_space_available(xemacpsif_s *emac);
+
+/* xemacpsif_dma.c */
+
+void process_sent_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *txring);
+u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr);
+void detect_phy(XEmacPs *xemacpsp);
+void emacps_send_handler(void *arg);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p,
+ u32_t block_till_tx_complete, u32_t *to_block_index);
+#else
+XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p);
+#endif
+void emacps_recv_handler(void *arg);
+void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord);
+void setup_rx_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *rxring);
+void HandleTxErrors(struct xemac_s *xemac);
+void HandleEmacPsError(struct xemac_s *xemac);
+XEmacPs_Config *xemacps_lookup_config(unsigned mac_base);
+void init_emacps(xemacpsif_s *xemacps, struct netif *netif);
+void setup_isr (struct xemac_s *xemac);
+XStatus init_dma(struct xemac_s *xemac);
+void start_emacps (xemacpsif_s *xemacps);
+void free_txrx_pbufs(xemacpsif_s *xemacpsif);
+void free_onlytx_pbufs(xemacpsif_s *xemacpsif);
+void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif);
+void clean_dma_txdescs(struct xemac_s *xemac);
+void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif);
+void reset_dma(struct xemac_s *xemac);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XAXIEMACIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xlltemacif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xlltemacif.h
new file mode 100644
index 0000000..3664f95
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xlltemacif.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XLLTEMACIF_H__
+#define __NETIF_XLLTEMACIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "netif/xadapter.h"
+
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xlltemac.h"
+#include "xlldma.h"
+#include "xllfifo.h"
+#include "xlldma_bdring.h"
+
+#include "netif/xpqueue.h"
+#include "xlwipconfig.h"
+
+void xlltemacif_setmac(u32_t index, u8_t *addr);
+u8_t* xlltemacif_getmac(u32_t index);
+err_t xlltemacif_init(struct netif *netif);
+int xlltemacif_input(struct netif *netif);
+unsigned get_IEEE_phy_speed(XLlTemac *xlltemacp);
+unsigned Phy_Setup (XLlTemac *xlltemacp);
+unsigned configure_IEEE_phy_speed(XLlTemac *xlltemacp, unsigned speed);
+
+/* xlltemacif_hw.c */
+void xlltemac_error_handler(XLlTemac * Temac);
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular temac instance
+ */
+typedef struct {
+ XLlDma lldma;
+ XLlFifo llfifo;
+ XLlTemac lltemac;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+
+ /* pointers to memory holding buffer descriptors (used only with SDMA) */
+ void *rx_bdspace;
+ void *tx_bdspace;
+} xlltemacif_s;
+
+extern xlltemacif_s xlltemacif;
+
+/* xlltemacif_sdma.c */
+XStatus init_sdma(struct xemac_s *xemac);
+int process_sent_bds(XLlDma_BdRing *txring);
+void lldma_send_handler(void *arg);
+XStatus lldma_sgsend(xlltemacif_s *xlltemacif, struct pbuf *p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XLLTEMACIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xpqueue.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xpqueue.h
new file mode 100644
index 0000000..132f02f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xpqueue.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __LWIP_PBUF_QUEUE_H_
+#define __LWIP_PBUF_QUEUE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PQ_QUEUE_SIZE 4096
+
+typedef struct {
+ void *data[PQ_QUEUE_SIZE];
+ int head, tail, len;
+} pq_queue_t;
+
+pq_queue_t* pq_create_queue();
+int pq_enqueue(pq_queue_t *q, void *p);
+void* pq_dequeue(pq_queue_t *q);
+int pq_qlength(pq_queue_t *q);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xtopology.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xtopology.h
new file mode 100644
index 0000000..51718f1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/xtopology.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XTOPOLOGY_H_
+#define __XTOPOLOGY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+
+enum xemac_types { xemac_type_unknown = -1, xemac_type_xps_emaclite, xemac_type_xps_ll_temac, xemac_type_axi_ethernet, xemac_type_emacps };
+
+struct xtopology_t {
+ UINTPTR emac_baseaddr;
+ enum xemac_types emac_type;
+ UINTPTR intc_baseaddr;
+ unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */
+ UINTPTR scugic_baseaddr; /* valid only for Zynq */
+ unsigned scugic_emac_intr; /* valid only for GEM */
+};
+
+extern int xtopology_n_emacs;
+extern struct xtopology_t xtopology[];
+
+int xtopology_find_index(unsigned base);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/zepif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/zepif.h
new file mode 100644
index 0000000..2a801b4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/netif/zepif.h
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * A netif implementing the ZigBee Eencapsulation Protocol (ZEP).
+ * This is used to tunnel 6LowPAN over UDP.
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#ifndef LWIP_HDR_ZEPIF_H
+#define LWIP_HDR_ZEPIF_H
+
+#include "lwip/opt.h"
+#include "netif/lowpan6.h"
+
+#if LWIP_IPV6 && LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ZEPIF_DEFAULT_UDP_PORT 17754
+
+/** Pass this struct as 'state' to netif_add to control the behaviour
+ * of this netif. If NULL is passed, default behaviour is chosen */
+struct zepif_init {
+ /** The UDP port used to ZEP frames from (0 = default) */
+ u16_t zep_src_udp_port;
+ /** The UDP port used to ZEP frames to (0 = default) */
+ u16_t zep_dst_udp_port;
+ /** The IP address to sed ZEP frames from (NULL = ANY) */
+ const ip_addr_t *zep_src_ip_addr;
+ /** The IP address to sed ZEP frames to (NULL = BROADCAST) */
+ const ip_addr_t *zep_dst_ip_addr;
+ /** If != NULL, the udp pcb is bound to this netif */
+ const struct netif *zep_netif;
+ /** MAC address of the 6LowPAN device */
+ u8_t addr[6];
+};
+
+err_t zepif_init(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 && LWIP_UDP */
+
+#endif /* LWIP_HDR_ZEPIF_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/profile.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/profile.h
new file mode 100644
index 0000000..63f503a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/profile.h
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef PROFILE_H
+#define PROFILE_H 1
+
+#include
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define HISTCOUNTER u16
+
+struct tostruct {
+ u32 selfpc;
+ s32 count;
+ s16 link;
+ u16 pad;
+};
+
+struct fromstruct {
+ u32 frompc ;
+ s16 link ;
+ u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y) (((x)/(y))*(y))
+#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+ s32 state;
+
+ /* Histogram Information */
+ u16 *kcount; /* No. of bins in histogram */
+ u32 kcountsize; /* Histogram samples */
+
+ /* Call-graph Information */
+ struct fromstruct *froms;
+ u32 fromssize;
+ struct tostruct *tos;
+ u32 tossize;
+
+ /* Initialization I/Ps */
+ u32 lowpc;
+ u32 highpc;
+ u32 textsize;
+ /* u32 cg_froms, */
+ /* u32 cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define GMON_PROF_ON 0
+#define GMON_PROF_BUSY 1
+#define GMON_PROF_ERROR 2
+#define GMON_PROF_OFF 3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define GPROF_STATE 0 /* int: profiling enabling variable */
+#define GPROF_COUNT 1 /* struct: profile tick count buffer */
+#define GPROF_FROMS 2 /* struct: from location hash bucket */
+#define GPROF_TOS 3 /* struct: destination/count structure */
+#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PROFILE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/sleep.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/sleep.h
new file mode 100644
index 0000000..f3a632b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/sleep.h
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+* related APIs.
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 11/02/17 Added processor specific sleep rountines
+* function prototypes.
+*
+*
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param IO_func - accessor function to read the register contents.
+* Depends on the register width.
+* @param ADDR - Address to be polled
+* @param VALUE - variable to read the value
+* @param COND - Condition to checked (usually involves VALUE)
+* @param TIMEOUT_US - timeout in micro seconds
+*
+* @return 0 - when the condition is met
+* -1 - when the condition is not met till the timeout period
+*
+* @note none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( { \
+ u64 timeout = TIMEOUT_US/100; \
+ if(TIMEOUT_US%100!=0) \
+ timeout++; \
+ for(;;) { \
+ VALUE = IO_func(ADDR); \
+ if(COND) \
+ break; \
+ else { \
+ usleep(100); \
+ timeout--; \
+ if(timeout==0) \
+ break; \
+ } \
+ } \
+ (timeout>0) ? 0 : -1; \
+ } )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/smc.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/smc.h
new file mode 100644
index 0000000..f7cc91c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/smc.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 11/03/09 Initial release.
+* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+* as smc.c is removed
+*
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET 0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/vectors.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/vectors.h
new file mode 100644
index 0000000..56bacbc
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/vectors.h
@@ -0,0 +1,84 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
+* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xadcps.h
new file mode 100644
index 0000000..900edf0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xadcps.h
@@ -0,0 +1,589 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_3
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+* - 10-bit, 200-KSPS (kilo samples per second)
+* Analog-to-Digital Converter (ADC)
+* - Monitoring of on-chip supply voltages and temperature
+* - 1 dedicated differential analog-input pair and
+* 16 auxiliary differential analog-input pairs
+* - Automatic alarms based on user defined limits for the on-chip
+* supply voltages and temperature
+* - Automatic Channel Sequencer, programmable averaging, programmable
+* acquisition time for the external inputs, unipolar or differential
+* input selection for the external inputs
+* - Inbuilt Calibration
+* - Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* XADC Channel Sequencer Modes
+*
+* The XADC Channel Sequencer supports the following operating modes:
+*
+* - Default : This is the default mode after power up.
+* In this mode of operation the XADC operates in
+* a sequence mode, monitoring the on chip sensors:
+* Temperature, VCCINT, and VCCAUX.
+* - One pass through sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers for a single pass and then stops.
+* - Continuous cycling of sequence : In this mode the XADC
+* converts the channels enabled in the Sequencer Channel Enable
+* registers continuously.
+* - Single channel mode: In this mode the XADC Channel
+* Sequencer is disabled and the XADC operates in a
+* Single Channel Mode.
+* The XADC can operate either in a Continuous or Event
+* driven sampling mode in the single channel mode.
+* - Simultaneous Sampling Mode: In this mode the XADC Channel
+* Sequencer will automatically sequence through eight fixed pairs
+* of auxiliary analog input channels for simulataneous conversion.
+* - Independent ADC mode: In this mode the first ADC (A) is used to
+* is used to implement a fixed monitoring mode similar to the
+* default mode but the alarm fucntions ar eenabled.
+* The second ADC (B) is available to be used with external analog
+* input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* Building the driver
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* Limitations of the driver
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+* in xadcps.c to fix CR #693371
+* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
+* CR#749687
+* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+* functions.
+* Modified Assert for XAdcPs_SetSingleChParams in
+* xadcps.c to fix CR #807563.
+* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
+* xadcps.c (CR#854437).
+* ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of xadcps
+* examples to recognize it as documentation block
+* for doxygen generation.
+* 2.3 mn 07/09/18 Fix Doxygen warning
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */
+#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */
+#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP 0x4 /**< VREFP */
+#define XADCPS_CH_VREFN 0x5 /**< VREFN */
+#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */
+#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */
+#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */
+#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XAdcPs_Config Config; /**< XAdcPs_Config of current device */
+ u32 IsReady; /**< Device is initialized and ready */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in Event Sampling Mode.
+* - FALSE if the device is in Continuous Sampling Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
+ TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+* - TRUE if the device is in External Mux Mode.
+* - FALSE if the device is NOT in External Mux Mode.
+*
+* @note C-Style signature:
+* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
+ (((XAdcPs_ReadInternalReg(InstancePtr, \
+ XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
+ TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param AdcData is the Raw ADC Data from XADC.
+*
+* @return The Temperature in centigrades.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData) \
+ ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param AdcData is the XADC/ADC Raw Data.
+*
+* @return The Voltage in volts.
+*
+* @note C-Style signature:
+* float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) \
+ ((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param Temperature is the Temperature in centigrades to be
+* converted to XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature) \
+ ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param Voltage is the Voltage in volts to be converted to
+* XADC/ADC Raw Data.
+*
+* @return The XADC/ADC Raw Data.
+*
+* @note C-Style signature:
+* int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage) \
+ ((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+* @param Data is the value to be written to XADC register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data) \
+ XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return Data read from the FIFO
+*
+* @note C-Style signature:
+* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr) \
+ XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+ XAdcPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+ u8 Channel,
+ int IncreaseAcqCycles,
+ int IsEventMode,
+ int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* End of protection macro. */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xadcps_hw.h
new file mode 100644
index 0000000..dd51473
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xadcps_hw.h
@@ -0,0 +1,498 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_3
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note None.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------------
+* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
+* CR#749687
+*
+*
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+ * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between
+ * successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+ *
+ * The definitions are same for the Interrupt Status Register and
+ * Interrupt Mask Register. They are defined only once.
+ * @{
+ */
+#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */
+#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */
+#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */
+#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */
+#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */
+#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */
+#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */
+#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+ * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */
+#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */
+#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */
+#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */
+#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */
+#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */
+#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */
+#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/
+ * Continuous mode selection
+ */
+#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power
+ Supply Gain/Offset
+ Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power
+ Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+ Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset
+ Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
+*
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
+#define XBASIC_TYPES_H /* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char Xuint8; /**< unsigned 8-bit */
+typedef char Xint8; /**< signed 8-bit */
+typedef unsigned short Xuint16; /**< unsigned 16-bit */
+typedef short Xint16; /**< signed 16-bit */
+typedef unsigned long Xuint32; /**< unsigned 32-bit */
+typedef long Xint32; /**< signed 32-bit */
+typedef float Xfloat32; /**< 32-bit floating point */
+typedef double Xfloat64; /**< 64-bit double precision FP */
+typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+ Xuint32 Upper;
+ Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32 u32;
+typedef Xuint16 u16;
+typedef Xuint8 u8;
+#endif
+#else
+#include
+#endif
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL NULL
+#define XTRUE TRUE
+#define XFALSE FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning Please refer the Standalone BSP UG647 for further details
+
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
new file mode 100644
index 0000000..70b8aad
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_4
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
new file mode 100644
index 0000000..e4a5e28
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_7
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
+# extra compiler flags. Now, user can remove default flags
+# from extra compiler flags. It fixes CR#998768.
+******************************************************************************/
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xddrps.h
new file mode 100644
index 0000000..b4d1f56
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xddrps.h
@@ -0,0 +1,62 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ *
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdebug.h
new file mode 100644
index 0000000..650946b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG /* prevent circular inclusions */
+#define XDEBUG /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
+#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
+#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x) x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdevcfg.h
new file mode 100644
index 0000000..6586370
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdevcfg.h
@@ -0,0 +1,399 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* Interrupts
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
new file mode 100644
index 0000000..80b6678
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
@@ -0,0 +1,391 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdmaps.h
new file mode 100644
index 0000000..73e2b1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdmaps.h
@@ -0,0 +1,349 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_4
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
+*
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+int XDmaPs_Instr_DMARMB(char *DmaProg);
+int XDmaPs_Instr_DMAWMB(char *DmaProg);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
new file mode 100644
index 0000000..42dfe69
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
@@ -0,0 +1,289 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+*
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps.h
new file mode 100644
index 0000000..c22354f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps.h
@@ -0,0 +1,807 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_8
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * Driver Description
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * Initialization & Configuration
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * Interrupts and Asynchronous Callbacks
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * Virtual Memory
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * DMA
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * Alignment & Data Cache Restrictions
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * Buffer Copying
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * Checksum Offloading
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * PHY Interfaces
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * Asserts
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
+ * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_bd.h
new file mode 100644
index 0000000..2b22223
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_bd.h
@@ -0,0 +1,784 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_8
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * Buffer Descriptors
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * Performance
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
+ * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+ *
+ *
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param InstancePtr is the pointer to XEmacps instance
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
new file mode 100644
index 0000000..ed8ce2a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
@@ -0,0 +1,237 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_hw.h
new file mode 100644
index 0000000..4a01aea
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xemacps_hw.h
@@ -0,0 +1,653 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 3.8 hk 09/17/18 Fix PTP interrupt masks.
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
+
+#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
+
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xenv.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xenv.h
new file mode 100644
index 0000000..9c7c4c3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xenv.h
@@ -0,0 +1,183 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch 10/24/02 Added XENV_LINUX
+* 1.00a rmm 04/17/02 First release
+*
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr is the destination address to copy data to.
+ * @param SrcPtr is the source address to copy data from.
+ * @param Bytes is the number of bytes to copy.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr is the destination address to set.
+ * @param Data contains the value to set.
+ * @param Bytes is the number of bytes to set.
+ *
+ * @return None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param Stamp1Ptr - First sampled time stamp.
+ * @param Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param delay is the number of microseconds to delay.
+ *
+ * @return None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xenv_standalone.h
new file mode 100644
index 0000000..ef905af
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xenv_standalone.h
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* This file is not intended to be included directly by driver code.
+* Instead, the generic xenv.h file is intended to be included by driver
+* code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr 02/28/07 Added cache handling macros.
+* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+* used under Xilinx standalone BSP.
+* 1.00a xd 11/03/04 Improved support for doxygen.
+* 1.00a rmm 03/21/02 First release
+* 1.00a wgr 03/22/07 Converted to new coding style.
+* 1.00a rpm 06/29/07 Added udelay macro for standalone
+* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
+* to in MICROBLAZE section
+* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include
+
+#if defined __MICROBLAZE__
+# include "mb_interface.h"
+# include "xparameters.h" /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+# include "sleep.h"
+# include "xcache_l.h" /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param SrcPtr
+ * Source address to copy data from.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * This implemention MAY BREAK work if source and target memory
+ * area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+ memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param DestPtr
+ * Destination address to copy data to.
+ *
+ * @param Data
+ * Value to set.
+ *
+ * @param Bytes
+ * Number of bytes to copy.
+ *
+ * @return None.
+ *
+ * @note
+ * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+ memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param Stamp1Ptr is the first sampled time stamp.
+ * @param Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return 0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param delay
+ * Number of microseconds to delay.
+ *
+ * @return None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay) usleep(delay)
+#define udelay(delay) usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE() \
+ { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE() \
+ { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
+# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
+# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
+
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+# define XCACHE_ENABLE_DCACHE()
+# define XCACHE_DISABLE_DCACHE()
+# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
+# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
+
+# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
+
+# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+ microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+# define XCACHE_ENABLE_ICACHE()
+# define XCACHE_DISABLE_ICACHE()
+#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ * specific memory region (0x80000001). Each bit (0-30) in the regions
+ * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ * range.
+ *
+ * regions --> cached address range
+ * ------------|--------------------------------------------------
+ * 0x80000000 | [0, 0x7FFFFFF]
+ * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
+ * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+ XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+ XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef XENV_STANDALONE_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xgpiops.h
new file mode 100644
index 0000000..3ab40b9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xgpiops.h
@@ -0,0 +1,274 @@
+
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_4
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
new file mode 100644
index 0000000..59ec921
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_assert.h
new file mode 100644
index 0000000..917de31
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_assert.h
@@ -0,0 +1,191 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
+*
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE 0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for void functions. This in
+* conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to
+* continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to
+* false, the assert occurs.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief This assert macro is to be used for functions that do return a
+* value. This in conjunction with the Xil_AssertWait boolean can be
+* used to accomodate tests so that asserts which fail allow execution
+* to continue.
+*
+* @param Expression: expression to be evaluated. If it evaluates to false,
+* the assert occurs.
+*
+* @return Returns 0 unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression) \
+{ \
+ if (Expression) { \
+ Xil_AssertStatus = XIL_ASSERT_NONE; \
+ } else { \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+ } \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for void functions.
+* Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return; \
+}
+
+/*****************************************************************************/
+/**
+* @brief Always assert. This assert macro is to be used for functions that
+* do return a value. Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+* case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways() \
+{ \
+ Xil_Assert(__FILE__, __LINE__); \
+ Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
+ return 0; \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache.h
new file mode 100644
index 0000000..ce6fcf4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache.h
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/29/10 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+* APIs.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+ XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache_l.h
new file mode 100644
index 0000000..b6ff809
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache_l.h
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 01/24/10 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
new file mode 100644
index 0000000..7e2a7d9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
@@ -0,0 +1,89 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 12/11/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+ cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+ cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_errata.h
new file mode 100644
index 0000000..8ac0795
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_errata.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt 04/18/13 First release
+* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
+*
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ * Errata No: 742230
+ * Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ * Errata No: 743622
+ * Description: Faulty hazard checking in the Store Buffer may lead
+ * to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ * Errata No: 775420
+ * Description: A data cache maintenance operation which aborts,
+ * might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ * Errata No: 794073
+ * Description: Speculative instruction fetches with MMU disabled
+ * might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ * Errata No: 588369
+ * Description: Clean & Invalidate maintenance operations do not
+ * invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ * Errata No: 727915
+ * Description: Background Clean and Invalidate by Way operation
+ * can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif /* ENABLE_ARM_ERRATA */
+
+#endif /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_exception.h
new file mode 100644
index 0000000..4da1b73
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_exception.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2 pkp 28/05/15 First release
+* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT 1U
+#define XIL_EXCEPTION_ID_IRQ_INT 2U
+#define XIL_EXCEPTION_ID_FIQ_INT 3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_LAST 5U
+#else
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief Enable Exceptions.
+*
+* @param Mask: Value for enabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+/****************************************************************************/
+/**
+* @brief Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief Disable Exceptions.
+*
+* @param Mask: Value for disabling the exceptions.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
+* API is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief Disable the nested interrupts by setting the I and F bits. This API
+* is defined for cortex-a9 and cortex-r5.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_hal.h
new file mode 100644
index 0000000..720adf9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_hal.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/28/09 Initial release
+*
+*
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_io.h
new file mode 100644
index 0000000..00207cf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_io.h
@@ -0,0 +1,341 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/29/14 First release
+* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+* ARM processors
+*
+******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+# define INST_SYNC mbar(0)
+# define DATA_SYNC mbar(1)
+# else
+# define SYNCHRONIZE_IO dmb()
+# define INST_SYNC isb()
+# define DATA_SYNC dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading
+* from the specified address and returning the 8 bit Value read from
+* that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+ return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading from
+* the specified address and returning the 16 bit Value read from that
+* address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+ return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by
+* reading from the specified address and returning the 32 bit Value
+* read from that address.
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+ return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an input operation for a memory location by reading the
+* 64 bit Value read from that address.
+*
+*
+* @param Addr: contains the address to perform the input operation
+*
+* @return The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+ return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for an memory location by
+* writing the 8 bit Value to the the specified address.
+*
+* @param Addr: contains the address to perform the output operation
+* @param Value: contains the 8 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+ volatile u8 *LocalAddr = (volatile u8 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 16 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+ volatile u16 *LocalAddr = (volatile u16 *)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 32 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains the 32 bit Value to be written at the specified
+* address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+ volatile u32 *LocalAddr = (volatile u32 *)Addr;
+ *LocalAddr = Value;
+#else
+ XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief Performs an output operation for a memory location by writing the
+* 64 bit Value to the the specified address.
+*
+* @param Addr contains the address to perform the output operation
+* @param Value contains 64 bit Value to be written at the specified address.
+*
+* @return None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+ volatile u64 *LocalAddr = (volatile u64 *)Addr;
+ *LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+# else
+# define Xil_In16BE Xil_In16
+# define Xil_In32BE Xil_In32
+# define Xil_Out16BE Xil_Out16
+# define Xil_Out32BE Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE Xil_In16
+# define Xil_In32LE Xil_In32
+# define Xil_Out16LE Xil_Out16
+# define Xil_Out32LE Xil_Out32
+# define Xil_Htons Xil_EndianSwap16
+# define Xil_Htonl Xil_EndianSwap32
+# define Xil_Ntohs Xil_EndianSwap16
+# define Xil_Ntohl Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+ u16 value = Xil_In16(Addr);
+ return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+ u32 value = Xil_In32(Addr);
+ return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+ Value = Xil_EndianSwap16(Value);
+ Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+ Value = Xil_EndianSwap32(Value);
+ Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_macroback.h
new file mode 100644
index 0000000..cdc2fe2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_macroback.h
@@ -0,0 +1,1048 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ * XGpio_mSetDataDirection
+ * XGpio_mGetDataReg
+ * XGpio_mSetDataReg
+ * XIIC_RESET
+ * XIIC_CLEAR_STATS
+ * XSpi_mReset
+ * XSysAce_mSetCfgAddr
+ * XSysAce_mIsCfgDone
+ * XTft_mSetPixel
+ * XTft_mGetPixel
+ * XWdtTb_mEnableWdt
+ * XWdtTb_mDisbleWdt
+ * XWdtTb_mRestartWdt
+ * XWdtTb_mGetTimebaseReg
+ * XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_mem.h
new file mode 100644
index 0000000..afc0f8b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_mem.h
@@ -0,0 +1,55 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1 nsk 11/07/16 First release.
+*
+*
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
new file mode 100644
index 0000000..3a26175
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
@@ -0,0 +1,273 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc 03/07/13 First release.
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
+#define XIL_MISC_RESET_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR 0xF8006000U
+#define XSLCR_BASEADDR 0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE 0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_mmu.h
new file mode 100644
index 0000000..3b63c0b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_mmu.h
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 01/12/12 Initial version
+* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
+* u32 which resolves issue of CR#805869
+* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02 /* Strongly ordered */
+#define DEVICE_MEMORY 0xC06 /* Device memory */
+#define RESERVED 0x0 /* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE (~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_printf.h
new file mode 100644
index 0000000..016ae3b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+#include
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to */
+/* make xil_printf re-entrant. */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and */
+/* that is unacceptable in most embedded systems. */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/* */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
new file mode 100644
index 0000000..4449ba6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+*
+* MODIFICATION HISTORY :
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6 srm 10/18/17 First Release.
+*
+*
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H /* by using protection macros */
+/**************************** Include Files ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT 32U
+#define XSleep_ReadCounterVal Xil_In32
+#define XCntrVal u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT 16U
+#define XSleep_ReadCounterVal Xil_In16
+#define XCntrVal u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
+ /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
+ /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
+ /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
+ /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
+ /**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
+ /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testcache.h
new file mode 100644
index 0000000..8289ca9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testcache.h
@@ -0,0 +1,67 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+*
Cache test
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 07/29/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
+#define XIL_TESTCACHE_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testio.h
new file mode 100644
index 0000000..6f0fc1c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testio.h
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+*
I/O test
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/05/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H /* prevent circular inclusions */
+#define XIL_TESTIO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 0
+#define XIL_TESTIO_LE 1
+#define XIL_TESTIO_BE 2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testmem.h
new file mode 100644
index 0000000..ecce6b7
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_testmem.h
@@ -0,0 +1,154 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+*
Memory test
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+* - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+* location 1 = 0x00000001
+* location 2 = 0x00000002
+* ...
+* @endcode
+*
+* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+* location 1 = 0xFFFFFFFE
+* location 2 = 0xFFFFFFFD
+* ...
+*@endcode
+*
+* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm 08/25/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
+#define XIL_TESTMEM_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE 1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS 0x00U
+#define XIL_TESTMEM_INCREMENT 0x01U
+#define XIL_TESTMEM_WALKONES 0x02U
+#define XIL_TESTMEM_WALKZEROS 0x03U
+#define XIL_TESTMEM_INVERSEADDR 0x04U
+#define XIL_TESTMEM_FIXEDPATTERN 0x05U
+#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_types.h
new file mode 100644
index 0000000..8adaf1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xil_types.h
@@ -0,0 +1,205 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm 07/14/09 First release
+* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
+* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
+* Define LONG and ULONG datatypes and mask values
+*
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H /* prevent circular inclusions */
+#define XIL_TYPES_H /* by using protection macros */
+
+#include
+#include
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+# define TRUE 1U
+#endif
+
+#ifndef FALSE
+# define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
+ assigend to "IsReady" member of driver
+ instance to indicate that driver
+ instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
+ "IsStarted" member of driver instance
+ to indicate that driver instance is
+ started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+ u32 Upper;
+ u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK ~ULONG64_HI_MASK
+
+#else
+#include
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief Returns 32-63 bits of a number.
+ * @param n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note A basic shift-right of a 64- or 32-bit quantity.
+ * Use this to suppress the "right shift count >= width of type"
+ * warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief Returns 0-31 bits of a number
+ * @param n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef NULL
+#define NULL 0U
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xl2cc.h
new file mode 100644
index 0000000..22373c1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xl2cc.h
@@ -0,0 +1,168 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm 02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+* 'xil_errata.h' for errata description
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET 0x0000U
+#define XPS_L2CC_TYPE_OFFSET 0x0004U
+#define XPS_L2CC_CNTRL_OFFSET 0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
+
+#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
+ /* Cache replacement policy, Parity enable, */
+ /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
new file mode 100644
index 0000000..b8d768f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
+* inside the APIs
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO 0x1
+#define XL2CC_DRHIT 0x2
+#define XL2CC_DRREQ 0x3
+#define XL2CC_DWHIT 0x4
+#define XL2CC_DWREQ 0x5
+#define XL2CC_DWTREQ 0x6
+#define XL2CC_IRHIT 0x7
+#define XL2CC_IRREQ 0x8
+#define XL2CC_WA 0x9
+#define XL2CC_IPFALLOC 0xa
+#define XL2CC_EPFHIT 0xb
+#define XL2CC_EPFALLOC 0xc
+#define XL2CC_SRRCVD 0xd
+#define XL2CC_SRCONF 0xe
+#define XL2CC_EPFRCVD 0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xlwipconfig.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xlwipconfig.h
new file mode 100644
index 0000000..8f8f3e2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xlwipconfig.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef __XLWIPCONFIG_H_
+#define __XLWIPCONFIG_H_
+
+
+/* This is a generated file - do not edit */
+
+#define XLWIP_CONFIG_INCLUDE_GEM 1
+#define XLWIP_CONFIG_EMAC_NUMBER 0
+#define XLWIP_CONFIG_N_TX_DESC 64
+#define XLWIP_CONFIG_N_RX_DESC 64
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xparameters.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xparameters.h
new file mode 100644
index 0000000..6723c24
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xparameters.h
@@ -0,0 +1,406 @@
+#ifndef XPARAMETERS_H /* prevent circular inclusions */
+#define XPARAMETERS_H /* by using protection macros */
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0U
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+
+
+/******************************************************************/
+
+#include "xparameters_ps.h"
+
+#define STDIN_BASEADDRESS 0xE0001000
+#define STDOUT_BASEADDRESS 0xE0001000
+
+/******************************************************************/
+
+/* Platform specific definitions */
+#define PLATFORM_ZYNQ
+
+/* Definitions for sleep timer configuration */
+#define XSLEEP_TIMER_IS_DEFAULT_TIMER
+
+
+/******************************************************************/
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
+#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
+#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
+#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
+#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral MYDNA_READ_V1_0_0 */
+#define XPAR_MYDNA_READ_V1_0_0_BASEADDR 0x43C00000
+#define XPAR_MYDNA_READ_V1_0_0_HIGHADDR 0x43C0FFFF
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 142857132
+#define XPAR_PS7_QSPI_0_QSPI_MODE 0
+#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 142857132
+#define XPAR_XQSPIPS_0_QSPI_MODE 0
+#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1U
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0U
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUTIMER */
+#define XPAR_XSCUTIMER_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
+#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver SDPS */
+#define XPAR_XSDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
+#define XPAR_PS7_SD_0_BUS_WIDTH 0
+#define XPAR_PS7_SD_0_MIO_BANK 0
+#define XPAR_PS7_SD_0_HAS_EMIO 0
+
+
+/******************************************************************/
+
+#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_XSDPS_0_BASEADDR 0xE0100000
+#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 0
+#define XPAR_XSDPS_0_MIO_BANK 0
+#define XPAR_XSDPS_0_HAS_EMIO 0
+#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+#endif /* end of protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h
new file mode 100644
index 0000000..2a6a0e0
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xparameters_ps.h
@@ -0,0 +1,334 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
+* driver tcl
+* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
+*
+*
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************** Include Files *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR 0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts */
+#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES 1U
+#define XPAR_XSLCR_0_DEVICE_ID 0U
+#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES 1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
+#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE 0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
+#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
+#define XPS_UART0_BASEADDR 0xE0000000U
+#define XPS_UART1_BASEADDR 0xE0001000U
+#define XPS_USB0_BASEADDR 0xE0002000U
+#define XPS_USB1_BASEADDR 0xE0003000U
+#define XPS_I2C0_BASEADDR 0xE0004000U
+#define XPS_I2C1_BASEADDR 0xE0005000U
+#define XPS_SPI0_BASEADDR 0xE0006000U
+#define XPS_SPI1_BASEADDR 0xE0007000U
+#define XPS_CAN0_BASEADDR 0xE0008000U
+#define XPS_CAN1_BASEADDR 0xE0009000U
+#define XPS_GPIO_BASEADDR 0xE000A000U
+#define XPS_GEM0_BASEADDR 0xE000B000U
+#define XPS_GEM1_BASEADDR 0xE000C000U
+#define XPS_QSPI_BASEADDR 0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
+#define XPS_SDIO0_BASEADDR 0xE0100000U
+#define XPS_SDIO1_BASEADDR 0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
+#define XPS_NAND_BASEADDR 0xE1000000U
+#define XPS_PARPORT0_BASEADDR 0xE2000000U
+#define XPS_PARPORT1_BASEADDR 0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
+#define XPS_TTC0_BASEADDR 0xF8001000U
+#define XPS_TTC1_BASEADDR 0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
+#define XPS_WDT_BASEADDR 0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
+#define XPS_AFI0_BASEADDR 0xF8008000U
+#define XPS_AFI1_BASEADDR 0xF8009000U
+#define XPS_AFI2_BASEADDR 0xF800A000U
+#define XPS_AFI3_BASEADDR 0xF800B000U
+#define XPS_OCM_BASEADDR 0xF800C000U
+#define XPS_EFUSE_BASEADDR 0xF800D000U
+#define XPS_CORESIGHT_BASEADDR 0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
+#define XPS_SCU_PERIPH_BASE 0xF8F00000U
+#define XPS_L2CC_BASEADDR 0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID 32U
+#define XPS_CORE_PARITY1_INT_ID 33U
+#define XPS_L2CC_INT_ID 34U
+#define XPS_OCMINTR_INT_ID 35U
+#define XPS_ECC_INT_ID 36U
+#define XPS_PMU0_INT_ID 37U
+#define XPS_PMU1_INT_ID 38U
+#define XPS_SYSMON_INT_ID 39U
+#define XPS_DVC_INT_ID 40U
+#define XPS_WDT_INT_ID 41U
+#define XPS_TTC0_0_INT_ID 42U
+#define XPS_TTC0_1_INT_ID 43U
+#define XPS_TTC0_2_INT_ID 44U
+#define XPS_DMA0_ABORT_INT_ID 45U
+#define XPS_DMA0_INT_ID 46U
+#define XPS_DMA1_INT_ID 47U
+#define XPS_DMA2_INT_ID 48U
+#define XPS_DMA3_INT_ID 49U
+#define XPS_SMC_INT_ID 50U
+#define XPS_QSPI_INT_ID 51U
+#define XPS_GPIO_INT_ID 52U
+#define XPS_USB0_INT_ID 53U
+#define XPS_GEM0_INT_ID 54U
+#define XPS_GEM0_WAKE_INT_ID 55U
+#define XPS_SDIO0_INT_ID 56U
+#define XPS_I2C0_INT_ID 57U
+#define XPS_SPI0_INT_ID 58U
+#define XPS_UART0_INT_ID 59U
+#define XPS_CAN0_INT_ID 60U
+#define XPS_FPGA0_INT_ID 61U
+#define XPS_FPGA1_INT_ID 62U
+#define XPS_FPGA2_INT_ID 63U
+#define XPS_FPGA3_INT_ID 64U
+#define XPS_FPGA4_INT_ID 65U
+#define XPS_FPGA5_INT_ID 66U
+#define XPS_FPGA6_INT_ID 67U
+#define XPS_FPGA7_INT_ID 68U
+#define XPS_TTC1_0_INT_ID 69U
+#define XPS_TTC1_1_INT_ID 70U
+#define XPS_TTC1_2_INT_ID 71U
+#define XPS_DMA4_INT_ID 72U
+#define XPS_DMA5_INT_ID 73U
+#define XPS_DMA6_INT_ID 74U
+#define XPS_DMA7_INT_ID 75U
+#define XPS_USB1_INT_ID 76U
+#define XPS_GEM1_INT_ID 77U
+#define XPS_GEM1_WAKE_INT_ID 78U
+#define XPS_SDIO1_INT_ID 79U
+#define XPS_I2C1_INT_ID 80U
+#define XPS_SPI1_INT_ID 81U
+#define XPS_UART1_INT_ID 82U
+#define XPS_CAN1_INT_ID 83U
+#define XPS_FPGA8_INT_ID 84U
+#define XPS_FPGA9_INT_ID 85U
+#define XPS_FPGA10_INT_ID 86U
+#define XPS_FPGA11_INT_ID 87U
+#define XPS_FPGA12_INT_ID 88U
+#define XPS_FPGA13_INT_ID 89U
+#define XPS_FPGA14_INT_ID 90U
+#define XPS_FPGA15_INT_ID 91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID 0U
+#define XPAR_SCUWDT_DEVICE_ID 0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xplatform_info.h
new file mode 100644
index 0000000..771d4ba
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xplatform_info.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+* function for PMUFW.
+*
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
+#define XPLATFORM_INFO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info(void);
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpm_counter.h
new file mode 100644
index 0000000..39db7d8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpm_counter.h
@@ -0,0 +1,572 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm 07/11/11 First release
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ * - b00 no instructions renamed
+ * - b01 one instruction renamed
+ * - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
+ * XPM_EVENT_DATA_WRITE,
+ * XPM_EVENT_EXCEPTION,
+ * XPM_EVENT_EXCEPRETURN,
+ * XPM_EVENT_CHANGECONTEXT,
+ * XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
+ * XPM_EVENT_UNALIGNEDACCESS,
+ * XPM_EVENT_BRANCHMISS,
+ * XPM_EVENT_CLOCKCYCLES,
+ * XPM_EVENT_BRANCHPREDICT,
+ * XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
+ * XPM_EVENT_JAVABACKBRANCH,
+ * XPM_EVENT_COHERLINEMISS,
+ * XPM_EVENT_COHERLINEHIT,
+ * XPM_EVENT_INSTRSTALL,
+ * XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
+ * XPM_EVENT_STREXPASS,
+ * XPM_EVENT_STREXFAIL,
+ * XPM_EVENT_DATAEVICT,
+ * XPM_EVENT_NODISPATCH,
+ * XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
+ * XPM_EVENT_PREDICTFUNCRET,
+ * XPM_EVENT_MAINEXEC,
+ * XPM_EVENT_SECEXEC,
+ * XPM_EVENT_LDRSTR,
+ * XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
+ * XPM_EVENT_PLDSTALL,
+ * XPM_EVENT_WRITESTALL,
+ * XPM_EVENT_INSTRTLBSTALL,
+ * XPM_EVENT_DATATLBSTALL,
+ * XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
+ * XPM_EVENT_DMB_STALL,
+ * XPM_EVENT_INT_CLKEN,
+ * XPM_EVENT_DE_CLKEN,
+ * XPM_EVENT_INSTRISB,
+ * XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
+ * XPM_EVENT_EXTINT,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
+ * XPM_EVENT_PLE_PROG,
+ * XPM_EVENT_PLE_LRC,
+ * XPM_EVENT_PLE_LRS,
+ * XPM_EVENT_PLE_FLUSH,
+ * XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
+ * XPM_EVENT_INSRFETCH_CACHEREFILL,
+ * XPM_EVENT_INSTRFECT_TLBREFILL,
+ * XPM_EVENT_DATA_CACHEREFILL,
+ * XPM_EVENT_DATA_CACHEACCESS,
+ * XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1 0
+#define XPM_CNTRCFG2 1
+#define XPM_CNTRCFG3 2
+#define XPM_CNTRCFG4 3
+#define XPM_CNTRCFG5 4
+#define XPM_CNTRCFG6 5
+#define XPM_CNTRCFG7 6
+#define XPM_CNTRCFG8 7
+#define XPM_CNTRCFG9 8
+#define XPM_CNTRCFG10 9
+#define XPM_CNTRCFG11 10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
new file mode 100644
index 0000000..8000a68
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..85b067d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
@@ -0,0 +1,252 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 pkp 05/21/14 First release
+* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
+*
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ asm volatile("mrs %0, DAIF" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei() //__asm__ __volatile__("cpsie i\n")
+#define cpsidi() //__asm__ __volatile__("cpsid i\n")
+
+#define cpsief() //__asm__ __volatile__("cpsie f\n")
+#define cpsidf() //__asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) /*__asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )*/
+
+#define mfgpr(rn) /*({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u64 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define mfelrel3() ({u64 rval = 0U; \
+ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
+ rval;\
+ })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#endif
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
+
+#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg) ({u64 rval = 0U;\
+ __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
+ rval;\
+ })
+
+#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval = 0U; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xqspips.h
new file mode 100644
index 0000000..302c870
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xqspips.h
@@ -0,0 +1,797 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_5
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* Linear Mode
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device. The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+* static configuration structure defined in xqspips_g.c. This is setup
+* by the tools. For some operating systems the config structure will be
+* initialized by the software and this call is not needed.
+* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the provided virtual memory base address
+* replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+* is written into the TXFIFO and de asserted when the TXFIFO becomes
+* empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+* TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+* the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+* TXFIFO write otherwise there could be a race condition where the TXFIFO
+* becomes empty before the new word is written. In that case the
+* transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+* This results in a single transaction to be split into multiple pieces each
+* with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data. The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+* in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* Removed code related to mode fault for CR 671468
+* The XQspiPs_SetSlaveSelect has been modified to remove
+* the argument of the slave select as the QSPI controller
+* only supports one slave.
+* XQspiPs_GetSlaveSelect API has been removed
+* Added a flag ShiftReadData to the instance structure
+*. and is used in the XQspiPs_GetReadData API.
+* The ShiftReadData Flag indicates whether the data
+* read from the Rx FIFO needs to be shifted
+* in cases where the data is less than 4 bytes
+* Removed the selection for the following options:
+* Master mode (XQSPIPS_MASTER_OPTION) and
+* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+* as the QSPI driver supports the Master mode
+* and Flash Interface mode and doesnot support
+* Slave mode or the legacy mode.
+* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+* APIs so that the last argument (IsInst) specifying whether
+* it is instruction or data has been removed. The first byte
+* in the SendBufPtr argument of these APIs specify the
+* instruction to be sent to the Flash Device.
+* This version of the driver fixes CRs 670197/663787/
+* 670297/671468.
+* Added the option for setting the Holdb_dr bit in the
+* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+* is the option to be used for setting this bit in the
+* configuration register.
+* The XQspiPs_PolledTransfer function has been updated
+* to fill the data to fifo depth.
+* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+* Added macros for Set/Get Rx Watermark. Changed QSPI
+* Enable/Disable macro argument from BaseAddress to
+* Instance Pointer. Added DelayNss argument to SetDelays
+* and GetDelays API's.
+* Created macros XQspiPs_IsManualStart and
+* XQspiPs_IsManualChipSelect.
+* Changed QSPI transfer logic for polled and interrupt
+* modes to be based on filled tx fifo count and receive
+* based on it. RXNEMPTY interrupt is not used.
+* Added assertions to XQspiPs_LqspiRead function.
+* SetDelays and GetDelays API's include DelayNss parameter.
+* Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register. Renamed Fixed burst error to
+* data FSM error in LQSPI Status register.
+*
+* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
+* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+* Added enable and disable to the XQspiPs_LqspiRead() function
+* Removed XQspi_Reset() in Set_Options() function when
+* LQSPI_MODE_OPTION is set.
+* Added instructions for bank selection, die erase and
+* flag status register to the flash instruction table
+* Handling for instructions not in flash instruction
+* table added. Checking for Tx FIFO empty when switching from
+* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+* byte count 3 (spansion), instruction size and TXD register
+* changed accordingly. CR# 712502 and 703869.
+* Added prefix to constant definitions for ConnectionMode
+* Added (#ifdef linear base address) in the Linear read function.
+* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+* XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
+* thresholds. This is to improve performance.
+* Added API's for QSPI reset and
+* linear mode initialization for boot.
+* Added RX and TX threshold reset to one in XQspiPs_Abort.
+* Added RX threshold reset(1) after transfer in polled and
+* interrupt transfers. Made changes to make sure threshold
+* change is done only when no transfer is in progress.
+* Updated linear init API for parallel and stacked modes.
+* CR#737760.
+* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
+* to remove compilation warnings. CR# 868893.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Modified Comment lines in functions of qspips
+* examples to recognize it as documentation block
+* and modified filename tag in
+* xqspips_dual_flash_stack_lqspi_example.c to include it in
+* doxygen examples.
+* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
+* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_H /* prevent circular inclusions */
+#define XQSPIPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device. Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats. A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver. These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
+ * RX FIFO full
+ */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
+#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
+#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
+#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
+#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
+#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
+#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
+#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
+#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
+#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
+#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
+#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
+#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
+#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 1
+#define XQSPIPS_SIZE_TWO 2
+#define XQSPIPS_SIZE_THREE 3
+#define XQSPIPS_SIZE_FOUR 4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE 0
+#define XQSPIPS_CONNECTION_MODE_STACKED 1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device. The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode. The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param CallBackRef is the callback reference passed in by the upper
+ * layer when setting the callback functions, and passed back to
+ * the upper layer when the callback is invoked. Its type is
+ * not important to the driver, so it is a void pointer.
+ * @param StatusEvent holds one or more status events that have occurred.
+ * See the XQspiPs_SetStatusHandler() for details on the status
+ * events that can be passed in the callback.
+ * @param ByteCount indicates how many bytes of data were successfully
+ * transferred. This may be less than the number of bytes
+ * requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+ unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XQspiPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+
+ u8 *SendBufferPtr; /**< Buffer to send (state) */
+ u8 *RecvBufferPtr; /**< Buffer to receive (state) */
+ int RequestedBytes; /**< Number of bytes to transfer (state) */
+ int RemainingBytes; /**< Number of bytes left to transfer(state) */
+ u32 IsBusy; /**< A transfer is in progress (state) */
+ XQspiPs_StatusHandler StatusHandler;
+ void *StatusRef; /**< Callback reference for status handler */
+ u32 ShiftReadData; /**< Flag to indicate whether the data
+ * read from the Rx FIFO needs to be shifted
+ * in cases where the data is less than 4
+ * bytes
+ */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+* - TRUE if option is set
+* - FALSE if option is not set
+*
+* @note C-Style signature:
+* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+ ((XQspiPs_GetOptions(InstancePtr) & \
+ XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are
+* 0-255.
+*
+* @return None
+*
+* @note C-Style signature:
+* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return An 8-bit value representing Slave Idle Count.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr) \
+ XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Tx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 6-bit value representing Rx Watermark level.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+ XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr) \
+ XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+* @param RegisterValue is the value to be written to the Linear QSPI
+* configuration register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+* u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
+ XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return A 32-bit value representing the contents of the LQSPI Config
+* register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
+ XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
+ XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
+ u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+ u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+ u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+ u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+ XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+ u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+ u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xqspips_hw.h
new file mode 100644
index 0000000..9a47979
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xqspips_hw.h
@@ -0,0 +1,419 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00 sdm 11/25/10 First release
+* 2.00a ka 07/25/12 Added a few register defines for CR 670297
+* and removed some defines of reserved fields for
+* CR 671468
+* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+* bit in Configuration register.
+* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+* which need write to clear. Removed Read zeros mask from
+* LQSPI Config register.
+* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
+* linear mode initialization for boot. Added related
+* constant definitions.
+* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
+* required bits leaving reserved bits untouched. CR# 796813.
+* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
+* controller does not update FIFO status flags as expected
+* when thresholds are used.
+*
+*
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
+#define XQSPIPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+ Enable */
+#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
+ transferred */
+#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
+ XQSPIPS_CR_SSCTRL_MASK | \
+ XQSPIPS_CR_DATA_SZ_MASK | \
+ XQSPIPS_CR_MSTREN_MASK | \
+ XQSPIPS_CR_SSFORCE_MASK | \
+ XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
+ XQSPIPS_CR_CPHA_MASK | \
+ XQSPIPS_CR_PRESC_MASK | \
+ XQSPIPS_CR_MANSTRTEN_MASK | \
+ XQSPIPS_CR_MANSTRT_MASK | \
+ XQSPIPS_CR_ENDIAN_MASK | \
+ XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Disable Register
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
+ mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
+ need write to clear */
+#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
+ between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
+ between two words shift */
+#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
+ mask */
+#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
+ * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
+ or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
+ between addr and return
+ read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
+ received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
+ received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+ XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
new file mode 100644
index 0000000..ad93665
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
@@ -0,0 +1,587 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+*
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscugic.h
new file mode 100644
index 0000000..befa209
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscugic.h
@@ -0,0 +1,369 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_10
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+* - specific individual interrupt enabling/disabling
+* - specific individual interrupt acknowledging
+* - attaching specific callback function to handle interrupt source
+* - assigning desired priority to interrupt source if default is not
+* acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only. Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* Interrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs. The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg 01/19/00 First release
+* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+* The HandlerTable (of type XScuGic_VectorTableEntry) is
+* moved to XScuGic_Config structure from XScuGic structure.
+*
+* The "Config" entry in XScuGic structure is made as
+* pointer for better efficiency.
+*
+* A new file named as xscugic_hw.c is now added. It is
+* to implement low level driver routines without using
+* any xscugic instance pointer. They are useful when the
+* user wants to use xscugic through device id or
+* base address. The driver routines provided are explained
+* below.
+* XScuGic_DeviceInitialize that takes device id as
+* argument and initializes the device (without calling
+* XScuGic_CfgInitialize).
+* XScuGic_DeviceInterruptHandler that takes device id
+* as argument and calls appropriate handlers from the
+* HandlerTable.
+* XScuGic_RegisterHandler that registers a new handler
+* by taking xscugic hardware base address as argument.
+* LookupConfigByBaseAddress is used to return the
+* corresponding config structure from XScuGic_ConfigTable
+* based on the scugic base address passed.
+* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+* structure.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+* *_hw.h
+* Added APIs
+* - XScuGic_SetPriTrigTypeByDistAddr()
+* - XScuGic_GetPriTrigTypeByDistAddr()
+* (CR 702687)
+* Added support to direct interrupts to the appropriate CPU. Earlier
+* interrupts were directed to CPU1 (hard coded). Now depending
+* upon the CPU selected by the user (xparameters.h), interrupts
+* will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+* This is fix for CR#705621.
+* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+* xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0 adk 12/10/13 Updated as per the New Tcl API's
+* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
+* distributor is left uninitialized for Zynq AMP. It is assumed
+* that the distributor will be initialized by Linux master. However
+* for CortexR5 case, the earlier code is left unchanged where the
+* the interrupt processor target registers in the distributor is
+* initialized with the corresponding CPU ID on which the application
+* built over the scugic driver runs.
+* These changes fix CR#937243.
+*
+* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
+* the flow and avoid code duplication. Changes are made for
+* USE_AMP use case for R5. In a scenario (in R5 split mode) when
+* one R5 is operating with A53 in open amp config and other
+* R5 running baremetal app, the existing code
+* had the potential to stop the whole AMP solution to work (if
+* for some reason the R5 running the baremetal app tasked to
+* initialize the Distributor hangs or crashes before initializing).
+* Changes are made so that the R5 under AMP first checks if
+* the distributor is enabled or not and if not, it does the
+* standard Distributor initialization.
+* This fixes the CR#952962.
+* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* kvn 02/17/17 Add support for changing GIC CPU master at run time.
+* kvn 02/28/17 Make the CpuId as static variable and Added new
+* XScugiC_GetCpuId to access CpuId.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
+* definitions of scugic in xparameters.h
+* 3.8 mus 07/05/17 Updated scugic.tcl to add support for intrrupts connected
+* through util_reduced_vector IP(OR gate)
+* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+* the HandlerTable in XScuGic_ConfigTable to 0, it removes
+* the compilation warning in xscugic_g.c. Fix for CR#978736.
+* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
+* definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+* XScuGic_InterruptUnmapFromCpu, These API's can be used
+* by applications to unmap specific/all interrupts from
+* target CPU.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET 0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config *Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32 XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscugic_hw.h
new file mode 100644
index 0000000..54f1035
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscugic_hw.h
@@ -0,0 +1,648 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_10
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device. The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+* added to enable or disable interrupts based on
+* Distributor Register base address. Normally users use
+* XScuGic instance and call XScuGic_Enable or
+* XScuGic_Disable to enable/disable interrupts. These
+* new macros are provided when user does not want to
+* use an instance pointer but still wants to enable or
+* disable interrupts.
+* Function prototypes for functions (present in newly
+* added file xscugic_hw.c) are added.
+* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+* 702687).
+* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+* XScuGic_SetPriTrigTypeByDistAddr and
+* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+* Zynq Ultrascale Mp
+* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
+* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+* API's can be used by applications to unmap specific/all
+* interrupts from target CPU. It fixes CR#992490.
+* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
+*
+*
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef PLATFORM_ZYNQ
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
+ Shared Peripheral
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
+ b00-Use the target List
+ b01-All CPUs except requester
+ b10-To Requester
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
+ 0=separate registers,
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
+ interrupts,
+ 0= use IRQ for both,
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
+ Value Secure Non-secure
+ b000 0xFE 0xFF
+ b001 0xFC 0xFE
+ b010 0xF8 0xFC
+ b011 0xF0 0xF8
+ b100 0xE0 0xF0
+ b101 0xC0 0xE0
+ b110 0x80 0xC0
+ b111 0x00 0x80
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param Register is the register offset for the clear/enable bank.
+* @param InterruptID is the interrupt number.
+*
+* @return The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param BaseAddress is the base address of the device.
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param DistBaseAddress is the Distributor Register base address of the
+* device
+* @param Int_Id is the ID of the interrupt source and should be in the
+* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+ u8 Cpu_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscutimer.h
new file mode 100644
index 0000000..5434684
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscutimer.h
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* Interrupts
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
new file mode 100644
index 0000000..d577784
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscutimer_hw.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscuwdt.h
new file mode 100644
index 0000000..551eaf5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscuwdt.h
@@ -0,0 +1,379 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_H /* prevent circular inclusions */
+#define XSCUWDT_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuWdt_Config Config;/**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_RST_STS_OFFSET) & \
+ XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+* - TRUE if the watchdog has expired.
+* - FALSE if the watchdog has not expired.
+*
+* @note C-style signature:
+* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr) \
+ ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_ISR_OFFSET) & \
+ XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr) \
+ XScuWdt_LoadWdt((InstancePtr), \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param Value is the value to be written to the Watchdog Load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, \
+ (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET) | \
+ (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr) \
+{ \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE1); \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_DISABLE_OFFSET, \
+ XSCUWDT_DISABLE_VALUE2); \
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return Contents of the watchdog control register.
+*
+* @note C-style signature:
+ u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr) \
+ XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+* @param ControlReg is the value to be written to the watchdog control
+* register.
+*
+* @return None.
+*
+* @note C-style signature:
+ void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
+ XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr) \
+ XScuWdt_SetControlReg((InstancePtr), \
+ (XScuWdt_GetControlReg(InstancePtr) | \
+ XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+ XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
new file mode 100644
index 0000000..ad87a05
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h
@@ -0,0 +1,178 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+* of 0x20 as the base address obtained from the tools
+* starts at 0x20.
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H /* prevent circular inclusions */
+#define XSCUWDT_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
+ timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+ timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
+ value 1 */
+#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
+ value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xsdps.h
new file mode 100644
index 0000000..b81ec7c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xsdps.h
@@ -0,0 +1,274 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_6
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
+* Add sleep for microblaze designs. CR# 781117.
+* 2.2 hk 07/28/14 Make changes to enable use of data cache.
+* 2.3 sk 09/23/14 Send command for relative card address
+* when re-initialization is done.CR# 819614.
+* Use XSdPs_Change_ClkFreq API whenever changing
+* clock.CR# 816586.
+* 2.4 sk 12/04/14 Added support for micro SD without
+* WP/CD. CR# 810655.
+* Checked for DAT Inhibit mask instead of CMD
+* Inhibit mask in Cmd Transfer API.
+* Added Support for SD Card v1.0
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
+* sk 12/10/15 Added support for MMC cards.
+* 01/08/16 Added workaround for issue in auto tuning mode
+* of SDR50, SDR104 and HS200.
+* sk 02/16/16 Corrected the Tuning logic.
+* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/07/16 Used usleep API for both arm and microblaze.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+* CR#956899.
+* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
+* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
+* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
+* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
+* sk 02/01/17 Added HSD and DDR mode support for eMMC.
+* sk 02/01/17 Consider bus width parameter from design for switching
+* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+* sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
+* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
+* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
+* information.
+* mn 09/06/17 Resolved compilation errors with IAR toolchain
+* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+*
+*
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */
+#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of the device */
+ u32 InputClockHz; /**< Input clock frequency */
+ u32 CardDetect; /**< Card Detect */
+ u32 WriteProtect; /**< Write Protect */
+ u32 BusWidth; /**< Bus Width */
+ u32 BankNumber; /**< MIO Bank selection for SD */
+ u32 HasEMIO; /**< If SD is connected to EMIO */
+ u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+ u16 Attribute; /**< Attributes of descriptor */
+ u16 Length; /**< Length of current dma transfer */
+ u64 Address; /**< Address of current dma transfer */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+} __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XSdPs_Config Config; /**< Configuration structure */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 Host_Caps; /**< Capabilities of host controller */
+ u32 Host_CapsExt; /**< Extended Capabilities */
+ u32 HCS; /**< High capacity support in card */
+ u8 CardType; /**< Type of card - SD/MMC/eMMC */
+ u8 Card_Version; /**< Card version */
+ u8 HC_Version; /**< Host controller version */
+ u8 BusWidth; /**< Current operating bus width */
+ u32 BusSpeed; /**< Current operating bus speed */
+ u8 Switch1v8; /**< 1.8V Switch support */
+ u32 CardID[4]; /**< Card ID Register */
+ u32 RelCardAddr; /**< Relative Card Address */
+ u32 CardSpecData[4]; /**< Card Specific Data Register */
+ u32 SectorCount; /**< Sector Count */
+ u32 SdCardConfig; /**< Sd Card Configuration Register */
+ u32 Mode; /**< Bus Speed Mode */
+ XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */
+ /**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+ XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+ u64 Dma64BitAddr; /**< 64 Bit DMA Address */
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xsdps_hw.h
new file mode 100644
index 0000000..901fa5c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xsdps_hw.h
@@ -0,0 +1,1298 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_6
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a hk/sg 10/17/13 Initial release
+* 2.5 sg 07/09/15 Added SD 3.0 features
+* kvn 07/15/15 Modified the code according to MISRAC-2012.
+* 2.7 sk 12/10/15 Added support for MMC cards.
+* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8 sk 04/20/16 Added new workaround for auto tuning.
+* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
+* sk 07/16/16 Added support for UHS modes.
+* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
+* operating modes.
+* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
+* 3.3 mn 08/22/17 Updated for Word Access System support
+* mn 09/06/17 Added support for ARMCC toolchain
+* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
+*
+*
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
+ Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
+ /**< SDMA System Address
+ Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
+ High Register */
+#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
+ /**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
+#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
+#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
+#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
+#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
+ Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
+ Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
+ Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
+ Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
+ Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
+ Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
+ Register */
+#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
+ Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
+ Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
+ Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
+ Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
+ Register */
+#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
+ Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
+ Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
+ register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
+ Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
+ Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
+ Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
+#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT 256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
+#define XSDPS_CC_EXT_DIV_SHIFT 6U
+
+#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK 0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV 9U
+#define XSDPS_CC_DIV_SHIFT 8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * Normal and Error Interrupt Status Register
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * Normal and Error Interrupt Status Enable Register
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * Normal and Error Interrupt Signal Enable Register
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
+ Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
+ Interrupt */
+#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
+ Error */
+#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
+ Error */
+#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
+ Error */
+#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024 0x400U
+#define XSDPS_BLK_SIZE_2048 0x800U
+#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
+ Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
+ Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
+ Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
+ Select */
+#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
+ check busy after
+ response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
+ Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
+ Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
+ Set to CMD0-63,
+ AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
+ Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
+ Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
+ Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
+ select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
+ MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
+ support */
+#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
+ support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
+ support */
+#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
+ support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
+ Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
+ tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
+ support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
+ for Programmable clock
+ mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
+ pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
+ Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
+ Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
+ Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
+ executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
+ Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
+ Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
+ Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
+ Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
+ Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
+ Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
+ Error */
+#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
+ STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
+ FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
+ TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
+ Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
+ Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
+ Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
+ mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
+ Specification
+ version mask */
+#define XSDPS_HC_SPEC_V3 0x0002U
+#define XSDPS_HC_SPEC_V2 0x0001U
+#define XSDPS_HC_SPEC_V1 0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK 0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX 0x8000U
+#define CMD0 0x0000U
+#define CMD1 0x0100U
+#define CMD2 0x0200U
+#define CMD3 0x0300U
+#define CMD4 0x0400U
+#define CMD5 0x0500U
+#define CMD6 0x0600U
+#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7 0x0700U
+#define CMD8 0x0800U
+#define CMD9 0x0900U
+#define CMD10 0x0A00U
+#define CMD11 0x0B00U
+#define CMD12 0x0C00U
+#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16 0x1000U
+#define CMD17 0x1100U
+#define CMD18 0x1200U
+#define CMD19 0x1300U
+#define CMD21 0x1500U
+#define CMD23 0x1700U
+#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24 0x1800U
+#define CMD25 0x1900U
+#define CMD41 0x2900U
+#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52 0x3400U
+#define CMD55 0x3700U
+#define CMD58 0x3A00U
+
+#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+ (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+ (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN 0xAAU
+#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
+#define XSDPS_CIC_VOLT_LOW (1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS (1U<<31)
+#define XSDPS_OCR_CC_STS (1U<<30)
+#define XSDPS_OCR_S18 (1U<<24)
+#define XSDPS_OCR_3V5_3V6 (1U<<23)
+#define XSDPS_OCR_3V4_3V5 (1U<<22)
+#define XSDPS_OCR_3V3_3V4 (1U<<21)
+#define XSDPS_OCR_3V2_3V3 (1U<<20)
+#define XSDPS_OCR_3V1_3V2 (1U<<19)
+#define XSDPS_OCR_3V0_3V1 (1U<<18)
+#define XSDPS_OCR_2V9_3V0 (1U<<17)
+#define XSDPS_OCR_2V8_2V9 (1U<<16)
+#define XSDPS_OCR_2V7_2V8 (1U<<15)
+#define XSDPS_OCR_1V7_1V95 (1U<<7)
+#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
+#define XSDPS_OCR_LOW_VOL 0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN 8U
+#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0 0U
+#define XSDPS_SCR_SPEC_1V1 (1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE 0U
+#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
+#define XSDPS_SCR_SPEC3_MASK (1U<<12)
+#define XSDPS_SCR_SPEC3_2V0 0U
+#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
+#define XSDPS_SCR_CMD23_SUPP (1U<<1)
+#define XSDPS_SCR_CMD20_SUPP (1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
+#define XSDPS_CD_STS_WP_VIO (1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
+#define XSDPS_CD_STS_CC_ERR (1U<<20)
+#define XSDPS_CD_STS_ERR (1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
+#define XSDPS_CD_STS_ER_RST (1U<<13)
+#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
+#define XSDPS_CD_STS_APP_CMD (1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN 64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK 0U
+
+#define XSDPS_MODE_FUNC_GRP1 1U
+#define XSDPS_MODE_FUNC_GRP2 2U
+#define XSDPS_MODE_FUNC_GRP3 3U
+#define XSDPS_MODE_FUNC_GRP4 4U
+#define XSDPS_MODE_FUNC_GRP5 5U
+#define XSDPS_MODE_FUNC_GRP6 6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12 0U
+#define XSDPS_ACC_MODE_HS_SDR25 1U
+#define XSDPS_ACC_MODE_SDR50 2U
+#define XSDPS_ACC_MODE_SDR104 3U
+#define XSDPS_ACC_MODE_DDR50 4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT 4U
+#define XSDPS_CMD_SYS_DEF 0U
+#define XSDPS_CMD_SYS_eC 1U
+#define XSDPS_CMD_SYS_OTP 3U
+#define XSDPS_CMD_SYS_ASSD 4U
+#define XSDPS_CMD_SYS_VEND 5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
+#define XSDPS_DRV_TYPE_B 0U
+#define XSDPS_DRV_TYPE_A 1U
+#define XSDPS_DRV_TYPE_C 2U
+#define XSDPS_DRV_TYPE_D 3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT 12U
+#define XSDPS_CUR_LIM_200 0U
+#define XSDPS_CUR_LIM_400 1U
+#define XSDPS_CUR_LIM_600 2U
+#define XSDPS_CUR_LIM_800 3U
+
+#define CSD_SPEC_VER_MASK 0x3C0000U
+#define READ_BLK_LEN_MASK 0x00000F00U
+#define C_SIZE_MULT_MASK 0x00000380U
+#define C_SIZE_LOWER_MASK 0xFFC00000U
+#define C_SIZE_UPPER_MASK 0x00000003U
+#define CSD_STRUCT_MASK 0x00C00000U
+#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE 512U
+
+#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
+ /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
+ /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
+ | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
+ /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE 183U
+#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE 185U
+#define EXT_CSD_HS_TIMING_DEF 0U
+#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE 162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET 0U
+#define XSDPS_EXT_CSD_SET_BITS 1U
+#define XSDPS_EXT_CSD_CLR_BITS 2U
+#define XSDPS_EXT_CSD_WRITE_BYTE 3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+ | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+ | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+ | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY 2960U
+#define XSDPS_100CLK_DELAY 4000U
+#define XSDPS_INIT_DELAY 10000U
+
+#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR 0x1234U
+
+#define XSDPS_CARD_SD 1U
+#define XSDPS_CARD_MMC 2U
+#define XSDPS_CARD_SDIO 3U
+#define XSDPS_CARD_SDCOMBO 4U
+#define XSDPS_CHIP_EMMC 5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID (0x1U << 0)
+#define XSDPS_DESC_END (0x1U << 1)
+#define XSDPS_DESC_INT (0x1U << 2)
+#define XSDPS_DESC_TRAN (0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
+#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
+#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT 1U
+#define XSDPS_SCR_BLKSIZE 8U
+#define XSDPS_1_BIT_WIDTH 0x1U
+#define XSDPS_4_BIT_WIDTH 0x2U
+#define XSDPS_8_BIT_WIDTH 0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
+#define XSDPS_HIGH_SPEED_MODE 0x5U
+#define XSDPS_DEFAULT_SPEED_MODE 0x6U
+#define XSDPS_HS200_MODE 0x7U
+#define XSDPS_DDR52_MODE 0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT 1U
+#define XSDPS_SWITCH_CMD_BLKSIZE 64U
+#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT 1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
+#define XSDPS_TUNING_CMD_BLKCNT 1U
+#define XSDPS_TUNING_CMD_BLKSIZE 64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK 208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK 100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK 50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK 25000000U
+
+#define SD_DRIVER_TYPE_B 0x01U
+#define SD_DRIVER_TYPE_A 0x02U
+#define SD_DRIVER_TYPE_C 0x04U
+#define SD_DRIVER_TYPE_D 0x08U
+#define SD_SET_CURRENT_LIMIT_200 0U
+#define SD_SET_CURRENT_LIMIT_400 1U
+#define SD_SET_CURRENT_LIMIT_600 2U
+#define SD_SET_CURRENT_LIMIT_800 3U
+
+#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK 25000000U
+#define XSDPS_SD_SDR25_MAX_CLK 50000000U
+#define XSDPS_SD_SDR50_MAX_CLK 100000000U
+#define XSDPS_SD_DDR50_MAX_CLK 50000000U
+#define XSDPS_SD_SDR104_MAX_CLK 208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK 175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK 200000000U
+#define XSDPS_MMC_HSD_MAX_CLK 52000000U
+#define XSDPS_MMC_DDR_MAX_CLK 52000000U
+
+#define XSDPS_CARD_STATE_IDLE 0U
+#define XSDPS_CARD_STATE_RDY 1U
+#define XSDPS_CARD_STATE_IDEN 2U
+#define XSDPS_CARD_STATE_STBY 3U
+#define XSDPS_CARD_STATE_TRAN 4U
+#define XSDPS_CARD_STATE_DATA 5U
+#define XSDPS_CARD_STATE_RCV 6U
+#define XSDPS_CARD_STATE_PROG 7U
+#define XSDPS_CARD_STATE_DIS 8U
+#define XSDPS_CARD_STATE_BTST 9U
+#define XSDPS_CARD_STATE_SLP 10U
+
+#define XSDPS_SLOT_REM 0U
+#define XSDPS_SLOT_EMB 1U
+
+#define XSDPS_WIDTH_8 8U
+#define XSDPS_WIDTH_4 4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
+#define SD_DLL_CTRL 0x00000358U
+#define SD_ITAPDLY 0x00000314U
+#define SD_OTAPDLY 0x00000318U
+#define SD0_DLL_RST 0x00000004U
+#define SD1_DLL_RST 0x00040000U
+#define SD0_ITAPCHGWIN 0x00000200U
+#define SD0_ITAPDLYENA 0x00000100U
+#define SD0_OTAPDLYENA 0x00000040U
+#define SD1_ITAPCHGWIN 0x02000000U
+#define SD1_ITAPDLYENA 0x01000000U
+#define SD1_OTAPDLYENA 0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U
+#define SD0_ITAPDLYSEL_SD50 0x00000014U
+#define SD0_OTAPDLYSEL_SD50 0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U
+#define SD0_ITAPDLYSEL_HSD 0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U
+#define SD1_ITAPDLYSEL_SD50 0x00140000U
+#define SD1_OTAPDLYSEL_SD50 0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U
+#define SD1_ITAPDLYSEL_HSD 0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+ XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param InstancePtr is the pointer to the sdps instance.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+* u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+ XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+ (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+ XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u16)Reg;
+#else
+ return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to the target register.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg >>= ((RegOffset & 0x3)*8);
+ return (u8)Reg;
+#else
+ return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the 1st register of the
+* device to target register.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+ u32 Reg;
+ BaseAddress += RegOffset & 0xFC;
+ Reg = XSdPs_In32(BaseAddress);
+ Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+ Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+ XSdPs_Out32(BaseAddress, Reg);
+#else
+ XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+ XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xstatus.h
new file mode 100644
index 0000000..c6e18ab
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xstatus.h
@@ -0,0 +1,531 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /*!< An error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /*!< An error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /*!< The device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /*!< There was no data available */
+#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /*!< The device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
+#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /*!< Device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /*!< Device is busy */
+#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /*!< Used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /*!< Used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /*!< Driver defined error */
+#define XST_RECV_ERROR 27L /*!< Generic receive error */
+#define XST_SEND_ERROR 28L /*!< Generic transmit error */
+#define XST_NOT_ENABLED 29L /*!< A requested service is not
+ available because it has not
+ been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500 *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
+ * empty and full simultaneously
+ */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
+ error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
+#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
+ * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
+#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
+ device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /*!< Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /*!< Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
+ */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xtime_l.h
new file mode 100644
index 0000000..12004e1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xtime_l.h
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
+* implementation
+* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
+*
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#ifdef __GNUC__
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xuartps.h
new file mode 100644
index 0000000..c6c2a0a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xuartps.h
@@ -0,0 +1,517 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_5
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+* configuration structure provided by the caller. If running in a system
+* with address translation, the parameter EffectiveAddr should be the
+* virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+*
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a drg/jz 01/12/10 First Release
+* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
+* in XUartPs_SetFlowDelay where the value was not
+* being written to the register.
+* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
+* instance structure and the driver is updated to use
+* InputClockHz parameter from the XUartPs_Config config
+* structure.
+* Added a parameter to XUartPs_Config structure which
+* specifies whether the user has selected Modem pins
+* to be connected to MIO or FMIO.
+* Added the tcl file to generate the xparameters.h
+* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+* with the correct values for CR 666724
+* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the name of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added API for uart reset and related
+* constant definitions.
+* 2.0 hk 03/07/14 Version number revised.
+* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
+* baud rate. CR# 804281.
+* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
+* Support for Zynq Ultrascale Mp added.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
+* platform variable in driver instance structure.
+* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
+* uart is connected to a valid interrupt controller CR#946803.
+* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
+* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
+* control register.
+* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
+*
+*
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H /* prevent circular inclusions */
+#define XUARTPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE 921600U
+#define XUARTPS_MIN_RATE 110U
+
+#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified. These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
+ * error detected */
+#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+ u32 InputClockHz;/**< Input clock frequency */
+ s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+ * to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+ u8 *NextBytePtr;
+ u32 RequestedBytes;
+ u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+ u32 BaudRate; /**< In bps, ie 1200 */
+ u32 DataBits; /**< Number of data bits */
+ u32 Parity; /**< Parity */
+ u8 StopBits; /**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the handler, and is passed back to the upper layer
+ * when the handler is called. It is used to find the device driver
+ * instance.
+ * @param Event contains one of the event constants indicating events that
+ * have occurred.
+ * @param EventData contains the number of bytes sent or received at the
+ * time of the call for send and receive events and contains the
+ * modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+ u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XUartPs_Config Config; /* Configuration data structure */
+ u32 InputClockHz; /* Input clock frequency */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 BaudRate; /* Current baud rate */
+
+ XUartPsBuffer SendBuffer;
+ XUartPsBuffer ReceiveBuffer;
+
+ XUartPs_Handler Handler;
+ void *CallBackRef; /* Callback reference for event handler */
+ u32 Platform;
+ u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr) \
+ Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+ (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+ Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+ (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+ (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+* - TRUE if a byte can be sent
+* - FALSE if the Transmitter Fifo is not empty
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr) \
+ ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+ XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+ u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+ void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xuartps_hw.h
new file mode 100644
index 0000000..8c46ecf
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/include/xuartps_hw.h
@@ -0,0 +1,447 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_5
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 drg/jz 01/12/10 First Release
+* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+* and XUARTPS_IXR_TTRIG.
+* Modified the names of these defines
+* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk 08/22/13 Added prototype for uart reset and related
+* constant definitions.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+* 3.6 ms 02/16/18 Updates flow control mode offset value in
+* modem control register.
+*
+*
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+*
+* @return The value read from the register.
+*
+* @note C-Style signature:
+* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the
+* device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note C-Style signature:
+* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if there is receive data, FALSE otherwise.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param BaseAddress contains the base address of the device.
+*
+* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+* FIFO.
+*
+* @note C-Style signature:
+* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
+ (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
new file mode 100644
index 0000000..007162d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner coresightps_dcc_comp_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling coresightps_dcc"
+
+coresightps_dcc_comp_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: coresightps_dcc_includes
+
+coresightps_dcc_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
new file mode 100644
index 0000000..ec9a365
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.c
+* @addtogroup coresightps_dcc_v1_4
+* @{
+*
+* Functions in this file are the minimum required functions for the
+* XCoreSightPs driver.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.2 kvn 10/09/15 Add support for IAR Compiler.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
+
+#include
+#include
+
+#ifdef __ICCARM__
+#define INLINE
+#else
+#define INLINE __inline
+#endif
+
+/* DCC Status Bits */
+#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
+#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
+
+static INLINE u32 XCoresightPs_DccGetStatus(void);
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the DCC. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+* @param Data is the byte of data to send
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
+{
+ (void) BaseAddress;
+ while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
+ dsb();
+#ifdef __aarch64__
+ asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mcr p14, 0, %0, c0, c5, 0"
+ : : "r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Reg = Data;
+ }
+#endif
+ isb();
+
+}
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the DCC. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param BaseAddress is a dummy parameter to match the function proto
+* of functions for other stdio devices.
+*
+* @return The byte of data received.
+*
+* @note None.
+*
+******************************************************************************/
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
+{
+ u8 Data = 0U;
+ (void) BaseAddress;
+
+ while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
+ dsb();
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c5, 0"
+ : "=r" (Data));
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+ Data = Reg;
+ }
+#endif
+ isb();
+
+ return Data;
+}
+
+
+/****************************************************************************/
+/**INLINE
+*
+* This functions read the status register of the DCC.
+*
+* @param BaseAddress is the base address of the device
+*
+* @return The contents of the Status Register.
+*
+* @note None.
+*
+******************************************************************************/
+static INLINE u32 XCoresightPs_DccGetStatus(void)
+{
+ u32 Status = 0U;
+
+#ifdef __aarch64__
+ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+ asm volatile("mrc p14, 0, %0, c0, c1, 0"
+ : "=r" (Status) : : "cc");
+#else
+ {
+ volatile register u32 Reg __asm("cp14:0:c0:c1:0");
+ Status = Reg;
+ }
+#endif
+ return Status;
+#endif
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
new file mode 100644
index 0000000..70b8aad
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_4
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ----- -------- -----------------------------------------------
+* 1.00 kvn 02/14/15 First release
+* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
+* kvn 08/18/15 Modified Makefile according to compiler changes.
+* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
+* for MB BSPs. Instead it throws up a warning. This
+* fixes the CR#953056.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/Makefile
new file mode 100644
index 0000000..7ea505c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/Makefile
@@ -0,0 +1,25 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+LIBSOURCES=*.c
+INCLUDEFILES=*.h
+
+libs:
+ echo "Compiling cpu_cortexa9"
+
+.PHONY: include
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/xcpu_cortexa9.h
new file mode 100644
index 0000000..e4a5e28
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src/xcpu_cortexa9.h
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_7
+* @{
+* @details
+*
+* dummy file
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
+* parameter of cpu_cortexa9 in xparameters.h
+# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
+# extra compiler flags. Now, user can remove default flags
+# from extra compiler flags. It fixes CR#998768.
+******************************************************************************/
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
new file mode 100644
index 0000000..7b191dd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xddrps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling ddrps"
+
+xddrps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xddrps_includes
+
+xddrps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
new file mode 100644
index 0000000..b4d1f56
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
@@ -0,0 +1,62 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note None.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0 nsk 08/06/15 First Release
+ * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
+ * to support PBD Designs (CR #876857)
+ *
+ *
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
new file mode 100644
index 0000000..25ff740
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdevcfg_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling devcfg"
+
+xdevcfg_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdevcfg_includes
+
+xdevcfg_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
new file mode 100644
index 0000000..74e1d59
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c
@@ -0,0 +1,941 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface functions for XDcfg
+* driver. Refer to the header file xdevcfg.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Updated the XDcfg_Transfer function to use the
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+*
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize the Device Config Interface driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param ConfigPtr is the config structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note The very first APB access to the Device Configuration Interface
+* block needs to be a write to the UNLOCK register with the value
+* of 0x757BDF0D. This step is to be done once after reset, any
+* other APB access has to come after this. The APB access is
+* considered illegal if the step is not done or if it is done
+* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
+* the following additional actions would be carried out.
+* In other words, if all bits are low, the following steps are not
+* done.
+* 1. AES is disabled
+* 2. All APB writes disabled
+* 3. SoC debug fully enabled
+*
+******************************************************************************/
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+ return XST_DEVICE_IS_STARTED;
+ }
+
+ /*
+ * Copy configuration into instance.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+ InstancePtr->IsStarted = 0;
+
+
+ /* Unlock the Device Configuration Interface */
+ XDcfg_Unlock(InstancePtr);
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* The functions enables the PCAP interface by setting the PCAP mode bit in the
+* control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note Enable FPGA programming from PCAP interface. Enabling this bit
+* disables all the external interfaces from programming of FPGA
+* except for ICAP. The user needs to ensure that the FPGA is
+* programmed through either PCAP or ICAP.
+*
+*****************************************************************************/
+void XDcfg_EnablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The functions disables the PCAP interface by clearing the PCAP mode bit in
+* the control register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_DisablePCAP(XDcfg *InstancePtr)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit mask data to be written to the Register.
+* The mask definitions are defined in the xdevcfg_hw.h file.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg | Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function Clears the specified bit positions of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the 32 bit value which holds the bit positions to be cleared.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 CtrlReg;
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+ (CtrlReg & ~Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Control
+* Register.
+* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Lock Register. These bits
+* can only be set to a 1. They will be cleared after a Power On Reset.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Lock Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Lock
+* Register.
+* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Lock Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Configuration Register with the
+* given value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Config
+* Register.
+* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
+* interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Status
+* Register.
+* Use the XDCFG_STATUS_*_MASK constants defined in
+* xdevcfg_hw.h to interpret the returned value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Status Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the ROM Shadow Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Data is the 32 bit data to be written to the Register.
+*
+* @return None.
+*
+* @note This register is can only be written and is used to control the
+* RAM shadow of 32 bit 4K page ROM pages in user mode
+*
+*****************************************************************************/
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
+ Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Software ID Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API for reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Software ID Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the bit mask for the feature in Miscellaneous Control
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the feature to be set.
+*
+* @return None.
+*
+* @note None
+*
+*****************************************************************************/
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegData;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
+ (RegData | Mask));
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return 32 Bit boot software ID.
+*
+* @note This register is locked for write once the system enters
+* usermode. Hence API to reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Miscellaneous Control Register and return the value.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
+}
+
+/******************************************************************************/
+/**
+*
+* This function checks if DMA command queue is full.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return XST_SUCCESS is the DMA is busy
+* XST_FAILURE if the DMA is idle
+*
+* @note The DMA queue has a depth of two.
+*
+****************************************************************************/
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
+{
+
+ u32 RegData;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Read the PCAP status register for DMA status */
+ RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_STATUS_OFFSET);
+
+ if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
+ XDCFG_STATUS_DMA_CMD_Q_F_MASK){
+ return XST_SUCCESS;
+ }
+
+ return XST_FAILURE;
+}
+
+/******************************************************************************/
+/**
+*
+* This function initiates the DMA transfer.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return None.
+*
+* @note It is the responsibility of the caller function to ensure that
+* correct values are passed to this function.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+****************************************************************************/
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength)
+{
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_ADDR_OFFSET,
+ SourcePtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_ADDR_OFFSET,
+ DestPtr);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_SRC_LEN_OFFSET,
+ SrcWordLength);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_DMA_DEST_LEN_OFFSET,
+ DestWordLength);
+}
+
+/******************************************************************************/
+/**
+*
+* This function Implements the DMA Read Command. This command is used to
+* transfer the image data from FPGA to the external memory.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+*
+* @return - XST_INVALID_PARAM if source address/length is invalid.
+* - XST_SUCCESS if DMA transfer initiated properly.
+*
+* @note None.
+*
+****************************************************************************/
+static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
+ u32 SrcWordLength, u32 DestPtr,
+ u32 DestWordLength)
+{
+ u32 IntrReg;
+
+ /*
+ * Send READ Frame command to FPGA
+ */
+ XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
+ SrcWordLength, 0);
+
+ /*
+ * Store the enabled interrupts to enable before the actual read
+ * transfer is initiated and Disable all the interrupts temporarily.
+ */
+ IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
+ XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
+
+ /*
+ * Wait till you get the DMA done for the read command sent
+ */
+ while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET) &
+ XDCFG_IXR_D_P_DONE_MASK) !=
+ XDCFG_IXR_D_P_DONE_MASK);
+ /*
+ * Enable the previously stored Interrupts .
+ */
+ XDcfg_IntrEnable(InstancePtr, IntrReg);
+
+ /*
+ * Initiate the DMA write command.
+ */
+ XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
+ 0, DestWordLength);
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function starts the DMA transfer. This function only starts the
+* operation and returns before the operation may be completed.
+* If the interrupt is enabled, an interrupt will be generated when the
+* operation is completed, otherwise it is necessary to poll the Status register
+* to determine when it is completed. It is the responsibility of the caller to
+* determine when the operation is completed by handling the generated interrupt
+* or polling the Status Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param SourcePtr contains a pointer to the source memory where the data
+* is to be transferred from.
+* @param SrcWordLength is the number of words (32 bit) to be transferred
+* for the source transfer.
+* @param DestPtr contains a pointer to the destination memory
+* where the data is to be transferred to.
+* @param DestWordLength is the number of words (32 bit) to be transferred
+* for the Destination transfer.
+* @param TransferType contains the type of PCAP transfer being requested.
+* The definitions can be found in the xdevcfg.h file.
+* @return
+* - XST_SUCCESS.if DMA transfer initiated successfully
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_INVALID_PARAM if invalid Source / Destination address
+* is sent or an invalid Source / Destination length is
+* sent
+*
+* @note It is the responsibility of the caller to ensure that the cache
+* is flushed and invalidated both before the DMA operation is
+* started and after the DMA operation completes if the memory
+* pointed to is cached. The caller must also ensure that the
+* pointers contain physical address rather than a virtual address
+* if address translation is being used.
+*
+* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+* address when equal to 2�b01 indicates the last DMA command of
+* an overall transfer.
+*
+*****************************************************************************/
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType)
+{
+
+ u32 CtrlReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+ if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
+ return XST_DEVICE_BUSY;
+ }
+
+ /*
+ * Check whether the fabric is in initialized state
+ */
+ if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
+ & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
+ /*
+ * We don't need to check PCFG_INIT to be high for
+ * non-encrypted loopback transfers.
+ */
+ if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ return XST_FAILURE;
+ }
+ }
+
+ if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
+ (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
+
+ /* Check for valid source pointer and length */
+ if ((!SourcePtr) || (SrcWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
+ /*
+ * AES engine handles only 8 bit data every clock cycle.
+ * Hence, Encrypted PCAP data which is 32 bit data can
+ * only be sent in every 4 clock cycles. Set the control
+ * register QUARTER_PCAP_RATE_EN bit to achieve this
+ * operation.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+
+ }
+
+ if (TransferType == XDCFG_PCAP_READBACK) {
+
+ if ((!DestPtr) || (DestWordLength == 0)) {
+
+ return XST_INVALID_PARAM;
+ }
+
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * For PCAP readback of FPGA configuration register or memory,
+ * the read command is first sent (written) to the FPGA fabric
+ * which responds by returning the required read data. Read data
+ * from the FPGA is captured if pcap_radata_v is active.A DMA
+ * read transfer is required to obtain the readback command,
+ * which is then sent to the FPGA, followed by a DMA write
+ * transfer to support this mode of operation.
+ */
+ return XDcfg_PcapReadback(InstancePtr,
+ (u32)SourcePtr, SrcWordLength,
+ (u32)DestPtr, DestWordLength);
+ }
+
+
+ if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
+ (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
+
+ if ((!SourcePtr) || (SrcWordLength == 0) ||
+ (!DestPtr) || (DestWordLength == 0)) {
+ return XST_INVALID_PARAM;
+ }
+
+ if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+ /* Enable internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg |
+ XDCFG_MCTRL_PCAP_LPBK_MASK));
+
+ /*
+ * Clear QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every clock
+ */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_CTRL_OFFSET, (CtrlReg &
+ ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+ }
+ if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
+ /* Clear internal PCAP loopback */
+ CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_MCTRL_OFFSET, (CtrlReg &
+ ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+ /*
+ * Set the QUARTER_PCAP_RATE_EN bit
+ * so that the PCAP data is transmitted every 4 clock
+ * cycles, this is required for encrypted data.
+ */
+ XDcfg_SetControlRegister(InstancePtr,
+ XDCFG_CTRL_PCAP_RATE_EN_MASK);
+ }
+
+ XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+ (u32)DestPtr, SrcWordLength, DestWordLength);
+ }
+
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
new file mode 100644
index 0000000..6586370
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h
@@ -0,0 +1,399 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_5
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+* 1. AXI-PCAP
+* 2. Security Policy
+* 3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* Interrupts
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
+* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+* APIs is words (32 bit) and not bytes.
+* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+* to add information that 2 LSBs of the Source/Destination
+* address when equal to 2�b01 indicate the last DMA command
+* of an overall transfer.
+* Destination Address passed to this API for secure transfers
+* instead of using 0xFFFFFFFF for CR 662197. This issue was
+* resulting in the failure of secure transfers of
+* non-bitstream images.
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+* Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg.
+* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+* and XDcfg_SelectPcapInterface APIs for CR 643295
+* The user has to call the XDcfg_SelectIcapInterface API
+* for the PL reconfiguration using AXI HwIcap.
+* Updated the XDcfg_Transfer API to clear the
+* QUARTER_PCAP_RATE_EN bit in the control register for
+* non secure writes for CR 675543.
+* 2.02a nm 01/31/13 Fixed CR# 679335.
+* Added Setting and Clearing the internal PCAP loopback.
+* Removed code for enabling/disabling AES engine as BootROM
+* locks down this setting.
+* Fixed CR# 681976.
+* Skip Checking the PCFG_INIT in case of non-secure DMA
+* loopback.
+* Fixed CR# 699558.
+* XDcfg_Transfer fails to transfer data in loopback mode.
+* Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 3.0 adk 10/12/13 Updated as per the New Tcl API's
+* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
+* updated driver code with != instead of ==,
+* while checking for Interrupt Status with DMA and
+* PCAP Done Mask
+* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+* XDCFG_INT_STS_OFFSET) &
+* XDCFG_IXR_D_P_DONE_MASK) !=
+* XDCFG_IXR_D_P_DONE_MASK);
+* A new example has been added to read back the
+* configuration registers from the PL region.
+* xdevcfg_reg_readback_example.c
+* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/10/17 Modified filename tag in interrupt and polled examples
+* to include them in doxygen examples.
+* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
+* definitions of devcfg in xparameters.h
+* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
+*
+******************************************************************************/
+#ifndef XDCFG_H /* prevent circular inclusions */
+#define XDCFG_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE 1
+#define XDCFG_SECURE_PCAP_WRITE 2
+#define XDCFG_PCAP_READBACK 3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param CallBackRef is the callback reference passed in by the upper
+* layer when setting the callback functions, and passed back to
+* the upper layer when the callback is invoked. Its type is
+* unimportant to the driver component, so it is a void pointer.
+* @param Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+ XDcfg_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device Configuration Interface
+ * is running
+ */
+ XDcfg_IntrHandler StatusHandler; /* Event handler function */
+ void *CallBackRef; /* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return Version of the PS.
+*
+* @note C-style signature:
+* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr) \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MCTRL_OFFSET)) & \
+ XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
+ XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr) \
+ XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr) \
+ XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
+ ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+ | XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+ XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+ u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+ void *SourcePtr, u32 SrcWordLength,
+ void *DestPtr, u32 DestWordLength,
+ u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
new file mode 100644
index 0000000..85881c6
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdevcfg.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDcfg_Config XDcfg_ConfigTable[] =
+{
+ {
+ XPAR_PS7_DEV_CFG_0_DEVICE_ID,
+ XPAR_PS7_DEV_CFG_0_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
new file mode 100644
index 0000000..8a1379a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given devcfg interface by
+* configuring the appropriate control bits in the devcfg specifc registers
+* the devcfg reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status
+* Update relevant config registers with reset values
+* Disbale the looopback mode and pcap rate enable
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* devcfg controller
+******************************************************************************/
+void XDcfg_ResetHw(u32 BaseAddr)
+{
+ u32 Regval = 0;
+
+ /* Mask the interrupts */
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
+ XDCFG_IXR_ALL_MASK);
+ /* Clear the interuupt status */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
+ XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
+ /* Clear the source address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
+ /* Clear the destination address register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
+ /* Clear the source length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
+ /* Clear the destination length register */
+ XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
+ /* Clear the loopback enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
+ Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
+ /*Reset the configuration register to reset value */
+ XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
+ XDCFG_CONFIG_RESET_VALUE);
+ /*Disable the PCAP rate enable bit */
+ Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
+ Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
+ XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
new file mode 100644
index 0000000..80b6678
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h
@@ -0,0 +1,391 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 08/01/12 Added defines for the PS Version bits,
+* removed the FIFO Flush bits from the
+* Miscellaneous Control Reg
+* 2.03a nm 04/19/13 Fixed CR# 703728.
+* Updated the register definitions as per the latest TRM
+* version UG585 (v1.4) November 16, 2012.
+* 2.04a kpc 10/07/13 Added function prototype.
+* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H /* prevent circular inclusions */
+#define XDCFG_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+ * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
+ * Secure Reset
+ */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
+ * Reset FPGA
+ */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
+ * to FPGA every 4 PCAP
+ * cycles
+ */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
+ * Status mask
+ */
+#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
+ * Debug Enable
+ */
+#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
+ * Enable
+ */
+#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+ * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
+ * USER_MODE
+ */
+#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
+ * security config
+ * including: DAP_En,
+ * DBGEN,,
+ * NIDEN, SPNIEN
+ */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+ * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
+ * Threshold Mask
+ */
+#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
+ * Mask
+ */
+#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
+ * clock edge
+ */
+#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
+ * clock edge
+ */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
+ * increment mask
+ */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
+ * address increment
+ * mask
+ */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+ * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
+ * HIZ
+ */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
+ * done
+ */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
+ * configuration
+ */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
+ * reset
+ */
+#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
+ * or Data or response
+ * timeout
+ */
+#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
+ * error
+ */
+#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
+ * response timeout
+ */
+#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
+ * error
+ */
+#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
+ * threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
+ * threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
+ * overflow
+ */
+#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
+ * transfers Done
+ */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
+ * length error
+ */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
+ * of Init Signal
+ */
+#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
+ XDCFG_IXR_AXI_WERR_MASK | \
+ XDCFG_IXR_AXI_RTO_MASK | \
+ XDCFG_IXR_AXI_RERR_MASK | \
+ XDCFG_IXR_RX_FIFO_OV_MASK | \
+ XDCFG_IXR_DMA_CMD_ERR_MASK |\
+ XDCFG_IXR_DMA_Q_OV_MASK | \
+ XDCFG_IXR_P2D_LEN_ERR_MASK |\
+ XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+ * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
+ * Queue full
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
+ * Queue empty
+ */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
+ * completed DMA
+ * transfers
+ */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
+ * during HIZ
+ */
+#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
+ * done
+ */
+#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
+ * config
+ */
+#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
+ * POR Status
+ */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
+ * access
+ */
+#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
+ * reset status
+ */
+#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
+ * Status
+ */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
+ /**< BBRAM key
+ * disable
+ */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
+ * Enable Status
+ */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
+ * Disable
+ * status
+ */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control Register Bit definitions
+ * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+ * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
+ * address
+ */
+#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
new file mode 100644
index 0000000..f0e5044
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c
@@ -0,0 +1,306 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_intr.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains the implementation of interrupt related functions of the XDcfg
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
+* set the mask instead of oring it with the
+* value read from the interrupt status register
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be enabled.
+* Bit positions of 1 will be enabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Enable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be disabled.
+* Bit positions of 1 will be disabled. Bit positions of 0 will
+* keep the previous setting. This mask is formed by OR'ing
+* XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
+{
+ u32 RegValue;
+
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Disable the specified interrupts in the Interrupt Mask Register.
+ */
+ RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET);
+ RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET,
+ RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the IMR.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Mask Register.
+ */
+ return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_MASK_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return A 32-bit value representing the contents of the Interrupt
+* Status register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Return the value read from the Interrupt Status register.
+ */
+ return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+* @param Mask is the bit-mask of the interrupts to be cleared.
+* Bit positions of 1 will be cleared. Bit positions of 0 will not
+* change the previous interrupt status. This mask is formed by
+* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
+{
+ /*
+ * Assert the arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET,
+ Mask);
+
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the Device Config Interface.
+*
+* Events are signaled to upper layer for proper handling.
+*
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return None.
+*
+* @note None.
+*
+****************************************************************************/
+void XDcfg_InterruptHandler(XDcfg *InstancePtr)
+{
+ u32 IntrStatusReg;
+
+ /*
+ * Assert validates the input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Interrupt status register.
+ */
+ IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET);
+
+ /*
+ * Write the status back to clear the interrupts so that no
+ * subsequent interrupts are missed while processing this interrupt.
+ * This also does the DMA acknowledgment automatically.
+ */
+ XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+ XDCFG_INT_STS_OFFSET, IntrStatusReg);
+
+ /*
+ * Signal application that there are events to handle.
+ */
+ InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+ IntrStatusReg);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param InstancePtr is a pointer to the XDcfg instance
+* @param CallBackFunc is the address of the callback function.
+* @param CallBackRef is a user data item that will be passed to the
+* callback function when it is invoked.
+*
+* @return None.
+*
+* @note None.
+*
+*
+*****************************************************************************/
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+ void *CallBackRef)
+{
+ /*
+ * Asserts validate the input arguments
+ * CallBackRef not checked, no way to know what is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(CallBackFunc != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
new file mode 100644
index 0000000..e8fc663
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_selftest.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* Contains diagnostic self-test functions for the XDcfg driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm 02/27/13 Fixed CR# 701348.
+* Peripheral test fails with Running
+* DcfgSelfTestExample() in SECURE bootmode.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the Device Configuration Interface. This test does a
+* control register write and reads back the same value.
+*
+* @param InstancePtr is a pointer to the XDcfg instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if fails.
+*
+* @note None.
+*
+******************************************************************************/
+int XDcfg_SelfTest(XDcfg *InstancePtr)
+{
+ u32 OldCfgReg;
+ u32 CfgReg;
+ int Status = XST_SUCCESS;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
+
+ CfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+ if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the original values of the register
+ */
+ XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
+
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
new file mode 100644
index 0000000..838db3a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdevcfg_sinit.c
+* @addtogroup devcfg_v3_5
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 3.5 ms 08/07/17 Fixed compilation warnings.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
+{
+ extern XDcfg_Config XDcfg_ConfigTable[];
+ XDcfg_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
+ if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XDcfg_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (CfgPtr);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/Makefile
new file mode 100644
index 0000000..d1240c5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdmaps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling dmaps"
+
+xdmaps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdmaps_includes
+
+xdmaps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.c
new file mode 100644
index 0000000..b30a66f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.c
@@ -0,0 +1,1978 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This file contains the implementation of the interface functions for XDmaPs
+* driver. Refer to the header file xdmaps.h for more detailed information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/2010 First Release
+* 1.00 nm 05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
+* since it is being defined in xil_io.h
+* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include
+
+#include "xstatus.h"
+#include "xdmaps.h"
+#include "xil_io.h"
+#include "xil_cache.h"
+
+#include "xil_printf.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread);
+
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
+
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
+
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength);
+
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
+
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XDmaPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param InstPtr is a pointer to the XDmaPs instance.
+* @param Config is a reference to a structure containing information
+* about a specific XDmaPs driver.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. The caller is responsible for keeping the
+* address mapping from EffectiveAddr to the device physical base
+* address unchanged once this function is invoked. Unexpected
+* errors may occur if the address mapping changes after this
+* function is called. If address translation is not used, pass in
+* the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS on initialization completion
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr)
+{
+ int Status = XST_SUCCESS;
+ unsigned int CacheLength = 0;
+ u32 CfgReg;
+ unsigned Channel;
+ XDmaPs_ChannelData *ChanData;
+
+ /*
+ * Assert validates the input arguments
+ */
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Config != NULL);
+
+ /*
+ * Setup the driver instance using passed in parameters
+ */
+ InstPtr->Config.DeviceId = Config->DeviceId;
+ InstPtr->Config.BaseAddress = EffectiveAddr;
+
+ CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
+ CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
+ if (CacheLength < 2 || CacheLength > 5)
+ CacheLength = 0;
+ else
+ CacheLength = 1 << CacheLength;
+
+ InstPtr->CacheLength = CacheLength;
+
+ memset(InstPtr->Chans, 0,
+ sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV]));
+
+ for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
+ ChanData = InstPtr->Chans + Channel;
+ ChanData->ChanId = Channel;
+ ChanData->DevId = Config->DeviceId;
+ }
+
+ InstPtr->IsReady = 1;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the DMA Manager.
+*
+* @param InstPtr is the DMA instance.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetManager(XDmaPs *InstPtr)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ 0, 0);
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the specified DMA Channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel to be reset.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
+{
+ int Status;
+ Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+ Channel, 1);
+
+ return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver fault interrupt service routine
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_FaultISR(XDmaPs *InstPtr)
+{
+
+ void *DmaProgBuf;
+ u32 Fsm; /* Fault status DMA manager register value */
+ u32 Fsc; /* Fault status DMA channel register value */
+ u32 FaultType; /* Fault type DMA manager register value */
+
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+
+ u32 Pc; /* DMA Pc or channel Pc */
+ XDmaPs_ChannelData *ChanData;
+
+ unsigned Chan;
+ unsigned DevId;
+
+ XDmaPs_Cmd *DmaCmd;
+
+ Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
+ Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
+
+
+ DevId = InstPtr->Config.DeviceId;
+
+ if (Fsm) {
+ /*
+ * if DMA manager is fault
+ */
+ FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET);
+ Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET);
+
+ xil_printf("PL330 device %d fault with type: %x at Pc %x\n",
+ DevId,
+ FaultType, Pc);
+
+ /* kill the DMA manager thread */
+ /* Should we disable interrupt?*/
+ XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0);
+ }
+
+ /*
+ * check which channel faults and kill the channel thread
+ */
+ for (Chan = 0;
+ Chan < XDMAPS_CHANNELS_PER_DEV;
+ Chan++) {
+ if (Fsc & (0x01 << Chan)) {
+ FaultType =
+ XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_FTCn_OFFSET(Chan));
+ Pc = XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CPCn_OFFSET(Chan));
+
+ /* kill the channel thread */
+ /* Should we disable interrupt? */
+ XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1);
+
+ /*
+ * get the fault type and fault Pc and invoke the
+ * fault callback.
+ */
+ ChanData = InstPtr->Chans + Chan;
+
+ DmaCmd = ChanData->DmaCmdToHw;
+
+ /* Should we check DmaCmd is not null */
+ DmaCmd->DmaStatus = -1;
+ DmaCmd->ChanFaultType = FaultType;
+ DmaCmd->ChanFaultPCAddr = Pc;
+ ChanData->DmaCmdFromHw = DmaCmd;
+ ChanData->DmaCmdToHw = NULL;
+
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ if (InstPtr->FaultHandler)
+ InstPtr->FaultHandler(Chan,
+ DmaCmd,
+ InstPtr->FaultRef);
+
+ }
+ }
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the done handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the channel number.
+* @param DoneHandler is the done interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef)
+{
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ if (Channel >= XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+
+ ChanData = InstPtr->Chans + Channel;
+
+ ChanData->DoneHandler = DoneHandler;
+ ChanData->DoneRef = CallbackRef;
+
+ return 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the fault handler for a channel.
+*
+* @param InstPtr is the DMA instance.
+* @param FaultHandler is the fault interrupt handler.
+* @param CallbackRef is the callback reference data.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ InstPtr->FaultHandler = FaultHandler;
+ InstPtr->FaultRef = CallbackRef;
+
+ return XST_SUCCESS;
+}
+
+
+
+/****************************************************************************/
+/**
+* Construction function for DMAEND instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for
+* the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
+{
+ /*
+ * DMAEND encoding:
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 0 0 0
+ */
+ *DmaProg = 0x0;
+
+ return 1;
+}
+
+static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
+{
+ *Dst = *Src;
+ *(Dst + 1) = *(Src + 1);
+ *(Dst + 2) = *(Src + 2);
+ *(Dst + 3) = *(Src + 3);
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAGO instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Cn is the Channel number, 0 - 7
+* @param Imm is 32-bit immediate number written to the Channel Program
+* Counter.
+* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in
+* the Non-secure state. If Ns is 0, the execution depends on the
+* security state of the DMA manager:
+* DMA manager is in the Secure state, DMA channel operates in the
+* Secure state.
+* DMA manager is in the Non-secure state, DMAC aborts.
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns)
+{
+ /*
+ * DMAGO encoding:
+ * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+ * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ */
+ *DmaProg = 0xA0 | ((Ns << 1) & 0x02);
+
+ *(DmaProg + 1) = (u8)(Cn & 0x07);
+
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ /* success */
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALD instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg the DMA program buffer, it's the starting address for the
+* instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
+{
+ /*
+ * DMALD encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 1 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x04;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALP instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Lc is the Loop counter register, can either be 0 or 1.
+* @param LoopIterations: the number of interations, LoopInterations - 1
+* will be encoded in the DMALP instruction.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations)
+{
+ /*
+ * DMALP encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | iter[7:0] |0 0 1 0 0 0 lc 0
+ */
+ *DmaProg = (u8)(0x20 | ((Lc & 1) << 1));
+ *(DmaProg + 1) = (u8)(LoopIterations - 1);
+ return 2;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALPEND instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param BodyStart is the starting address of the loop body. It is used
+* to calculate the bytes of backward jump.
+* @param Lc is the Loop counter register, can either be 0 or 1.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
+{
+ /*
+ * DMALPEND encoding
+ * 15 ... 8 7 6 5 4 3 2 1 0
+ * | backward_jump[7:0] |0 0 1 nf 1 lc bs x
+ *
+ * lc: loop counter
+ * nf is for loop forever. The driver does not support loop forever,
+ * so nf is 1.
+ * The driver does not support conditional LPEND, so bs is 0, x is 0.
+ */
+ *DmaProg = 0x38 | ((Lc & 1) << 2);
+ *(DmaProg + 1) = (u8)(DmaProg - BodyStart);
+
+ return 2;
+}
+
+/*
+ * Register number for the DMAMOV instruction
+ */
+#define XDMAPS_MOV_SAR 0x0
+#define XDMAPS_MOV_CCR 0x1
+#define XDMAPS_MOV_DAR 0x2
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAMOV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR
+* @param Imm is the 32-bit immediate number
+*
+* @return The number of bytes for this instruction which is 6.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
+{
+ /*
+ * DMAMOV encoding
+ * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0
+ * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0
+ *
+ * 47 ... 16
+ * imm[32:0]
+ *
+ * rd: b000 for SAR, b001 CCR, b010 DAR
+ */
+ *DmaProg = 0xBC;
+ *(DmaProg + 1) = Rd & 0x7;
+ // *((u32 *)(DmaProg + 2)) = Imm;
+ XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+ return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMANOP instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
+{
+ /*
+ * DMANOP encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 1 0 0 0
+ */
+ *DmaProg = 0x18;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMARMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_Instr_DMARMB(char *DmaProg)
+{
+ /*
+ * DMARMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x12;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMASEV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+* @param EventNumber is the Event number to signal.
+*
+* @return The number of bytes for this instruction which is 2.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
+{
+ /*
+ * DMASEV encoding
+ * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0
+ * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0
+ */
+ *DmaProg = 0x34;
+ *(DmaProg + 1) = (u8)(EventNumber << 3);
+
+ return 2;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAST instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
+{
+ /*
+ * DMAST encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 0 1 0 bs x
+ *
+ * Note: this driver doesn't support conditional load or store,
+ * so the bs bit is 0 and x bit is 0.
+ */
+ *DmaProg = 0x08;
+ return 1;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAWMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param DmaProg is the DMA program buffer, it's the starting address
+* for the instruction being constructed
+*
+* @return The number of bytes for this instruction which is 1.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_Instr_DMAWMB(char *DmaProg)
+{
+ /*
+ * DMAWMB encoding
+ * 7 6 5 4 3 2 1 0
+ * 0 0 0 1 0 0 1 0
+ */
+ *DmaProg = 0x13;
+ return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the endian swap size to the bit encoding of the CCR
+*
+* @param EndianSwapSize is the endian swap size, in terms of bits, it
+* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax)
+*
+* @return The endian swap size bit encoding for the CCR.
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
+{
+ switch (EndianSwapSize) {
+ case 0:
+ case 8:
+ return 0;
+ case 16:
+ return 1;
+ case 32:
+ return 2;
+ case 64:
+ return 3;
+ case 128:
+ return 4;
+ default:
+ return 0;
+ }
+
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the burst size to the bit encoding of the CCR
+*
+* @param BurstSize is the burst size. It's the data width.
+* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128.
+* It must be no larger than the bus width.
+* (We are using DMA assembly syntax.)
+*
+* @note None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
+{
+ switch (BurstSize) {
+ case 1:
+ return 0;
+ case 2:
+ return 1;
+ case 4:
+ return 2;
+ case 8:
+ return 3;
+ case 16:
+ return 4;
+ case 32:
+ return 5;
+ case 64:
+ return 6;
+ case 128:
+ return 7;
+ default:
+ return 0;
+ }
+}
+
+
+/****************************************************************************/
+/**
+*
+* Conversion function from PL330 bus transfer descriptors to CCR value. All the
+* values passed to the functions are in terms of assembly languages, not in
+* terms of the register bit encoding.
+*
+* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl.
+*
+* @return The 32-bit CCR value.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
+{
+ /*
+ * Channel Control Register encoding
+ * [31:28] - endian_swap_size
+ * [27:25] - dst_cache_ctrl
+ * [24:22] - dst_prot_ctrl
+ * [21:18] - dst_burst_len
+ * [17:15] - dst_burst_size
+ * [14] - dst_inc
+ * [13:11] - src_cache_ctrl
+ * [10:8] - src_prot_ctrl
+ * [7:4] - src_burst_len
+ * [3:1] - src_burst_size
+ * [0] - src_inc
+ */
+
+ unsigned es =
+ XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize);
+
+ unsigned dst_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
+ unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
+ unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
+ | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
+ unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
+ unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
+
+ unsigned src_burst_size =
+ XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
+ unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
+ unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
+ | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
+ unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
+ unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
+
+ u32 ccr_value = (es << 28)
+ | (dst_cache_ctrl << 25)
+ | (dst_prot_ctrl << 22)
+ | (dst_burst_len << 18)
+ | (dst_burst_size << 15)
+ | (dst_inc_bit << 14)
+ | (src_cache_ctrl << 11)
+ | (src_prot_ctrl << 8)
+ | (src_burst_len << 4)
+ | (src_burst_size << 1)
+ | (src_inc_bit);
+
+ return ccr_value;
+}
+
+/****************************************************************************/
+/**
+* Construct a loop with only DMALD and DMAST as the body using loop counter 0.
+* The function also makes sure the loop body and the lpend is in the same
+* cache line.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCount The inner loop count. Loop count - 1 will be used to
+* initialize the loop counter.
+*
+* @return The number of bytes the loop has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ int LoopCount)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount);
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 3;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/****************************************************************************/
+/**
+* Construct a nested loop with only DMALD and DMAST in the inner loop body.
+* It uses loop counter 1 for the outer loop and loop counter 0 for the
+* inner loop.
+*
+* @param DmaProgStart is the very start address of the DMA program.
+* This is used to calculate whether the loop is in a cache line.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+* @param DmaProgLoopStart The starting address of the loop (DMALP).
+* @param LoopCountOuter The outer loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+* @param LoopCountInner The inner loop count. Loop count - 1 will be
+* used to initialize the loop counter.
+*
+* @return The number byes the nested loop program has.
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
+ int CacheLength,
+ char *DmaProgLoopStart,
+ unsigned int LoopCountOuter,
+ unsigned int LoopCountInner)
+{
+ int CacheStartOffset;
+ int CacheEndOffset;
+ int NumNops;
+ char *InnerLoopStart;
+ char *DmaProgBuf = DmaProgLoopStart;
+
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter);
+ InnerLoopStart = DmaProgBuf;
+
+ if (CacheLength > 0) {
+ /*
+ * the CacheLength > 0 switch is ued to turn on/off nop
+ * insertion
+ */
+ if (CacheLength < 8) {
+ /*
+ * if the cache line is too small to fit both loops
+ * just align the inner loop
+ */
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCountInner);
+ /* outer loop end */
+ DmaProgBuf +=
+ XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart,
+ 1);
+
+ /*
+ * the nested loop is constructed for
+ * smaller cache line
+ */
+ return DmaProgBuf - DmaProgLoopStart;
+ }
+
+ /*
+ * Now let's handle the case where a cache line can
+ * fit the nested loops.
+ */
+ CacheStartOffset = DmaProgBuf - DmaProgStart;
+ CacheEndOffset = CacheStartOffset + 7;
+
+ /*
+ * check whether the body and lpend fit in one cache line
+ */
+ if (CacheStartOffset / CacheLength
+ != CacheEndOffset / CacheLength) {
+ /* insert the nops */
+ NumNops = CacheLength
+ - CacheStartOffset % CacheLength;
+ while (NumNops--) {
+ DmaProgBuf +=
+ XDmaPs_Instr_DMANOP(DmaProgBuf);
+ }
+ }
+ }
+
+ /* insert the inner DMALP */
+ DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner);
+
+ /* DMALD and DMAST instructions */
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+
+ /* inner DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ DmaProgBuf - 2, 0);
+ /* outer DMALPEND */
+ DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+ InnerLoopStart, 1);
+
+ /* return the number of bytes */
+ return DmaProgBuf - DmaProgLoopStart;
+}
+
+/*
+ * [31:28] endian_swap_size b0000
+ * [27:25] dst_cache_ctrl b000
+ * [24:22] dst_prot_ctrl b000
+ * [21:18] dst_burst_len b0000
+ * [17:15] dst_burst_size b000
+ * [14] dst_inc b0
+ * [27:25] src_cache_ctrl b000
+ * [24:22] src_prot_ctrl b000
+ * [21:18] src_burst_len b0000
+ * [17:15] src_burst_size b000
+ * [14] src_inc b0
+ */
+#define XDMAPS_CCR_SINGLE_BYTE (0x0)
+#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1)
+
+
+/****************************************************************************/
+/**
+*
+* Construct the DMA program based on the descriptions of the DMA transfer.
+* The function handles memory to memory DMA transfers.
+* It also handles unalgined head and small amount of residue tail.
+*
+* @param Channel DMA channel number
+* @param Cmd is the DMA command.
+* @param CacheLength is the icache line length, in terms of bytes.
+* If it's zero, the performance enhancement feature will be
+* turned off.
+*
+* @returns The number of bytes for the program.
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+ unsigned CacheLength)
+{
+ /*
+ * unpack arguments
+ */
+ char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg;
+ unsigned DevChan = Channel;
+ unsigned long DmaLength = Cmd->BD.Length;
+ u32 SrcAddr = Cmd->BD.SrcAddr;
+
+ unsigned SrcInc = Cmd->ChanCtrl.SrcInc;
+ u32 DstAddr = Cmd->BD.DstAddr;
+ unsigned DstInc = Cmd->ChanCtrl.DstInc;
+
+ char *DmaProgStart = DmaProgBuf;
+
+ unsigned int BurstBytes;
+ unsigned int LoopCount;
+ unsigned int LoopCount1 = 0;
+ unsigned int LoopResidue = 0;
+ unsigned int TailBytes;
+ unsigned int TailWords;
+ int DmaProgBytes;
+ u32 CCRValue;
+ unsigned int Unaligned;
+ unsigned int UnalignedCount;
+ unsigned int MemBurstSize = 1;
+ u32 MemAddr = 0;
+ unsigned int Index;
+ unsigned int SrcUnaligned = 0;
+ unsigned int DstUnaligned = 0;
+
+ XDmaPs_ChanCtrl *ChanCtrl;
+ XDmaPs_ChanCtrl WordChanCtrl;
+ static XDmaPs_ChanCtrl Mem2MemByteCC;
+
+ Mem2MemByteCC.EndianSwapSize = 0;
+ Mem2MemByteCC.DstCacheCtrl = 0;
+ Mem2MemByteCC.DstProtCtrl = 0;
+ Mem2MemByteCC.DstBurstLen = 1;
+ Mem2MemByteCC.DstBurstSize = 1;
+ Mem2MemByteCC.DstInc = 1;
+ Mem2MemByteCC.SrcCacheCtrl = 0;
+ Mem2MemByteCC.SrcProtCtrl = 0;
+ Mem2MemByteCC.SrcBurstLen = 1;
+ Mem2MemByteCC.SrcBurstSize = 1;
+ Mem2MemByteCC.SrcInc = 1;
+
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ /* insert DMAMOV for SAR and DAR */
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_SAR,
+ SrcAddr);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_DAR,
+ DstAddr);
+
+
+ if (ChanCtrl->SrcInc)
+ SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
+
+ if (ChanCtrl->DstInc)
+ DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
+
+ if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
+ ChanCtrl = &Mem2MemByteCC;
+ }
+
+ if (ChanCtrl->SrcInc) {
+ MemBurstSize = ChanCtrl->SrcBurstSize;
+ MemAddr = SrcAddr;
+
+ } else if (ChanCtrl->DstInc) {
+ MemBurstSize = ChanCtrl->DstBurstSize;
+ MemAddr = DstAddr;
+ }
+
+ /* check whether the head is aligned or not */
+ Unaligned = MemAddr % MemBurstSize;
+
+ if (Unaligned) {
+ /* if head is unaligned, transfer head in bytes */
+ UnalignedCount = MemBurstSize - Unaligned;
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ for (Index = 0; Index < UnalignedCount; Index++) {
+ DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+ DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+ }
+
+ DmaLength -= UnalignedCount;
+ }
+
+ /* now the burst transfer part */
+ CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
+ DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
+
+ LoopCount = DmaLength / BurstBytes;
+ TailBytes = DmaLength % BurstBytes;
+
+ /*
+ * the loop count register is 8-bit wide, so if we need
+ * a larger loop, we need to have nested loops
+ */
+ if (LoopCount > 256) {
+ LoopCount1 = LoopCount / 256;
+ if (LoopCount1 > 256) {
+ xil_printf("DMA operation cannot fit in a 2-level "
+ "loop for channel %d, please reduce the "
+ "DMA length or increase the burst size or "
+ "length",
+ Channel);
+ return 0;
+ }
+ LoopResidue = LoopCount % 256;
+
+ if (LoopCount1 > 1)
+ DmaProgBuf +=
+ XDmaPs_ConstructNestedLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount1,
+ 256);
+ else
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ 256);
+
+ /* there will be some that cannot be covered by
+ * nested loops
+ */
+ LoopCount = LoopResidue;
+ }
+
+ if (LoopCount > 0) {
+ DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ LoopCount);
+ }
+
+ if (TailBytes) {
+ /* handle the tail */
+ TailWords = TailBytes / MemBurstSize;
+ TailBytes = TailBytes % MemBurstSize;
+
+ if (TailWords) {
+ WordChanCtrl = *ChanCtrl;
+ /*
+ * if we can transfer the tail in words, we will
+ * transfer words as much as possible
+ */
+ WordChanCtrl.SrcBurstSize = MemBurstSize;
+ WordChanCtrl.SrcBurstLen = 1;
+ WordChanCtrl.DstBurstSize = MemBurstSize;
+ WordChanCtrl.DstBurstLen = 1;
+
+
+ /*
+ * the burst length is 1
+ */
+ CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailWords);
+
+ }
+
+ if (TailBytes) {
+ /*
+ * for the rest, we'll tranfer in bytes
+ */
+ /*
+ * So far just to be safe, the tail bytes
+ * are transfered in a loop. We can optimize a little
+ * to perform a burst.
+ */
+ CCRValue = XDMAPS_CCR_SINGLE_BYTE
+ | (SrcInc & 1)
+ | ((DstInc & 1) << 14);
+
+ DmaProgBuf +=
+ XDmaPs_Instr_DMAMOV(DmaProgBuf,
+ XDMAPS_MOV_CCR,
+ CCRValue);
+
+ DmaProgBuf +=
+ XDmaPs_ConstructSingleLoop(DmaProgStart,
+ CacheLength,
+ DmaProgBuf,
+ TailBytes);
+
+ }
+ }
+
+ DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan);
+ DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf);
+
+ DmaProgBytes = DmaProgBuf - DmaProgStart;
+
+ Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes);
+
+ return DmaProgBytes;
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* Generate a DMA program based for the DMA command, the buffer will be pointed
+* by the GeneratedDmaProg field of the command.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+*
+* @return - XST_SUCCESS on success.
+* - XST_FAILURE if it fails
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+ void *Buf;
+ int ProgLen;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_ChanCtrl *ChanCtrl;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ ChanData = InstPtr->Chans + Channel;
+ ChanCtrl = &Cmd->ChanCtrl;
+
+ if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen
+ != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) {
+ return XST_FAILURE;
+ }
+
+
+ /*
+ * unaligned fixed address is not supported
+ */
+ if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) {
+ return XST_FAILURE;
+ }
+
+ if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) {
+ return XST_FAILURE;
+ }
+
+ Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool);
+ if (Buf == NULL) {
+ return XST_FAILURE;
+ }
+
+ Cmd->GeneratedDmaProg = Buf;
+ ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
+ InstPtr->CacheLength);
+ Cmd->GeneratedDmaProgLength = ProgLen;
+
+
+#ifdef XDMAPS_DEBUG
+ XDmaPs_Print_DmaProg(Cmd);
+#endif
+
+ if (ProgLen <= 0) {
+ /* something wrong, release the buffer */
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProgLength = 0;
+ Cmd->GeneratedDmaProg = NULL;
+ return XST_FAILURE;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+ * Free the DMA program buffer that is pointed by the GeneratedDmaProg field
+ * of the command.
+ *
+ * @param InstPtr is then DMA instance.
+ * @param Channel is the DMA channel number.
+ * @param Cmd is the DMA command.
+ *
+ * @return XST_SUCCESS on success.
+ * XST_FAILURE if there is any error.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+
+ void *Buf;
+ XDmaPs_ChannelData *ChanData;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return XST_FAILURE;
+
+ Buf = (void *)Cmd->GeneratedDmaProg;
+ ChanData = InstPtr->Chans + Channel;
+
+ if (Buf) {
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+ Cmd->GeneratedDmaProg = 0;
+ Cmd->GeneratedDmaProgLength = 0;
+ }
+
+ return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Start a DMA command. The command can only be invoked when the channel
+* is idle. The driver takes the command, generates DMA program if needed,
+* then pass the program to DMAC to execute.
+*
+* @param InstPtr is then DMA instance.
+* @param Channel is the DMA channel number.
+* @param Cmd is the DMA command.
+* @param HoldDmaProg is tag indicating whether the driver can release
+* the allocated DMA buffer or not. If a user wants to examine the
+* generated DMA program, the flag should be set to 1. After the
+* DMA program is finished, a user needs to explicity free the
+* buffer.
+*
+* @return
+* - XST_SUCCESS on success
+* - XST_DEVICE_BUSY if DMA is busy
+* - XST_FAILURE on other failures
+*
+* @note None.
+*
+****************************************************************************/
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg)
+{
+ int Status;
+ u32 DmaProg = 0;
+ u32 Inten;
+
+ Xil_AssertNonvoid(InstPtr != NULL);
+ Xil_AssertNonvoid(Cmd != NULL);
+
+
+ Cmd->DmaStatus = XST_FAILURE;
+
+ if (XDmaPs_IsActive(InstPtr, Channel))
+ return XST_DEVICE_BUSY;
+
+ if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
+ Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
+ if (Status)
+ return XST_FAILURE;
+ }
+
+ InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
+
+ if (Cmd->UserDmaProg)
+ DmaProg = (u32)Cmd->UserDmaProg;
+ else if (Cmd->GeneratedDmaProg)
+ DmaProg = (u32)Cmd->GeneratedDmaProg;
+
+ if (DmaProg) {
+ /* enable the interrupt */
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+ Inten |= 0x01 << Channel; /* set the correpsonding bit */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET,
+ Inten);
+ Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTEN_OFFSET);
+
+ InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
+
+ if (Cmd->ChanCtrl.SrcInc) {
+ Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length);
+ }
+ if (Cmd->ChanCtrl.DstInc) {
+ Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
+ Cmd->BD.Length);
+ }
+
+ Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
+ Channel, DmaProg);
+ }
+ else {
+ InstPtr->Chans[Channel].DmaCmdToHw = NULL;
+ Status = XST_FAILURE;
+ }
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Checks whether the DMA channel is active or idle.
+*
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel number.
+*
+* @return 0: if the channel is idle
+* 1: otherwise
+*
+* @note None.
+*
+*****************************************************************************/
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
+{
+ Xil_AssertNonvoid(InstPtr != NULL);
+
+ /* Need to assert Channel is in range */
+ if (Channel > XDMAPS_CHANNELS_PER_DEV)
+ return 0;
+
+ return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Allocate a buffer of the DMA program buffer from the pool.
+*
+* @param Pool the DMA program pool.
+*
+* @return The allocated buffer, NULL if there is any error.
+*
+* @note None.
+*
+*****************************************************************************/
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool)
+{
+ int Index;
+
+ Xil_AssertNonvoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (!Pool[Index].Allocated) {
+ Pool[Index].Allocated = 1;
+ return Pool[Index].Buf;
+ }
+ }
+
+ return NULL;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 0. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 0);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 1. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 1);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 2. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 2);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 3. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 3);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 4. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 4);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 5. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 5);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 6. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 6);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 7. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param InstPtr is the DMA instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
+{
+ XDmaPs_DoneISR_n(InstPtr, 7);
+}
+
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+
+/****************************************************************************/
+/**
+* Use the debug registers to kill the DMA thread.
+*
+* @param BaseAddr is DMA device base address.
+* @param Channel is the DMA channel number.
+* @param Thread is Debug thread encoding.
+* 0: DMA manager thread, 1: DMA channel.
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+*****************************************************************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+ unsigned int Channel,
+ unsigned int Thread)
+{
+ u32 DbgInst0;
+ int WaitCount;
+
+ DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread);
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ /* wait time out */
+ xil_printf("PL330 device at %x debug status busy time out\n",
+ BaseAddr);
+
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0);
+
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+/****************************************************************************/
+/**
+*
+*
+* Free a buffer of the DMA program buffer.
+* @param Pool the DMA program pool.
+* @param Buf the DMA program buffer to be release.
+*
+* @return None
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf)
+{
+ int Index;
+ Xil_AssertVoid(Pool != NULL);
+
+ for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+ if (Pool[Index].Buf == Buf) {
+ if (Pool[Index].Allocated) {
+ Pool[Index].Allocated = 0;
+ }
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel.
+*
+* @param BaseAddr PL330 device base address
+* @param Channel Channel number for the device
+* @param DmaProg DMA program starting address, this should be DMA address
+*
+* @return 0 on success, -1 on time out
+*
+* @note None.
+*
+****************************************************************************/
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
+{
+ char DmaGoProg[8];
+ u32 DbgInst0;
+ u32 DbgInst1;
+
+ int WaitCount;
+
+ XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0);
+
+ DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0);
+ DbgInst1 = (u32)DmaProg;
+
+ /* wait while debug status is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT)) {
+
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* write debug instruction 0 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+ /* write debug instruction 1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1);
+
+
+ /* wait while the DMA Manager is busy */
+ WaitCount = 0;
+ while ((XDmaPs_ReadReg(BaseAddr,
+ XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
+ != XDMAPS_DS_DMA_STATUS_STOPPED
+ && WaitCount <= XDMAPS_MAX_WAIT) {
+ WaitCount++;
+ }
+
+ if (WaitCount >= XDMAPS_MAX_WAIT) {
+ xil_printf("PL330 device at %x debug status busy time out\r\n",
+ BaseAddr);
+ return -1;
+ }
+
+ /* run the command in DbgInst0 and DbgInst1 */
+ XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+ return 0;
+}
+
+
+/****************************************************************************/
+/**
+*
+* It's the generic Done ISR.
+* @param InstPtr is the DMA instance.
+* @param Channel is the DMA channel numer.
+*
+* @return None.*
+*
+* @note None.
+*
+*****************************************************************************/
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
+{
+
+ void *DmaProgBuf;
+ XDmaPs_ChannelData *ChanData;
+ XDmaPs_Cmd *DmaCmd;
+ //u32 Value;
+
+ ChanData = InstPtr->Chans + Channel;
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+ /* clear the interrupt status */
+ XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTCLR_OFFSET,
+ 1 << ChanData->ChanId);
+
+ /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+ XDMAPS_INTSTATUS_OFFSET);*/
+
+
+ DmaCmd = ChanData->DmaCmdToHw;
+ if (DmaCmd) {
+ if (!ChanData->HoldDmaProg) {
+ DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+ if (DmaProgBuf)
+ XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+ DmaProgBuf);
+ DmaCmd->GeneratedDmaProg = NULL;
+ }
+
+ DmaCmd->DmaStatus = 0;
+ ChanData->DmaCmdToHw = NULL;
+ ChanData->DmaCmdFromHw = DmaCmd;
+
+ if (ChanData->DoneHandler)
+ ChanData->DoneHandler(Channel, DmaCmd,
+ ChanData->DoneRef);
+ }
+
+}
+
+
+/****************************************************************************/
+/**
+* Prints the content of the buffer in bytes
+* @param Buf is the buffer.
+* @param Length is the length of the DMA program.
+*
+* @return None.
+*
+* @note None.
+****************************************************************************/
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
+{
+ int Index;
+ for (Index = 0; Index < Length; Index++)
+ xil_printf("[%x] %x\r\n", Index, Buf[Index]);
+
+}
+/****************************************************************************/
+/**
+* Print the Dma Prog Contents.
+*
+* @param Cmd is the command buffer.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+ void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
+{
+ if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
+ xil_printf("Generated DMA program (%d):\r\n",
+ Cmd->GeneratedDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
+ Cmd->GeneratedDmaProgLength);
+ }
+
+ if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
+ xil_printf("User defined DMA program (%d):\r\n",
+ Cmd->UserDmaProgLength);
+ XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
+ Cmd->UserDmaProgLength);
+ }
+}
+
+
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.h
new file mode 100644
index 0000000..73e2b1e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps.h
@@ -0,0 +1,349 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_4
+* @{
+* @details
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00 hbm 08/19/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+* Added the tcl file to automatically generate the
+* xparameters.h
+* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
+* header from the xdmaps.h file to xdmaps.c file
+* Other cleanup for coding guidelines and CR 657109
+* and CR 657898
+* The xdmaps_example_no_intr.c example is removed
+* as it is using interrupts and is similar to
+* the interrupt example - CR 652477
+* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm 10/22/2012 Fixed CR# 681671.
+* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+* with -Wall and -Wextra option in bsp.
+* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+* function description.
+* Fixed CR# 704396. Removed unused variables
+* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+* function.
+* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
+* Removed the PDBG prints. By default they were always
+* defined out and never used. The PDBG is non-standard for
+* Xilinx drivers and no other driver does something similar.
+* Since there is no easy way to fix compilation issues with
+* the IARCC compiler around PDBG, it is better to remove it.
+* Users can always use xil_printfs if they want to debug.
+* 2.0 adk 10/12/13 Updated as per the New Tcl API's
+* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
+* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
+* linker error for IAR compiler
+* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
+* examples to ensure that "Successfully ran" and "Failed"
+* strings are available in all examples. This is a fix
+* for CR-965028.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
+*
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H /* prevent circular inclusions */
+#define XDMAPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+ unsigned int EndianSwapSize; /**< Endian swap size. */
+ unsigned int DstCacheCtrl; /**< Destination cache control */
+ unsigned int DstProtCtrl; /**< Destination protection control */
+ unsigned int DstBurstLen; /**< Destination burst length */
+ unsigned int DstBurstSize; /**< Destination burst size */
+ unsigned int DstInc; /**< Destination incrementing or fixed
+ * address */
+ unsigned int SrcCacheCtrl; /**< Source cache control */
+ unsigned int SrcProtCtrl; /**< Source protection control */
+ unsigned int SrcBurstLen; /**< Source burst length */
+ unsigned int SrcBurstSize; /**< Source burst size */
+ unsigned int SrcInc; /**< Source incrementing or fixed
+ * address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+ u32 SrcAddr; /**< Source starting address */
+ u32 DstAddr; /**< Destination starting address */
+ unsigned int Length; /**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+ XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
+ XDmaPs_BD BD; /**< Together with SgLength field,
+ * it's a scatter-gather list.
+ */
+ void *UserDmaProg; /**< If user wants the driver to
+ * execute their own DMA program,
+ * this field points to the DMA
+ * program.
+ */
+ int UserDmaProgLength; /**< The length of user defined
+ * DMA program.
+ */
+
+ void *GeneratedDmaProg; /**< The DMA program genreated
+ * by the driver. This field will be
+ * set if a user invokes the DMA
+ * program generation function. Or
+ * the DMA command is finished and
+ * a user informs the driver not to
+ * release the program buffer.
+ * This field has two purposes, one
+ * is to ask the driver to generate
+ * a DMA program while the DMAC is
+ * performaning DMA transactions. The
+ * other purpose is to debug the
+ * driver.
+ */
+ int GeneratedDmaProgLength; /**< The length of the DMA program
+ * generated by the driver
+ */
+ int DmaStatus; /**< 0 on success, otherwise error code
+ */
+ u32 ChanFaultType; /**< Channel fault type in case of fault
+ */
+ u32 ChanFaultPCAddr; /**< Channel fault PC address
+ */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+ XDmaPs_Cmd *DmaCmd,
+ void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS 2
+#define XDMAPS_CHAN_BUF_LEN 128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+ char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
+ * content */
+ unsigned Len; /**< The actual length of the DMA
+ * program in bytes. */
+ int Allocated; /**< A tag indicating whether the
+ * buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+ unsigned DevId; /**< Device id indicating which DMAC */
+ unsigned ChanId; /**< Channel number of the DMAC */
+ XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+ program buffers*/
+ XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
+ void *DoneRef; /**< Done interrupt callback data */
+ XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
+ XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
+ * This field is for debugging purpose
+ */
+ int HoldDmaProg; /**< A tag indicating whether to hold the
+ * DMA program after the DMA is done.
+ */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+ XDmaPs_Config Config; /**< Configuration data structure */
+ int IsReady; /**< Device is Ready */
+ int CacheLength; /**< icache length */
+ XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+ void *FaultRef; /**< fault call back data */
+ XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+ /**<
+ * channel data
+ */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+ XDmaPs_Config *Config,
+ u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd,
+ int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+ XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+ unsigned Channel,
+ XDmaPsDoneHandler DoneHandler,
+ void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+ XDmaPsFaultHandler FaultHandler,
+ void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+int XDmaPs_Instr_DMARMB(char *DmaProg);
+int XDmaPs_Instr_DMAWMB(char *DmaProg);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+ u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+ unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_g.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_g.c
new file mode 100644
index 0000000..97cb370
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_DMA_NS_DEVICE_ID,
+ XPAR_PS7_DMA_NS_BASEADDR
+ },
+ {
+ XPAR_PS7_DMA_S_DEVICE_ID,
+ XPAR_PS7_DMA_S_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.c
new file mode 100644
index 0000000..5fbe4ca
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_hw.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+* for XDmaPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+/************************** Function Prototypes *****************************/
+
+/************************** Variable Definitions ****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given dmaps interface by
+* configuring the appropriate control bits in the dmaps specifc registers
+* the dmaps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the pending interrupts
+* Kill all the active channel threads
+* Kill the manager thread
+*
+* @param BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* dmaps controller
+******************************************************************************/
+void XDmaPs_ResetHw(u32 BaseAddress)
+{
+ u32 DbgInst;
+ u32 WaitCount = 0;
+ u32 ChanIndex;
+
+ /* Disable all the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
+ /* Clear the interrupts */
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
+ /* Kill the dma channel threads */
+ for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
+ while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ && (WaitCount < XDMAPS_MAX_WAIT))
+ WaitCount++;
+
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+ }
+ /* Kill the manager thread */
+ DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
+ XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+}
+
+
+
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.h
new file mode 100644
index 0000000..42dfe69
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_hw.h
@@ -0,0 +1,289 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- ----------------------------------------------
+* 1.00a hbm 08/18/10 First Release
+* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+* the maximum number of channels.
+* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg 05/16/12 Made changes for doxygen
+* 1.06a kpc 07/10/13 Added function prototype
+*
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H /* prevent circular inclusions */
+#define XDMAPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
+ */
+#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
+ * Register
+ */
+#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
+ */
+#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
+ * Channel 0
+ */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
+ * Channel 0
+ */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
+ * DMA Channel 0
+ */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
+ * DMA Channel 0
+ */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
+ * Register 0
+ */
+#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
+ * Register 1
+ */
+#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
+ * Register 2
+ */
+#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
+ * Register 3
+ */
+#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
+ * Register 0
+ */
+#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
+ * Register 1
+ */
+#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
+ * Register 2
+ */
+#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
+ * Register 3
+ */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
+ * llast 3 bits of CS register
+ */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+ (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV 8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK 0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param BaseAddress contains the base address of the device.
+* @param RegOffset contains the offset from the base address of the device.
+* @param RegisterValue is the value to be written to the register.
+*
+* @return None.
+*
+* @note
+* C-Style signature:
+* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+* u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_selftest.c
new file mode 100644
index 0000000..37e70f8
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_selftest.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_selftest.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* This file contains the self-test functions for the XDmaPs driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00 hbm 03/29/2010 First Release
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param InstPtr is a pointer to the XDmaPs instance
+*
+* @return
+*
+* - XST_SUCCESS if the test was successful
+* - XST_FAILURE if the test failed
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+int XDmaPs_SelfTest(XDmaPs *InstPtr)
+{
+ u32 BaseAddr = InstPtr->Config.BaseAddress;
+ int i;
+
+ if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+ & XDMAPS_DBGSTATUS_BUSY)
+ return XST_FAILURE;
+
+ for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
+ if (XDmaPs_ReadReg(BaseAddr,
+ XDmaPs_CSn_OFFSET(i)))
+ return XST_FAILURE;
+ }
+ return XST_SUCCESS;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_sinit.c
new file mode 100644
index 0000000..e0b6fae
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_4/src/xdmaps_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_sinit.c
+* @addtogroup dmaps_v2_4
+* @{
+*
+* The implementation of the XDmaPs driver's static initialzation
+* functionality.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm 08/13/10 First Release
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+extern XDmaPs_Config XDmaPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return
+*
+* A pointer to the configuration structure or NULL if the specified device
+* is not in the system.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
+{
+ XDmaPs_Config *CfgPtr = NULL;
+
+ int i;
+
+ for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
+ if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XDmaPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/Makefile
new file mode 100644
index 0000000..7002e62
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xemacps_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling emacps"
+
+xemacps_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xemacps_includes
+
+xemacps_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.c
new file mode 100644
index 0000000..b8be326
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.c
@@ -0,0 +1,488 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* The XEmacPs driver. Functions in this file are the minimum required functions
+* for this driver. See xemacps.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+* 64-bit changes.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
+* Disable extended mode. Perform all 64 bit changes under
+* check for arch64.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5 hk 08/14/17 Update cache coherency information of the interface in
+* its config structure.
+* 3.8 hk 09/17/18 Cleanup stale comments.
+* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XEmacPs_StubHandler(void); /* Default handler routine */
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* Initialize a specific XEmacPs instance/driver. The initialization entails:
+* - Initialize fields of the XEmacPs instance structure
+* - Reset hardware and apply default options
+* - Configure the DMA channels
+*
+* The PHY is setup independently from the device. Use the MII or whatever other
+* interface may be present for setup.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param CfgPtr is the device configuration structure containing required
+* hardware build data.
+* @param EffectiveAddress is the base address of the device. If address
+* translation is not utilized, this parameter can be passed in using
+* CfgPtr->Config.BaseAddress to specify the physical base address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+******************************************************************************/
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
+ UINTPTR EffectiveAddress)
+{
+ /* Verify arguments */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(CfgPtr != NULL);
+
+ /* Set device base address and ID */
+ InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+ InstancePtr->Config.BaseAddress = EffectiveAddress;
+ InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
+
+ /* Set callbacks to an initial stub routine */
+ InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
+
+ /* Reset the hardware and set default options */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ XEmacPs_Reset(InstancePtr);
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+* Start the Ethernet controller as follows:
+* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
+* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
+* - Start the SG DMA send and receive channels and enable the device
+* interrupt
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return N/A
+*
+* @note
+* Hardware is configured with scatter-gather DMA, the driver expects to start
+* the scatter-gather channels and expects that the user has previously set up
+* the buffer descriptor lists.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
+* device options while another is trying to start the device, the user is
+* required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* This function must not be preempted by an interrupt that may service the
+* device.
+*
+******************************************************************************/
+void XEmacPs_Start(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Start DMA */
+ /* When starting the DMA channels, both transmit and receive sides
+ * need an initialized BD list.
+ */
+ if (InstancePtr->Version == 2) {
+ Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+ Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ InstancePtr->RxBdRing.BaseBdAddr);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ InstancePtr->TxBdRing.BaseBdAddr);
+ }
+
+ /* clear any existed int status */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Enable transmitter if not already enabled */
+ if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
+ }
+ }
+
+ /* Enable receiver if not already enabled */
+ if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
+ }
+ }
+
+ /* Enable TX and RX interrupts */
+ XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
+ XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
+ (u32)XEMACPS_IXR_TXCOMPL_MASK));
+
+ /* Enable TX Q1 Interrupts */
+ if (InstancePtr->Version > 2)
+ XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+
+ /* Mark as started */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+ return;
+}
+
+
+/*****************************************************************************/
+/**
+* Gracefully stop the Ethernet MAC as follows:
+* - Disable all interrupts from this device
+* - Stop DMA channels
+* - Disable the tansmitter and receiver
+*
+* Device options currently in effect are not changed.
+*
+* This function will disable all interrupts. Default interrupts settings that
+* had been enabled will be restored when XEmacPs_Start() is called.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @note
+* This function makes use of internal resources that are shared between the
+* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
+* setting device options while another is trying to start the device, the user
+* is required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* Stopping the DMA channels causes this function to block until the DMA
+* operation is complete.
+*
+******************************************************************************/
+void XEmacPs_Stop(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Disable all interrupts */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ /* Disable the receiver & transmitter */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Mark as stopped */
+ InstancePtr->IsStarted = 0U;
+}
+
+
+/*****************************************************************************/
+/**
+* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
+* transmitter, and the receiver.
+*
+* Steps to reset
+* - Stops transmit and receive channels
+* - Stops DMA
+* - Configure transmit and receive buffer size to default
+* - Clear transmit and receive status register and counters
+* - Clear all interrupt sources
+* - Clear phy (if there is any previously detected) address
+* - Clear MAC addresses (1-4) as well as Type IDs and hash value
+*
+* All options are placed in their default state. Any frames in the
+* descriptor lists will remain in the lists. The side effect of doing
+* this is that after a reset and following a restart of the device, frames
+* were in the list before the reset may be transmitted or received.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required, the driver notifies the upper layer software of
+* this need through the ErrorHandler callback and specific status codes.
+* The upper layer software is responsible for calling this Reset function
+* and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+******************************************************************************/
+void XEmacPs_Reset(XEmacPs *InstancePtr)
+{
+ u32 Reg;
+ u8 i;
+ s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* Stop the device and reset hardware */
+ XEmacPs_Stop(InstancePtr);
+ InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
+
+ InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
+
+ InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
+
+ InstancePtr->MaxMtuSize = XEMACPS_MTU;
+ InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
+ XEMACPS_TRL_SIZE;
+ InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+ XEMACPS_HDR_VLAN_SIZE;
+ InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+
+ /* Setup hardware with default values */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ (XEMACPS_NWCTRL_STATCLR_MASK |
+ XEMACPS_NWCTRL_MDEN_MASK) &
+ (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
+
+ Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
+ (u32)XEMACPS_NWCFG_FDEN_MASK |
+ (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
+ XEMACPS_NWCFG_DWIDTH_64_MASK));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET,
+ (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+ (((((u32)XEMACPS_RX_BUF_SIZE %
+ (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+ (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+ (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
+ (u32)XEMACPS_DMACR_RXSIZE_MASK |
+ (u32)XEMACPS_DMACR_TXSIZE_MASK);
+
+
+ if (InstancePtr->Version > 2) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
+#if defined(__aarch64__) || defined(__arch64__)
+ (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
+#endif
+ (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
+ }
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, 0x0U);
+
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
+ if (InstancePtr->Version > 2)
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+ XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, 0x0U);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+ XEMACPS_IXR_ALL_MASK);
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ Reg);
+
+ XEmacPs_ClearHash(InstancePtr);
+
+ for (i = 1U; i < 5U; i++) {
+ (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
+ (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
+ }
+
+ /* clear all counters */
+ for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
+ i++) {
+ (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
+ }
+
+ /* Disable the receiver */
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ /* Sync default options with hardware but leave receiver and
+ * transmitter disabled. They get enabled with XEmacPs_Start() if
+ * XEMACPS_TRANSMITTER_ENABLE_OPTION and
+ * XEMACPS_RECEIVER_ENABLE_OPTION are set.
+ */
+ (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
+ ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
+
+ (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
+}
+
+
+/******************************************************************************/
+/**
+ * This is a stub for the asynchronous callbacks. The stub is here in case the
+ * upper layer forgot to set the handler(s). On initialization, all handlers are
+ * set to this callback. It is considered an error for this handler to be
+ * invoked.
+ *
+ ******************************************************************************/
+void XEmacPs_StubHandler(void)
+{
+ Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+* This function sets the start address of the transmit/receive buffer queue.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param QPtr is the address of the Queue to be written
+* @param QueueNum is the Buffer Queue Index
+* @param Direction indicates Transmit/Recive
+*
+* @note
+* The buffer queue addresses has to be set before starting the transfer, so
+* this function has to be called in prior to XEmacPs_Start()
+*
+******************************************************************************/
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction)
+{
+ /* Assert bad arguments and conditions */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* If already started, then there is nothing to do */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ return;
+ }
+
+ if (QueueNum == 0x00U) {
+ if (Direction == XEMACPS_SEND) {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ } else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXQBASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+ }
+ else {
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXQ1BASE_OFFSET,
+ (QPtr & ULONG64_LO_MASK));
+ }
+#ifdef __aarch64__
+ if (Direction == XEMACPS_SEND) {
+ /* Set the MSB of TX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_TXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ } else {
+ /* Set the MSB of RX Queue start address */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_MSBBUF_RXQBASE_OFFSET,
+ (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+ }
+#endif
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.h
new file mode 100644
index 0000000..c22354f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps.h
@@ -0,0 +1,807 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_8
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ * - Memory mapped access to host interface registers
+ * - Statistics counter registers for RMON/MIB
+ * - API for interrupt driven frame transfers for hardware configured DMA
+ * - Virtual memory support
+ * - Unicast, broadcast, and multicast receive address filtering
+ * - Full and half duplex operation
+ * - Automatic PAD & FCS insertion and stripping
+ * - Flow control
+ * - Support up to four 48bit addresses
+ * - Address checking for four specific 48bit addresses
+ * - VLAN frame support
+ * - Pause frame support
+ * - Large frame support up to 1536 bytes
+ * - Checksum offload
+ *
+ * Driver Description
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * Initialization & Configuration
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
+ * configuration structure provided by the caller. If running in a system
+ * with address translation, the provided virtual memory base address
+ * replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * Interrupts and Asynchronous Callbacks
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * Virtual Memory
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * DMA
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ * 1. Idle. The driver controls BDs in this state.
+ * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ * reserve BD(s). Once allocated, the user may setup the BD(s) with
+ * frame buffer address, length, and other attributes. The user controls
+ * BDs in this state.
+ * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ * in this state are either waiting to be processed by hardware, are in
+ * process, or have been processed. The DMA engine controls BDs in this
+ * state.
+ * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ * user. Once retrieved, the user can examine each BD for the outcome of
+ * the DMA transfer. The user controls BDs in this state. After examining
+ * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ * into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * Alignment & Data Cache Restrictions
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ * - If frame buffers exist in cached memory, then they must be flushed
+ * prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ * - If frame buffers exist in cached memory, then the cache must be
+ * invalidated for the memory region containing the frame prior to data
+ * access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * Buffer Copying
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * Checksum Offloading
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ * must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ * encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * PHY Interfaces
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * Asserts
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter. The driver is independent of OS and processor
+ * and is intended to be highly portable. The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Earlier it was checking for
+ * "BdLimit"(passed argument) number of BDs for finding out
+ * which BDs are successfully processed. Now one more check
+ * is added. It looks for BDs till the current BD pointer
+ * reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ * xemacps_bdring.c is modified. Now start of packet is
+ * searched for returning the number of BDs processed.
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * registers. Added a new API to set the bust length.
+ * Added some new hash-defines.
+ * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
+ * Rx errors. Under heavy Rx traffic, there will be a large
+ * number of errors related to receive buffer not available.
+ * Because of a HW bug (SI #692601), under such heavy errors,
+ * the Rx data path can become unresponsive. To reduce the
+ * probabilities for hitting this HW bug, the SW writes to
+ * bit 18 to flush a packet from Rx DPRAM immediately. The
+ * changes for it are done in the function
+ * XEmacPs_IntrHandler.
+ * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+ * removed. It is expected that all BDs are allocated in
+ * from uncached area.
+ * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ * to 0x1fff. This fixes the CR#744902.
+ * Made changes in example file xemacps_example.h to fix compilation
+ * issues with iarcc compiler.
+ * 2.0 adk 10/12/13 Updated as per the New Tcl API's
+ * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ * address in xparameters.h when GMII to RGMII converter
+ * is present in hw.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ * changes.
+ * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ * 1000BASE-X mode export proper values to the xparameters.h
+ * file. Changes are made in the driver tcl file.
+ * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
+ * configured with PCS/PMA Core. Changes are made in the
+ * test app tcl(CR:827686).
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * Remove "used bit set" from TX error interrupt masks.
+ * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+ * there is no error. CR# 869403
+ * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
+ * examples to ensure that "Successfully ran" and "Failed"
+ * strings are available in all examples. This is a fix
+ * for CR-965028.
+ * ms 03/17/17 Modified text file in examples folder for doxygen
+ * generation.
+ * ms 04/05/17 Added tabspace for return statements in functions of
+ * xemacps_ieee1588_example.c for proper documentation
+ * while generating doxygen.
+ * 3.5 hk 08/14/17 Update cache coherency information of the interface in
+ * its config structure.
+ * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ * changed to volatile.
+ * Add API XEmacPs_BdRingPtrReset() to reset pointers
+ * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
+ * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H /* prevent circular inclusions */
+#define XEMACPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME "xemacps"
+#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION 0x00000001U
+/**< Accept all incoming packets.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION 0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION 0x00000004U
+/**< VLAN Rx & Tx frame support.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ * stripped.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ * set, the MAC will filter frames that have a mismatched type/length field
+ * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ * types of frames are encountered. When this option is cleared, the MAC will
+ * allow these types of frames to be received.
+ *
+ * This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
+/**< Enable the transmitter.
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
+/**< Enable the receiver
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION 0x00000400U
+/**< Allow reception of the broadcast address
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION 0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ * This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
+/**< Enable the RX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
+/**< Enable the TX checksum offload
+ * This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS \
+ ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
+ (u32)XEMACPS_FCS_INSERT_OPTION | \
+ (u32)XEMACPS_FCS_STRIP_OPTION | \
+ (u32)XEMACPS_BROADCAST_OPTION | \
+ (u32)XEMACPS_LENTYPE_ERR_OPTION | \
+ (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
+ (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
+ (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
+ (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR 3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
+
+#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+ XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST 0x00000001
+#define XEMACPS_4BYTE_BURST 0x00000004
+#define XEMACPS_8BYTE_BURST 0x00000008
+#define XEMACPS_16BYTE_BURST 0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+ u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+ u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+ * describes whether Cache Coherent or not */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+ XEmacPs_Config Config; /* Hardware configuration */
+ u32 IsStarted; /* Device is currently started */
+ u32 IsReady; /* Device is initialized and ready */
+ u32 Options; /* Current options word */
+
+ XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
+ XEmacPs_BdRing RxBdRing; /* Receive BD ring */
+
+ XEmacPs_Handler SendHandler;
+ XEmacPs_Handler RecvHandler;
+ void *SendRef;
+ void *RecvRef;
+
+ XEmacPs_ErrHandler ErrorHandler;
+ void *ErrorRef;
+ u32 Version;
+ u32 RxBufMask;
+ u32 MaxMtuSize;
+ u32 MaxFrameSize;
+ u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IER_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_IDR_OFFSET, \
+ ((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IER_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+* be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_INTQ1_IDR_OFFSET, \
+ ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr) \
+ XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET, \
+ (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr) \
+ ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
+ XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
+ ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+ UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+ u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+ XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bd.h
new file mode 100644
index 0000000..2b22223
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bd.h
@@ -0,0 +1,784 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_8
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * Buffer Descriptors
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements. See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * Performance
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ * and 64-bit changes.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * Disable extended mode. Perform all 64 bit changes under
+ * check for arch64.
+ * 3.2 hk 11/18/15 Change BD typedef and number of words.
+ * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
+ * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+ *
+ *
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H /* prevent circular inclusions */
+#define XEMACPS_BD_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr) \
+ memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to read
+* @param Offset is the word offset to be read
+*
+* @return The 32-bit value of the field
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset) \
+ (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param BaseAddress is the base address of the BD to write
+* @param Offset is the word offset to be written
+* @param Data is the 32-bit value to write to the field
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
+ (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ (u32)((Addr) & ULONG64_LO_MASK)); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Addr is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ * read-modify-write is performed.
+ *
+ * C-style signature:
+ * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
+ (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param Data is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr) \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#if defined(__aarch64__) || defined(__arch64__)
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ * @param LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
+ XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param InstancePtr is the pointer to XEmacps instance
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ * XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ * RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
+ (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
+ XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
+ XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
+ XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr) \
+ (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
+ XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr) \
+ ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
+ XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.c
new file mode 100644
index 0000000..208deb9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.c
@@ -0,0 +1,1098 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* This file implements buffer descriptor ring related functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+* Earlier it used to search in "BdLimit" number of BDs to
+* know which BDs are processed. Now one more check is
+* added. It looks for BDs till the current BD pointer
+* reaches HwTail. By doing this processing time is saved.
+* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
+* xemacps_bdring.c is modified. Now start of packet is
+* searched for returning the number of BDs processed.
+* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
+* removed. It is expected that all BDs are allocated in
+* from uncached area. Fix for CR #663885.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* pointers
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_cache.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************
+ * Compute the virtual address of a descriptor from its physical address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Virtual address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
+ ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Compute the physical address of a descriptor from its virtual address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Physical address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
+ ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
+ * to the beginning of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is greater than
+ * the high address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr += ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
+ { \
+ Addr -= (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
+ }
+
+/****************************************************************************
+ * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
+ * around to the end of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is less than
+ * the base address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ * final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
+ { \
+ UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
+ \
+ Addr -= ((RingPtr)->Separation * (NumBd)); \
+ if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
+ { \
+ Addr += (RingPtr)->Length; \
+ } \
+ \
+ (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
+ }
+
+
+/************************** Function Prototypes ******************************/
+
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * Using a memory segment allocated by the caller, create and setup the BD list
+ * for the given DMA channel.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param PhysAddr is the physical base address of user memory region.
+ * @param VirtAddr is the virtual base address of the user memory region. If
+ * address translation is not being utilized, then VirtAddr should be
+ * equivalent to PhysAddr.
+ * @param Alignment governs the byte alignment of individual BDs. This function
+ * will enforce a minimum alignment of 4 bytes with no maximum as long
+ * as it is specified as a power of 2.
+ * @param BdCount is the number of BDs to setup in the user memory region. It
+ * is assumed the region is large enough to contain the BDs.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if initialization was successful
+ * - XST_NO_FEATURE if the provided instance is a non DMA type
+ * channel.
+ * - XST_INVALID_PARAM under any of the following conditions:
+ * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
+ * parameter.
+ * 2) Alignment parameter does not meet minimum requirements or is not a
+ * power of 2 value.
+ * 3) BdCount is 0.
+ * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
+ * over address 0x00000000 in virtual address space.
+ *
+ * @note
+ * Make sure to pass in the right alignment value.
+ *****************************************************************************/
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
+{
+ u32 i;
+ UINTPTR BdVirtAddr;
+ UINTPTR BdPhyAddr;
+ UINTPTR VirtAddrLoc = VirtAddr;
+
+ /* In case there is a failure prior to creating list, make sure the
+ * following attributes are 0 to prevent calls to other functions
+ * from doing anything.
+ */
+ RingPtr->AllCnt = 0U;
+ RingPtr->FreeCnt = 0U;
+ RingPtr->HwCnt = 0U;
+ RingPtr->PreCnt = 0U;
+ RingPtr->PostCnt = 0U;
+
+ /* Make sure Alignment parameter meets minimum requirements */
+ if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure Alignment is a power of 2 */
+ if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Make sure PhysAddr and VirtAddr are on same Alignment */
+ if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is BdCount reasonable? */
+ if (BdCount == 0x00000000U) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Figure out how many bytes will be between the start of adjacent BDs */
+ RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
+
+ /* Must make sure the ring doesn't span address 0x00000000. If it does,
+ * then the next/prev BD traversal macros will fail.
+ */
+ if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Initial ring setup:
+ * - Clear the entire space
+ * - Setup each BD's BDA field with the physical address of the next BD
+ */
+ (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
+
+ BdVirtAddr = VirtAddrLoc;
+ BdPhyAddr = PhysAddr + RingPtr->Separation;
+ for (i = 1U; i < BdCount; i++) {
+ BdVirtAddr += RingPtr->Separation;
+ BdPhyAddr += RingPtr->Separation;
+ }
+
+ /* Setup and initialize pointers and counters */
+ RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
+ RingPtr->BaseBdAddr = VirtAddrLoc;
+ RingPtr->PhysBaseAddr = PhysAddr;
+ RingPtr->HighBdAddr = BdVirtAddr;
+ RingPtr->Length =
+ ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
+ RingPtr->AllCnt = (u32)BdCount;
+ RingPtr->FreeCnt = (u32)BdCount;
+ RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
+ RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
+ RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clone the given BD into every BD in the list.
+ * every field of the source BD is replicated in every BD of the list.
+ *
+ * This function can be called only when all BDs are in the free group such as
+ * they are immediately after initialization with XEmacPs_BdRingCreate().
+ * This prevents modification of BDs while they are in use by hardware or the
+ * user.
+ *
+ * @param RingPtr is the pointer of BD ring instance to be worked on.
+ * @param SrcBdPtr is the source BD template to be cloned into the list. This
+ * BD will be modified.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the list was modified.
+ * - XST_DMA_SG_NO_LIST if a list has not been created.
+ * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
+ * hardware or user control.
+ * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction)
+{
+ u32 i;
+ UINTPTR CurBd;
+
+ /* Can't do this function if there isn't a ring */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't do this function with the channel running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_DEVICE_IS_STARTED);
+ }
+
+ /* Can't do this function with some of the BDs in use */
+ if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Starting from the top of the ring, save BD.Next, overwrite the entire
+ * BD with the template, then restore BD.Next
+ */
+ CurBd = RingPtr->BaseBdAddr;
+ for (i = 0U; i < RingPtr->AllCnt; i++) {
+ memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+ CurBd += RingPtr->Separation;
+ }
+
+ CurBd -= RingPtr->Separation;
+
+ if (Direction == XEMACPS_RECV) {
+ XEmacPs_BdSetRxWrap(CurBd);
+ }
+ else {
+ XEmacPs_BdSetTxWrap(CurBd);
+ }
+
+ return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Reserve locations in the BD list. The set of returned BDs may be modified
+ * in preparation for future DMA transaction(s). Once the BDs are ready to be
+ * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
+ * order which they were allocated here. Example:
+ *
+ *
+ * NumBd = 2,
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ * if (Status != XST_SUCCESS)
+ * {
+ * *Not enough BDs available for the request*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ *
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ * parameter.
+ * - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ * parameter. Doing so will lead to data corruption and system
+ * instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ LONG Status;
+ /* Enough free BDs available for the request? */
+ if (RingPtr->FreeCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead forward */
+ *BdSetPtr = RingPtr->FreeHead;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+ RingPtr->FreeCnt -= NumBd;
+ RingPtr->PreCnt += NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ *
+ * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ * ...
+ * if (Error)
+ * {
+ * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ * }
+ *
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ *
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for modification.
+ *
+ * @return
+ * - XST_SUCCESS if the BDs were unallocated.
+ * - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ * the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ (void) BdSetPtr;
+ Xil_AssertNonvoid(RingPtr != NULL);
+ Xil_AssertNonvoid(BdSetPtr != NULL);
+
+ /* Enough BDs in the free state for the request? */
+ if (RingPtr->PreCnt < NumBd) {
+ Status = (LONG)(XST_FAILURE);
+ } else {
+ /* Set the return argument and move FreeHead backward */
+ XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PreCnt -= NumBd;
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ * - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ * did not have its "last" bit set.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 i;
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+ if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ CurBdPtr = BdSetPtr;
+ for (i = 0U; i < NumBd; i++) {
+ CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+ }
+ /* Adjust ring pointers & counters */
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+ RingPtr->PreCnt -= NumBd;
+ RingPtr->HwTail = CurBdPtr;
+ RingPtr->HwCnt += NumBd;
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ *
+ * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ * if (NumBd == 0)
+ * {
+ * * hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ *
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Sop = 0U;
+ u32 Status;
+ u32 BdLimitLoc = BdLimit;
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ if (BdLimitLoc > RingPtr->HwCnt){
+ BdLimitLoc = RingPtr->HwCnt;
+ }
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has not completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimitLoc) {
+ /* Read the status */
+ if(CurBdPtr != NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+
+ if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+ Sop = 1U;
+ }
+ if (Sop == 0x00000001U) {
+ BdCount++;
+ BdPartialCount++;
+ }
+
+ /* hardware has processed this BD so check the "last" bit.
+ * If it is clear, then there are more BDs for the current
+ * packet. Keep a count of these partial packet BDs.
+ */
+ if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+ Sop = 0U;
+ BdPartialCount = 0U;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ } else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ *
+ * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ * if (NumBd == 0)
+ * {
+ * *hardware has nothing ready for us yet*
+ * }
+ *
+ * CurBd = MyBdSet,
+ * for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ *
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ * for examination.
+ *
+ * @return
+ * The number of BDs processed by hardware. A value of 0 indicates that no
+ * data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr)
+{
+ XEmacPs_Bd *CurBdPtr;
+ u32 BdStr = 0U;
+ u32 BdCount;
+ u32 BdPartialCount;
+ u32 Status;
+
+ CurBdPtr = RingPtr->HwHead;
+ BdCount = 0U;
+ BdPartialCount = 0U;
+
+ /* If no BDs in work group, then there's nothing to search */
+ if (RingPtr->HwCnt == 0x00000000U) {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ } else {
+
+ /* Starting at HwHead, keep moving forward in the list until:
+ * - A BD is encountered with its new/used bit set which means
+ * hardware has completed processing of that BD.
+ * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+ * - The number of requested BDs has been processed
+ */
+ while (BdCount < BdLimit) {
+
+ /* Read the status */
+ if(CurBdPtr!=NULL){
+ BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+ }
+ if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+ break;
+ }
+
+ BdCount++;
+
+ /* hardware has processed this BD so check the "last" bit. If
+ * it is clear, then there are more BDs for the current packet.
+ * Keep a count of these partial packet BDs.
+ */
+ if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+ BdPartialCount = 0U;
+ } else {
+ BdPartialCount++;
+ }
+
+ /* Move on to next BD in work group */
+ CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+ }
+
+ /* Subtract off any partial packet BDs found */
+ BdCount -= BdPartialCount;
+
+ /* If BdCount is non-zero then BDs were found to return. Set return
+ * parameters, update pointers and counters, return success
+ */
+ if (BdCount > 0x00000000U) {
+ *BdSetPtr = RingPtr->HwHead;
+ RingPtr->HwCnt -= BdCount;
+ RingPtr->PostCnt += BdCount;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+ Status = (BdCount);
+ }
+ else {
+ *BdSetPtr = NULL;
+ Status = 0U;
+ }
+}
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr)
+{
+ LONG Status;
+ /* if no bds to process, simply return. */
+ if (0x00000000U == NumBd){
+ Status = (LONG)(XST_SUCCESS);
+ } else {
+ /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+ if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+ Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+ } else {
+ /* Update pointers and counters */
+ RingPtr->FreeCnt += NumBd;
+ RingPtr->PostCnt -= NumBd;
+ XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ * - Is the BD ring linked correctly in physical address space.
+ * - Do the internal pointers point to BDs in the ring.
+ * - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ * which direction.
+ *
+ * @return
+ * - XST_SUCCESS if the set of BDs was freed.
+ * - XST_DMA_SG_NO_LIST if the list has not been created.
+ * - XST_IS_STARTED if the channel is not stopped.
+ * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ * structures. If this value is returned, the channel should be reset to
+ * avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ * call that modifies the BD space. It is the caller's responsibility to
+ * provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+ UINTPTR AddrV, AddrP;
+ u32 i;
+
+ if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+ return (LONG)(XST_INVALID_PARAM);
+ }
+
+ /* Is the list created */
+ if (RingPtr->AllCnt == 0x00000000U) {
+ return (LONG)(XST_DMA_SG_NO_LIST);
+ }
+
+ /* Can't check if channel is running */
+ if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+ return (LONG)(XST_IS_STARTED);
+ }
+
+ /* RunState doesn't make sense */
+ if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal pointers point to correct memory space */
+ AddrV = (UINTPTR) RingPtr->FreeHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PreHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->HwTail;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ AddrV = (UINTPTR) RingPtr->PostHead;
+ if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify internal counters add up */
+ if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+ RingPtr->PostCnt) != RingPtr->AllCnt) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Verify BDs are linked correctly */
+ AddrV = RingPtr->BaseBdAddr;
+ AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+ for (i = 1U; i < RingPtr->AllCnt; i++) {
+ /* Check BDA for this BD. It should point to next physical addr */
+ if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+
+ /* Move on to next BD */
+ AddrV += RingPtr->Separation;
+ AddrP += RingPtr->Separation;
+ }
+
+ /* Last BD should have wrap bit set */
+ if (XEMACPS_SEND == Direction) {
+ if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+ else { /* XEMACPS_RECV */
+ if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+ return (LONG)(XST_DMA_SG_LIST_ERROR);
+ }
+ }
+
+ /* No problems found */
+ return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueRx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueRx = *TempPtr;
+ DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+ *TempPtr = DataValueRx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+ u32 DataValueTx;
+ u32 *TempPtr;
+
+ BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+ TempPtr = (u32 *)BdPtr;
+ if(TempPtr != NULL) {
+ DataValueTx = *TempPtr;
+ DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+ *TempPtr = DataValueTx;
+ }
+}
+
+/*****************************************************************************/
+/**
+ * Reset BD ring head and tail pointers.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param virtaddrloc is the virtual base address of the user memory region.
+ *
+ * @note
+ * Should be called after XEmacPs_Stop()
+ *
+ * @note
+ * C-style signature:
+ * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+ *
+ *****************************************************************************/
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+{
+ RingPtr->FreeHead = virtaddrloc;
+ RingPtr->PreHead = virtaddrloc;
+ RingPtr->HwHead = virtaddrloc;
+ RingPtr->HwTail = virtaddrloc;
+ RingPtr->PostHead = virtaddrloc;
+}
+
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.h
new file mode 100644
index 0000000..ed8ce2a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_bdring.h
@@ -0,0 +1,237 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+* changed to volatile.
+*
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
+#define XEMACPS_BDRING_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+ UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+ UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
+ UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
+ u32 Length; /**< Total size of ring in bytes */
+ u32 RunState; /**< Flag to indicate DMA is started */
+ u32 Separation; /**< Number of bytes between the starting address
+ of adjacent BDs */
+ XEmacPs_Bd *FreeHead;
+ /**< First BD in the free group */
+ XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+ XEmacPs_Bd *HwHead; /**< First BD in the work group */
+ XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+ XEmacPs_Bd *PostHead;
+ /**< First BD in the post-work group */
+ XEmacPs_Bd *BdaRestart;
+ /**< BDA to load when channel is started */
+
+ volatile u32 HwCnt; /**< Number of BDs in work group */
+ u32 PreCnt; /**< Number of BDs in pre-work group */
+ u32 FreeCnt; /**< Number of allocatable BDs in the free group */
+ u32 PostCnt; /**< Number of BDs in post-work group */
+ u32 AllCnt; /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
+ (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+* parameter must be a power of 2 to get an accurate calculation (32, 64,
+* 128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+* given memory constraints.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
+ (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
+ (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
+ (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
+ (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param RingPtr is the DMA channel to operate on.
+* @param BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+* XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
+ (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
+ (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
+ (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+ UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+ u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+ XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+ XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_control.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_control.c
new file mode 100644
index 0000000..38dbabb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_control.c
@@ -0,0 +1,1155 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_8
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy 01/10/10 First release
+ * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
+ * register. Added a new API for setting the BURST length
+ * in DMACR register.
+ * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0 hk 02/20/15 Added support for jumbo frames.
+ * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ *
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device. The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Aptr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Be sure device has been stopped */
+ if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+ Status = (LONG)(XST_DEVICE_IS_STARTED);
+ }
+ else{
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ /* Set the MAC bits [31:0] in BOT */
+ MacAddr = *(Aptr);
+ MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+ MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+ MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ /* There are reserved bits in TOP so don't affect them */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+ MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+ /* Set MAC bits [47:32] in TOP */
+ MacAddr |= (u32)(*(Aptr+4));
+ MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ * which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+ u32 MacAddr;
+ u8 *Aptr = (u8 *)(void *)AddressPtr;
+ u8 IndexLoc = Index;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Aptr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+ /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+ IndexLoc--;
+
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *Aptr = (u8) MacAddr;
+ *(Aptr+1) = (u8) (MacAddr >> 8U);
+ *(Aptr+2) = (u8) (MacAddr >> 16U);
+ *(Aptr+3) = (u8) (MacAddr >> 24U);
+
+ /* Read MAC bits [47:32] in TOP */
+ MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+ *(Aptr+4) = (u8) MacAddr;
+ *(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ *
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ *
+ * 000 : divide pclk by 8 (pclk up to 20 MHz)
+ * 001 : divide pclk by 16 (pclk up to 40 MHz)
+ * 010 : divide pclk by 32 (pclk up to 80 MHz)
+ * 011 : divide pclk by 48 (pclk up to 120 MHz)
+ * 100 : divide pclk by 64 (pclk up to 160 MHz)
+ * 101 : divide pclk by 96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+ u32 Reg;
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET);
+ /* clear these three bits, could be done with mask */
+ Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+ Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+* which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpReadTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpReadTemp = Ipisr;
+ } while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ /* Read data */
+ *PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET);
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY. Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+* PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+* to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+* status from the MAC on a write, the user should read the PHY to verify the
+* write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyData)
+{
+ u32 Mgtcr;
+ volatile u32 Ipisr;
+ u32 IpWriteTemp;
+ LONG Status;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+
+ /* Make sure no other PHY operation is currently in progress */
+ if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET) &
+ XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+ Status = (LONG)(XST_EMAC_MII_BUSY);
+ } else {
+ /* Construct Mgtcr mask for the operation */
+ Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+ (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+ (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+ /* Write Mgtcr and wait for completion */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+ do {
+ Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWSR_OFFSET);
+ IpWriteTemp = Ipisr;
+ } while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+ Status = (LONG)(XST_SUCCESS);
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+ u32 Reg;
+ u32 RegUpdateVal = 0;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+ (BLength == XEMACPS_4BYTE_BURST) ||
+ (BLength == XEMACPS_8BYTE_BURST) ||
+ (BLength == XEMACPS_16BYTE_BURST));
+
+ switch (BLength) {
+ case XEMACPS_SINGLE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+ break;
+
+ case XEMACPS_4BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+ break;
+
+ case XEMACPS_8BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+ break;
+
+ case XEMACPS_16BYTE_BURST:
+ RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+ break;
+ }
+ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+
+ Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+ Reg |= RegUpdateVal;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+ Reg);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_g.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_g.c
new file mode 100644
index 0000000..d7a5a6d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_g.c
@@ -0,0 +1,52 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_ETHERNET_0_DEVICE_ID,
+ XPAR_PS7_ETHERNET_0_BASEADDR,
+ XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.c
new file mode 100644
index 0000000..aa8aa51
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.c
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc 28/06/13 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+* Disable all the interuupts
+* Clear the status registers
+* Disable Rx and Tx engines
+* Update the Tx and Rx descriptor queue registers with reset values
+* Update the other relevant control registers with reset value
+*
+* @param BaseAddr of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+ u32 RegVal;
+
+ /* Disable the interrupts */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+ /* Stop transmission,disable loopback and Stop tx and Rx engines */
+ RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+ RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+ (u32)XEMACPS_NWCTRL_RXEN_MASK|
+ (u32)XEMACPS_NWCTRL_HALTTX_MASK|
+ (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+ /* Clear the statistic registers, flush the packets in DPRAM*/
+ RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+ XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+ /* Clear the interrupt status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+ /* Clear the tx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+ (u32)XEMACPS_TXSR_TXCOMPL_MASK|
+ (u32)XEMACPS_TXSR_TXGO_MASK));
+ /* Clear the rx status */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+ XEMACPS_RXSR_FRAMERX_MASK);
+ /* Clear the tx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+ /* Clear the rx base address */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+ /* Update the network config register with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+ /* Update the hash address registers with reset value */
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+ XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.h
new file mode 100644
index 0000000..4a01aea
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_hw.h
@@ -0,0 +1,653 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_8
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release.
+* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+* to 0x1fff. This fixes the CR#744902.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0 hk 03/18/15 Added support for jumbo frames.
+* Remove "used bit set" from TX error interrupt masks.
+* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 3.8 hk 09/17/18 Fix PTP interrupt masks.
+*
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H /* prevent circular inclusions */
+#define XEMACPS_HW_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
+ supported */
+#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
+ on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
+ options that impose alignment
+ restrictions on the buffer data on
+ the local bus */
+
+/** @name Direction identifiers
+ *
+ * These are used by several functions and callbacks that need
+ * to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND 1U /**< send direction */
+#define XEMACPS_RECV 2U /**< receive direction */
+/*@}*/
+
+/** @name MDC clock division
+ * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+ MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+ bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
+ unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
+ reg */
+#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
+ reg */
+
+#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
+ transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
+ Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
+ Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
+ Counter */
+#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
+ Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
+ Frames Transmitted
+ counter */
+#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
+ Frames Transmitted
+ counter*/
+#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
+ Frames transmitted
+ counter */
+#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
+ 1519 byte Frames
+ transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
+ counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
+ Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
+ Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+ Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
+ Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
+ Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
+ Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
+ Low */
+#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
+ High */
+
+#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
+ Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
+ Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
+ Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
+ Received Counter */
+#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
+ Received Counter */
+#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
+ Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
+ Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
+ Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
+ Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
+ Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
+ Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
+ Counter */
+#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
+ Counter */
+#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
+ Counter */
+#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
+ Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
+ Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
+ Counter */
+#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
+ Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
+ Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
+ Counter */
+#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
+ offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
+ adjustment counter */
+#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
+ increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
+ counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+ nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
+ counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+ nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
+ second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+ nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
+ second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+ nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
+ reg */
+#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
+ reg */
+#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
+ reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
+ reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
+ reg */
+#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
+ reg */
+#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
+ reg */
+#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
+ reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
+ Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+ pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
+ after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
+ stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
+ registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
+ registers */
+#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+ non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
+ FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
+ offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+ Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
+ received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
+ frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+ frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+ frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
+ broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
+ frames */
+#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
+ bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
+ size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
+ size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
+ checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
+ mid frame */
+#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_TXSR_URUN_MASK | \
+ (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+ (u32)XEMACPS_TXSR_RXOVR_MASK | \
+ (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+ (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+ (u32)XEMACPS_RXSR_RXOVR_MASK | \
+ (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+ (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
+#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
+#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
+#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
+
+#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
+#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
+#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
+#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
+
+#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
+ zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
+ no buffers*/
+#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
+ (u32)XEMACPS_IXR_RETRY_MASK | \
+ (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
+ (u32)XEMACPS_IXR_RXUSED_MASK | \
+ (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process. After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
+ matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32 Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note
+* C-style signature:
+* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+ XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param BaseAddress is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note
+* C-style signature:
+* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+* u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+ XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_intr.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_intr.c
new file mode 100644
index 0000000..acb0a50
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_intr.c
@@ -0,0 +1,264 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 First release
+* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
+* Rx errors. Under heavy Rx traffic, there will be a large
+* number of errors related to receive buffer not available.
+* Because of a HW bug (SI #692601), under such heavy errors,
+* the Rx data path can become unresponsive. To reduce the
+* probabilities for hitting this HW bug, the SW writes to
+* bit 18 to flush a packet from Rx DPRAM immediately. The
+* changes for it are done in the function
+* XEmacPs_IntrHandler.
+* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+* and 64-bit changes.
+* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
+* there is no error. CR# 869403
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ * XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ * when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+ void *FuncPointer, void *CallBackRef)
+{
+ LONG Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(FuncPointer != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ switch (HandlerType) {
+ case XEMACPS_HANDLER_DMASEND:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->SendRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_DMARECV:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+ InstancePtr->RecvRef = CallBackRef;
+ break;
+ case XEMACPS_HANDLER_ERROR:
+ Status = (LONG)(XST_SUCCESS);
+ InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+ InstancePtr->ErrorRef = CallBackRef;
+ break;
+ default:
+ Status = (LONG)(XST_INVALID_PARAM);
+ break;
+ }
+ return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+* interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+ u32 RegISR;
+ u32 RegSR;
+ u32 RegCtrl;
+ u32 RegQ1ISR = 0U;
+ XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+ /* This ISR will try to handle as many interrupts as it can in a single
+ * call. However, in most of the places where the user's error handler
+ * is called, this ISR exits because it is expected that the user will
+ * reset the device in nearly all instances.
+ */
+ RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_ISR_OFFSET);
+
+ /* Read Transmit Q1 ISR */
+
+ if (InstancePtr->Version > 2)
+ RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET);
+
+ /* Clear the interrupt status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+ RegISR);
+
+ /* Receive complete interrupt */
+ if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+ /* Clear RX status register RX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET,
+ ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+ (u32)XEMACPS_RXSR_BUFFNA_MASK));
+ InstancePtr->RecvHandler(InstancePtr->RecvRef);
+ }
+
+ /* Transmit Q1 complete interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET,
+ XEMACPS_INTQ1SR_TXCOMPL_MASK);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Transmit complete interrupt */
+ if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+ /* Clear TX status register TX complete indication but preserve
+ * error bits if there is any */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET,
+ ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+ (u32)XEMACPS_TXSR_USEDREAD_MASK));
+ InstancePtr->SendHandler(InstancePtr->SendRef);
+ }
+
+ /* Receive error conditions interrupt */
+ if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+ /* Clear RX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_RXSR_OFFSET, RegSR);
+
+ /* Fix for CR # 692702. Write to bit 18 of net_ctrl
+ * register to flush a packet out of Rx SRAM upon
+ * an error for receive buffer not available. */
+ if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+ RegCtrl =
+ XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, RegCtrl);
+ }
+
+ if(RegSR != 0) {
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+ XEMACPS_RECV, RegSR);
+ }
+ }
+
+ /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+ * will be asserted the same time.
+ * Have to distinguish this bit to handle the real error condition.
+ */
+ /* Transmit Q1 error conditions interrupt */
+ if ((InstancePtr->Version > 2) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+ ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear Interrupt Q1 status register */
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegQ1ISR);
+ }
+
+ /* Transmit error conditions interrupt */
+ if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+ (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+ /* Clear TX status register */
+ RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET);
+ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+ XEMACPS_TXSR_OFFSET, RegSR);
+ InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+ RegSR);
+ }
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_sinit.c
new file mode 100644
index 0000000..123e6e5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/emacps_v3_8/src/xemacps_sinit.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_8
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy 01/10/10 New
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+ XEmacPs_Config *CfgPtr = NULL;
+ u32 i;
+
+ for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+ if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+ CfgPtr = &XEmacPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/Makefile
new file mode 100644
index 0000000..8601ce4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+ ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+ echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+ ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+ rm -rf ${OBJECTS}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.c
new file mode 100644
index 0000000..c781335
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.c
@@ -0,0 +1,626 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device. The interrupts are disabled
+* for output pins on all banks during initialization.
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1 aru 07/13/18 Resolved doxygen reported warnings. CR# 1006331.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param ConfigPtr points to the XGpioPs device configuration structure.
+* @param EffectiveAddr is the device base address in the virtual memory
+* address space. If the address translation is not used then the
+* physical address should be passed.
+* Unexpected errors may occur if the address mapping is changed
+* after this function is invoked.
+*
+* @return XST_SUCCESS always.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr)
+{
+ s32 Status = XST_SUCCESS;
+ u8 i;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+ Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+ /*
+ * Set some default values for instance data, don't indicate the device
+ * is ready to use until everything has been initialized successfully.
+ */
+ InstancePtr->IsReady = 0U;
+ InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+ InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+ InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
+ InstancePtr->Platform = XGetPlatform_Info();
+
+ /* Initialize the Bank data based on platform */
+ if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * Max pins in the ZynqMP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+ InstancePtr->MaxPinNum = (u32)174;
+ InstancePtr->MaxBanks = (u8)6;
+ } else {
+ /*
+ * Max pins in the GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+ InstancePtr->MaxPinNum = (u32)118;
+ InstancePtr->MaxBanks = (u8)4;
+ }
+
+ /*
+ * By default, interrupts are not masked in GPIO. Disable
+ * interrupts for all pins in all the 4 banks.
+ */
+ for (i=0;iMaxBanks;i++) {
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+ }
+
+ /* Indicate the component is now ready to use. */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Current value of the Data register.
+*
+* @note This function is used for reading the state of all the GPIO pins
+* of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the data has to be read.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return Current value of the Pin (0 or 1).
+*
+* @note This function is used for reading the state of the specified
+* GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Data is the value to be written to the Data register.
+*
+* @return None.
+*
+* @note This function is used for writing to all the GPIO pins of
+* the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Data is the data to be written to the specified pin (0 or 1).
+*
+* @return None.
+*
+* @note This function does a masked write to the specified pin of
+* the specified GPIO bank. The previous state of other pins
+* is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+ u32 RegOffset;
+ u32 Value;
+ u8 Bank;
+ u8 PinNumber;
+ u32 DataVar = Data;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ if (PinNumber > 15U) {
+ /* There are only 16 data bits in bit maskable register. */
+ PinNumber -= (u8)16;
+ RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+ } else {
+ RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+ }
+
+ /*
+ * Get the 32 bit value to be written to the Mask/Data register where
+ * the upper 16 bits is the mask and lower 16 bits is the data.
+ */
+ DataVar &= (u32)0x01;
+ Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+ RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Direction is the 32 bit mask of the Pin direction to be set for
+* all the pins in the Bank. Bits with 0 are set to Input mode,
+* bits with 1 are set to Output Mode.
+*
+* @return None.
+*
+* @note This function is used for setting the direction of all the pins
+* in the specified bank. The previous state of the pins is
+* not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param Direction is the direction to be set for the specified pin.
+* Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 DirModeReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(Direction <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+
+ if (Direction!=(u32)0) { /* Output Direction */
+ DirModeReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Input Direction */
+ DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Returns a 32 bit mask of the Direction register. Bits with 0 are
+* in Input mode, bits with 1 are in Output Mode.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Direction is to be
+* retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Direction of the specified pin.
+* - 0 for Input Direction
+* - 1 for Output Direction
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param OpEnable is the 32 bit mask of the Output Enables to be set for
+* all the pins in the Bank. The Output Enable of bits with 0 are
+* disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return None.
+*
+* @note This function is used for setting the Output Enables of all the
+* pins in the specified bank. The previous state of the Output
+* Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number to which the Data is to be written.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param OpEnable specifies whether the Output Enable for the specified
+* pin should be enabled.
+* Valid values are 0 for Disabling Output Enable,
+* 1 for Enabling Output Enable.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 OpEnableReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(OpEnable <= (u32)1);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+
+ if (OpEnable != (u32)0) { /* Enable Output Enable */
+ OpEnableReg |= ((u32)1 << (u32)PinNumber);
+ } else { /* Disable Output Enable */
+ OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Returns a a 32 bit mask of the Output Enable register.
+* Bits with 0 are in Disabled state, bits with 1 are in
+* Enabled State.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the Output Enable status is to
+* be retrieved.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return Output Enable of the specified pin.
+* - 0 if Output Enable is disabled for this pin
+* - 1 if Output Enable is enabled for this pin
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param PinNumber is the Pin number in the GPIO device.
+* @param BankNumber returns the Bank in which this GPIO pin is present.
+* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+ u32 XGpioPsPinTable[6] = {0};
+ u32 Platform = XGetPlatform_Info();
+
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /*
+ * This structure defines the mapping of the pin numbers to the banks when
+ * the driver APIs are used for working on the individual pins.
+ */
+
+ XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+ XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+ XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+ XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+ XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+ XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < 6U) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ } else {
+ XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+ XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+ XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+ XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+ *BankNumber = 0U;
+ while (*BankNumber < 4U) {
+ if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+ break;
+ }
+ (*BankNumber)++;
+ }
+ }
+ if (*BankNumber == (u8)0) {
+ *PinNumberInBank = PinNumber;
+ } else {
+ *PinNumberInBank = (u8)((u32)PinNumber %
+ (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+ }
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.h
new file mode 100644
index 0000000..3ab40b9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops.h
@@ -0,0 +1,274 @@
+
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_4
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+* - 4 banks
+* - Masked writes (There are no masked reads)
+* - Bypass mode
+* - Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+* relevant to Zynq device.The interrupts are disabled
+* for output pins on all banks during initialization.
+* 1.02a hk 08/22/13 Added low level reset API
+* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to APIs. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* ms 03/17/17 Added readme.txt file in examples folder for doxygen
+* generation.
+* ms 04/05/17 Added tabspace for return statements in functions of
+* gpiops examples for proper documentation while
+* generating doxygen.
+* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
+* for zcu102 and zc702 boards in polled and interrupt
+* example, configured Interrupt pin to input pin for
+* proper functioning of interrupt example.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_H /* prevent circular inclusions */
+#define XGPIOPS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ * @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
+ * Zynq Ultrascale+ MP GPIO device
+ */
+#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
+ * Zynq Ultrascale+ MP GPIO device
+ * 0 - 25, Bank 0
+ * 26 - 51, Bank 1
+ * 52 - 77, Bank 2
+ * 78 - 109, Bank 3
+ * 110 - 141, Bank 4
+ * 142 - 173, Bank 5
+ */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
+ * 0 - 31, Bank 0
+ * 32 - 53, Bank 1
+ * 54 - 85, Bank 2
+ * 86 - 117, Bank 3
+ */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ * when setting the callback functions for a GPIO bank. It is
+ * passed back to the upper layer when the callback is invoked. Its
+ * type is not important to the driver component, so it is a void
+ * pointer.
+ * @param Bank is the bank for which the interrupt status has changed.
+ * @param Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+ XGpioPs_Config GpioConfig; /**< Device configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ XGpioPs_Handler Handler; /**< Status handlers for all banks */
+ void *CallBackRef; /**< Callback ref for bank handlers */
+ u32 Platform; /**< Platform data */
+ u32 MaxPinNum; /**< Max pins in the GPIO device */
+ u8 MaxBanks; /**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+ u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_g.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_g.c
new file mode 100644
index 0000000..c4e9e85
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_g.c
@@ -0,0 +1,51 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2018.3
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2023 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+ {
+ XPAR_PS7_GPIO_0_DEVICE_ID,
+ XPAR_PS7_GPIO_0_BASEADDR
+ }
+};
+
+
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.c
new file mode 100644
index 0000000..6c53b8d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains low level GPIO functions.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk 08/22/13 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param Base address of GPIO module
+*
+* @return None
+*
+* @note None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+ u32 BankCount;
+ u32 Platform,MaxBanks;
+
+ Platform = XGetPlatform_Info();
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ MaxBanks = (u32)6;
+ } else {
+ MaxBanks = (u32)4;
+ }
+ /* Write reset values to all mask data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+ XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+ }
+ /* Write reset values to all output data registers */
+ for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+ XGPIOPS_DATA_OFFSET), 0x0U);
+ }
+
+ /* Reset all registers of all GPIO banks */
+ for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_DIRM_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_OUTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET), 0x0U);
+ XGpioPs_WriteReg(BaseAddress,
+ ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET), 0x0U);
+ }
+
+ /* Bank 0 Int type */
+ XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+ XGPIOPS_INTTYPE_BANK0_RESET);
+ /* Bank 1 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK1_RESET);
+ /* Bank 2 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK2_RESET);
+ /* Bank 3 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK3_RESET);
+
+ if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+ /* Bank 4 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK4_RESET);
+ /* Bank 5 Int type */
+ XGpioPs_WriteReg(BaseAddress,
+ (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+ XGPIOPS_INTTYPE_BANK5_RESET);
+ }
+
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.h
new file mode 100644
index 0000000..59ec921
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_hw.h
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 1.02a hk 08/22/13 Added low level reset API function prototype and
+* related constant definitions
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Corrected reset values of banks.
+*
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
+#define XGPIOPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ * @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ * @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ * @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the register offset to be read.
+*
+* @return The 32-bit value of the register
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param BaseAddr is the base address of the device.
+* @param RegOffset is the offset of the register to be written.
+* @param Data is the 32-bit value to write to the register.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_intr.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_intr.c
new file mode 100644
index 0000000..1bcc84b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_intr.c
@@ -0,0 +1,730 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
+* passed to API's. CR# 822636
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1 aru 07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
+* 3.4 aru 08/09/18 Ressolved cppcheck warnings.
+* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are to
+* be enabled. Bit positions of 1 will be enabled. Bit positions
+* of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be enabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the bit mask of the pins for which interrupts are
+* to be disabled. Bit positions of 1 will be disabled. Bit
+* positions of 0 will keep the previous setting.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt is to be disabled.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = ((u32)1 << (u32)PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+* indicate that the interrupt for that pin is enabled, bit
+* positions with 0 indicate that the interrupt for that pin is
+* disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+ u32 IntrMask;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+ return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt is enabled.
+* - FALSE if the interrupt is disabled.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTMASK_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return The value read from Interrupt Status Register.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+ return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt enable status
+* is to be known.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+* - TRUE if the interrupt has occurred.
+* - FALSE if the interrupt has not occurred.
+*
+* @note None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param Mask is the mask of the interrupts to be cleared. Bit positions
+* of 1 will be cleared. Bit positions of 0 will not change the
+* previous interrupt status.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ /* Clear the currently pending interrupts. */
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param Pin is the pin number for which the interrupt status is to be
+* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u8 Bank;
+ u8 PinNumber;
+ u32 IntrReg;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ /* Clear the specified pending interrupts. */
+ IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET);
+
+ IntrReg &= ((u32)1 << PinNumber);
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType is the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
+* 0 means Active Low or Falling Edge and 1 means Active High or
+* Rising Edge.
+* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note This function is used for setting the interrupt related
+* properties of all the pins in the specified bank. The previous
+* state of the pins is not maintained.
+* To change the Interrupt properties of a single GPIO pin, use the
+* function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+ u32 IntrPolarity, u32 IntrOnAny)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Bank is the bank number of the GPIO to operate on.
+* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param IntrType returns the 32 bit mask of the interrupt type.
+* 0 means Level Sensitive and 1 means Edge Sensitive.
+* @param IntrPolarity returns the 32 bit mask of the interrupt
+* polarity. 0 means Active Low or Falling Edge and 1 means
+* Active High or Rising Edge.
+* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
+* edge triggered interrupts. 0 means trigger on single edge using
+* the configured interrupt polarity and 1 means trigger on both
+* edges.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+ u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+ *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be set.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+* defined in xgpiops.h to specify the IRQ type.
+*
+* @return None.
+*
+* @note None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+ u32 IntrTypeReg;
+ u32 IntrPolReg;
+ u32 IntrOnAnyReg;
+ u8 Bank;
+ u8 PinNumber;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+ Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET);
+
+ IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET);
+
+ IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET);
+
+ switch (IrqType) {
+ case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+ IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+ IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg |= ((u32)1 << (u32)PinNumber);
+ break;
+ case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+ IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+ IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+ break;
+ default:
+ /**< Default statement is added for MISRA C compliance. */
+ break;
+ }
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+ XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param InstancePtr is a pointer to an XGpioPs instance.
+* @param Pin is the pin number whose IRQ type is to be obtained.
+* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return None.
+*
+* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+* returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+ u32 IntrType;
+ u32 IntrPol;
+ u32 IntrOnAny;
+ u8 Bank;
+ u8 PinNumber;
+ u8 IrqType;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+ /* Get the Bank number and Pin number within the bank. */
+ XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+ IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrType == ((u32)1 << PinNumber)) {
+
+ IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+ if (IntrOnAny == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+ } else if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+ }
+ } else {
+
+ IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+ ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+ XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+ if (IntrPol == ((u32)1 << PinNumber)) {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+ } else {
+ IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+ }
+ }
+
+ return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+* @param CallBackRef is the upper layer callback reference passed back
+* when the callback function is invoked.
+* @param FuncPointer is the pointer to the callback function.
+*
+*
+* @return None.
+*
+* @note The handler is called within interrupt context, so it should do
+* its work quickly and queue potentially time-consuming work to a
+* task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+ XGpioPs_Handler FuncPointer)
+{
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(FuncPointer != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->Handler = (XGpioPs_Handler)FuncPointer;
+ InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return None.
+*
+* @note This function does not save and restore the processor context
+* such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+ u8 Bank;
+ u32 IntrStatus;
+ u32 IntrEnabled;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+ IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+ if (IntrStatus != (u32)0) {
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+ Bank);
+ XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+ (IntrStatus & IntrEnabled));
+ InstancePtr->Handler(InstancePtr->
+ CallBackRef, Bank,
+ (IntrStatus & IntrEnabled));
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param Bank is the GPIO Bank in which an interrupt occurred.
+* @param Status is the Interrupt status of the GPIO bank.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+ (void) CallBackRef;
+ (void) Bank;
+ (void) Status;
+
+ Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_selftest.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_selftest.c
new file mode 100644
index 0000000..0fe83aa
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_selftest.c
@@ -0,0 +1,129 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/18/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+* - XST_SUCCESS if the self-test passed.
+* - XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+ s32 Status = XST_SUCCESS;
+ u32 IntrEnabled;
+ u32 CurrentIntrType = 0U;
+ u32 CurrentIntrPolarity = 0U;
+ u32 CurrentIntrOnAny = 0U;
+ u32 IntrType = 0U;
+ u32 IntrPolarity = 0U;
+ u32 IntrOnAny = 0U;
+ u32 IntrTestValue = 0x22U;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /* Disable the Interrupts for Bank 0 . */
+ IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+ XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ /*
+ * Get the Current Interrupt properties for Bank 0.
+ * Set them to a known value, read it back and compare.
+ */
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+ &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+ IntrTestValue, IntrTestValue);
+
+ XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+ &IntrPolarity, &IntrOnAny);
+
+ if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+ (IntrOnAny != IntrTestValue)) {
+
+ Status = XST_FAILURE;
+ }
+
+ /*
+ * Restore the contents of all the interrupt registers modified in this
+ * test.
+ */
+ XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+ CurrentIntrPolarity, CurrentIntrOnAny);
+
+ XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+ return Status;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_sinit.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_sinit.c
new file mode 100644
index 0000000..5cd560a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_4/src/xgpiops_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_4
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note None.
+*
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv 01/15/10 First Release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+ XGpioPs_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+ if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XGpioPs_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/ChangeLog b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/ChangeLog
new file mode 100644
index 0000000..b51ce7a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/ChangeLog
@@ -0,0 +1,474 @@
+Change Log for lwip
+=================================
+2020-01-08
+ * Remove references to deprecated Xilkernel.
+2020-10-09
+ * Fix the optimization out of delay code with level O2 by
+ replacing the for loop with sleep for 1 second.
+2020-10-04
+ * Modify the sys_now function to return milliseconds instead
+ of ticks to fix lwip timers issue.
+2020-09-24
+ * Use Xil_In32 and Xil_Out32 functions to read/write
+ registers.
+2020-09-22
+ * Fix lwip application failure on VCU118 board.
+2020-08-18
+ * Add axiethernet support on versal.
+2020-08-14
+ * Fix RX pbuf freeing in GEM error handling path.
+2020-06-22
+ * Fix the Zynq base address check to use internal definition
+ instead of canonical definition.
+2020-05-08
+ * Fix the RX BD setup order to avoid clearing used bit without
+ buffer address.
+2019-08-24
+ * Add support for clock config in EL1 Non secure for Versal.
+2019-08-12
+ * Add support for clock setup for Versal.
+2019-07-30
+ * Add support for A53 32 bit compiler.
+2019-07-11
+ * Fix emacps hotplug bug.
+2019-05-17
+ * Add support for Versal
+2019-04-10
+ * Fix typos.
+2019-03-12
+ * Fix BYTE_ORDER redefined warnings in lwip arch/cpu.h.
+ * Fix warnings in emaclite adapter source.
+ * Fix xemacliteif_input() for freertos multi-packet scenario.
+2019-02-09
+ * PL Ethernet requires 8 byte padding when IEEE1588 is enabled;
+ Migrate this change from lwip202 to lwip211.
+2019-02-05
+ * Pick correct compiler for R5
+2019-01-21
+ * Fix freertos echo server compilation on emaclite platform.
+2019-01-11
+ * Upgrage to lwip211
+ * Fix cache handling in RX path for GEM
+2018-10-01
+ * Fix warning for redefining BYTE_ORDER
+2018-09-19
+ * In lwip tcl to support hierarchical designs pass -hier option to
+ get_cells command.
+2018-08-24
+ * Modify update_axi_ethernet_topology func(lwip202.tcl) to derive
+ interrupt source order programmatically. It fixes build error
+ due to change in HSI get_connected_intr_cntrl API output.
+2018-03-30
+ * Add AXI 2.5G Ethernet support
+2018-03-29
+ * Add mcdma support and handle IEEE_1588 for SGMII Phy in ethernet
+ * header
+2018-03-05
+ * Add Hot plug detect support for EmacPS and AXI Ethernet
+2018-03-14
+ * Avoid axi ethernet config initialize in two places.
+2018-01-19
+ * Add support for Realtek RTL8211 phy.
+2018-01-11
+ * Use UINTPTR for axidma baseaddr.
+2018-01-10
+ * Update xInsideISR flag in emacps_error_handler.
+2017-12-06
+ * Fix jumbo frame checks to work on R5
+2017-11-01
+ * Perform AXI DMA lookup based on base address.
+2017-10-27
+ * Correct proper references of TX BD ring in init_dma() and
+ emacps_error_handler().
+2017-10-04
+ * Include options to configure mbox in lwip202.mld and lwip202.tcl
+2017-10-13
+ * Add multicast MAC update for IPv6 in xemacpsif.c and xaxiemacif.c
+ * Add IPv6 source in lwip.makefile
+2017-09-20
+ * Disable L1 prefetch for ARMv8 in init_axi_dma function in xaxiemacif_dma.c.
+2017-09-12
+ * Disable L1 prefetch for ARMv8 in init_dma function in xemacpsif_dma.c.
+2017-09-09
+ * Add rx_reset_nodata workaround for Zynq GEM for freertos.
+2017-08-29
+ * Add support of IGMP in emacps
+2017-08-17
+ * Upgrade to LWIP2.0.2 version.
+ * Removed PPC References
+2017-08-14
+ * Don't perform data cache related operations when CCI is
+ enabled.
+2017-08-11
+ * Fix for conflicting types for xInsideISR. Fixes CR-981909.
+ * Fix for warnings in lwip141 axiethernet adapter.
+2017-08-03
+ * Correct compiler used for A9.
+2017-07-18
+ * Add freertos support for axiethernet fifo configuration.
+ * SW workaround for TI DP83867 PHY Data integrity issues on KCU116/VCU118 Boards.
+2017-06-14
+ * Add support for EL1 non secure mode.
+2017-03-07
+ * SW workaround for unstable link with TI DP83867 PHY
+ when RX CTRL is not strapped to MODE 3 or 4.
+2017-02-13
+ * Correct TI PHYCR register initialization
+2017-02-03
+ * Add jumbo frame support for ZynqMP ethernet
+2016-12-19
+ * Export options for user to change NO_SYS_NO_TIMERS and
+ LWIP_TCP_KEEP_ALIVE.
+2016-12-07
+ * Add Support for TI PHY DP83867 SGMII Mode configuration.
+2016-11-22
+ * Add support in xemaps_physpeed.c for newer version of Xilinx
+ PCS PMA core with phy address scanning.
+2016-11-09
+ * Fix compilation errors for microblaze based designs CR#963580
+ * dsb() is not available for Microblaze added checks for the same
+ * in the xaxiemacif_dma.c file.
+2016-11-06
+ * Axi Ethernet Lwip Performance issue on ZynqMP Fix for CR#953533
+ * The uncached memory needed for BDs were not aligned properly to meet
+ * AR3/R5 MMU requirements. The performance was low because of that anomaly.
+ * Fixed the issue by properly aligning the memory allocated for BDs.
+ * (Changes are made in the xaxiemacif_dma.c file).
+2016-08-30
+ * Add support for freertos in the emaclite adapter. Fix for CR#957572.
+2016-08-17
+ * Update divisors in CRL_APB (for ZynqMP) based on speed negotiated.
+2016-07-29
+ * Don't set clk dividers in Zynq SLCR when EMIO clock source is used.
+2016-07-11
+ * Change Zynq BD space attributes to device memory.
+2016-04-07
+ * Correct return handling in xemacps phy negotiation.
+2016-02-11
+ * Add Support for Axi Etherent on ZyqnMP.
+ * Update lwip.tcl to export proper gic baseadress for r5
+ to fix issues with AxiEthernet on ZynqMP R5.
+ * Fix compilation errors for Axi Ethernet on ZynqMP.
+2016-01-14
+ * Created a new version lwip141_v1_4
+ * Made changes for lwip to work with A53 with caches enabled.
+ * Corrected last tx and rx bd updation for corner scenarios.
+ * Make Zynq BD space normal non-cacheable instead of strongly ordered.
+ * Correct condition to select SLCR offset for emacps clk cfg(CR#930997).
+2015-10-12
+ * Created a new version lwip141_v1_3.
+ * Made changes in xemacpsif_dma.c to add required barriers.
+ * Remove repeated sysarch protect and unprotect calls.
+ * Replace printf with xil_printf.
+ * Add support for TI phy.
+2015-09-09
+ * Fix compilation issues with the non hier axi eth design
+2015-09-04
+ * Update makefile to allow incremental build.
+ * Add support for latest freertos (freertos821_xilinx)
+2015-08-19
+ * Fix bsp compilation errors when elite is configured
+ with interrupts though a concat IP (CR#875527)
+2015-08-18
+ * Error out for A53 32 bit compiler
+2015-08-10
+ * Add support for A53
+2015-07-19
+ * Add support for Zynq Ultrascale MPSoC emacps
+2015-07-15
+ * Add Support for Axi ethernet with fifo on zynq.
+2015-06-15
+ * Update the lwip tcl for Hier IP(To support User parameters).
+2015-05-15
+ * Don't inline the functions with the Toolchain. Fix RGMII Ethernet
+ Not working on Artix devices (CR#861391).
+2015-03-12
+ * Fix compilation Errors during generation of LWIP Echo server
+ application (CR#853861).
+2015-02-09
+ * Removed support for lltemac.
+ * Made changes in axiethernet adapter files as part of general
+ cleanup.
+ * Added support for 2 GigEs for GEM.
+ * Added support for non-Marvell PHY reporting.
+ * Made changes for axiethernet checksum validation logic that resulted
+ in performance improvement.
+2015-01-23
+ * Added support for the lwip141 stack.
+ * Created a New version of lwip141_v1_0.
+2014-9-12
+ * Created a new version lwip140_v2_4.
+ * It has CR fixes for 827638, 830976, 828866.
+2014-12-11
+ * Fixed the bug in the emaclite on zynq. Added the parameter
+ use_emaclite_on_zynq to the mld file.
+2014-11-11
+ * Fix for CR 835081 - lwip adapter for AxiEthernet does not
+ work for SGMII mode.
+2014-29-10
+ * Fix for CR 827686 - Gem connected 1000BASE-X in PL
+ getting "PHY not connected" error.
+ * Fix for CR 828796 - 2014.3 - AXI Ethernet - 1000BASEX interface not
+ working with echo server design on Zynq.
+ * Fix for CR 823736 - Fix typo error in xmaecliteif.c file.
+2014-13-06
+ * Fix for CR 802558 - LWIP library doesn't compile
+ with XilKernel/FreeRTOS BSP.
+ * Fix for CR 801076 - Few configurable options of
+ library are not propagated during compilation.
+2014-06-06
+ * Fix for CR 800240 - Removed the limitation of
+ supporting only Marvel PHY in AXI Ethernet adapter.
+2014-1-30
+ * Fix for CRs 771112 and 766087. The sys_arch.c
+ last made (related to freertos) are reverted back.
+2013-12-1
+ * A new version of lwip (v2_0) is created with tcl
+ changes related to HSM and new versioing scheme.
+2013-11-08
+ * Fix for CR#759896.
+2013-11-02
+ * Made changes in the file
+ src/contrib/ports/xilinx/sys_arch.c to fix issues
+ in the freertos port.
+2013-10-24
+ * New version of lwip140(1_07_a) created. Support
+ for emaclite on zynq is added by making changes in the
+ files:
+ data/lwip140_v2_1_0.mld
+ data/lwip140_v2_1_0.tcl
+ src/contrib/ports/xilinx/netif/xemacliteif.c
+ * Support for gmii to sgmii converter PHY is added by
+ making changes in the file:
+ src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c
+2013-09-07
+ * Fix for CR# 735656. Modified
+ src/contrib/ports/xilinx/include/arch/cc.h
+ to add a hash define for LWIP_RAND
+2013-08-06
+ * New version of lwIP library (lwip140_v1_06a) is
+ created.
+ * Added support for AC701 board PHY and added
+ AxiEthernetUtilPhyDelay() API (CR 725551).
+ Files changed:
+ src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c
+ * Fixed CR 727441 - AXI Ethernet design on Zynq with
+ checksum configuration parameters disabled will fail
+ to work.
+ Files changed:
+ data/lwip140_v2_1_0.tcl
+
+2013-05-06
+ * Added new parameter 'ip_reass_max_pbufs' to IP options of
+ lwIP settings and removed unused parameter 'ip_reass_bufsize'.
+ Files Changed:
+ data/lwip140_v2_1_0.mld
+ data/lwip140_v2_1_0.tcl
+ * Increased PBUF Queue Size to fix TSR #715250 - "UDP RX mode is
+ not working for 64K datagram packets".
+ Files Changed:
+ src/contrib/ports/xilinx/netif/xpqueue.c
+ src/contrib/ports/xilinx/include/netif/xpqueue.h
+
+2013-05-01
+ * Modified the handling of fragmented packets in the
+ Zynq lwIP adapter (src/contrib/ports/xilinx/netif/xemacpsif_dma.c).
+ This is done to fix the CR 716040. The Used bit of the 1st BD
+ in the BD chain allocated for the packet fragments is cleared
+ at the end after clearing out the Used bits of all other BDs in
+ the chain.
+2013-04-26
+ * Modified parameter *_SGMII_PHYADDR to *_PHYADDR, the
+ config parameter C_PHYADDR applies to SGMII/1000BaseX
+ modes of operation (CR 704195).
+
+2013-04-19
+ * Created a new version of lwip140 (v1_05_a). The changes
+ are made in src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c
+ to add support for the gmii2rgmii converter core.
+2013-02-18
+ * Added support for AXI Ethernet on Zynq. Changes
+ done in lwip140_v2_1_0.mld, lwip140_v2_1_0.tcl for
+ this support
+ Changed the AXI-Ethernet adapter files:
+ src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c,
+ src/contrib/ports/xilinx/netif/xaxiemacif.c,
+ src/contrib/ports/xilinx/netif/xaxiemacif_dma.c,
+ src/contrib/ports/xilinx/netif/xaxiemacif_hw.c
+ * A new configuration parameter 'use_axieth_on_zynq'
+ is added to lwIP software library. This parameter
+ should be selected if the AXI Ethernet adapter is
+ being used for lwIP on Zynq.
+
+2013-01-24
+ * Added SW workaround support for the SI #692601.
+ Description for the SI:
+ Under heavy Rx traffic, there will be a large
+ number of errors related to receive buffer not available
+ and the Rx data path can become unresponsive. To reduce the
+ probabilities for hitting this Silicon Issue, the SW writes
+ to bit 18 to flush a packet from Rx DPRAM immediately.
+
+2013-01-21
+ * Created a new version of lwIP (v1_04_a).
+ * Changed the Emac adapter file:
+ src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c,
+ Added support for SGMII mode (CR:676793);
+
+2012-08-17
+ * Created a new version of lwIP (v1_03_a).
+ * Changed data/lwip140_v2_1_0.tcl to fix UDP isses in FreeRTOS and
+ fix compilation issues when Emac1 is used (instead of Emac0).
+ * Changed the EmacPs adapter files:
+ src/contrib/ports/xilinx/netif/xemacpsif_dma.c,
+ src/contrib/ports/xilinx/netif/xemacpsif_hw.c,
+ src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c,
+ src/contrib/ports/xilinx/netif/xemacpsif.c
+ src/contrib/ports/xilinx/include/netif/xemacpsif.h
+ to do code cleanups, modify the BD handling on Rx path for error cases,
+ modify error handling.
+ Added fast interrupt support for microblaze/axiethernet. Made
+ changes in xaxiemacif_dma.c for this.
+ Made changes to src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c
+ to simplify the handling of SLCR register update for Emac0 and Emac1.
+ Made changes in tcl amd mld file to add a new configuration entry
+ for Zynq to specify the Emac Interface number. If only one
+ interface is present, then this entry will have no effect. But
+ if both the interfaces are present in the hardware, then depending
+ on this configuration entry a particular Emac will be chosen.
+ lwIP does not support use of both the interfaces simultaneously.
+
+2012-07-06
+ * Made changes in src/contrib/ports/xilinx/netif/xaxiemacif_dma.c
+ to make changes in some of AxiDMA API calls which are changed in
+ the latest version of AxiDma driver.
+
+2012-06-04
+ * Added support for freertos. Changes are done in lwip140_v2_1_0.mld,
+ lwip140_v2_1_0.tcl, sys_arch.h, xadapter.h, xadapter.c, xemacpsif.c,
+ xemacpsif_dma.c, xemacpsif_hw.c, sys_arch.c.
+ * Modified error handling for EmacPs errors. Changes are done in
+ xemacpsif.c, xemacpsif_dma.c, xemacpsif_hw.c.
+
+2012-04-15
+ * In function init_dma in file xemacpsif_dma.c, the calls to
+ Xil_DisableMMU and Xil_EnableMMU are removed. Now for changing
+ attributes in the translation table, the only function called is
+ Xil_SetTlbAttributes.
+
+2012-03-12
+ * In file xaxiemacif_dma.c, the function alloc_bdspace is updated
+ so that the assert calls are under #if DEBUG statement. This is
+ done to remove compilation issues with the new microblaze
+ toolchain.
+ Similar changes are done in xlltemacif_dma.c.
+
+2012-03-12
+ * In file xemacliteif.c the function xemacif_recv_handler is
+ updated to free the pbufs upon error conditions (before returning
+ back from the function).
+
+2012-03-03
+ * The SLCR divisor settings for GEM Tx clock for Zynq is now used
+ from xparameters.h. Corresponding changes are made in
+ src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c.
+ * Changes are made in src/contrib/ports/xilinx/sys_arch_raw.c for
+ functions sys_arch_protect and sys_arch_unprotect. Earlier for
+ Zynq/PEEP cases for sys_arch_protect we used to disable only the
+ Emac interrupt and enable back it in sys_arch_unprotect. Now
+ for Zynq all interrupts are disabled in CPSR (sys_arch_protect)
+ and enabled back in sys_arch_unprotect.
+ * Changes are made in src/contrib/ports/xilinx/netif/xemacpsif_dma.c
+ for proper interrupt disabling and enabling for Tx. Also some
+ optimizations are done to improve performance numbers.
+
+2012-01-25
+ * Following changes are made in file
+ src/contrib/ports/xilinx/netif/xemacpsif_dma.c :
+ Changes are made for Zynq/PEEP adapter so that the BDs are allocated
+ at fixed addresses 0xFF00000 (for Rx Bds) and 0xFF10000 (for Tx Bds).
+ The address range of 1 MB starting at 0xFF00000 is made uncached by
+ setting attributes in the MMU table (in function init_dma).
+ * Changes are made in
+ src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c to have separate
+ PHY initializations for PEEP and Zynq boards.
+ * Changes are made in src/contrib/ports/xilinx/sys_arch_raw.c. In
+ function sys_arch_protect the EmacIntr is disabled instead of disabling
+ the IRQ in CPSR. This change needs to be revisited later and a better
+ solution needs to be adapted. Similar changes are done in
+ sys_arch_unprotect.
+ * DMA/GEM Error handling is added/changed for Zynq/PEEP. Hence changes
+ are made in src/contrib/ports/xilinx/netif/xemacpsif.c and
+ src/contrib/ports/xilinx/netif/xemacpsif_hw.c.
+ * The MDIO divisor is set as 224 in file
+ src/contrib/ports/xilinx/netif/xemacpsif_hw.c.
+2011-11-18
+ * Upgraded the to lwip140. Because of it there are lots of changes
+ throughout the lwip files.
+ * There was an existing bug because of which txperf used to hang
+ after a few minutes. It is fixed in src/lwip-1.4.0/src/core/tcp_out.c.
+ After entering into the function tcp_output, we disable interrupts
+ and just before existing the function, we enable back the interrupts.
+ This is done for microblaze and ppc platforms.
+ * For lwip140 the semaphore, mutex, mailbox and pthread interfaces
+ have changed. Corresponding changes are done in file sys_arch.c.
+ * The functions SYS_ARCH_PROTECT and SYS_ARCH_UNPROTECT are now
+ made as macros for better performance.
+ * The file src/include/lwip/def.h is changed so that for endian
+ swapping only macros are used instead of functions. This is done
+ to have better performance.
+ * Support for Zynq is added.
+2011-08-29
+ * src/makefile: Made changes not to echo files being compiled.
+ * src/contrib/ports/xilinx/include/netif/xaxiemacif.h: Added function
+ prototypes for PHY configuration.
+ * src/contrib/ports/xilinx/include/netif/xlltemacif.h: Added function
+ prototypes for PHY configuration.
+ * src/contrib/ports/xilinx/netif/xadapter.c: Made changes in function
+ xemacif_input to remove compilation warnings. The exact change is,
+ replacing "return;" statements with "return 0;".
+ * src/contrib/ports/xilinx/netif/xaxiemacif_dma.c: Removed the unused
+ variable "csum_in_packet" in the function "is_checksum_valid".
+ * src/contrib/ports/xilinx/netif/xaxiemacif_hw.c: Removed unused variables
+ "rdy" and "lock_message_printed" in function "init_axiemac".
+ The PHY configuration related code is removed from the function
+ "init_axiemac", since it is now being done in a separate function.
+ * src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c: The unused function
+ "get_marvel_phy_speed" is removed.
+ The function "get_IEEE_phy_speed" is changed to correctly advertise speeds
+ and restart autonegotiation.
+ A new function "configure_IEEE_phy_speed" is added to configure PHY speeds
+ when autonegotiation is not done.
+ A new function "Phy_Setup" is added to configure the PHY.
+ Hash defines for PHY registers and PHY bit settings are added.
+ * src/contrib/ports/xilinx/netif/xemacliteif: The function
+ "low_level_init" is changed to start PHY autonegotiation when required
+ and to set correct PHY speeds when autonegotiation is not being used.
+ A new function "detect_phy_emaclite" is added to detect the PHY address
+ connected.
+ A new function "get_IEEE_phy_speed_emaclite" is added to correctly
+ advertise relevant PHY speeds (1000 Mbps not advertised) and to restart
+ PHY autonegotiation. This function returns the autonegotiated PHY speed.
+ A new function "configure_IEEE_phy_speed_emaclite" is added to
+ configure the proper PHY speed when PHY autonegotiation is not
+ happenning.
+ Hash defines for PHY registers and PHY bit settings are added.
+ * src/contrib/ports/xilinx/netif/xlltemacif_hw.c:The PHY configuration
+ related code is removed from the function "init_lltemac", since it is now
+ being done in a separate function.
+ * src/contrib/ports/xilinx/netif/xlltemacif_physpeed.c:The unused function
+ "get_marvel_phy_speed" is removed.
+ The function "get_IEEE_phy_speed" is changed to correctly advertise speeds
+ and restart autonegotiation.
+ A new function "configure_IEEE_phy_speed" is added to configure PHY speeds
+ when autonegotiation is not done.
+ A new function "Phy_Setup" is added to configure the PHY.
+ Hash defines for PHY registers and PHY bit settings are added.
+2014-02-12
+ * Change makefile to remove -p option with mkdir. CR# 773090.
+2014-04-16
+ * Fixed the CR#788954 Changes are Made in the xemacliteif.c file
+2014-04-20
+ * Fixed the CR#792040 Changes are Made in the lwip tcl file
+2014-04-23
+ * Fixed the CR#781147 Changes are made in the Makefile.
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile
new file mode 100644
index 0000000..6e9719d
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile
@@ -0,0 +1,55 @@
+include Makefile.lwip
+include Makefile.adapter
+include Makefile.config
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+EXTRA_ARCHIVE_FLAGS=rc
+LIB=liblwip4.a
+
+ifeq ($(CONFIG_PROCESSOR_LITTLE_ENDIAN), y)
+ ENDIAN_FLAGS=-DPROCESSOR_LITTLE_ENDIAN
+else
+ ENDIAN_FLAGS=-DPROCESSOR_BIG_ENDIAN
+endif
+
+CC_FLAGS = $(COMPILER_FLAGS)
+CC_FLAGS += $(ENDIAN_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR} -I$(LWIP_DIR)/src/include/ -I$(LWIP_DIR)/src/include/lwip -I$(PORT)/include
+OBJ_DIR = .
+LWIP_OBJ1 = $(LWIP_OBJS) $(ADAPTER_OBJS)
+VPATH = $(LWIP_DIR)/src/core/ $(LWIP_DIR)/src/core/ipv4/ $(LWIP_DIR)/src/core/ipv6 \
+ $(LWIP_DIR)/src/netif $(LWIP_DIR)/src/api $(PORT) $(PORT)/netif
+INCLUDEFILES = $(ADAPTER_INCLUDES)
+
+libs: liblwip4.a
+
+liblwip4.a: print_msg_lwip $(LWIP_OBJ1)
+ $(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} $(LWIP_OBJ1)
+
+print_msg_lwip:
+ @echo "Compiling lwip src and adapter files"
+
+.PHONY: include
+include: liblwip4_includes
+
+liblwip4_includes:
+ ${CP} -r $(LWIP_DIR)/src/include/lwip ${INCLUDEDIR}
+ ${CP} -r $(LWIP_DIR)/src/include/netif ${INCLUDEDIR}
+ ${CP} -r contrib/ports/xilinx/include/netif ${INCLUDEDIR}
+ ${CP} -r contrib/ports/xilinx/include/arch ${INCLUDEDIR}
+ ${CP} -r contrib/ports/xilinx/include/lwipopts.h ${INCLUDEDIR}
+ ${CP} -r contrib/ports/xilinx/include/xlwipconfig.h ${INCLUDEDIR}
+
+clean:
+ rm -rf ${LWIP_OBJ1}
+ rm -rf ${RELEASEDIR}/${LIB}
+
+$(OBJ_DIR)/%.o: $(OBJ_DIR)/%.c $(INCLUDEFILES)
+ $(GCC_COMPILER) $(CC_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.adapter b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.adapter
new file mode 100644
index 0000000..8bc9a9a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.adapter
@@ -0,0 +1,82 @@
+include Makefile.config
+
+PORT = contrib/ports/xilinx
+
+COMMON_SRCS = $(PORT)/sys_arch_raw.c \
+ $(PORT)/netif/xpqueue.c \
+ $(PORT)/netif/xadapter.c \
+ $(PORT)/netif/xtopology_g.c
+
+ADAPTER_INCLUDES = $(PORT)/include/arch/cc.h \
+ $(PORT)/include/arch/cpu.h \
+ $(PORT)/include/arch/perf.h \
+ $(PORT)/include/arch/sys_arch.h \
+ $(PORT)/include/netif/xadapter.h \
+ $(PORT)/include/netif/xaxiemacif.h \
+ $(PORT)/include/netif/xemacliteif.h \
+ $(PORT)/include/netif/xemacpsif.h \
+ $(PORT)/include/netif/xlltemacif.h \
+ $(PORT)/include/netif/xpqueue.h \
+ $(PORT)/include/netif/xtopology.h \
+ $(PORT)/netif/xaxiemacif_fifo.h \
+ $(PORT)/netif/xaxiemacif_hw.h \
+ $(PORT)/netif/xemacpsif_hw.h \
+ $(PORT)/include/lwipopts.h \
+ $(PORT)/include/xlwipconfig.h
+
+EMACLITE_SRCS = $(PORT)/netif/xemacliteif.c
+
+TEMAC_SRCS = $(PORT)/netif/xlltemacif_hw.c \
+ $(PORT)/netif/xlltemacif_physpeed.c \
+ $(PORT)/netif/xlltemacif_fifo.c \
+ $(PORT)/netif/xlltemacif_sdma.c \
+ $(PORT)/netif/xlltemacif.c
+
+AXI_ETHERNET_SRCS = $(PORT)/netif/xaxiemacif_hw.c \
+ $(PORT)/netif/xaxiemacif_physpeed.c \
+ $(PORT)/netif/xaxiemacif.c
+
+AXI_ETHERNET_FIFO_SRCS = $(PORT)/netif/xaxiemacif_fifo.c
+AXI_ETHERNET_DMA_SRCS = $(PORT)/netif/xaxiemacif_dma.c
+AXI_ETHERNET_MCDMA_SRCS = $(PORT)/netif/xaxiemacif_mcdma.c
+
+PS_ETHERNET_SRCS = $(PORT)/netif/xemacpsif_hw.c \
+ $(PORT)/netif/xemacpsif_physpeed.c \
+ $(PORT)/netif/xemacpsif.c \
+ $(PORT)/netif/xemacpsif_dma.c
+
+SYSARCH_SOCKET_SRCS = $(PORT)/sys_arch.c
+
+ADAPTER_SRCS = $(COMMON_SRCS)
+
+ifeq ($(CONFIG_SOCKETS), y)
+ADAPTER_SRCS += $(SYSARCH_SOCKET_SRCS)
+endif
+
+ifeq ($(CONFIG_XEMACLITE), y)
+ADAPTER_SRCS += $(EMACLITE_SRCS)
+endif
+
+ifeq ($(CONFIG_XLLTEMAC), y)
+ADAPTER_SRCS += $(TEMAC_SRCS)
+endif
+
+ifeq ($(CONFIG_AXI_ETHERNET), y)
+ADAPTER_SRCS += $(AXI_ETHERNET_SRCS)
+endif
+ifeq ($(CONFIG_AXI_ETHERNET_FIFO), y)
+ADAPTER_SRCS += $(AXI_ETHERNET_FIFO_SRCS)
+endif
+ifeq ($(CONFIG_AXI_ETHERNET_DMA), y)
+ADAPTER_SRCS += $(AXI_ETHERNET_DMA_SRCS)
+endif
+ifeq ($(CONFIG_AXI_ETHERNET_MCDMA), y)
+ADAPTER_SRCS += $(AXI_ETHERNET_MCDMA_SRCS)
+endif
+
+ifeq ($(CONFIG_PS_ETHERNET), y)
+ADAPTER_SRCS += $(PS_ETHERNET_SRCS)
+endif
+
+ADAPTER_OBJS1 = $(ADAPTER_SRCS:%.c=%.o)
+ADAPTER_OBJS = $(notdir $(ADAPTER_OBJS1))
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.config b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.config
new file mode 100644
index 0000000..7b6473b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.config
@@ -0,0 +1,3 @@
+GCC_COMPILER=arm-none-eabi-gcc
+CONFIG_PROCESSOR_LITTLE_ENDIAN=y
+CONFIG_PS_ETHERNET=y
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.lwip b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.lwip
new file mode 100644
index 0000000..e5a3617
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/Makefile.lwip
@@ -0,0 +1,140 @@
+include Makefile.config
+
+LWIP_DIR = lwip-2.1.1
+
+CORE_SRCS = $(LWIP_DIR)/src/core/init.c \
+ $(LWIP_DIR)/src/core/def.c \
+ $(LWIP_DIR)/src/core/dns.c \
+ $(LWIP_DIR)/src/core/inet_chksum.c \
+ $(LWIP_DIR)/src/core/ip.c \
+ $(LWIP_DIR)/src/core/mem.c \
+ $(LWIP_DIR)/src/core/memp.c \
+ $(LWIP_DIR)/src/core/netif.c \
+ $(LWIP_DIR)/src/core/pbuf.c \
+ $(LWIP_DIR)/src/core/raw.c \
+ $(LWIP_DIR)/src/core/stats.c \
+ $(LWIP_DIR)/src/core/def.c \
+ $(LWIP_DIR)/src/core/timeouts.c \
+ $(LWIP_DIR)/src/core/sys.c \
+ $(LWIP_DIR)/src/netif/ethernet.c
+
+CORE_IPV4_SRCS = $(LWIP_DIR)/src/core/ipv4/ip4_addr.c \
+ $(LWIP_DIR)/src/core/ipv4/icmp.c \
+ $(LWIP_DIR)/src/core/ipv4/igmp.c \
+ $(LWIP_DIR)/src/core/ipv4/ip4.c \
+ $(LWIP_DIR)/src/core/ipv4/ip4_frag.c \
+ $(LWIP_DIR)/src/core/ipv4/etharp.c \
+ $(LWIP_DIR)/src/core/ipv4/autoip.c
+
+CORE_IPV6_SRCS = $(LWIP_DIR)/src/core/ipv6/inet6.c \
+ $(LWIP_DIR)/src/core/ipv6/ip6_addr.c \
+ $(LWIP_DIR)/src/core/ipv6/ip6_frag.c \
+ $(LWIP_DIR)/src/core/ipv6/icmp6.c \
+ $(LWIP_DIR)/src/core/ipv6/ip6.c \
+ $(LWIP_DIR)/src/core/ipv6/dhcp6.c \
+ $(LWIP_DIR)/src/core/ipv6/ethip6.c \
+ $(LWIP_DIR)/src/core/ipv6/mld6.c \
+ $(LWIP_DIR)/src/core/ipv6/nd6.c
+
+CORE_TCP_SRCS = $(LWIP_DIR)/src/core/tcp.c \
+ $(LWIP_DIR)/src/core/tcp_in.c \
+ $(LWIP_DIR)/src/core/tcp_out.c
+
+CORE_DHCP_SRCS = $(LWIP_DIR)/src/core/ipv4/dhcp.c
+
+CORE_UDP_SRCS = $(LWIP_DIR)/src/core/udp.c
+
+# SNMPFILES: SNMPv2c agent
+CORE_SNMP_SRCS=$(LWIP_DIR)/src/apps/snmp/snmp_asn1.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_core.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2_icmp.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2_interfaces.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2_ip.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2_snmp.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2_system.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2_tcp.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_mib2_udp.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_msg.c \
+ $(LWIP_DIR)/src/apps/snmp/snmpv3.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_netconn.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_pbuf_stream.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_raw.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_scalar.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_table.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_threadsync.c \
+ $(LWIP_DIR)/src/apps/snmp/snmp_traps.c \
+ $(LWIP_DIR)/src/apps/snmp/snmpv3_mbedtls.c \
+ $(LWIP_DIR)/src/apps/snmp/snmpv3_dummy.c
+
+
+CORE_ARP_SRCS = $(LWIP_DIR)/src/netif/etharp.c
+
+API_SOCK_SRCS = $(LWIP_DIR)/src/api/api_lib.c \
+ $(LWIP_DIR)/src/api/api_msg.c \
+ $(LWIP_DIR)/src/api/err.c \
+ $(LWIP_DIR)/src/api/netbuf.c \
+ $(LWIP_DIR)/src/api/netdb.c \
+ $(LWIP_DIR)/src/api/netifapi.c \
+ $(LWIP_DIR)/src/api/sockets.c \
+ $(LWIP_DIR)/src/api/tcpip.c
+
+LWIP_INCLUDES = $(LWIP_DIR)/src/include/lwip/autoip.h \
+ $(LWIP_DIR)/src/include/lwip/icmp.h \
+ $(LWIP_DIR)/src/include/lwip/igmp.h \
+ $(LWIP_DIR)/src/include/lwip/inet.h \
+ $(LWIP_DIR)/src/include/lwip/inet_chksum.h \
+ $(LWIP_DIR)/src/include/lwip/ip.h \
+ $(LWIP_DIR)/src/include/lwip/ip_addr.h \
+ $(LWIP_DIR)/src/include/lwip/ip4_frag.h \
+ $(LWIP_DIR)/src/include/lwip/icmp6.h \
+ $(LWIP_DIR)/src/include/lwip/api.h \
+ $(LWIP_DIR)/src/include/lwip/arch.h \
+ $(LWIP_DIR)/src/include/lwip/debug.h \
+ $(LWIP_DIR)/src/include/lwip/def.h \
+ $(LWIP_DIR)/src/include/lwip/dhcp.h \
+ $(LWIP_DIR)/src/include/lwip/dhcp6.h \
+ $(LWIP_DIR)/src/include/lwip/dns.h \
+ $(LWIP_DIR)/src/include/lwip/err.h \
+ $(LWIP_DIR)/src/include/lwip/init.h \
+ $(LWIP_DIR)/src/include/lwip/mem.h \
+ $(LWIP_DIR)/src/include/lwip/memp.h \
+ $(LWIP_DIR)/src/include/lwip/netbuf.h \
+ $(LWIP_DIR)/src/include/lwip/netdb.h \
+ $(LWIP_DIR)/src/include/lwip/netif.h \
+ $(LWIP_DIR)/src/include/lwip/netifapi.h \
+ $(LWIP_DIR)/src/include/lwip/opt.h \
+ $(LWIP_DIR)/src/include/lwip/raw.h \
+ $(LWIP_DIR)/src/include/lwip/pbuf.h \
+ $(LWIP_DIR)/src/include/lwip/sio.h \
+ $(LWIP_DIR)/src/include/lwip/snmp.h \
+ $(LWIP_DIR)/src/include/lwip/sockets.h \
+ $(LWIP_DIR)/src/include/lwip/stats.h \
+ $(LWIP_DIR)/src/include/lwip/sys.h \
+ $(LWIP_DIR)/src/include/lwip/tcp.h \
+ $(LWIP_DIR)/src/include/lwip/tcpip.h \
+ $(LWIP_DIR)/src/include/lwip/timeouts.h \
+ $(LWIP_DIR)/src/include/lwip/udp.h \
+ $(LWIP_DIR)/src/include/netif/etharp.h \
+ $(LWIP_DIR)/src/include/netif/ppp/ppp_oe.h \
+ $(LWIP_DIR)/src/include/netif/slipif.h
+
+
+# create LWIP_SRCS based on configured options
+
+LWIP_SRCS = $(CORE_SRCS)
+
+# we always include ARP, IPv4, TCP and UDP sources
+LWIP_SRCS += $(CORE_ARP_SRCS)
+LWIP_SRCS += $(CORE_IPV4_SRCS)
+LWIP_SRCS += $(CORE_IPV6_SRCS)
+LWIP_SRCS += $(CORE_TCP_SRCS)
+LWIP_SRCS += $(CORE_UDP_SRCS)
+LWIP_SRCS += $(CORE_DHCP_SRCS)
+
+ifeq ($(CONFIG_SOCKETS), y)
+LWIP_SRCS += $(API_SOCK_SRCS)
+endif
+
+LWIP_OBJS1 = $(LWIP_SRCS:%.c=%.o)
+LWIP_OBJS = $(notdir $(LWIP_OBJS1))
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/cc.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/cc.h
new file mode 100644
index 0000000..bae8653
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/cc.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __ARCH_CC_H__
+#define __ARCH_CC_H__
+
+#include
+#include
+
+#include "lwipopts.h"
+
+/** if you want to use the struct timeval provided
+ * by your system, set this to 0 and include in cc.h */
+#define LWIP_TIMEVAL_PRIVATE 0
+#include
+#include "cpu.h"
+
+/* As per new design of lwip-2.0.2,
+ * LWIP_NO_STDINT_H should be defined as 1 in cc.h */
+#define LWIP_NO_STDINT_H 1
+
+typedef unsigned char u8_t;
+typedef signed char s8_t;
+typedef unsigned short u16_t;
+typedef signed short s16_t;
+typedef unsigned int u32_t;
+typedef signed int s32_t;
+typedef unsigned long long u64_t;
+typedef signed long long s64_t;
+
+#define S16_F "d"
+#define U16_F "d"
+#define S32_F "d"
+#define U32_F "x"
+
+#define X16_F "x"
+#define X32_F "x"
+
+#define LWIP_RAND rand
+
+typedef unsigned long mem_ptr_t;
+
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_END
+
+#define LWIP_PLATFORM_ASSERT(x)
+#define LWIP_PLATFORM_DIAG(x) do { xil_printf x; } while(0)
+
+#endif /* __ARCH_CC_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/cpu.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/cpu.h
new file mode 100644
index 0000000..ec05a8c
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __ARCH_CPU_H__
+#define __ARCH_CPU_H__
+
+#include "lwipopts.h"
+
+#ifndef BYTE_ORDER
+#ifdef PROCESSOR_LITTLE_ENDIAN
+#define BYTE_ORDER LITTLE_ENDIAN
+#else
+#define BYTE_ORDER BIG_ENDIAN
+#endif
+#endif
+
+#endif /* __ARCH_CPU_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/perf.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/perf.h
new file mode 100644
index 0000000..dd12bf3
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/perf.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __ARCH_PERF_H__
+#define __ARCH_PERF_H__
+
+#define PERF_START /* null definition */
+#define PERF_STOP(x) /* null definition */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void perf_init(char *fname);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARCH_PERF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/sys_arch.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/sys_arch.h
new file mode 100644
index 0000000..5e6f978
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/arch/sys_arch.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+
+#ifndef __SYS_XILINX_ARCH_H__
+#define __SYS_XILINX_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "lwipopts.h"
+
+
+#if !NO_SYS
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+#include "timers.h"
+
+#define SYS_MBOX_NULL ( ( xQueueHandle ) NULL )
+#define SYS_SEM_NULL ( ( xSemaphoreHandle ) NULL )
+#define SYS_DEFAULT_THREAD_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xSemaphoreHandle sys_mutex_t;
+typedef xQueueHandle sys_mbox_t;
+typedef xTaskHandle sys_thread_t;
+
+typedef unsigned long sys_prot_t;
+
+#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL )
+#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
+#endif /* !NO_SYS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYS_XILINX_ARCH_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/lwipopts.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/lwipopts.h
new file mode 100644
index 0000000..560f7bb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/lwipopts.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef __LWIPOPTS_H_
+#define __LWIPOPTS_H_
+
+#ifndef PROCESSOR_LITTLE_ENDIAN
+#define PROCESSOR_LITTLE_ENDIAN
+#endif
+
+#define SYS_LIGHTWEIGHT_PROT 1
+
+#define NO_SYS 1
+#define LWIP_SOCKET 0
+#define LWIP_COMPAT_SOCKETS 0
+#define LWIP_NETCONN 0
+
+#define NO_SYS_NO_TIMERS 1
+
+#define LWIP_TCP_KEEPALIVE 0
+
+#define MEM_ALIGNMENT 64
+#define MEM_SIZE 131072
+#define MEMP_NUM_PBUF 16
+#define MEMP_NUM_UDP_PCB 4
+#define MEMP_NUM_TCP_PCB 32
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+#define MEMP_NUM_TCP_SEG 256
+#define MEMP_NUM_SYS_TIMEOUT 8
+#define MEMP_NUM_NETBUF 8
+#define MEMP_NUM_NETCONN 16
+#define MEMP_NUM_TCPIP_MSG_API 16
+#define MEMP_NUM_TCPIP_MSG_INPKT 64
+
+#define MEMP_NUM_SYS_TIMEOUT 8
+#define PBUF_POOL_SIZE 2048
+#define PBUF_POOL_BUFSIZE 1700
+#define PBUF_LINK_HLEN 16
+
+#define ARP_TABLE_SIZE 10
+#define ARP_QUEUEING 1
+
+#define ICMP_TTL 255
+
+#define IP_OPTIONS 0
+#define IP_FORWARD 0
+#define IP_REASSEMBLY 1
+#define IP_FRAG 1
+#define IP_REASS_MAX_PBUFS 128
+#define IP_FRAG_MAX_MTU 1500
+#define IP_DEFAULT_TTL 255
+#define LWIP_CHKSUM_ALGORITHM 3
+
+#define LWIP_UDP 1
+#define UDP_TTL 255
+#define LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE 0
+
+#define LWIP_TCP 1
+#define TCP_MSS 1460
+#define TCP_SND_BUF 8192
+#define TCP_WND 2048
+#define TCP_TTL 255
+#define TCP_MAXRTX 12
+#define TCP_SYNMAXRTX 4
+#define TCP_QUEUE_OOSEQ 1
+#define TCP_SND_QUEUELEN 16 * TCP_SND_BUF/TCP_MSS
+#define CHECKSUM_GEN_TCP 0
+#define CHECKSUM_GEN_UDP 0
+#define CHECKSUM_GEN_IP 0
+#define CHECKSUM_CHECK_TCP 0
+#define CHECKSUM_CHECK_UDP 0
+#define CHECKSUM_CHECK_IP 0
+#define LWIP_FULL_CSUM_OFFLOAD_RX 1
+#define LWIP_FULL_CSUM_OFFLOAD_TX 1
+
+#define MEMP_SEPARATE_POOLS 1
+#define MEMP_NUM_FRAG_PBUF 256
+#define IP_OPTIONS_ALLOWED 0
+#define TCP_OVERSIZE TCP_MSS
+
+#define LWIP_DHCP 1
+#define DHCP_DOES_ARP_CHECK 1
+
+#define CONFIG_LINKSPEED_AUTODETECT 1
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xadapter.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xadapter.h
new file mode 100644
index 0000000..4d32b7f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xadapter.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2007 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XADAPTER_H_
+#define __XADAPTER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwipopts.h"
+
+#if !NO_SYS
+#include "lwip/sys.h"
+#endif
+
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#include "netif/xtopology.h"
+
+struct xemac_s {
+ enum xemac_types type;
+ int topology_index;
+ void *state;
+#if !NO_SYS
+ sys_sem_t sem_rx_data_available;
+#if defined(__arm__) && !defined(ARMR5)
+ TimerHandle_t xTimer;
+#endif
+#endif
+};
+
+enum ethernet_link_status {
+ ETH_LINK_UNDEFINED = 0,
+ ETH_LINK_UP,
+ ETH_LINK_DOWN,
+ ETH_LINK_NEGOTIATING
+};
+
+void eth_link_detect(struct netif *netif);
+void lwip_raw_init();
+int xemacif_input(struct netif *netif);
+void xemacif_input_thread(struct netif *netif);
+struct netif * xemac_add(struct netif *netif,
+ ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
+ unsigned char *mac_ethernet_address,
+ UINTPTR mac_baseaddr);
+#if defined (__arm__) || defined (__aarch64__)
+void xemacpsif_resetrx_on_no_rxdata(struct netif *netif);
+#endif
+
+/* global lwip debug variable used for debugging */
+extern int lwip_runtime_debug;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xaxiemacif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xaxiemacif.h
new file mode 100644
index 0000000..3a25466
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xaxiemacif.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2010 - 2020 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XAXIEMACIF_H__
+#define __NETIF_XAXIEMACIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xlwipconfig.h"
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "netif/xadapter.h"
+
+#include "xparameters.h"
+#include "xstatus.h"
+
+#include "xaxiethernet.h"
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+#include "xllfifo.h"
+#elif XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+#include "xmcdma.h"
+#else
+#include "xaxidma.h"
+#include "xaxidma_hw.h"
+#endif
+
+#include "netif/xpqueue.h"
+#include "xlwipconfig.h"
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#define AXIDMA_TX_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define AXIDMA_RX_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define AXIETH_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define TRIG_TYPE_RISING_EDGE_SENSITIVE 0x3
+
+#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
+#endif
+
+void xaxiemacif_setmac(u32_t index, u8_t *addr);
+u8_t* xaxiemacif_getmac(u32_t index);
+err_t xaxiemacif_init(struct netif *netif);
+int xaxiemacif_input(struct netif *netif);
+
+unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp);
+void enable_sgmii_clock(XAxiEthernet *xaxiemacp);
+unsigned configure_IEEE_phy_speed(XAxiEthernet *xaxiemacp, unsigned speed);
+unsigned phy_setup_axiemac (XAxiEthernet *xaxiemacp);
+
+/* xaxiemacif_hw.c */
+void xaxiemac_error_handler(XAxiEthernet * Temac);
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular temac instance
+ */
+typedef struct {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+ XLlFifo axififo;
+#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA)
+ XMcdma aximcdma;
+#else
+ XAxiDma axidma;
+#endif
+ XAxiEthernet axi_ethernet;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+
+ /* pointers to memory holding buffer descriptors (used only with SDMA) */
+ void *rx_bdspace;
+ void *tx_bdspace;
+} xaxiemacif_s;
+
+extern xaxiemacif_s xaxiemacif;
+
+#ifndef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+s32_t is_tx_space_available(xaxiemacif_s *emac);
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+s32_t process_sent_bds(XMcdma_ChanCtrl *Tx_Chan);
+#else
+s32_t process_sent_bds(XAxiDma_BdRing *txring);
+#endif
+#endif
+
+/* xaxiemacif_dma.c/xaxiemacif_mcdma.c */
+#ifndef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+XStatus init_axi_mcdma(struct xemac_s *xemac);
+XStatus axi_mcdma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p);
+#else
+XStatus init_axi_dma(struct xemac_s *xemac);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+XStatus axidma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p,
+ u32_t block_till_tx_complete, u32_t *to_block_index);
+#else
+XStatus axidma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p);
+#endif
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XAXIEMACIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xemacliteif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xemacliteif.h
new file mode 100644
index 0000000..c083660
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xemacliteif.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XEMACLITEIF_H__
+#define __NETIF_XEMACLITEIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "netif/xpqueue.h"
+#include "xemaclite.h"
+#include "xemaclite_i.h"
+#include "xstatus.h"
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular emaclite instance
+ */
+typedef struct {
+ XEmacLite *instance;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+} xemacliteif_s;
+
+void xemacliteif_setmac(u32_t index, u8_t *addr);
+u8_t* xemacliteif_getmac(u32_t index);
+err_t xemacliteif_init(struct netif *netif);
+int xemacliteif_input(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XEMACLITEIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xemacpsif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xemacpsif.h
new file mode 100644
index 0000000..f108920
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xemacpsif.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XEMACPSIF_H__
+#define __NETIF_XEMACPSIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xlwipconfig.h"
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "lwip/sys.h"
+#include "netif/xadapter.h"
+
+#include "xstatus.h"
+#include "sleep.h"
+#include "xparameters.h"
+#include "xparameters_ps.h" /* defines XPAR values */
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xil_cache.h"
+#include "xil_printf.h"
+#include "xscugic.h"
+#include "xemacps.h" /* defines XEmacPs API */
+
+#include "netif/xpqueue.h"
+#include "xlwipconfig.h"
+
+#if defined (__aarch64__) && (EL1_NONSECURE == 1)
+#include "xil_smc.h"
+#endif
+
+#define ZYNQ_EMACPS_0_BASEADDR 0xE000B000
+#define ZYNQ_EMACPS_1_BASEADDR 0xE000C000
+
+#define ZYNQMP_EMACPS_0_BASEADDR 0xFF0B0000
+#define ZYNQMP_EMACPS_1_BASEADDR 0xFF0C0000
+#define ZYNQMP_EMACPS_2_BASEADDR 0xFF0D0000
+#define ZYNQMP_EMACPS_3_BASEADDR 0xFF0E0000
+
+#define CRL_APB_GEM0_REF_CTRL 0xFF5E0050
+#define CRL_APB_GEM1_REF_CTRL 0xFF5E0054
+#define CRL_APB_GEM2_REF_CTRL 0xFF5E0058
+#define CRL_APB_GEM3_REF_CTRL 0xFF5E005C
+
+#define CRL_APB_GEM_DIV0_MASK 0x00003F00
+#define CRL_APB_GEM_DIV0_SHIFT 8
+#define CRL_APB_GEM_DIV1_MASK 0x003F0000
+#define CRL_APB_GEM_DIV1_SHIFT 16
+
+#define VERSAL_EMACPS_0_BASEADDR 0xFF0C0000
+#define VERSAL_EMACPS_1_BASEADDR 0xFF0D0000
+
+#define VERSAL_CRL_GEM0_REF_CTRL 0xFF5E0118
+#define VERSAL_CRL_GEM1_REF_CTRL 0xFF5E011C
+
+#define VERSAL_CRL_GEM_DIV_MASK 0x0003FF00
+#define VERSAL_CRL_APB_GEM_DIV_SHIFT 8
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (__MICROBLAZE__)
+#if defined (USE_JUMBO_FRAMES)
+#define ZYNQMP_USE_JUMBO
+#endif
+#endif
+
+#define GEM_VERSION_ZYNQMP 7
+#define GEM_VERSION_VERSAL 0x107
+
+#define MAX_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE)
+
+void xemacpsif_setmac(u32_t index, u8_t *addr);
+u8_t* xemacpsif_getmac(u32_t index);
+err_t xemacpsif_init(struct netif *netif);
+s32_t xemacpsif_input(struct netif *netif);
+
+/* xaxiemacif_hw.c */
+void xemacps_error_handler(XEmacPs * Temac);
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular temac instance
+ */
+typedef struct {
+ XEmacPs emacps;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+
+ /* pointers to memory holding buffer descriptors (used only with SDMA) */
+ void *rx_bdspace;
+ void *tx_bdspace;
+
+ unsigned int last_rx_frms_cntr;
+
+} xemacpsif_s;
+
+extern xemacpsif_s xemacpsif;
+
+s32_t is_tx_space_available(xemacpsif_s *emac);
+
+/* xemacpsif_dma.c */
+
+void process_sent_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *txring);
+u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr);
+void detect_phy(XEmacPs *xemacpsp);
+void emacps_send_handler(void *arg);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p,
+ u32_t block_till_tx_complete, u32_t *to_block_index);
+#else
+XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p);
+#endif
+void emacps_recv_handler(void *arg);
+void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord);
+void setup_rx_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *rxring);
+void HandleTxErrors(struct xemac_s *xemac);
+void HandleEmacPsError(struct xemac_s *xemac);
+XEmacPs_Config *xemacps_lookup_config(unsigned mac_base);
+void init_emacps(xemacpsif_s *xemacps, struct netif *netif);
+void setup_isr (struct xemac_s *xemac);
+XStatus init_dma(struct xemac_s *xemac);
+void start_emacps (xemacpsif_s *xemacps);
+void free_txrx_pbufs(xemacpsif_s *xemacpsif);
+void free_onlytx_pbufs(xemacpsif_s *xemacpsif);
+void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif);
+void clean_dma_txdescs(struct xemac_s *xemac);
+void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif);
+void reset_dma(struct xemac_s *xemac);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XAXIEMACIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xlltemacif.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xlltemacif.h
new file mode 100644
index 0000000..3664f95
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xlltemacif.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __NETIF_XLLTEMACIF_H__
+#define __NETIF_XLLTEMACIF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "netif/xadapter.h"
+
+#include "xparameters.h"
+#include "xstatus.h"
+#include "xlltemac.h"
+#include "xlldma.h"
+#include "xllfifo.h"
+#include "xlldma_bdring.h"
+
+#include "netif/xpqueue.h"
+#include "xlwipconfig.h"
+
+void xlltemacif_setmac(u32_t index, u8_t *addr);
+u8_t* xlltemacif_getmac(u32_t index);
+err_t xlltemacif_init(struct netif *netif);
+int xlltemacif_input(struct netif *netif);
+unsigned get_IEEE_phy_speed(XLlTemac *xlltemacp);
+unsigned Phy_Setup (XLlTemac *xlltemacp);
+unsigned configure_IEEE_phy_speed(XLlTemac *xlltemacp, unsigned speed);
+
+/* xlltemacif_hw.c */
+void xlltemac_error_handler(XLlTemac * Temac);
+
+/* structure within each netif, encapsulating all information required for
+ * using a particular temac instance
+ */
+typedef struct {
+ XLlDma lldma;
+ XLlFifo llfifo;
+ XLlTemac lltemac;
+
+ /* queue to store overflow packets */
+ pq_queue_t *recv_q;
+ pq_queue_t *send_q;
+
+ /* pointers to memory holding buffer descriptors (used only with SDMA) */
+ void *rx_bdspace;
+ void *tx_bdspace;
+} xlltemacif_s;
+
+extern xlltemacif_s xlltemacif;
+
+/* xlltemacif_sdma.c */
+XStatus init_sdma(struct xemac_s *xemac);
+int process_sent_bds(XLlDma_BdRing *txring);
+void lldma_send_handler(void *arg);
+XStatus lldma_sgsend(xlltemacif_s *xlltemacif, struct pbuf *p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_XLLTEMACIF_H__ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xpqueue.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xpqueue.h
new file mode 100644
index 0000000..132f02f
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xpqueue.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __LWIP_PBUF_QUEUE_H_
+#define __LWIP_PBUF_QUEUE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PQ_QUEUE_SIZE 4096
+
+typedef struct {
+ void *data[PQ_QUEUE_SIZE];
+ int head, tail, len;
+} pq_queue_t;
+
+pq_queue_t* pq_create_queue();
+int pq_enqueue(pq_queue_t *q, void *p);
+void* pq_dequeue(pq_queue_t *q);
+int pq_qlength(pq_queue_t *q);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xtopology.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xtopology.h
new file mode 100644
index 0000000..51718f1
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/netif/xtopology.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XTOPOLOGY_H_
+#define __XTOPOLOGY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+
+enum xemac_types { xemac_type_unknown = -1, xemac_type_xps_emaclite, xemac_type_xps_ll_temac, xemac_type_axi_ethernet, xemac_type_emacps };
+
+struct xtopology_t {
+ UINTPTR emac_baseaddr;
+ enum xemac_types emac_type;
+ UINTPTR intc_baseaddr;
+ unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */
+ UINTPTR scugic_baseaddr; /* valid only for Zynq */
+ unsigned scugic_emac_intr; /* valid only for GEM */
+};
+
+extern int xtopology_n_emacs;
+extern struct xtopology_t xtopology[];
+
+int xtopology_find_index(unsigned base);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/xlwipconfig.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/xlwipconfig.h
new file mode 100644
index 0000000..8f8f3e2
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/include/xlwipconfig.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2018 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels
+ *
+ */
+#ifndef __XLWIPCONFIG_H_
+#define __XLWIPCONFIG_H_
+
+
+/* This is a generated file - do not edit */
+
+#define XLWIP_CONFIG_INCLUDE_GEM 1
+#define XLWIP_CONFIG_EMAC_NUMBER 0
+#define XLWIP_CONFIG_N_TX_DESC 64
+#define XLWIP_CONFIG_N_RX_DESC 64
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xadapter.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xadapter.c
new file mode 100644
index 0000000..9594ff5
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xadapter.c
@@ -0,0 +1,425 @@
+/*
+ * Copyright (C) 2007 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwipopts.h"
+#include "xlwipconfig.h"
+#include "xemac_ieee_reg.h"
+
+#if !NO_SYS
+#endif
+
+#include "lwip/mem.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/ip.h"
+#include "lwip/tcp.h"
+#include "lwip/udp.h"
+#include "lwip/priv/tcp_priv.h"
+
+#include "netif/etharp.h"
+#include "netif/xadapter.h"
+
+#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
+#include "netif/xemacliteif.h"
+#endif
+
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
+#include "netif/xaxiemacif.h"
+#endif
+
+#ifdef XLWIP_CONFIG_INCLUDE_GEM
+#include "netif/xemacpsif.h"
+#endif
+
+#if !NO_SYS
+#include "lwip/tcpip.h"
+
+#define THREAD_STACKSIZE 256
+#define LINK_DETECT_THREAD_INTERVAL 1000 /* one second */
+
+void link_detect_thread(void *p);
+#endif
+
+/* global lwip debug variable used for debugging */
+int lwip_runtime_debug = 0;
+
+enum ethernet_link_status eth_link_status = ETH_LINK_UNDEFINED;
+u32_t phyaddrforemac;
+
+void
+lwip_raw_init()
+{
+ ip_init(); /* Doesn't do much, it should be called to handle future changes. */
+#if LWIP_UDP
+ udp_init(); /* Clears the UDP PCB list. */
+#endif
+#if LWIP_TCP
+ tcp_init(); /* Clears the TCP PCB list and clears some internal TCP timers. */
+ /* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */
+ /* predefined regular intervals after this initialization. */
+#endif
+}
+
+static enum xemac_types
+find_mac_type(unsigned base)
+{
+ int i;
+
+ for (i = 0; i < xtopology_n_emacs; i++) {
+ if (xtopology[i].emac_baseaddr == base)
+ return xtopology[i].emac_type;
+ }
+
+ return xemac_type_unknown;
+}
+
+int
+xtopology_find_index(unsigned base)
+{
+ int i;
+
+ for (i = 0; i < xtopology_n_emacs; i++) {
+ if (xtopology[i].emac_baseaddr == base)
+ return i;
+ }
+
+ return -1;
+}
+
+/*
+ * xemac_add: this is a wrapper around lwIP's netif_add function.
+ * The objective is to provide portability between the different Xilinx MAC's
+ * This function can be used to add both xps_ethernetlite and xps_ll_temac
+ * based interfaces
+ */
+struct netif *
+xemac_add(struct netif *netif,
+ ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
+ unsigned char *mac_ethernet_address,
+ UINTPTR mac_baseaddr)
+{
+ int i;
+
+#if !NO_SYS
+ /* Start thread to detect link periodically for Hot Plug autodetect */
+ sys_thread_new("link_detect_thread", link_detect_thread, netif,
+ THREAD_STACKSIZE, tskIDLE_PRIORITY);
+#endif
+
+ /* set mac address */
+ netif->hwaddr_len = 6;
+ for (i = 0; i < 6; i++)
+ netif->hwaddr[i] = mac_ethernet_address[i];
+
+ /* initialize based on MAC type */
+ switch (find_mac_type(mac_baseaddr)) {
+ case xemac_type_xps_emaclite:
+#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
+ return netif_add(netif, ipaddr, netmask, gw,
+ (void*)mac_baseaddr,
+ xemacliteif_init,
+#if NO_SYS
+ ethernet_input
+#else
+ tcpip_input
+#endif
+ );
+#else
+ return NULL;
+#endif
+ case xemac_type_axi_ethernet:
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
+ return netif_add(netif, ipaddr, netmask, gw,
+ (void*)mac_baseaddr,
+ xaxiemacif_init,
+#if NO_SYS
+ ethernet_input
+#else
+ tcpip_input
+#endif
+ );
+#else
+ return NULL;
+#endif
+#if defined (__arm__) || defined (__aarch64__)
+ case xemac_type_emacps:
+#ifdef XLWIP_CONFIG_INCLUDE_GEM
+ return netif_add(netif, ipaddr, netmask, gw,
+ (void*)mac_baseaddr,
+ xemacpsif_init,
+#if NO_SYS
+ ethernet_input
+#else
+ tcpip_input
+#endif
+
+ );
+#endif
+#endif
+ default:
+ xil_printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n",
+ mac_baseaddr);
+ return NULL;
+ }
+}
+
+#if !NO_SYS
+/*
+ * The input thread calls lwIP to process any received packets.
+ * This thread waits until a packet is received (sem_rx_data_available),
+ * and then calls xemacif_input which processes 1 packet at a time.
+ */
+void
+xemacif_input_thread(struct netif *netif)
+{
+ struct xemac_s *emac = (struct xemac_s *)netif->state;
+ while (1) {
+ /* sleep until there are packets to process
+ * This semaphore is set by the packet receive interrupt
+ * routine.
+ */
+ sys_sem_wait(&emac->sem_rx_data_available);
+
+ /* move all received packets to lwIP */
+ xemacif_input(netif);
+ }
+}
+#endif
+
+int
+xemacif_input(struct netif *netif)
+{
+ struct xemac_s *emac = (struct xemac_s *)netif->state;
+
+ int n_packets = 0;
+
+ switch (emac->type) {
+ case xemac_type_xps_emaclite:
+#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE
+ n_packets = xemacliteif_input(netif);
+ break;
+#else
+ print("incorrect configuration: xps_ethernetlite drivers not present?");
+ while(1);
+ return 0;
+#endif
+ case xemac_type_axi_ethernet:
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET
+ n_packets = xaxiemacif_input(netif);
+ break;
+#else
+ print("incorrect configuration: axi_ethernet drivers not present?");
+ while(1);
+ return 0;
+#endif
+#if defined (__arm__) || defined (__aarch64__)
+ case xemac_type_emacps:
+#ifdef XLWIP_CONFIG_INCLUDE_GEM
+ n_packets = xemacpsif_input(netif);
+ break;
+#else
+ xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n");
+ while(1);
+ return 0;
+#endif
+#endif
+ default:
+ print("incorrect configuration: unknown temac type");
+ while(1);
+ return 0;
+ }
+
+ return n_packets;
+}
+
+#if defined(XLWIP_CONFIG_INCLUDE_GEM)
+static u32_t phy_link_detect(XEmacPs *xemacp, u32_t phy_addr)
+{
+ u16_t status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+ XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ if (status & IEEE_STAT_LINK_STATUS)
+ return 1;
+ return 0;
+}
+#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
+static u32_t phy_link_detect(XAxiEthernet *xemacp, u32_t phy_addr)
+{
+ u16_t status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+ XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ if (status & IEEE_STAT_LINK_STATUS)
+ return 1;
+ return 0;
+}
+#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
+static u32_t phy_link_detect(XEmacLite *xemacp, u32_t phy_addr)
+{
+ u16_t status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+ XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ if (status & IEEE_STAT_LINK_STATUS)
+ return 1;
+ return 0;
+}
+#endif
+
+#if defined(XLWIP_CONFIG_INCLUDE_GEM)
+static u32_t phy_autoneg_status(XEmacPs *xemacp, u32_t phy_addr)
+{
+ u16_t status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+ XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
+ return 1;
+ return 0;
+}
+#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
+static u32_t phy_autoneg_status(XAxiEthernet *xemacp, u32_t phy_addr)
+{
+ u16_t status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+ XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ XAxiEthernet_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
+ return 1;
+ return 0;
+}
+#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
+static u32_t phy_autoneg_status(XEmacLite *xemacp, u32_t phy_addr)
+{
+ u16_t status;
+
+ /* Read Phy Status register twice to get the confirmation of the current
+ * link status.
+ */
+ XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ if (status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)
+ return 1;
+ return 0;
+}
+#endif
+
+void eth_link_detect(struct netif *netif)
+{
+ u32_t link_speed, phy_link_status;
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+
+#if defined(XLWIP_CONFIG_INCLUDE_GEM)
+ xemacpsif_s *xemacs = (xemacpsif_s *)(xemac->state);
+ XEmacPs *xemacp = &xemacs->emacps;
+#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
+ xaxiemacif_s *xemacs = (xaxiemacif_s *)(xemac->state);
+ XAxiEthernet *xemacp = &xemacs->axi_ethernet;
+#elif defined(XLWIP_CONFIG_INCLUDE_EMACLITE)
+ xemacliteif_s *xemacs = (xemacliteif_s *)(xemac->state);
+ XEmacLite *xemacp = xemacs->instance;
+#endif
+
+ if ((xemacp->IsReady != (u32)XIL_COMPONENT_IS_READY) ||
+ (eth_link_status == ETH_LINK_UNDEFINED))
+ return;
+
+ phy_link_status = phy_link_detect(xemacp, phyaddrforemac);
+
+ if ((eth_link_status == ETH_LINK_UP) && (!phy_link_status))
+ eth_link_status = ETH_LINK_DOWN;
+
+ switch (eth_link_status) {
+ case ETH_LINK_UNDEFINED:
+ case ETH_LINK_UP:
+ return;
+ case ETH_LINK_DOWN:
+ netif_set_link_down(netif);
+ eth_link_status = ETH_LINK_NEGOTIATING;
+ xil_printf("Ethernet Link down\r\n");
+ break;
+ case ETH_LINK_NEGOTIATING:
+ if (phy_link_status &&
+ phy_autoneg_status(xemacp, phyaddrforemac)) {
+
+ /* Initiate Phy setup to get link speed */
+#if defined(XLWIP_CONFIG_INCLUDE_GEM)
+ link_speed = phy_setup_emacps(xemacp,
+ phyaddrforemac);
+ XEmacPs_SetOperatingSpeed(xemacp, link_speed);
+#elif defined(XLWIP_CONFIG_INCLUDE_AXI_ETHERNET)
+ link_speed = phy_setup_axiemac(xemacp);
+ XAxiEthernet_SetOperatingSpeed(xemacp,
+ link_speed);
+#endif
+ netif_set_link_up(netif);
+ eth_link_status = ETH_LINK_UP;
+ xil_printf("Ethernet Link up\r\n");
+ }
+ break;
+ }
+}
+
+#if !NO_SYS
+void link_detect_thread(void *p)
+{
+ struct netif *netif = (struct netif *) p;
+
+ while (1) {
+ /* Call eth_link_detect() every second to detect Ethernet link
+ * change.
+ */
+ eth_link_detect(netif);
+ vTaskDelay(LINK_DETECT_THREAD_INTERVAL / portTICK_RATE_MS);
+ }
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif.c
new file mode 100644
index 0000000..a428c13
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif.c
@@ -0,0 +1,746 @@
+/*
+ * Copyright (C) 2010 - 2020 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include
+#include
+
+#include
+
+#include "xlwipconfig.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/igmp.h"
+
+#include "netif/etharp.h"
+#include "netif/xaxiemacif.h"
+#include "netif/xadapter.h"
+#include "netif/xpqueue.h"
+
+#include "xaxiemacif_fifo.h"
+#include "xaxiemacif_hw.h"
+
+#include "xparameters.h"
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#include "xscugic.h"
+#else
+#include "xintc.h"
+#endif
+
+#if LWIP_IPV6
+#include "lwip/ethip6.h"
+#endif
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 't'
+#define IFNAME1 'e'
+
+#if LWIP_IGMP
+static err_t xaxiemacif_mac_filter_update (struct netif *netif,
+ ip_addr_t *group, u8_t action);
+
+static u8_t xaxiemac_mcast_entry_mask = 0;
+#endif
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+#define XAXIEMAC_MAX_MAC_ADDR 4
+static err_t xaxiemacif_mld6_mac_filter_update (struct netif *netif,
+ ip_addr_t *group, u8_t action);
+
+static u8_t xaxiemac_mld6_mcast_entry_mask;
+#endif
+
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+extern volatile u32_t notifyinfo[XLWIP_CONFIG_N_TX_DESC];
+#endif
+
+/*
+ * this function is always called with interrupts off
+ * this function also assumes that there are available BD's
+ */
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+static err_t _unbuffered_low_level_output(xaxiemacif_s *xaxiemacif,
+ struct pbuf *p, u32_t block_till_tx_complete, u32_t *to_block_index )
+#else
+static err_t _unbuffered_low_level_output(xaxiemacif_s *xaxiemacif,
+ struct pbuf *p)
+#endif
+{
+ XStatus status = 0;
+ err_t err = ERR_MEM;
+
+#if ETH_PAD_SIZE
+ pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+ if (XAxiEthernet_IsDma(&xaxiemacif->axi_ethernet)) {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_DMA
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (block_till_tx_complete == 1) {
+ status = axidma_sgsend(xaxiemacif, p, 1, to_block_index);
+ } else {
+ status = axidma_sgsend(xaxiemacif, p, 0, to_block_index);
+ }
+#else
+ status = axidma_sgsend(xaxiemacif, p);
+#endif
+#endif
+ } else if (XAxiEthernet_IsMcDma(&xaxiemacif->axi_ethernet)) {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+ status = axi_mcdma_sgsend(xaxiemacif, p);
+#endif
+ } else {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+ status = axififo_send(xaxiemacif, p);
+#endif
+ }
+
+ if (status != XST_SUCCESS) {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ } else {
+ err = ERR_OK;
+ }
+
+#if ETH_PAD_SIZE
+ pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+#if LINK_STATS
+ lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+
+ return err;
+
+}
+
+/*
+ * low_level_output():
+ *
+ * Should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ */
+
+static err_t low_level_output(struct netif *netif, struct pbuf *p)
+{
+ err_t err = ERR_MEM;
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ u32_t notfifyblocksleepcntr;
+ u32_t to_block_index;
+#endif
+
+ SYS_ARCH_DECL_PROTECT(lev);
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_DMA
+ /*
+ * With AXI Ethernet on Zynq, we observed unexplained delays for
+ * BD Status update. As a result, we are hitting a condition where
+ * there are no BDs free to transmit packets. So, we have added
+ * this logic where we look for the status update in a definite
+ * loop.
+ */
+ XAxiDma_BdRing *txring = XAxiDma_GetTxRing(&xaxiemacif->axidma);
+#endif
+ int count = 100;
+
+ SYS_ARCH_PROTECT(lev);
+
+ while (count) {
+
+ /* check if space is available to send */
+ if (is_tx_space_available(xaxiemacif)) {
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (netif_is_opt_block_tx_set(netif, NETIF_ENABLE_BLOCKING_TX_FOR_PACKET)) {
+ err = _unbuffered_low_level_output(xaxiemacif, p, 1, &to_block_index);
+ break;
+ } else {
+ err = _unbuffered_low_level_output(xaxiemacif, p, 0, &to_block_index);
+ break;
+ }
+#else
+ err = _unbuffered_low_level_output(xaxiemacif, p);
+ break;
+#endif
+ } else {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_DMA
+ process_sent_bds(txring);
+#endif
+ count--;
+ }
+ }
+
+ if (count == 0) {
+ print("pack dropped, no space\r\n");
+ SYS_ARCH_UNPROTECT(lev);
+ goto return_pack_dropped;
+ }
+
+ SYS_ARCH_UNPROTECT(lev);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (netif_is_opt_block_tx_set(netif, NETIF_ENABLE_BLOCKING_TX_FOR_PACKET)) {
+ /* Wait for approx 1 second before timing out */
+ notfifyblocksleepcntr = 900000;
+ while(notifyinfo[to_block_index] == 1) {
+ usleep(1);
+ notfifyblocksleepcntr--;
+ if (notfifyblocksleepcntr <= 0) {
+ err = ERR_TIMEOUT;
+ break;
+ }
+ }
+ }
+ netif_clear_opt_block_tx(netif, NETIF_ENABLE_BLOCKING_TX_FOR_PACKET);
+#endif
+return_pack_dropped:
+ return err;
+}
+
+/*
+ * low_level_input():
+ *
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ */
+static struct pbuf *low_level_input(struct netif *netif)
+{
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ struct pbuf *p;
+
+ /* see if there is data to process */
+ if (pq_qlength(xaxiemacif->recv_q) == 0)
+ return NULL;
+
+ /* return one packet from receive q */
+ p = (struct pbuf *)pq_dequeue(xaxiemacif->recv_q);
+ return p;
+}
+
+/*
+ * xaxiemacif_output():
+ *
+ * This function is called by the TCP/IP stack when an IP packet
+ * should be sent. It calls the function called low_level_output() to
+ * do the actual transmission of the packet.
+ *
+ */
+
+static err_t xaxiemacif_output(struct netif *netif, struct pbuf *p,
+ const ip_addr_t *ipaddr)
+{
+ /* resolve hardware address, then send (or queue) packet */
+ return etharp_output(netif, p, ipaddr);
+}
+
+/*
+ * xaxiemacif_input():
+ *
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.
+ *
+ * Returns the number of packets read (max 1 packet on success,
+ * 0 if there are no packets)
+ *
+ */
+
+int xaxiemacif_input(struct netif *netif)
+{
+ struct eth_hdr *ethhdr;
+ struct pbuf *p;
+ SYS_ARCH_DECL_PROTECT(lev);
+
+#if !NO_SYS
+ while (1)
+#endif
+ {
+ /* move received packet into a new pbuf */
+ SYS_ARCH_PROTECT(lev);
+ p = low_level_input(netif);
+ SYS_ARCH_UNPROTECT(lev);
+
+ /* no packet could be read, silently ignore this */
+ if (p == NULL)
+ return 0;
+
+ /* points to packet payload, which starts with an Ethernet header */
+ ethhdr = p->payload;
+
+#if LINK_STATS
+ lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+ switch (htons(ethhdr->type)) {
+ /* IP or ARP packet? */
+ case ETHTYPE_IP:
+ case ETHTYPE_ARP:
+#if LWIP_IPV6
+ /*IPv6 Packet?*/
+ case ETHTYPE_IPV6:
+#endif
+#if PPPOE_SUPPORT
+ /* PPPoE packet? */
+ case ETHTYPE_PPPOEDISC:
+ case ETHTYPE_PPPOE:
+#endif /* PPPOE_SUPPORT */
+ /* full packet send to tcpip_thread to process */
+ if (netif->input(p, netif) != ERR_OK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xaxiemacif_input: IP input error\r\n"));
+ pbuf_free(p);
+ p = NULL;
+ }
+ break;
+
+ default:
+ pbuf_free(p);
+ p = NULL;
+ break;
+ }
+ }
+ return 1;
+}
+
+static err_t low_level_init(struct netif *netif)
+{
+ unsigned mac_address = (unsigned)(UINTPTR)(netif->state);
+ struct xemac_s *xemac;
+ xaxiemacif_s *xaxiemacif;
+ XAxiEthernet_Config *mac_config;
+
+ xaxiemacif = mem_malloc(sizeof *xaxiemacif);
+ if (xaxiemacif == NULL) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xaxiemacif_init: out of memory\r\n"));
+ return ERR_MEM;
+ }
+
+ xemac = mem_malloc(sizeof *xemac);
+ if (xemac == NULL) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xaxiemacif_init: out of memory\r\n"));
+ return ERR_MEM;
+ }
+
+ xemac->state = (void *)xaxiemacif;
+ xemac->topology_index = xtopology_find_index(mac_address);
+ xemac->type = xemac_type_axi_ethernet;
+
+ xaxiemacif->send_q = NULL;
+ xaxiemacif->recv_q = pq_create_queue();
+ if (!xaxiemacif->recv_q)
+ return ERR_MEM;
+
+ /* maximum transfer unit */
+#ifdef USE_JUMBO_FRAMES
+ netif->mtu = XAE_JUMBO_MTU - XAE_HDR_SIZE;
+#else
+ netif->mtu = XAE_MTU - XAE_HDR_SIZE;
+#endif
+
+#if LWIP_IGMP
+ netif->igmp_mac_filter = xaxiemacif_mac_filter_update;
+#endif
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+ netif->mld_mac_filter = xaxiemacif_mld6_mac_filter_update;
+#endif
+
+ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP |
+ NETIF_FLAG_LINK_UP;
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+ netif->flags |= NETIF_FLAG_MLD6;
+#endif
+
+#if LWIP_IGMP
+ netif->flags |= NETIF_FLAG_IGMP;
+#endif
+
+#if !NO_SYS
+ sys_sem_new(&xemac->sem_rx_data_available, 0);
+#endif
+
+ /* obtain config of this emac */
+ mac_config = xaxiemac_lookup_config((unsigned)(UINTPTR)netif->state);
+
+ XAxiEthernet_Initialize(&xaxiemacif->axi_ethernet, mac_config,
+ mac_config->BaseAddress);
+
+#ifdef XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT
+ enable_sgmii_clock(&xaxiemacif->axi_ethernet);
+#endif
+
+ /* figure out if the system has DMA */
+ if (XAxiEthernet_IsDma(&xaxiemacif->axi_ethernet)) {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_DMA
+ /* initialize the DMA engine */
+ init_axi_dma(xemac);
+#endif
+ } else if (XAxiEthernet_IsFifo(&xaxiemacif->axi_ethernet)) {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO
+ /* initialize the locallink FIFOs */
+ init_axi_fifo(xemac);
+#endif
+ } else if (XAxiEthernet_IsMcDma(&xaxiemacif->axi_ethernet)) {
+#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_MCDMA
+ /* Initialize MCDMA engine */
+ init_axi_mcdma(xemac);
+#endif
+ } else {
+ /* should not occur */
+ LWIP_DEBUGF(NETIF_DEBUG, ("xaxiemacif_init: mac is not configured with DMA, MCDMA or FIFO\r\n"));
+ return ERR_IF;
+ }
+
+ /* initialize the mac */
+ init_axiemac(xaxiemacif, netif);
+
+ /* replace the state in netif (currently the emac baseaddress)
+ * with the mac instance pointer.
+ */
+ netif->state = (void *)xemac;
+
+ return ERR_OK;
+}
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+static u8_t xaxiemacif_ip6_addr_ismulticast(ip6_addr_t* ip_addr)
+{
+ if(ip6_addr_ismulticast_linklocal(ip_addr)||
+ ip6_addr_ismulticast_iflocal(ip_addr) ||
+ ip6_addr_ismulticast_adminlocal(ip_addr)||
+ ip6_addr_ismulticast_sitelocal(ip_addr) ||
+ ip6_addr_ismulticast_orglocal(ip_addr) ||
+ ip6_addr_ismulticast_global(ip_addr)) {
+ /*Return TRUE if IPv6 is Multicast type*/
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+static void xaxiemacif_mld6_mac_hash_update (struct netif *netif, u8_t *ip_addr,
+ u8_t action,u8_t entry)
+{
+ u8_t multicast_mac_addr[6];
+ u8_t multicast_mac_addr_to_clr[6];
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+
+
+ if (action == NETIF_ADD_MAC_FILTER) {
+ /* Set Mulitcast mac address in hash table */
+ multicast_mac_addr[0] = LL_IP6_MULTICAST_ADDR_0;
+ multicast_mac_addr[1] = LL_IP6_MULTICAST_ADDR_1;
+ multicast_mac_addr[2] = ip_addr[12];
+ multicast_mac_addr[3] = ip_addr[13];
+ multicast_mac_addr[4] = ip_addr[14];
+ multicast_mac_addr[5] = ip_addr[15];
+
+ XAxiEthernet_Stop(&xaxiemacif->axi_ethernet);
+
+ XAxiEthernet_MulticastAdd(&xaxiemacif->axi_ethernet,multicast_mac_addr, entry);
+
+ XAxiEthernet_Start(&xaxiemacif->axi_ethernet);
+
+ } else if (action == NETIF_DEL_MAC_FILTER) {
+ /* Remove Mulitcast mac address in hash table */
+
+ XAxiEthernet_MulticastGet(&xaxiemacif->axi_ethernet,multicast_mac_addr_to_clr, entry);
+
+ XAxiEthernet_Stop(&xaxiemacif->axi_ethernet);
+
+ XAxiEthernet_MulticastClear(&xaxiemacif->axi_ethernet, entry);
+
+ XAxiEthernet_Start(&xaxiemacif->axi_ethernet);
+ }
+}
+static err_t
+xaxiemacif_mld6_mac_filter_update (struct netif *netif, ip_addr_t *group,
+ u8_t action)
+{
+ u8_t temp_mask;
+ unsigned int i;
+ u8_t entry;
+ u8_t * ip_addr = (u8_t *) group;
+
+ if(!(xaxiemacif_ip6_addr_ismulticast((ip6_addr_t*) ip_addr))) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: The requested MAC address is not a multicast address.\r\n", __func__)); LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast address add operation failure !!\r\n"));
+ return ERR_ARG;
+
+ }
+ if (action == NETIF_ADD_MAC_FILTER) {
+
+ for (i = 0; i < XAXIEMAC_MAX_MAC_ADDR; i++) {
+ temp_mask = (0x01) << i;
+ if ((xaxiemac_mld6_mcast_entry_mask & temp_mask) == temp_mask) {
+ continue;
+ }
+ entry = i;
+ xaxiemac_mld6_mcast_entry_mask |= temp_mask;
+
+ /* Update mac address in hash table */
+ xaxiemacif_mld6_mac_hash_update(netif, ip_addr, action,entry);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: Multicast MAC address successfully added.\r\n", __func__));
+
+ return ERR_OK;
+ }
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: No multicast address registers left.\r\n", __func__));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast MAC address add operation failure !!\r\n"));
+ return ERR_MEM;
+
+ } else if (action == NETIF_DEL_MAC_FILTER) {
+ for (i = 0; i < XAXIEMAC_MAX_MAC_ADDR; i++) {
+ temp_mask = (0x01) << i;
+ if ((xaxiemac_mld6_mcast_entry_mask & temp_mask) == temp_mask) {
+ entry = i;
+ xaxiemacif_mld6_mac_hash_update(netif, ip_addr,action, entry);
+
+ xaxiemac_mld6_mcast_entry_mask &= (~temp_mask);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: Multicast MAC address successfully removed.\r\n", __func__));
+
+ return ERR_OK;
+ } else {
+ continue;
+ }
+ }
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: No multicast address registers present with\r\n", __func__));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("the requested Multicast MAC address.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast MAC address removal failure!!.\r\n"));
+ return ERR_MEM;
+ }
+ return ERR_ARG;
+}
+#endif
+
+#if LWIP_IGMP
+static err_t
+xaxiemacif_mac_filter_update (struct netif *netif, ip_addr_t *group,
+ u8_t action)
+{
+ err_t return_val = ERR_OK;
+ u8_t multicast_mac_addr[6];
+ u8_t multicast_mac_addr_to_clr[6];
+ u8_t temp_mask;
+ int entry;
+ int i;
+ u8_t * ip_addr_temp = (u8_t *)group;
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+
+ if (action == IGMP_ADD_MAC_FILTER) {
+ if ((ip_addr_temp[0] >= 224) && (ip_addr_temp[0] <= 239)) {
+ if (xaxiemac_mcast_entry_mask >= 0x0F) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("xaxiemacif_mac_filter_update: No multicast address registers left.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ (" Multicast MAC address add operation failure !!\r\n"));
+
+ return_val = ERR_MEM;
+ } else {
+ for (i = 0; i < 4; i++) {
+ temp_mask = (0x01) << i;
+ if ((xaxiemac_mcast_entry_mask &
+ temp_mask) == temp_mask) {
+
+ continue;
+
+ } else {
+ entry = i;
+ xaxiemac_mcast_entry_mask
+ |= temp_mask;
+ multicast_mac_addr[0] = 0x01;
+ multicast_mac_addr[1] = 0x00;
+ multicast_mac_addr[2] = 0x5E;
+
+ multicast_mac_addr[3] =
+ ip_addr_temp[1] & 0x7F;
+ multicast_mac_addr[4] =
+ ip_addr_temp[2];
+ multicast_mac_addr[5] =
+ ip_addr_temp[3];
+
+ XAxiEthernet_Stop
+ (&xaxiemacif->axi_ethernet);
+
+ XAxiEthernet_MulticastAdd
+ (&xaxiemacif->axi_ethernet,
+ multicast_mac_addr,entry);
+
+ XAxiEthernet_Start
+ (&xaxiemacif->axi_ethernet);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("xaxiemacif_mac_filter_update: Multicast MAC address successfully added.\r\n"));
+
+ return_val = ERR_OK;
+ break;
+ }
+ }
+ if (i == 4) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("xaxiemacif_mac_filter_update: No multicast address registers left.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ (" Multicast MAC address add operation failure !!\r\n"));
+
+ return_val = ERR_MEM;
+ }
+ }
+ } else {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("xaxiemacif_mac_filter_update: The requested MAC address is not a multicast address.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ (" Multicast address add operation failure !!\r\n"));
+
+ return_val = ERR_ARG;
+ }
+ } else if (action == IGMP_DEL_MAC_FILTER) {
+ if ((ip_addr_temp[0] < 224) || (ip_addr_temp[0] > 239)) {
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("xaxiemacif_mac_filter_update: The requested MAC address is not a multicast address.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ (" Multicast address add operation failure !!\r\n"));
+
+ return_val = ERR_ARG;
+ } else {
+ for (i = 0; i < 4; i++) {
+ temp_mask = (0x01) << i;
+ if ((xaxiemac_mcast_entry_mask & temp_mask)
+ == temp_mask) {
+ XAxiEthernet_MulticastGet
+ (&xaxiemacif->axi_ethernet,
+ multicast_mac_addr_to_clr, i);
+
+ if ((ip_addr_temp[3] ==
+ multicast_mac_addr_to_clr[5]) &&
+ (ip_addr_temp[2] ==
+ multicast_mac_addr_to_clr[4]) &&
+ ((ip_addr_temp[1] & 0x7f) ==
+ multicast_mac_addr_to_clr[3])) {
+
+ XAxiEthernet_Stop
+ (&xaxiemacif->axi_ethernet);
+
+ XAxiEthernet_MulticastClear
+ (&xaxiemacif->axi_ethernet, i);
+
+ XAxiEthernet_Start
+ (&xaxiemacif->axi_ethernet);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("xaxiemacif_mac_filter_update: Multicast MAC address successfully removed.\r\n"));
+
+ return_val = ERR_OK;
+ xaxiemac_mcast_entry_mask &=
+ (~temp_mask);
+ break;
+ } else {
+ continue;
+ }
+ } else {
+ continue;
+ }
+ }
+ if (i == 4) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("xaxiemacif_mac_filter_update: No multicast address registers present with\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ (" the requested Multicast MAC address.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ (" Multicast MAC address removal failure!!.\r\n"));
+
+ return_val = ERR_MEM;
+ }
+ }
+ }
+ return return_val;
+}
+#endif
+
+/*
+ * xaxiemacif_init():
+ *
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ */
+
+err_t
+xaxiemacif_init(struct netif *netif)
+{
+#if LWIP_SNMP
+ /* ifType ethernetCsmacd(6) @see RFC1213 */
+ netif->link_type = 6;
+ /* your link speed here */
+ netif->link_speed = ;
+ netif->ts = 0;
+ netif->ifinoctets = 0;
+ netif->ifinucastpkts = 0;
+ netif->ifinnucastpkts = 0;
+ netif->ifindiscards = 0;
+ netif->ifoutoctets = 0;
+ netif->ifoutucastpkts = 0;
+ netif->ifoutnucastpkts = 0;
+ netif->ifoutdiscards = 0;
+#endif
+
+ netif->name[0] = IFNAME0;
+ netif->name[1] = IFNAME1;
+ netif->output = xaxiemacif_output;
+ netif->linkoutput = low_level_output;
+#if LWIP_IPV6
+ netif->output_ip6 = ethip6_output;
+#endif
+
+ low_level_init(netif);
+
+ return ERR_OK;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c
new file mode 100644
index 0000000..22a6a38
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c
@@ -0,0 +1,949 @@
+/*
+ * Copyright (C) 2010 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwipopts.h"
+
+#if !NO_SYS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "timers.h"
+#include "lwip/sys.h"
+#endif
+
+#include "lwip/stats.h"
+#include "lwip/inet_chksum.h"
+
+#include "netif/xadapter.h"
+#include "netif/xaxiemacif.h"
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#include "xscugic.h"
+#else
+#include "xintc_l.h"
+#endif
+
+#include "xstatus.h"
+
+#include "xlwipconfig.h"
+#include "xparameters.h"
+
+#ifdef CONFIG_XTRACE
+#include "xtrace.h"
+#endif
+
+#if defined __aarch64__
+#include "xil_mmu.h"
+#endif
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#ifndef XCACHE_FLUSH_DCACHE_RANGE
+#define XCACHE_FLUSH_DCACHE_RANGE(data, length) \
+ Xil_DCacheFlushRange((UINTPTR)data, length)
+#endif
+#ifndef XCACHE_INVALIDATE_DCACHE_RANGE
+#define XCACHE_INVALIDATE_DCACHE_RANGE(data, length) \
+ Xil_DCacheInvalidateRange((u32)data, length)
+#endif
+
+#endif
+
+/* Byte alignment of BDs */
+#define BD_ALIGNMENT (XAXIDMA_BD_MINIMUM_ALIGNMENT*2)
+
+#if XPAR_INTC_0_HAS_FAST == 1
+/*********** Function Prototypes *********************************************/
+/*
+ * Function prototypes of the functions used for registering Fast
+ * Interrupt Handlers
+ */
+static void axidma_sendfast_handler(void) __attribute__ ((fast_interrupt));
+static void axidma_recvfast_handler(void) __attribute__ ((fast_interrupt));
+static void xaxiemac_errorfast_handler(void) __attribute__ ((fast_interrupt));
+
+/**************** Variable Declarations **************************************/
+/** Variables for Fast Interrupt handlers ***/
+struct xemac_s *xemac_fast;
+xaxiemacif_s *xaxiemacif_fast;
+#endif
+
+#if !NO_SYS
+u32 xInsideISR = 0;
+#endif
+
+#if defined (__aarch64__) || defined (ARMR5)
+u8_t bd_space[0x200000] __attribute__ ((aligned (0x200000)));
+#endif
+
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+volatile u32_t notifyinfo[XLWIP_CONFIG_N_TX_DESC];
+#endif
+
+#define XAxiDma_BD_TO_INDEX(ringptr, bdptr) \
+ (((UINTPTR)bdptr - (UINTPTR)(ringptr)->FirstBdAddr) / (ringptr)->Separation)
+
+static inline void bd_csum_enable(XAxiDma_Bd *bd)
+{
+ XAxiDma_BdWrite((bd), XAXIDMA_BD_USR0_OFFSET,
+ (XAxiDma_BdRead((bd), XAXIDMA_BD_USR0_OFFSET)
+ | 1));
+}
+
+static inline void bd_csum_disable(XAxiDma_Bd *bd)
+{
+ XAxiDma_BdWrite((bd), XAXIDMA_BD_USR0_OFFSET,
+ (XAxiDma_BdRead((bd), XAXIDMA_BD_USR0_OFFSET)
+ & ~1));
+}
+
+static inline void bd_fullcsum_disable(XAxiDma_Bd *bd)
+{
+ XAxiDma_BdWrite((bd), XAXIDMA_BD_USR0_OFFSET,
+ (XAxiDma_BdRead((bd), XAXIDMA_BD_USR0_OFFSET)
+ & ~3));
+}
+
+static inline void bd_fullcsum_enable(XAxiDma_Bd *bd)
+{
+ XAxiDma_BdWrite((bd), XAXIDMA_BD_USR0_OFFSET,
+ (XAxiDma_BdRead((bd), XAXIDMA_BD_USR0_OFFSET)
+ | 2));
+}
+
+static inline void bd_csum_set(XAxiDma_Bd *bd, u16_t tx_csbegin, u16_t tx_csinsert,
+ u16_t tx_csinit)
+{
+ u32_t app1;
+
+ bd_csum_enable(bd);
+
+ /* write start offset and insert offset into BD */
+ app1 = ((u32_t)tx_csbegin << 16) | (u32_t) tx_csinsert;
+ XAxiDma_BdWrite(bd, XAXIDMA_BD_USR1_OFFSET, app1);
+
+ /* insert init value */
+ XAxiDma_BdWrite(bd, XAXIDMA_BD_USR2_OFFSET, tx_csinit);
+}
+
+static inline u16_t extract_packet_len(XAxiDma_Bd *rxbd) {
+ u16_t packet_len = XAxiDma_BdRead(rxbd, XAXIDMA_BD_USR4_OFFSET) & 0x3fff;
+ return packet_len;
+}
+
+static inline u16_t extract_csum(XAxiDma_Bd *rxbd) {
+ u16_t csum = XAxiDma_BdRead(rxbd, XAXIDMA_BD_USR3_OFFSET) & 0xffff;
+ return csum;
+}
+
+static inline u32_t csum_sub(u32_t csum, u16_t v)
+{
+ csum += (u32_t)v;
+ return csum + (csum < (u32_t)v);
+}
+
+/*
+ * compare if the h/w computed checksum (stored in the rxbd)
+ * equals the TCP checksum value in the packet
+ */
+s32_t is_checksum_valid(XAxiDma_Bd *rxbd, struct pbuf *p) {
+ struct ethip_hdr *ehdr = p->payload;
+ u8_t proto = IPH_PROTO(&ehdr->ip);
+
+ /* check if it is a TCP packet */
+ if (htons(ehdr->eth.type) == ETHTYPE_IP && proto == IP_PROTO_TCP) {
+ u32_t iphdr_len;
+ u16_t csum_in_rxbd, pseudo_csum, iphdr_csum, padding_csum;
+ u16_t tcp_payload_offset;
+ u32_t computed_csum;
+ u16_t padding_len, tcp_payload_len, packet_len;
+ u16_t csum;
+
+ /* determine length of IP header */
+ iphdr_len = (IPH_HL(&ehdr->ip) * 4);
+ tcp_payload_offset = XAE_HDR_SIZE + iphdr_len;
+ tcp_payload_len = htons(IPH_LEN(&ehdr->ip)) - IPH_HL(&ehdr->ip) * 4;
+ packet_len = extract_packet_len(rxbd);
+ padding_len = packet_len - tcp_payload_offset - tcp_payload_len;
+
+ csum_in_rxbd = extract_csum(rxbd);
+ pseudo_csum = htons(inet_chksum_pseudo(NULL,
+ proto, tcp_payload_len, (ip_addr_t *)&ehdr->ip.src,
+ (ip_addr_t *)&ehdr->ip.dest));
+
+ /* xps_ll_temac computes the checksum of the packet starting at byte 14
+ * we need to subtract the values of the ethernet & IP headers
+ */
+ iphdr_csum = inet_chksum(p->payload + 14, tcp_payload_offset - 14);
+
+ /* compute csum of padding bytes, if any */
+ padding_csum = inet_chksum(p->payload + p->tot_len - padding_len,
+ padding_len);
+
+ /* get the h/w checksum value */
+ computed_csum = (u32_t)csum_in_rxbd;
+
+ /* remove the effect of csumming the iphdr */
+ computed_csum = csum_sub(computed_csum, ~iphdr_csum);
+
+ /* add in the pseudo csum */
+ computed_csum = csum_sub(computed_csum, ~pseudo_csum);
+
+ /* remove any padding effect */
+ computed_csum = csum_sub(computed_csum, ~padding_csum);
+
+ /* normalize computed csum */
+ while (computed_csum >> 16) {
+ computed_csum = (computed_csum & 0xffff) + (computed_csum >> 16);
+ }
+
+ /* convert to 16 bits and take 1's complement */
+ csum = (u16_t)computed_csum;
+ csum = ~csum;
+
+ /* chksum is valid if: computed csum over the packet is 0 */
+ return !csum;
+ } else {
+ /* just say yes to all other packets */
+ /* the upper layers in the stack will compute and verify the checksum */
+ return 1;
+ }
+}
+
+static inline void *alloc_bdspace(int n_desc)
+{
+ int space = XAxiDma_BdRingMemCalc(BD_ALIGNMENT, n_desc);
+ int padding = BD_ALIGNMENT*2;
+ void *unaligned_mem = mem_malloc(space + padding*4);
+ void *aligned_mem =
+ (void *)(((UINTPTR)(unaligned_mem + BD_ALIGNMENT)) & ~(BD_ALIGNMENT - 1));
+
+#if DEBUG
+ assert(aligned_mem > unaligned_mem);
+ assert(aligned_mem + space < unaligned_mem + space + padding);
+#endif
+ return aligned_mem;
+}
+
+static void axidma_send_handler(void *arg)
+{
+ unsigned irq_status;
+ struct xemac_s *xemac;
+ xaxiemacif_s *xaxiemacif;
+ XAxiDma_BdRing *txringptr;
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+ xemac = (struct xemac_s *)(arg);
+ xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ txringptr = XAxiDma_GetTxRing(&xaxiemacif->axidma);
+
+ XAxiDma_BdRingIntDisable(txringptr, XAXIDMA_IRQ_ALL_MASK);
+
+ /* Read pending interrupts */
+ irq_status = XAxiDma_BdRingGetIrq(txringptr);
+
+ /* Acknowledge pending interrupts */
+ XAxiDma_BdRingAckIrq(txringptr, irq_status);
+
+ /* If error interrupt is asserted, raise error flag, reset the
+ * hardware to recover from the error, and return with no further
+ * processing.
+ */
+ if (irq_status & XAXIDMA_IRQ_ERROR_MASK) {
+ xil_printf("%s: Error: axidma error interrupt is asserted\r\n",
+ __FUNCTION__);
+ XAxiDma_Reset(&xaxiemacif->axidma);
+#if !NO_SYS
+ xInsideISR--;
+#endif
+ return;
+ }
+ /* If Transmit done interrupt is asserted, process completed BD's */
+ if (irq_status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)) {
+ process_sent_bds(txringptr);
+ }
+
+ XAxiDma_BdRingIntEnable(txringptr, XAXIDMA_IRQ_ALL_MASK);
+
+#if !NO_SYS
+ xInsideISR--;
+#endif
+}
+
+static void setup_rx_bds(XAxiDma_BdRing *rxring)
+{
+ XAxiDma_Bd *rxbd;
+ s32_t n_bds;
+ XStatus status;
+ struct pbuf *p;
+ u32 bdsts;
+
+ n_bds = XAxiDma_BdRingGetFreeCnt(rxring);
+ while (n_bds > 0) {
+ n_bds--;
+#ifdef USE_JUMBO_FRAMES
+ p = pbuf_alloc(PBUF_RAW, XAE_MAX_JUMBO_FRAME_SIZE, PBUF_POOL);
+#else
+ p = pbuf_alloc(PBUF_RAW, XAE_MAX_FRAME_SIZE, PBUF_POOL);
+#endif
+ if (!p) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ printf("unable to alloc pbuf in recv_handler\r\n");
+ return;
+ }
+ status = XAxiDma_BdRingAlloc(rxring, 1, &rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("setup_rx_bds: Error allocating RxBD\r\n"));
+ pbuf_free(p);
+ return;
+ }
+ /* Setup the BD. */
+ XAxiDma_BdSetBufAddr(rxbd, (UINTPTR)p->payload);
+ /* Clear everything but the COMPLETE bit, which is cleared when
+ * committed to hardware.
+ */
+ bdsts = XAxiDma_BdGetSts(rxbd);
+ bdsts &= XAXIDMA_BD_STS_COMPLETE_MASK;
+ XAxiDma_BdWrite(rxbd, XAXIDMA_BD_STS_OFFSET, bdsts);
+ XAxiDma_BdSetLength(rxbd, p->len, rxring->MaxTransferLen);
+ XAxiDma_BdSetCtrl(rxbd, 0);
+ XAxiDma_BdSetId(rxbd, p);
+#if !defined (__MICROBLAZE__)
+ dsb();
+#endif
+#ifdef USE_JUMBO_FRAMES
+ XCACHE_FLUSH_DCACHE_RANGE((UINTPTR)p->payload, (UINTPTR)XAE_MAX_JUMBO_FRAME_SIZE);
+#else
+ XCACHE_FLUSH_DCACHE_RANGE((UINTPTR)p->payload, (UINTPTR)XAE_MAX_FRAME_SIZE);
+#endif
+#if !defined(__aarch64__)
+ XCACHE_FLUSH_DCACHE_RANGE(rxbd, sizeof *rxbd);
+#endif
+
+ /* Enqueue to HW */
+ status = XAxiDma_BdRingToHw(rxring, 1, rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error committing RxBD to hardware: "));
+ if (status == XST_DMA_SG_LIST_ERROR) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with XAxiDma_BdRingAlloc()\r\n"));
+ }
+ else {
+ LWIP_DEBUGF(NETIF_DEBUG, ("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n"));
+ }
+ pbuf_free(p);
+ XAxiDma_BdRingUnAlloc(rxring, 1, rxbd);
+ return;
+ }
+ }
+}
+
+static void axidma_recv_handler(void *arg)
+{
+ struct pbuf *p;
+ u32 irq_status, i, timeOut;
+ XAxiDma_Bd *rxbd, *rxbdset;
+ struct xemac_s *xemac;
+ xaxiemacif_s *xaxiemacif;
+ XAxiDma_BdRing *rxring;
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+
+ xemac = (struct xemac_s *)(arg);
+ xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ rxring = XAxiDma_GetRxRing(&xaxiemacif->axidma);
+
+ XAxiDma_BdRingIntDisable(rxring, XAXIDMA_IRQ_ALL_MASK);
+
+ /* Read pending interrupts */
+ irq_status = XAxiDma_BdRingGetIrq(rxring);
+
+ /* Acknowledge pending interrupts */
+ XAxiDma_BdRingAckIrq(rxring, irq_status);
+
+ /* If error interrupt is asserted, raise error flag, reset the
+ * hardware to recover from the error, and return with no further
+ * processing.
+ */
+ if ((irq_status & XAXIDMA_IRQ_ERROR_MASK)) {
+ setup_rx_bds(rxring);
+ xil_printf("%s: Error: axidma error interrupt is asserted\r\n",
+ __FUNCTION__);
+ XAxiDma_Reset(&xaxiemacif->axidma);
+ timeOut = 10000;
+ while (timeOut) {
+ if (XAxiDma_ResetIsDone(&xaxiemacif->axidma)) {
+ break;
+ }
+ timeOut -= 1;
+ }
+ XAxiDma_BdRingIntEnable(rxring, XAXIDMA_IRQ_ALL_MASK);
+ XAxiDma_Resume(&xaxiemacif->axidma);
+#if !NO_SYS
+ xInsideISR--;
+#endif
+ return;
+ }
+ /* If Reception done interrupt is asserted, call RX call back function
+ * to handle the processed BDs and then raise the according flag.
+ */
+ if (irq_status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)) {
+ u32 bd_processed;
+ u32 rx_bytes;
+
+ bd_processed = XAxiDma_BdRingFromHw(rxring, XAXIDMA_ALL_BDS, &rxbdset);
+
+ for (i = 0, rxbd = rxbdset; i < bd_processed; i++) {
+ p = (struct pbuf *)(UINTPTR)XAxiDma_BdGetId(rxbd);
+ /* Adjust the buffer size to the actual number of bytes received.*/
+ rx_bytes = extract_packet_len(rxbd);
+ pbuf_realloc(p, rx_bytes);
+
+#if defined(__aarch64__)
+#ifdef USE_JUMBO_FRAMES
+ XCACHE_INVALIDATE_DCACHE_RANGE(p->payload,
+ XAE_MAX_JUMBO_FRAME_SIZE);
+#else
+ XCACHE_INVALIDATE_DCACHE_RANGE(p->payload, XAE_MAX_FRAME_SIZE);
+#endif
+#endif
+
+#if LWIP_PARTIAL_CSUM_OFFLOAD_RX==1
+ /* Verify for partial checksum offload case */
+ if (!is_checksum_valid(rxbd, p)) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Incorrect csum as calculated by the hw\r\n"));
+ }
+#endif
+ /* store it in the receive queue,
+ * where it'll be processed by a different handler
+ */
+ if (pq_enqueue(xaxiemacif->recv_q, (void*)p) < 0) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ pbuf_free(p);
+ }
+ rxbd = (XAxiDma_Bd *)XAxiDma_BdRingNext(rxring, rxbd);
+ }
+ /* free up the BD's */
+ XAxiDma_BdRingFree(rxring, bd_processed, rxbdset);
+ /* return all the processed bd's back to the stack */
+ /* setup_rx_bds -> use XAxiDma_BdRingGetFreeCnt */
+ setup_rx_bds(rxring);
+ }
+ XAxiDma_BdRingIntEnable(rxring, XAXIDMA_IRQ_ALL_MASK);
+#if !NO_SYS
+ sys_sem_signal(&xemac->sem_rx_data_available);
+ xInsideISR--;
+#endif
+
+}
+
+s32_t is_tx_space_available(xaxiemacif_s *emac)
+{
+ XAxiDma_BdRing *txring;
+
+ txring = XAxiDma_GetTxRing(&emac->axidma);
+ /* tx space is available as long as there are valid BD's */
+ return XAxiDma_BdRingGetFreeCnt(txring);
+}
+
+s32_t process_sent_bds(XAxiDma_BdRing *txring)
+{
+ XAxiDma_Bd *txbdset, *txbd;
+ int n_bds, i;
+ u32_t bdindex;
+
+ /* obtain a list of processed BD's */
+ n_bds = XAxiDma_BdRingFromHw(txring, XAXIDMA_ALL_BDS, &txbdset);
+ if (n_bds == 0) {
+ return XST_FAILURE;
+ }
+ /* free the pbuf associated with each BD */
+ for (i = 0, txbd = txbdset; i < n_bds; i++) {
+ bdindex = XAxiDma_BD_TO_INDEX(txring, txbd);
+ struct pbuf *p = (struct pbuf *)(UINTPTR)XAxiDma_BdGetId(txbd);
+ pbuf_free(p);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ notifyinfo[bdindex] = 0;
+#endif
+ txbd = (XAxiDma_Bd *)XAxiDma_BdRingNext(txring, txbd);
+ }
+ /* free the processed BD's */
+ return (XAxiDma_BdRingFree(txring, n_bds, txbdset));
+}
+
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+XStatus axidma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p,
+ u32_t block_till_tx_complete, u32_t *to_block_index)
+#else
+XStatus axidma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p)
+#endif
+{
+ struct pbuf *q;
+ s32_t n_pbufs;
+ XAxiDma_Bd *txbdset, *txbd, *last_txbd = NULL;
+ XStatus status;
+ XAxiDma_BdRing *txring;
+ u32_t max_frame_size;
+ u32_t bdindex = 0;
+
+#ifdef USE_JUMBO_FRAMES
+ max_frame_size = XAE_MAX_JUMBO_FRAME_SIZE - 18;
+#else
+ max_frame_size = XAE_MAX_FRAME_SIZE - 18;
+#endif
+ txring = XAxiDma_GetTxRing(&xaxiemacif->axidma);
+
+ /* first count the number of pbufs */
+ for (q = p, n_pbufs = 0; q != NULL; q = q->next)
+ n_pbufs++;
+
+ /* obtain as many BD's */
+ status = XAxiDma_BdRingAlloc(txring, n_pbufs, &txbdset);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
+ return ERR_IF;
+ }
+
+ for(q = p, txbd = txbdset; q != NULL; q = q->next) {
+ bdindex = XAxiDma_BD_TO_INDEX(txring, txbd);
+ /* Send the data from the pbuf to the interface, one pbuf at a
+ * time. The size of the data in each pbuf is kept in the ->len
+ * variable.
+ */
+ XAxiDma_BdSetBufAddr(txbd, (UINTPTR)q->payload);
+ if (q->len > max_frame_size) {
+ XAxiDma_BdSetLength(txbd, max_frame_size,
+ txring->MaxTransferLen);
+ }
+ else {
+ XAxiDma_BdSetLength(txbd, q->len, txring->MaxTransferLen);
+ }
+ XAxiDma_BdSetId(txbd, (void *)q);
+ XAxiDma_BdSetCtrl(txbd, 0);
+ XCACHE_FLUSH_DCACHE_RANGE(q->payload, q->len);
+
+ pbuf_ref(q);
+
+ last_txbd = txbd;
+ txbd = (XAxiDma_Bd *)XAxiDma_BdRingNext(txring, txbd);
+ }
+
+ if (n_pbufs == 1) {
+ XAxiDma_BdSetCtrl(txbdset, XAXIDMA_BD_CTRL_TXSOF_MASK
+ | XAXIDMA_BD_CTRL_TXEOF_MASK);
+ } else {
+ /* in the first packet, set the SOP */
+ XAxiDma_BdSetCtrl(txbdset, XAXIDMA_BD_CTRL_TXSOF_MASK);
+ /* in the last packet, set the EOP */
+ XAxiDma_BdSetCtrl(last_txbd, XAXIDMA_BD_CTRL_TXEOF_MASK);
+ }
+
+#if LWIP_FULL_CSUM_OFFLOAD_TX==1
+ bd_fullcsum_disable(txbdset);
+ if (p->len > sizeof(struct ethip_hdr)) {
+ bd_fullcsum_enable(txbdset);
+ }
+#endif
+#if LWIP_PARTIAL_CSUM_OFFLOAD_TX==1
+ bd_csum_disable(txbdset);
+ if (p->len > sizeof(struct ethip_hdr)) {
+ struct ethip_hdr *ehdr = p->payload;
+ u8_t proto = IPH_PROTO(&ehdr->ip);
+
+ /* check if it is a TCP packet */
+ if (htons(ehdr->eth.type) == ETHTYPE_IP && proto ==
+ IP_PROTO_TCP) {
+ u32_t iphdr_len, csum_insert_offset;
+ u16_t tcp_len; /* TCP header length + data length in bytes */
+ u16_t csum_init = 0;
+ u16_t tcp_payload_offset;
+
+ /* determine length of IP header */
+ iphdr_len = (IPH_HL(&ehdr->ip) * 4);
+
+ tcp_payload_offset = XAE_HDR_SIZE + iphdr_len;
+ tcp_len = p->tot_len - tcp_payload_offset;
+
+ /* insert checksum at offset 16 for TCP, 6 for UDP */
+ if (proto == IP_PROTO_TCP)
+ csum_insert_offset = tcp_payload_offset + 16;
+ else if (proto == IP_PROTO_UDP)
+ csum_insert_offset = tcp_payload_offset + 6;
+ else
+ csum_insert_offset = 0;
+ /* compute pseudo header checksum value */
+ csum_init = inet_chksum_pseudo(NULL,
+ (ip_addr_t *)&ehdr->ip.src,
+ (ip_addr_t *)&ehdr->ip.dest, proto, tcp_len);
+ /* init buffer descriptor */
+ bd_csum_set(txbdset, tcp_payload_offset,
+ csum_insert_offset, htons(~csum_init));
+ }
+ }
+#endif
+
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (block_till_tx_complete == 1) {
+ notifyinfo[bdindex] = 1;
+ *to_block_index = bdindex;
+ }
+#endif
+
+ /* enq to h/w */
+ return XAxiDma_BdRingToHw(txring, n_pbufs, txbdset);
+}
+
+XStatus init_axi_dma(struct xemac_s *xemac)
+{
+ XAxiDma_Config *dmaconfig;
+ XAxiDma_Bd bdtemplate;
+ XAxiDma_BdRing *rxringptr, *txringptr;
+ XAxiDma_Bd *rxbd;
+ struct pbuf *p;
+ XStatus status;
+ u32_t i;
+ UINTPTR baseaddr;
+
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+
+#if XPAR_INTC_0_HAS_FAST == 1
+ xaxiemacif_fast = xaxiemacif;
+ xemac_fast = xemac;
+#endif
+#if NO_SYS
+ struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
+#endif
+#if !NO_SYS
+ struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
+#endif
+
+ /* FIXME: On ZyqnMP Multiple Axi Ethernet are not supported */
+#if defined (__aarch64__) || defined (ARMR5)
+ xaxiemacif->rx_bdspace = (void *)(UINTPTR)&(bd_space[0]);;
+ xaxiemacif->tx_bdspace = (void *)(UINTPTR)&(bd_space[0x10000]);
+#endif
+
+#if !defined (__aarch64__) && !defined (ARMR5)
+ xaxiemacif->rx_bdspace = alloc_bdspace(XLWIP_CONFIG_N_RX_DESC);
+ xaxiemacif->tx_bdspace = alloc_bdspace(XLWIP_CONFIG_N_TX_DESC);
+#endif
+
+ /* For A53 case Mark the BD Region as uncaheable */
+#if defined(__aarch64__)
+ Xil_SetTlbAttributes((UINTPTR)xaxiemacif->tx_bdspace, NORM_NONCACHE | INNER_SHAREABLE);
+ Xil_SetTlbAttributes((UINTPTR)xaxiemacif->rx_bdspace, NORM_NONCACHE | INNER_SHAREABLE);
+#endif
+
+
+ LWIP_DEBUGF(NETIF_DEBUG, ("rx_bdspace: 0x%08x\r\n",
+ xaxiemacif->rx_bdspace));
+ LWIP_DEBUGF(NETIF_DEBUG, ("tx_bdspace: 0x%08x\r\n",
+ xaxiemacif->tx_bdspace));
+
+ if (!xaxiemacif->rx_bdspace || !xaxiemacif->tx_bdspace) {
+ xil_printf("%s@%d: Error: Unable to allocate memory for RX buffer descriptors",
+ __FILE__, __LINE__);
+ return ERR_IF;
+ }
+ /* initialize DMA */
+ baseaddr = xaxiemacif->axi_ethernet.Config.AxiDevBaseAddress;
+ dmaconfig = XAxiDma_LookupConfigBaseAddr(baseaddr);
+ XAxiDma_CfgInitialize(&xaxiemacif->axidma, dmaconfig);
+
+ rxringptr = XAxiDma_GetRxRing(&xaxiemacif->axidma);
+ txringptr = XAxiDma_GetTxRing(&xaxiemacif->axidma);
+ LWIP_DEBUGF(NETIF_DEBUG, ("rxringptr: 0x%08x\r\n", rxringptr));
+ LWIP_DEBUGF(NETIF_DEBUG, ("txringptr: 0x%08x\r\n", txringptr));
+
+ /* Setup RxBD space.
+ * Setup a BD template for the Rx channel. This template will be copied to
+ * every RxBD. We will not have to explicitly set these again.
+ */
+ XAxiDma_BdClear(&bdtemplate);
+ /* Create the RxBD ring */
+ status = XAxiDma_BdRingCreate(rxringptr, (UINTPTR) xaxiemacif->rx_bdspace,
+ (UINTPTR) xaxiemacif->rx_bdspace, BD_ALIGNMENT,
+ XLWIP_CONFIG_N_RX_DESC);
+
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error setting up RxBD space\r\n"));
+ return ERR_IF;
+ }
+ XAxiDma_BdClear(&bdtemplate);
+ status = XAxiDma_BdRingClone(rxringptr, &bdtemplate);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error initializing RxBD space\r\n"));
+ return ERR_IF;
+ }
+ /* Create the TxBD ring */
+ status = XAxiDma_BdRingCreate(txringptr, (UINTPTR) xaxiemacif->tx_bdspace,
+ (UINTPTR) xaxiemacif->tx_bdspace, BD_ALIGNMENT,
+ XLWIP_CONFIG_N_TX_DESC);
+ if (status != XST_SUCCESS) {
+ return ERR_IF;
+ }
+ /* We reuse the bd template, as the same one will work for both rx and tx. */
+ status = XAxiDma_BdRingClone(txringptr, &bdtemplate);
+ if (status != XST_SUCCESS) {
+ return ERR_IF;
+ }
+ /* Allocate RX descriptors, 1 RxBD at a time.*/
+ for (i = 0; i < XLWIP_CONFIG_N_RX_DESC; i++) {
+ status = XAxiDma_BdRingAlloc(rxringptr, 1, &rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("init_axi_dma: Error allocating RxBD\r\n"));
+ return ERR_IF;
+ }
+#ifdef USE_JUMBO_FRAMES
+ p = pbuf_alloc(PBUF_RAW, XAE_MAX_JUMBO_FRAME_SIZE, PBUF_POOL);
+#else
+ p = pbuf_alloc(PBUF_RAW, XAE_MAX_FRAME_SIZE, PBUF_POOL);
+#endif
+ if (!p) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ LWIP_DEBUGF(NETIF_DEBUG, ("unable to alloc pbuf in recv_handler\r\n"));
+ return ERR_IF;
+ }
+ /* Setup the BD. The BD template used in the call to
+ * XAxiEthernet_SgSetSpace() set the "last" field of all RxBDs.
+ * Therefore we are not required to issue a XAxiDma_Bd_SetLast(rxbd)
+ * here.
+ */
+ XAxiDma_BdSetBufAddr(rxbd, (UINTPTR)p->payload);
+ XAxiDma_BdSetLength(rxbd, p->len, rxringptr->MaxTransferLen);
+ XAxiDma_BdSetCtrl(rxbd, 0);
+ XAxiDma_BdSetId(rxbd, p);
+#ifdef USE_JUMBO_FRAMES
+ XCACHE_FLUSH_DCACHE_RANGE((UINTPTR)p->payload, (UINTPTR)XAE_MAX_JUMBO_FRAME_SIZE);
+#else
+ XCACHE_FLUSH_DCACHE_RANGE((UINTPTR)p->payload, (UINTPTR)XAE_MAX_FRAME_SIZE);
+#endif
+#if !defined(__aarch64__)
+ XCACHE_FLUSH_DCACHE_RANGE(rxbd, sizeof *rxbd);
+#endif
+
+ /* Enqueue to HW */
+ status = XAxiDma_BdRingToHw(rxringptr, 1, rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error: committing RxBD to HW\r\n"));
+ return ERR_IF;
+ }
+ }
+
+ status = XAxiDma_BdRingSetCoalesce(txringptr, XLWIP_CONFIG_N_TX_COALESCE,
+ 0x1);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error setting coalescing settings\r\n"));
+ return ERR_IF;
+ }
+ status = XAxiDma_BdRingSetCoalesce(rxringptr, XLWIP_CONFIG_N_RX_COALESCE,
+ 0x1);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error setting coalescing settings\r\n"));
+ return ERR_IF;
+ }
+ /* start DMA */
+ status = XAxiDma_BdRingStart(txringptr);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error: failed to start TX BD ring\r\n"));
+ return ERR_IF;
+ }
+ status = XAxiDma_BdRingStart(rxringptr);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error: failed to start RX BD ring\r\n"));
+ return ERR_IF;
+ }
+ /* enable DMA interrupts */
+ XAxiDma_BdRingIntEnable(txringptr, XAXIDMA_IRQ_ALL_MASK);
+ XAxiDma_BdRingIntEnable(rxringptr, XAXIDMA_IRQ_ALL_MASK);
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (Xil_ExceptionHandler)xaxiemac_error_handler,
+ &xaxiemacif->axi_ethernet);
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr,
+ (Xil_ExceptionHandler)axidma_send_handler,
+ xemac);
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr,
+ (Xil_ExceptionHandler)axidma_recv_handler,
+ xemac);
+
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ AXIETH_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr,
+ AXIDMA_TX_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr,
+ AXIDMA_RX_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.TemacIntr);
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr);
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr);
+#else
+#if NO_SYS
+#if XPAR_INTC_0_HAS_FAST == 1
+
+ /* Register axiethernet interrupt with interrupt controller as Fast
+ Interrupts */
+
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XFastInterruptHandler)xaxiemac_errorfast_handler);
+
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr,
+ (XFastInterruptHandler)axidma_sendfast_handler);
+
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr,
+ (XFastInterruptHandler)axidma_recvfast_handler);
+#else
+ /* Register axiethernet interrupt with interrupt controller */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XInterruptHandler)xaxiemac_error_handler,
+ &xaxiemacif->axi_ethernet);
+ /* connect & enable DMA interrupts */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr,
+ (XInterruptHandler)axidma_send_handler,
+ xemac);
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr,
+ (XInterruptHandler)axidma_recv_handler,
+ xemac);
+#endif
+ /* Enable EMAC interrupts in the interrupt controller */
+ do {
+ /* read current interrupt enable mask */
+ unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr +
+ XIN_IER_OFFSET);
+
+ /* form new mask enabling AXIDMA & axiethernet interrupts */
+ cur_mask = cur_mask
+ | (1 << xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr)
+ | (1 << xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr)
+ | (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
+
+ /* set new mask */
+ XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
+ } while (0);
+#else
+#if XPAR_INTC_0_HAS_FAST == 1
+
+ /* Register axiethernet interrupt with interrupt controller as Fast
+ Interrupts */
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XFastInterruptHandler)xaxiemac_errorfast_handler);
+
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr,
+ (XFastInterruptHandler)axidma_sendfast_handler);
+
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr,
+ (XFastInterruptHandler)axidma_recvfast_handler);
+#else
+ /* Register axiethernet interrupt with interrupt controller */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XInterruptHandler)xaxiemac_error_handler,
+ &xaxiemacif->axi_ethernet);
+ /* connect & enable DMA interrupts */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr,
+ (XInterruptHandler)axidma_send_handler,
+ xemac);
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr,
+ (XInterruptHandler)axidma_recv_handler,
+ xemac);
+#endif
+ /* Enable EMAC interrupts in the interrupt controller */
+ do {
+ /* read current interrupt enable mask */
+ unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr +
+ XIN_IER_OFFSET);
+
+ /* form new mask enabling AXIDMA & axiethernet interrupts */
+ cur_mask = cur_mask
+ | (1 << xaxiemacif->axi_ethernet.Config.AxiDmaTxIntr)
+ | (1 << xaxiemacif->axi_ethernet.Config.AxiDmaRxIntr)
+ | (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
+
+ /* set new mask */
+ XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
+ } while (0);
+#endif
+#endif
+ return 0;
+}
+
+#if XPAR_INTC_0_HAS_FAST == 1
+/****************************** Fast receive Handler *************************/
+static void axidma_recvfast_handler(void)
+{
+ axidma_recv_handler((void *)xemac_fast);
+}
+
+/****************************** Fast Send Handler ****************************/
+static void axidma_sendfast_handler(void)
+{
+ axidma_send_handler((void *)xemac_fast);
+}
+
+/****************************** Fast Error Handler ***************************/
+static void xaxiemac_errorfast_handler(void)
+{
+ xaxiemac_error_handler(&xaxiemacif_fast->axi_ethernet);
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c
new file mode 100644
index 0000000..6af0280
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2010 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwipopts.h"
+
+#if !NO_SYS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "timers.h"
+#include "lwip/sys.h"
+#endif
+
+#include "lwip/stats.h"
+#include "netif/xadapter.h"
+#include "netif/xaxiemacif.h"
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#include "xscugic.h"
+#else
+#include "xintc_l.h"
+#endif
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#define AXIFIFO_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define AXIETH_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define TRIG_TYPE_RISING_EDGE_SENSITIVE 0x3
+#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_DIST_BASEADDR
+#endif
+
+#include "xstatus.h"
+
+#include "xaxiemacif_fifo.h"
+
+#include "xlwipconfig.h"
+
+#if XPAR_INTC_0_HAS_FAST == 1
+/*********** Function Prototypes *********************************************/
+
+/*
+ * Function prototypes of the functions used for registering Fast
+ * Interrupt Handlers
+ */
+static void xllfifo_fastintr_handler(void) __attribute__ ((fast_interrupt));
+static void xaxiemac_fasterror_handler(void) __attribute__ ((fast_interrupt));
+
+/**************** Variable Declarations **************************************/
+
+/** Variables for Fast Interrupt handlers ***/
+struct xemac_s *xemac_fast;
+xaxiemacif_s *xaxiemacif_fast;
+#endif
+
+#if !NO_SYS
+unsigned int xInsideISR = 0;
+#endif
+
+int is_tx_space_available(xaxiemacif_s *emac)
+{
+ return ((XLlFifo_TxVacancy(&emac->axififo) * 4) > XAE_MAX_FRAME_SIZE);
+}
+
+static void
+xllfifo_recv_handler(struct xemac_s *xemac)
+{
+ u32_t frame_length;
+ struct pbuf *p;
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ XLlFifo *llfifo = &xaxiemacif->axififo;
+
+ /* While there is data in the fifo ... */
+ while (XLlFifo_RxOccupancy(llfifo)) {
+ /* find packet length */
+ frame_length = XLlFifo_RxGetLen(llfifo);
+
+ /* allocate a pbuf */
+ p = pbuf_alloc(PBUF_RAW, frame_length, PBUF_POOL);
+ if (!p) {
+ char tmp_frame[XAE_MAX_FRAME_SIZE];
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ /* receive and drop packet to keep data & len registers in sync */
+ XLlFifo_Read(llfifo, tmp_frame, frame_length);
+
+ continue;
+ }
+
+ /* receive packet */
+ XLlFifo_Read(llfifo, p->payload, frame_length);
+
+#if ETH_PAD_SIZE
+ len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
+#endif
+
+ /* store it in the receive queue, where it'll be processed by xemacif input thread */
+ if (pq_enqueue(xaxiemacif->recv_q, (void*)p) < 0) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ pbuf_free(p);
+ continue;
+ }
+
+#if !NO_SYS
+ sys_sem_signal(&xemac->sem_rx_data_available);
+#endif
+
+#if LINK_STATS
+ lwip_stats.link.recv++;
+#endif
+ }
+}
+
+static void
+fifo_error_handler(xaxiemacif_s *xaxiemacif, u32_t pending_intr)
+{
+ XLlFifo *llfifo = &xaxiemacif->axififo;
+
+ if (pending_intr & XLLF_INT_RPURE_MASK) {
+ print("llfifo: Rx under-read error");
+ }
+ if (pending_intr & XLLF_INT_RPORE_MASK) {
+ print("llfifo: Rx over-read error");
+ }
+ if (pending_intr & XLLF_INT_RPUE_MASK) {
+ print("llfifo: Rx fifo empty");
+ }
+ if (pending_intr & XLLF_INT_TPOE_MASK) {
+ print("llfifo: Tx fifo overrun");
+ }
+ if (pending_intr & XLLF_INT_TSE_MASK) {
+ print("llfifo: Tx length mismatch");
+ }
+
+ /* Reset the tx or rx side of the fifo as needed */
+ if (pending_intr & XLLF_INT_RXERROR_MASK) {
+ XLlFifo_IntClear(llfifo, XLLF_INT_RRC_MASK);
+ XLlFifo_RxReset(llfifo);
+ }
+
+ if (pending_intr & XLLF_INT_TXERROR_MASK) {
+ XLlFifo_IntClear(llfifo, XLLF_INT_TRC_MASK);
+ XLlFifo_TxReset(llfifo);
+ }
+}
+
+static void
+xllfifo_intr_handler(struct xemac_s *xemac)
+{
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ XLlFifo *llfifo = &xaxiemacif->axififo;
+
+ u32_t pending_fifo_intr = XLlFifo_IntPending(llfifo);
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+
+ while (pending_fifo_intr) {
+ if (pending_fifo_intr & XLLF_INT_RC_MASK) {
+ /* receive interrupt */
+ XLlFifo_IntClear(llfifo, XLLF_INT_RC_MASK);
+ xllfifo_recv_handler(xemac);
+ } else if (pending_fifo_intr & XLLF_INT_TC_MASK) {
+ /* tx intr */
+ XLlFifo_IntClear(llfifo, XLLF_INT_TC_MASK);
+ } else {
+ XLlFifo_IntClear(llfifo, XLLF_INT_ALL_MASK &
+ ~(XLLF_INT_RC_MASK |
+ XLLF_INT_TC_MASK));
+ fifo_error_handler(xaxiemacif, pending_fifo_intr);
+ }
+ pending_fifo_intr = XLlFifo_IntPending(llfifo);
+ }
+
+#if !NO_SYS
+ xInsideISR--;
+#endif
+
+}
+
+XStatus init_axi_fifo(struct xemac_s *xemac)
+{
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+#if XPAR_INTC_0_HAS_FAST == 1
+ xaxiemacif_fast = xaxiemacif;
+ xemac_fast = xemac;
+#endif
+ struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
+
+ /* initialize ll fifo */
+ XLlFifo_Initialize(&xaxiemacif->axififo,
+ XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
+
+ /* Clear any pending FIFO interrupts */
+ XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
+
+ /* enable fifo interrupts */
+ XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XInterruptHandler)xaxiemac_error_handler,
+ &xaxiemacif->axi_ethernet);
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+ (XInterruptHandler)xllfifo_intr_handler,
+ xemac);
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ AXIETH_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+ AXIFIFO_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.TemacIntr);
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
+#else
+#if NO_SYS
+#if XPAR_INTC_0_HAS_FAST == 1
+ /* Register temac interrupt with interrupt controller */
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XFastInterruptHandler)xaxiemac_fasterror_handler);
+
+ /* connect & enable FIFO interrupt */
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+ (XFastInterruptHandler)xllfifo_fastintr_handler);
+#else
+ /* Register temac interrupt with interrupt controller */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XInterruptHandler)xaxiemac_error_handler,
+ &xaxiemacif->axi_ethernet);
+
+ /* connect & enable FIFO interrupt */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+ (XInterruptHandler)xllfifo_intr_handler,
+ xemac);
+
+#endif
+ /* Enable EMAC interrupts in the interrupt controller */
+ do {
+ /* read current interrupt enable mask */
+ unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
+
+ /* form new mask enabling SDMA & ll_temac interrupts */
+ cur_mask = cur_mask
+ | (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
+ | (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
+
+ /* set new mask */
+ XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
+ } while (0);
+#else
+#if XPAR_INTC_0_HAS_FAST == 1
+ /* Register temac interrupt with interrupt controller */
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XFastInterruptHandler)xaxiemac_fasterror_handler);
+
+ /* connect & enable FIFO interrupt */
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+ (XFastInterruptHandler)xllfifo_fastintr_handler);
+#else
+ /* Register temac interrupt with interrupt controller */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (XInterruptHandler)xaxiemac_error_handler,
+ &xaxiemacif->axi_ethernet);
+
+ /* connect & enable FIFO interrupt */
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
+ (XInterruptHandler)xllfifo_intr_handler,
+ xemac);
+
+#endif
+ /* Enable EMAC interrupts in the interrupt controller */
+ do {
+ /* read current interrupt enable mask */
+ unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
+
+ /* form new mask enabling SDMA & ll_temac interrupts */
+ cur_mask = cur_mask
+ | (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
+ | (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
+
+ /* set new mask */
+ XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
+ } while (0);
+#endif
+#endif
+
+ return 0;
+}
+
+XStatus axififo_send(xaxiemacif_s *xaxiemacif, struct pbuf *p)
+{
+ XLlFifo *llfifo = &xaxiemacif->axififo;
+ u32_t l = 0;
+ struct pbuf *q;
+
+ for(q = p; q != NULL; q = q->next) {
+ /* write frame data to FIFO */
+ XLlFifo_Write(llfifo, q->payload, q->len);
+ l += q->len;
+ }
+
+ /* initiate transmit */
+ XLlFifo_TxSetLen(llfifo, l);
+
+ return 0;
+}
+
+#if XPAR_INTC_0_HAS_FAST == 1
+/*********** Fast Error Handler ********************************************/
+void xaxiemac_fasterror_handler(void)
+{
+ xaxiemac_error_handler(&xaxiemacif_fast->axi_ethernet);
+}
+
+/********** Fast Interrupt handler *****************************************/
+void xllfifo_fastintr_handler(void)
+{
+ xllfifo_intr_handler(xemac_fast);
+}
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h
new file mode 100644
index 0000000..f4c3250
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XAXIEMACIF_FIFO_H_
+#define __XAXIEMACIF_FIFO_H_
+
+#include "xparameters.h"
+#include "netif/xaxiemacif.h"
+#include "xlwipconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+XStatus init_axi_fifo(struct xemac_s *xemac);
+XStatus axififo_send(xaxiemacif_s *xaxiemacif, struct pbuf *p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c
new file mode 100644
index 0000000..091069e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/xaxiemacif.h"
+#include "lwipopts.h"
+
+extern enum ethernet_link_status eth_link_status;
+
+XAxiEthernet_Config *xaxiemac_lookup_config(unsigned mac_base)
+{
+ extern XAxiEthernet_Config XAxiEthernet_ConfigTable[];
+ XAxiEthernet_Config *CfgPtr = NULL;
+ unsigned int i;
+
+ for (i = 0; i < XPAR_XAXIETHERNET_NUM_INSTANCES; i++) {
+ if (XAxiEthernet_ConfigTable[i].BaseAddress == mac_base) {
+ CfgPtr = &XAxiEthernet_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (CfgPtr);
+}
+
+void init_axiemac(xaxiemacif_s *xaxiemac, struct netif *netif)
+{
+ unsigned link_speed = 1000;
+ unsigned options;
+ XAxiEthernet *xaxiemacp;
+
+ xaxiemacp = &xaxiemac->axi_ethernet;
+
+ XAxiEthernet_Reset(xaxiemacp);
+
+ options = XAxiEthernet_GetOptions(xaxiemacp);
+ options |= XAE_FLOW_CONTROL_OPTION;
+#ifdef USE_JUMBO_FRAMES
+ options |= XAE_JUMBO_OPTION;
+#endif
+ options |= XAE_TRANSMITTER_ENABLE_OPTION;
+ options |= XAE_RECEIVER_ENABLE_OPTION;
+ options |= XAE_FCS_STRIP_OPTION;
+ options |= XAE_MULTICAST_OPTION;
+ XAxiEthernet_SetOptions(xaxiemacp, options);
+ XAxiEthernet_ClearOptions(xaxiemacp, ~options);
+
+ /* set mac address */
+ XAxiEthernet_SetMacAddress(xaxiemacp, (unsigned char*)(netif->hwaddr));
+ link_speed = phy_setup_axiemac(xaxiemacp);
+ XAxiEthernet_SetOperatingSpeed(xaxiemacp, link_speed);
+
+ if (link_speed == 0)
+ eth_link_status = ETH_LINK_DOWN;
+ else
+ eth_link_status = ETH_LINK_UP;
+
+ /* Setting the operating speed of the MAC needs a delay. */
+ {
+ volatile int wait;
+ for (wait=0; wait < 100000; wait++);
+ for (wait=0; wait < 100000; wait++);
+ }
+
+#ifdef NOTNOW
+ /* in a soft temac implementation, we need to explicitly make sure that
+ * the RX DCM has been locked. See xps_ll_temac manual for details.
+ * This bit is guaranteed to be 1 for hard temac's
+ */
+ lock_message_printed = 0;
+ while (!(XAxiEthernet_ReadReg(xaxiemacp->Config.BaseAddress, XAE_IS_OFFSET)
+ & XAE_INT_RXDCMLOCK_MASK)) {
+ int first = 1;
+ if (first) {
+ print("Waiting for RX DCM to lock..");
+ first = 0;
+ lock_message_printed = 1;
+ }
+ }
+
+ if (lock_message_printed)
+ print("RX DCM locked.\r\n");
+#endif
+
+ /* start the temac */
+ XAxiEthernet_Start(xaxiemacp);
+
+ /* enable MAC interrupts */
+ XAxiEthernet_IntEnable(xaxiemacp, XAE_INT_RECV_ERROR_MASK);
+}
+
+void xaxiemac_error_handler(XAxiEthernet * Temac)
+{
+ unsigned Pending;
+
+ Pending = XAxiEthernet_IntPending(Temac);
+ XAxiEthernet_IntClear(Temac, Pending);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h
new file mode 100644
index 0000000..5ebd8bd
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XAXIEMACIF_HW_H_
+#define __XAXIEMACIF_HW_H_
+
+#include "netif/xaxiemacif.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+XAxiEthernet_Config * xaxiemac_lookup_config(unsigned mac_base);
+
+void init_axiemac(xaxiemacif_s *xaxiemacif, struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c
new file mode 100644
index 0000000..0deff02
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c
@@ -0,0 +1,841 @@
+/*
+ * Copyright (C) 2018 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwipopts.h"
+
+#if !NO_SYS
+#include "FreeRTOS.h"
+#include "lwip/sys.h"
+#endif
+
+#include "lwip/stats.h"
+#include "lwip/inet_chksum.h"
+
+#include "netif/xadapter.h"
+#include "netif/xaxiemacif.h"
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+#include "xscugic.h"
+#endif
+
+#include "xstatus.h"
+
+#include "xlwipconfig.h"
+#include "xparameters.h"
+
+#if defined __aarch64__
+#include "xil_mmu.h"
+#endif
+
+#if defined ARMR5
+#include "xil_mpu.h"
+#endif
+
+#define PARTIAL_CSUM_ENABLE 0x00000001 /* Option for partial csum enable */
+#define FULL_CSUM_ENABLE 0x00000002 /* Option for full csum enable */
+
+#define BD_USR0_OFFSET 0 /* AXI4-Stream Control Word offset from
+ * the start of app user words in BD.
+ * Offset 0 means, Control Word 0, used
+ * for enabling checksum offloading.
+ */
+#define BD_USR1_OFFSET 1 /* AXI4-Stream Control Word offset from
+ * the start of app user words in BD.
+ * Offset means, Control Word 1, used
+ * for mentioning checksum begin and
+ * checksum insert points
+ */
+#define BD_USR2_OFFSET 2 /* AXI4-Stream Control Word offset from
+ * the start of app user words in BD.
+ * Offset 2 means, Control Word 2, used
+ * for mentioning checksum seed.
+ */
+
+#define XMCDMA_ALL_BDS 0xFFFF
+#define XMCDMA_BD_LENGTH_MASK 0x007FFFFF
+#define XMCDMA_COALESCEDELAY 0x1
+
+#define RESET_TIMEOUT_COUNT 10000
+#define BLOCK_SIZE_2MB 0x200000
+#define BLOCK_SIZE_1MB 0x100000
+
+#if defined (__aarch64__)
+#define BD_SIZE BLOCK_SIZE_2MB
+static u8_t bd_space[BD_SIZE] __attribute__ ((aligned (BLOCK_SIZE_2MB)));
+#else
+#define BD_SIZE BLOCK_SIZE_1MB
+static u8_t bd_space[BD_SIZE] __attribute__ ((aligned (BLOCK_SIZE_1MB)));
+#endif
+
+static u8_t *bd_mem_ptr = bd_space;
+
+#if !NO_SYS
+u32 xInsideISR = 0;
+#endif
+
+static inline void bd_csum_enable(XMcdma_Bd *bd)
+{
+ XMcDma_BdSetAppWord(bd, BD_USR0_OFFSET, PARTIAL_CSUM_ENABLE);
+}
+
+static inline void bd_csum_disable(XMcdma_Bd *bd)
+{
+ XMcDma_BdSetAppWord(bd, BD_USR0_OFFSET, ~PARTIAL_CSUM_ENABLE);
+}
+
+static inline void bd_fullcsum_disable(XMcdma_Bd *bd)
+{
+ XMcDma_BdSetAppWord(bd, BD_USR0_OFFSET, ~FULL_CSUM_ENABLE);
+}
+
+static inline void bd_fullcsum_enable(XMcdma_Bd *bd)
+{
+ XMcDma_BdSetAppWord(bd, BD_USR0_OFFSET, FULL_CSUM_ENABLE);
+}
+
+static inline void bd_csum_set(XMcdma_Bd *bd, u16_t tx_csbegin,
+ u16_t tx_csinsert, u16_t tx_csinit)
+{
+ u32_t app1;
+
+ bd_csum_enable(bd);
+
+ /* write start offset and insert offset into BD */
+ app1 = ((u32_t)tx_csbegin << 16) | tx_csinsert;
+ XMcDma_BdSetAppWord(bd, BD_USR1_OFFSET, app1);
+
+ /* insert init value */
+ XMcDma_BdSetAppWord(bd, BD_USR2_OFFSET, tx_csinit);
+}
+
+static inline u32_t extract_packet_len(XMcdma_Bd *rxbd) {
+ return XMcDma_BdGetActualLength(rxbd, XMCDMA_BD_LENGTH_MASK);
+}
+
+static inline u16_t extract_csum(XMcdma_Bd *rxbd) {
+ return XMcdma_BdRead64(rxbd, XMCDMA_BD_USR3_OFFSET) & 0xffff;
+}
+
+static inline u32_t csum_sub(u32_t csum, u16_t v)
+{
+ csum += (u32_t)v;
+ return csum + (csum < (u32_t)v);
+}
+
+/*
+ * compare if the h/w computed checksum (stored in the rxbd)
+ * equals the TCP checksum value in the packet
+ */
+s32_t is_checksum_valid(XMcdma_Bd *rxbd, struct pbuf *p)
+{
+ struct ethip_hdr *ehdr = p->payload;
+ u8_t proto = IPH_PROTO(&ehdr->ip);
+
+ /* check if it is a TCP packet */
+ if (htons(ehdr->eth.type) == ETHTYPE_IP && proto == IP_PROTO_TCP) {
+ u32_t iphdr_len;
+ u16_t csum_in_rxbd, pseudo_csum, iphdr_csum, padding_csum;
+ u16_t tcp_payload_offset;
+ u32_t computed_csum;
+ u16_t padding_len, tcp_payload_len, packet_len;
+ u16_t csum;
+
+ /* determine length of IP header */
+ iphdr_len = (IPH_HL(&ehdr->ip) * 4);
+ tcp_payload_offset = XAE_HDR_SIZE + iphdr_len;
+ tcp_payload_len = htons(IPH_LEN(&ehdr->ip)) -
+ IPH_HL(&ehdr->ip) * 4;
+ packet_len = extract_packet_len(rxbd);
+ padding_len = packet_len - tcp_payload_offset - tcp_payload_len;
+
+ csum_in_rxbd = extract_csum(rxbd);
+ pseudo_csum = htons(ip_chksum_pseudo(NULL, proto,
+ tcp_payload_len,
+ (ip_addr_t *)&ehdr->ip.src,
+ (ip_addr_t *)&ehdr->ip.dest));
+
+ /* xps_ll_temac computes the checksum of the packet starting
+ * at byte XAE_HDR_SIZE we need to subtract the values of
+ * the ethernet & IP headers
+ */
+ iphdr_csum = inet_chksum(p->payload + XAE_HDR_SIZE, iphdr_len);
+
+ /* compute csum of padding bytes, if any */
+ padding_csum = inet_chksum(p->payload + p->tot_len -
+ padding_len, padding_len);
+
+ /* get the h/w checksum value */
+ computed_csum = (u32_t)csum_in_rxbd;
+
+ /* remove the effect of csumming the iphdr */
+ computed_csum = csum_sub(computed_csum, ~iphdr_csum);
+
+ /* add in the pseudo csum */
+ computed_csum = csum_sub(computed_csum, ~pseudo_csum);
+
+ /* remove any padding effect */
+ computed_csum = csum_sub(computed_csum, ~padding_csum);
+
+ /* normalize computed csum */
+ while (computed_csum >> 16) {
+ computed_csum = (computed_csum & 0xffff) +
+ (computed_csum >> 16);
+ }
+
+ /* convert to 16 bits and take 1's complement */
+ csum = (u16_t)computed_csum;
+ csum = ~csum;
+
+ /* chksum is valid if: computed csum over the packet is 0 */
+ return !csum;
+ } else {
+ /* just say yes to all other packets */
+ /* the upper layers in the stack will compute and
+ * verify the checksum */
+ return 1;
+ }
+}
+
+#define XMcdma_BdMemCalc(Alignment, NumBd) \
+ (int)((sizeof(XMcdma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)
+
+static inline void *alloc_bdspace(int n_desc, u32 alignment)
+{
+ int space = XMcdma_BdMemCalc(alignment, n_desc);
+ void *unaligned_mem = bd_mem_ptr;
+ void *aligned_mem =
+ (void *)(((UINTPTR)(unaligned_mem + alignment - 1)) & ~(alignment - 1));
+
+ if (aligned_mem + space > (void *)(bd_space + BD_SIZE)) {
+ xil_printf("Unable to allocate BD space\r\n");
+ return NULL;
+ }
+
+ bd_mem_ptr = aligned_mem + space;
+
+ return aligned_mem;
+}
+
+static void axi_mcdma_send_error_handler(void *CallBackRef, u32 ChanId, u32 Mask)
+{
+ u32 timeOut;
+ XMcdma *McDmaInstPtr = (XMcdma *)((void *)CallBackRef);
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+ xil_printf("%s: Error: aximcdma error interrupt is asserted, Chan_id = "
+ "%d, Mask = %d\r\n", __FUNCTION__, ChanId, Mask);
+
+ XMcDma_Reset(McDmaInstPtr);
+ timeOut = RESET_TIMEOUT_COUNT;
+ while (timeOut) {
+ if (XMcdma_ResetIsDone(McDmaInstPtr))
+ break;
+ timeOut -= 1;
+ }
+
+ if (!timeOut) {
+ xil_printf("%s: Error: aximcdma reset timed out\r\n", __func__);
+ }
+
+#if !NO_SYS
+ xInsideISR--;
+#endif
+}
+
+static void axi_mcdma_send_handler(void *CallBackRef, u32 ChanId)
+{
+ XMcdma *McDmaInstPtr = (XMcdma *)((void *)CallBackRef);
+ XMcdma_ChanCtrl *Tx_Chan = XMcdma_GetMcdmaTxChan(McDmaInstPtr, ChanId);
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+
+ process_sent_bds(Tx_Chan);
+
+#if !NO_SYS
+ xInsideISR--;
+#endif
+}
+
+static void setup_rx_bds(XMcdma_ChanCtrl *Rx_Chan, u32_t n_bds)
+{
+ XMcdma_Bd *rxbd;
+ u32_t i = 0;
+ XStatus status;
+ struct pbuf *p;
+ u32 bdsts;
+#ifdef USE_JUMBO_FRAMES
+ u32 max_frame_size = XAE_MAX_JUMBO_FRAME_SIZE + IEEE_1588_PAD_SIZE;
+#else
+ u32 max_frame_size = XAE_MAX_FRAME_SIZE + IEEE_1588_PAD_SIZE;
+#endif
+
+ for (i = 0; i < n_bds; i++) {
+ p = pbuf_alloc(PBUF_RAW, max_frame_size, PBUF_POOL);
+ if (!p) {
+ xil_printf("unable to alloc pbuf in recv_handler\r\n");
+ return;
+ }
+
+ rxbd = (XMcdma_Bd *)XMcdma_GetChanCurBd(Rx_Chan);
+ status = XMcDma_ChanSubmit(Rx_Chan, (UINTPTR)p->payload,
+ p->len);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("setup_rx_bds: Error allocating RxBD\r\n"));
+ pbuf_free(p);
+ return;
+ }
+ /* Clear everything but the COMPLETE bit, which is cleared when
+ * committed to hardware.
+ */
+ bdsts = XMcDma_BdGetSts(rxbd);
+ bdsts &= XMCDMA_BD_STS_COMPLETE_MASK;
+ XMcdma_BdWrite(rxbd, XMCDMA_BD_STS_OFFSET, bdsts);
+ XMcDma_BdSetCtrl(rxbd, 0);
+ XMcdma_BdSetSwId(rxbd, p);
+
+#if defined(__aarch64__)
+ Xil_DCacheInvalidateRange((UINTPTR)p->payload,
+ (UINTPTR)max_frame_size);
+#else
+ Xil_DCacheFlushRange((UINTPTR)p->payload,
+ (UINTPTR)max_frame_size);
+#endif
+ }
+
+#if !defined (__MICROBLAZE__)
+ dsb();
+#endif
+
+ if (n_bds) {
+ /* Enqueue to HW */
+ status = XMcDma_ChanToHw(Rx_Chan);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error committing RxBD to hardware\n\r"));
+ }
+ }
+}
+
+static void axi_mcdma_recv_error_handler(void *CallBackRef, u32 ChanId)
+{
+ u32 timeOut;
+ XMcdma_ChanCtrl *Rx_Chan;
+ struct xemac_s *xemac = (struct xemac_s *)(CallBackRef);
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ XMcdma *McDmaInstPtr = &xaxiemacif->aximcdma;
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+ xil_printf("%s: Error: aximcdma error interrupt is asserted\r\n",
+ __FUNCTION__);
+ Rx_Chan = XMcdma_GetMcdmaRxChan(McDmaInstPtr, ChanId);
+
+ setup_rx_bds(Rx_Chan, Rx_Chan->BdCnt);
+
+ XMcDma_Reset(McDmaInstPtr);
+ timeOut = RESET_TIMEOUT_COUNT;
+ while (timeOut) {
+ if (XMcdma_ResetIsDone(McDmaInstPtr))
+ break;
+ timeOut -= 1;
+ }
+
+ if (!timeOut) {
+ xil_printf("%s: Error: aximcdma reset timed out\r\n", __func__);
+ }
+
+ XMcDma_ChanToHw(Rx_Chan);
+
+#if !NO_SYS
+ xInsideISR--;
+#endif
+ return;
+}
+
+static void axi_mcdma_recv_handler(void *CallBackRef, u32 ChanId)
+{
+ struct pbuf *p;
+ u32 i, rx_bytes, ProcessedBdCnt;
+ XMcdma_Bd *rxbd, *rxbdset;
+ struct xemac_s *xemac = (struct xemac_s *)(CallBackRef);
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ XMcdma *McDmaInstPtr = &xaxiemacif->aximcdma;
+ XMcdma_ChanCtrl *Rx_Chan;
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+
+ Rx_Chan = XMcdma_GetMcdmaRxChan(McDmaInstPtr, ChanId);
+
+ ProcessedBdCnt = XMcdma_BdChainFromHW(Rx_Chan, XMCDMA_ALL_BDS, &rxbdset);
+
+ for (i = 0, rxbd = rxbdset; i < ProcessedBdCnt; i++) {
+
+ p = (struct pbuf *)(UINTPTR)XMcdma_BdGetSwId(rxbd);
+
+ /* Adjust the buffer size to actual number of bytes received.*/
+ rx_bytes = extract_packet_len(rxbd);
+#ifndef __aarch64__
+ Xil_DCacheInvalidateRange((UINTPTR)p->payload,
+ (UINTPTR)rx_bytes);
+#endif
+ pbuf_realloc(p, rx_bytes);
+
+#if LWIP_PARTIAL_CSUM_OFFLOAD_RX==1
+ /* Verify for partial checksum offload case */
+ if (!is_checksum_valid(rxbd, p)) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Incorrect csum as calculated by the hw\r\n"));
+ }
+#endif
+ /* store it in the receive queue,
+ * where it'll be processed by a different handler
+ */
+ if (pq_enqueue(xaxiemacif->recv_q, (void*)p) < 0) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ pbuf_free(p);
+ }
+ rxbd = (XMcdma_Bd *)XMcdma_BdChainNextBd(Rx_Chan, rxbd);
+ }
+
+ /* free up the BD's */
+ XMcdma_BdChainFree(Rx_Chan, ProcessedBdCnt, rxbdset);
+
+ /* return all the processed bd's back to the stack */
+ setup_rx_bds(Rx_Chan, Rx_Chan->BdCnt);
+#if !NO_SYS
+ sys_sem_signal(&xemac->sem_rx_data_available);
+ xInsideISR--;
+#endif
+}
+
+s32_t is_tx_space_available(xaxiemacif_s *xaxiemacif)
+{
+ XMcdma_ChanCtrl *Tx_Chan;
+ u8_t ChanId;
+ for (ChanId = 1;
+ ChanId <= xaxiemacif->axi_ethernet.Config.AxiMcDmaChan_Cnt;
+ ChanId++) {
+ Tx_Chan = XMcdma_GetMcdmaTxChan(&xaxiemacif->aximcdma, ChanId);
+
+ if (Tx_Chan->BdCnt) {
+ return Tx_Chan->BdCnt;
+ }
+ }
+ return 0;
+}
+
+s32_t process_sent_bds(XMcdma_ChanCtrl *Tx_Chan)
+{
+ int ProcessedBdCnt, i;
+ XStatus status;
+ XMcdma_Bd *txbdset, *txbd;
+
+ ProcessedBdCnt = XMcdma_BdChainFromHW(Tx_Chan, XMCDMA_ALL_BDS,
+ &txbdset);
+ if (ProcessedBdCnt == 0) {
+ return XST_FAILURE;
+ }
+
+ /* free the pbuf associated with each BD */
+ for (i = 0, txbd = txbdset; i < ProcessedBdCnt; i++) {
+ struct pbuf *p = (struct pbuf *)(UINTPTR)XMcdma_BdGetSwId(txbd);
+ pbuf_free(p);
+ txbd = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, txbd);
+ }
+
+ /* free the processed BD's */
+ status = XMcdma_BdChainFree(Tx_Chan, ProcessedBdCnt, txbdset);
+ if (status != XST_SUCCESS) {
+ xil_printf("Error freeing up TxBDs");
+ return XST_FAILURE;
+ }
+ return XST_SUCCESS;
+}
+
+#if LWIP_PARTIAL_CSUM_OFFLOAD_TX==1
+static void update_partial_cksum_offload(XMcdma_Bd *txbdset, struct pbuf *p)
+{
+ if (p->len > sizeof(struct ethip_hdr)) {
+ struct ethip_hdr *ehdr = p->payload;
+ u8_t proto = IPH_PROTO(&ehdr->ip);
+
+ /* check if it is a TCP packet */
+ if (htons(ehdr->eth.type) == ETHTYPE_IP && proto ==
+ IP_PROTO_TCP) {
+ u32_t iphdr_len, csum_insert_offset;
+ u16_t tcp_len; /* TCP header length + data length in bytes */
+ u16_t csum_init = 0;
+ u16_t tcp_payload_offset;
+
+ /* determine length of IP header */
+ iphdr_len = (IPH_HL(&ehdr->ip) * 4);
+
+ tcp_payload_offset = XAE_HDR_SIZE + iphdr_len;
+ tcp_len = p->tot_len - tcp_payload_offset;
+
+ /* insert checksum at offset 16 for TCP, 6 for UDP */
+ if (proto == IP_PROTO_TCP)
+ csum_insert_offset = tcp_payload_offset + 16;
+ else if (proto == IP_PROTO_UDP)
+ csum_insert_offset = tcp_payload_offset + 6;
+ else
+ csum_insert_offset = 0;
+ /* compute pseudo header checksum value */
+ csum_init = ip_chksum_pseudo(NULL, proto, tcp_len,
+ (ip_addr_t *)&ehdr->ip.src,
+ (ip_addr_t *)&ehdr->ip.dest);
+ /* init buffer descriptor */
+ bd_csum_set(txbdset, tcp_payload_offset,
+ csum_insert_offset, htons(~csum_init));
+ }
+ }
+}
+#endif
+
+XStatus axi_mcdma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p)
+{
+ struct pbuf *q;
+ u32_t n_pbufs = 0;
+ XMcdma_Bd *txbdset, *txbd, *last_txbd = NULL;
+ XMcdma_ChanCtrl *Tx_Chan;
+ XStatus status;
+ static u8_t ChanId = 1;
+ u8_t next_ChanId = ChanId;
+
+ /* first count the number of pbufs */
+ for (q = p; q != NULL; q = q->next)
+ n_pbufs++;
+
+ /* Transfer packets to TX DMA Channels in round-robin manner */
+ do {
+ Tx_Chan = XMcdma_GetMcdmaTxChan(&xaxiemacif->aximcdma, ChanId);
+
+ if (++ChanId > xaxiemacif->axi_ethernet.Config.AxiMcDmaChan_Cnt)
+ ChanId = 1;
+
+ if ((next_ChanId == ChanId) && (n_pbufs > Tx_Chan->BdCnt)) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error, not enough BD space in All Chans\r\n"));
+ return ERR_IF;
+ }
+
+ } while (n_pbufs > Tx_Chan->BdCnt);
+
+ txbdset = (XMcdma_Bd *)XMcdma_GetChanCurBd(Tx_Chan);
+
+ for (q = p, txbd = txbdset; q != NULL; q = q->next) {
+ /* Send the data from the pbuf to the interface, one pbuf at a
+ * time. The size of the data in each pbuf is kept in the ->len
+ * variable.
+ */
+ XMcDma_BdSetCtrl(txbd, 0);
+ XMcdma_BdSetSwId(txbd, (void *)q);
+
+ Xil_DCacheFlushRange((UINTPTR)q->payload, q->len);
+
+ status = XMcDma_ChanSubmit(Tx_Chan, (UINTPTR)q->payload,
+ q->len);
+ if (status != XST_SUCCESS) {
+ xil_printf("ChanSubmit failed\n\r");
+ return XST_FAILURE;
+ }
+
+ pbuf_ref(q);
+
+ last_txbd = txbd;
+ txbd = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, txbd);
+ }
+
+ if (n_pbufs == 1) {
+ XMcDma_BdSetCtrl(txbdset, XMCDMA_BD_CTRL_SOF_MASK
+ | XMCDMA_BD_CTRL_EOF_MASK);
+ } else {
+ /* in the first packet, set the SOP */
+ XMcDma_BdSetCtrl(txbdset, XMCDMA_BD_CTRL_SOF_MASK);
+ /* in the last packet, set the EOP */
+ XMcDma_BdSetCtrl(last_txbd, XMCDMA_BD_CTRL_EOF_MASK);
+ }
+
+#if LWIP_FULL_CSUM_OFFLOAD_TX==1
+ bd_fullcsum_disable(txbdset);
+ if (p->len > sizeof(struct ethip_hdr)) {
+ bd_fullcsum_enable(txbdset);
+ }
+#endif
+
+#if LWIP_PARTIAL_CSUM_OFFLOAD_TX==1
+ bd_csum_disable(txbdset);
+ update_partial_cksum_offload(txbdset, p);
+#endif
+ DATA_SYNC;
+ /* enq to h/w */
+ return XMcDma_ChanToHw(Tx_Chan);
+}
+
+void axi_mcdma_register_handlers(struct xemac_s *xemac, u8 ChanId)
+{
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ XMcdma *McDmaInstPtr = &xaxiemacif->aximcdma;
+
+ struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
+
+#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
+
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ (Xil_InterruptHandler)xaxiemac_error_handler,
+ &xaxiemacif->axi_ethernet);
+
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiMcDmaRxIntr[ChanId - 1],
+ (Xil_InterruptHandler)XMcdma_IntrHandler,
+ McDmaInstPtr);
+
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xaxiemacif->axi_ethernet.Config.AxiMcDmaTxIntr[ChanId - 1],
+ (Xil_InterruptHandler)XMcdma_TxIntrHandler,
+ McDmaInstPtr);
+
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.TemacIntr,
+ AXIETH_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiMcDmaTxIntr[ChanId - 1],
+ AXIDMA_TX_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiMcDmaRxIntr[ChanId - 1],
+ AXIDMA_RX_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.TemacIntr);
+
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiMcDmaTxIntr[ChanId - 1]);
+
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xaxiemacif->axi_ethernet.Config.AxiMcDmaRxIntr[ChanId - 1]);
+
+#endif /* XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ */
+}
+
+XStatus axi_mcdma_setup_rx_chan(struct xemac_s *xemac, u32_t ChanId)
+{
+ XMcdma_ChanCtrl *Rx_Chan;
+ XStatus status;
+
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+
+ /* RX chan configurations */
+ Rx_Chan = XMcdma_GetMcdmaRxChan(&xaxiemacif->aximcdma, ChanId);
+
+ /* Disable all interrupts */
+ XMcdma_IntrDisable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);
+
+ status = XMcDma_ChanBdCreate(Rx_Chan, (UINTPTR) xaxiemacif->rx_bdspace,
+ XLWIP_CONFIG_N_RX_DESC);
+ if (status != XST_SUCCESS) {
+ xil_printf("Rx bd create failed with %d\r\n", status);
+ return XST_FAILURE;
+ }
+
+ xaxiemacif->rx_bdspace += (XLWIP_CONFIG_N_RX_DESC * sizeof(XMcdma_Bd));
+
+ /* Setup Interrupt System and register callbacks */
+ XMcdma_SetCallBack(&xaxiemacif->aximcdma, XMCDMA_HANDLER_DONE,
+ (void *)axi_mcdma_recv_handler, xemac);
+ XMcdma_SetCallBack(&xaxiemacif->aximcdma, XMCDMA_HANDLER_ERROR,
+ (void *)axi_mcdma_recv_error_handler, xemac);
+
+ status = XMcdma_SetChanCoalesceDelay(Rx_Chan,
+ XLWIP_CONFIG_N_RX_COALESCE,
+ XMCDMA_COALESCEDELAY);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error setting coalescing settings\r\n"));
+ return ERR_IF;
+ }
+
+ setup_rx_bds(Rx_Chan, XLWIP_CONFIG_N_RX_DESC);
+
+ /* enable DMA interrupts */
+ XMcdma_IntrEnable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);
+
+ return XST_SUCCESS;
+}
+
+XStatus axi_mcdma_setup_tx_chan(struct xemac_s *xemac, u8 ChanId)
+{
+ XStatus status;
+ XMcdma_ChanCtrl *Tx_Chan;
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+
+ /* TX chan configurations */
+ Tx_Chan = XMcdma_GetMcdmaTxChan(&xaxiemacif->aximcdma, ChanId);
+
+ XMcdma_IntrDisable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);
+
+ status = XMcDma_ChanBdCreate(Tx_Chan, (UINTPTR) xaxiemacif->tx_bdspace,
+ XLWIP_CONFIG_N_TX_DESC);
+ if (status != XST_SUCCESS) {
+ xil_printf("TX bd create failed with %d\r\n", status);
+ return XST_FAILURE;
+ }
+
+ xaxiemacif->tx_bdspace += (XLWIP_CONFIG_N_TX_DESC * sizeof(XMcdma_Bd));
+
+ /* Setup Interrupt System and register callbacks */
+ XMcdma_SetCallBack(&xaxiemacif->aximcdma, XMCDMA_TX_HANDLER_DONE,
+ (void *)axi_mcdma_send_handler, &xaxiemacif->aximcdma);
+ XMcdma_SetCallBack(&xaxiemacif->aximcdma, XMCDMA_TX_HANDLER_ERROR,
+ (void *)axi_mcdma_send_error_handler,
+ &xaxiemacif->aximcdma);
+
+ status = XMcdma_SetChanCoalesceDelay(Tx_Chan,
+ XLWIP_CONFIG_N_TX_COALESCE,
+ XMCDMA_COALESCEDELAY);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error setting coalescing settings\r\n"));
+ return ERR_IF;
+ }
+
+ XMcdma_IntrEnable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);
+
+ return XST_SUCCESS;
+}
+
+XStatus init_axi_mcdma(struct xemac_s *xemac)
+{
+ XMcdma_Config *dmaconfig;
+ XStatus status;
+ u32_t ChanId;
+ xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
+ UINTPTR baseaddr;
+
+ /*
+ * Disable L1 prefetch if the processor type is Cortex A53. It is
+ * observed that the L1 prefetching for ARMv8 can cause issues while
+ * dealing with cache memory on Rx path. On Rx path, the lwIP adapter
+ * does a clean and invalidation of buffers (pbuf payload) before
+ * allocating them to Rx BDs. However, there are chances that the
+ * the same cache line may get prefetched by the time Rx data is
+ * DMAed to the same buffer. In such cases, CPU fetches stale data from
+ * cache memory instead of getting them from memory. To avoid such
+ * scenarios L1 prefetch is being disabled for ARMv8. That can cause
+ * a performance degradation in the range of 3-5%. In tests, it is
+ * generally observed that this performance degradation is quite
+ * insignificant to be really visible.
+ */
+#if defined __aarch64__
+ Xil_ConfigureL1Prefetch(0);
+#endif
+
+ xaxiemacif->rx_bdspace = alloc_bdspace(XLWIP_CONFIG_N_RX_DESC *
+ (XMCDMA_MAX_CHAN_PER_DEVICE / 2),
+ XMCDMA_BD_MINIMUM_ALIGNMENT);
+ if (!xaxiemacif->rx_bdspace) {
+ xil_printf("%s@%d: Error: Unable to allocate memory for "
+ "RX buffer descriptors", __FILE__, __LINE__);
+ return ERR_IF;
+ }
+
+ xaxiemacif->tx_bdspace = alloc_bdspace(XLWIP_CONFIG_N_TX_DESC *
+ (XMCDMA_MAX_CHAN_PER_DEVICE / 2),
+ XMCDMA_BD_MINIMUM_ALIGNMENT);
+ if (!xaxiemacif->tx_bdspace) {
+ xil_printf("%s@%d: Error: Unable to allocate memory for "
+ "TX buffer descriptors", __FILE__, __LINE__);
+ return ERR_IF;
+ }
+
+ /* Mark the BD Region as uncacheable */
+#if defined(__aarch64__)
+ Xil_SetTlbAttributes((UINTPTR)bd_space,
+ NORM_NONCACHE | INNER_SHAREABLE);
+#elif defined (ARMR5)
+ Xil_SetTlbAttributes((INTPTR)bd_space,
+ DEVICE_SHARED | PRIV_RW_USER_RW);
+#else
+ Xil_SetTlbAttributes((INTPTR)bd_space, DEVICE_MEMORY);
+#endif
+
+ LWIP_DEBUGF(NETIF_DEBUG, ("rx_bdspace: 0x%08x\r\n",
+ xaxiemacif->rx_bdspace));
+ LWIP_DEBUGF(NETIF_DEBUG, ("tx_bdspace: 0x%08x\r\n",
+ xaxiemacif->tx_bdspace));
+
+ /* Initialize MCDMA */
+ baseaddr = xaxiemacif->axi_ethernet.Config.AxiDevBaseAddress;
+ dmaconfig = XMcdma_LookupConfigBaseAddr(baseaddr);
+ if (!baseaddr) {
+ xil_printf("%s@%d: Error: Lookup Config failed\r\n", __FILE__,
+ __LINE__);
+ }
+ status = XMcDma_CfgInitialize(&xaxiemacif->aximcdma, dmaconfig);
+ if (status != XST_SUCCESS) {
+ xil_printf("%s@%d: Error: MCDMA config initialization failed\r\n",
+ __FILE__, __LINE__);
+ return XST_FAILURE;
+ }
+
+ /* Setup Rx/Tx chan and Interrupts */
+ for (ChanId = 1;
+ ChanId <= xaxiemacif->axi_ethernet.Config.AxiMcDmaChan_Cnt;
+ ChanId++) {
+
+ status = axi_mcdma_setup_rx_chan(xemac, ChanId);
+ if (status != XST_SUCCESS) {
+ xil_printf("%s@%d: Error: MCDMA Rx chan setup failed\r\n",
+ __FILE__, __LINE__);
+ return XST_FAILURE;
+ }
+
+ status = axi_mcdma_setup_tx_chan(xemac, ChanId);
+ if (status != XST_SUCCESS) {
+ xil_printf("%s@%d: Error: MCDMA Tx chan setup failed\r\n",
+ __FILE__, __LINE__);
+ return XST_FAILURE;
+ }
+
+ axi_mcdma_register_handlers(xemac, ChanId);
+
+ }
+ return XST_SUCCESS;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c
new file mode 100644
index 0000000..832149b
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c
@@ -0,0 +1,779 @@
+/*
+ * Copyright (C) 2010 - 2020 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/xaxiemacif.h"
+#include "lwipopts.h"
+#include "sleep.h"
+#include "xemac_ieee_reg.h"
+
+#define PHY_R0_ISOLATE 0x0400
+#define PHY_DETECT_REG 1
+#define PHY_IDENTIFIER_1_REG 2
+#define PHY_IDENTIFIER_2_REG 3
+#define PHY_DETECT_MASK 0x1808
+#define PHY_MARVELL_IDENTIFIER 0x0141
+#define PHY_TI_IDENTIFIER 0x2000
+
+/* Marvel PHY flags */
+#define MARVEL_PHY_IDENTIFIER 0x141
+#define MARVEL_PHY_MODEL_NUM_MASK 0x3F0
+#define MARVEL_PHY_88E1111_MODEL 0xC0
+#define MARVEL_PHY_88E1116R_MODEL 0x240
+#define PHY_88E1111_RGMII_RX_CLOCK_DELAYED_MASK 0x0080
+
+/* TI PHY Flags */
+#define TI_PHY_DETECT_MASK 0x796D
+#define TI_PHY_IDENTIFIER 0x2000
+#define TI_PHY_DP83867_MODEL 0xA231
+#define DP83867_RGMII_CLOCK_DELAY_CTRL_MASK 0x0003
+#define DP83867_RGMII_TX_CLOCK_DELAY_MASK 0x0030
+#define DP83867_RGMII_RX_CLOCK_DELAY_MASK 0x0003
+
+/* TI DP83867 PHY Registers */
+#define DP83867_R32_RGMIICTL1 0x32
+#define DP83867_R86_RGMIIDCTL 0x86
+
+#define TI_PHY_REGCR 0xD
+#define TI_PHY_ADDDR 0xE
+#define TI_PHY_PHYCTRL 0x10
+#define TI_PHY_CFGR2 0x14
+#define TI_PHY_SGMIITYPE 0xD3
+#define TI_PHY_CFGR2_SGMII_AUTONEG_EN 0x0080
+#define TI_PHY_SGMIICLK_EN 0x4000
+#define TI_PHY_REGCR_DEVAD_EN 0x001F
+#define TI_PHY_REGCR_DEVAD_DATAEN 0x4000
+#define TI_PHY_CFGR2_MASK 0x003F
+#define TI_PHY_REGCFG4 0x31
+#define TI_PHY_REGCR_DATA 0x401F
+#define TI_PHY_CFG4RESVDBIT7 0x80
+#define TI_PHY_CFG4RESVDBIT8 0x100
+#define TI_PHY_CFG4_AUTONEG_TIMER 0x60
+
+#define TI_PHY_CFG2_SPEEDOPT_10EN 0x0040
+#define TI_PHY_CFG2_SGMII_AUTONEGEN 0x0080
+#define TI_PHY_CFG2_SPEEDOPT_ENH 0x0100
+#define TI_PHY_CFG2_SPEEDOPT_CNT 0x0800
+#define TI_PHY_CFG2_SPEEDOPT_INTLOW 0x2000
+
+#define TI_PHY_CR_SGMII_EN 0x0800
+
+/* Loop counters to check for reset done
+ */
+#define RESET_TIMEOUT 0xFFFF
+#define AUTO_NEG_TIMEOUT 0x00FFFFFF
+
+#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1 || \
+ XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
+#define PCM_PMA_CORE_PRESENT
+#else
+#undef PCM_PMA_CORE_PRESENT
+#endif
+
+#ifdef PCM_PMA_CORE_PRESENT
+#define IEEE_CTRL_RESET 0x9140
+#define IEEE_CTRL_ISOLATE_DISABLE 0xFBFF
+#endif
+
+#define PHY_XILINX_PCS_PMA_ID1 0x0174
+#define PHY_XILINX_PCS_PMA_ID2 0x0C00
+
+extern u32_t phyaddrforemac;
+
+static void __attribute__ ((noinline)) AxiEthernetUtilPhyDelay(unsigned int Seconds);
+
+static int detect_phy(XAxiEthernet *xaxiemacp)
+{
+ u16 phy_reg;
+ u16 phy_id;
+ u32 phy_addr;
+
+ for (phy_addr = 31; phy_addr > 0; phy_addr--) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_DETECT_REG,
+ &phy_reg);
+
+ if ((phy_reg != 0xFFFF) &&
+ ((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+ /* Found a valid PHY address */
+ LWIP_DEBUGF(NETIF_DEBUG, ("XAxiEthernet detect_phy: PHY detected at address %d.\r\n", phy_addr));
+ LWIP_DEBUGF(NETIF_DEBUG, ("XAxiEthernet detect_phy: PHY detected.\r\n"));
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_IDENTIFIER_1_REG,
+ &phy_reg);
+ if ((phy_reg != PHY_MARVELL_IDENTIFIER) &&
+ (phy_reg != TI_PHY_IDENTIFIER)){
+ xil_printf("WARNING: Not a Marvell or TI Ethernet PHY. Please verify the initialization sequence\r\n");
+ }
+ phyaddrforemac = phy_addr;
+ return phy_addr;
+ }
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_IDENTIFIER_1_REG,
+ &phy_id);
+
+ if (phy_id == PHY_XILINX_PCS_PMA_ID1) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_IDENTIFIER_2_REG,
+ &phy_id);
+ if (phy_id == PHY_XILINX_PCS_PMA_ID2) {
+ /* Found a valid PHY address */
+ LWIP_DEBUGF(NETIF_DEBUG, ("XAxiEthernet detect_phy: PHY detected at address %d.\r\n",
+ phy_addr));
+ phyaddrforemac = phy_addr;
+ return phy_addr;
+ }
+ }
+ }
+
+ LWIP_DEBUGF(NETIF_DEBUG, ("XAxiEthernet detect_phy: No PHY detected. Assuming a PHY at address 0\r\n"));
+
+ /* default to zero */
+ return 0;
+}
+
+void XAxiEthernet_PhyReadExtended(XAxiEthernet *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 *PhyDataPtr)
+{
+ XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_CONTROL_REG, IEEE_MMD_ACCESS_CTRL_DEVAD_MASK);
+
+ XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_ADDRESS_DATA_REG, RegisterNum);
+
+ XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_CONTROL_REG, IEEE_MMD_ACCESS_CTRL_NOPIDEVAD_MASK);
+
+ XAxiEthernet_PhyRead(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_ADDRESS_DATA_REG, PhyDataPtr);
+
+}
+
+void XAxiEthernet_PhyWriteExtended(XAxiEthernet *InstancePtr, u32 PhyAddress,
+ u32 RegisterNum, u16 PhyDataPtr)
+{
+ XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_CONTROL_REG, IEEE_MMD_ACCESS_CTRL_DEVAD_MASK);
+
+ XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_ADDRESS_DATA_REG, RegisterNum);
+
+ XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_CONTROL_REG, IEEE_MMD_ACCESS_CTRL_NOPIDEVAD_MASK);
+
+ XAxiEthernet_PhyWrite(InstancePtr, PhyAddress,
+ IEEE_MMD_ACCESS_ADDRESS_DATA_REG, PhyDataPtr);
+
+}
+
+unsigned int get_phy_negotiated_speed (XAxiEthernet *xaxiemacp, u32 phy_addr)
+{
+ u16 control;
+ u16 status;
+ u16 partner_capabilities;
+ u16 partner_capabilities_1000;
+ u16 phylinkspeed;
+ u16 temp;
+
+#ifdef XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT
+ phy_addr = XPAR_PCSPMA_1000BASEX_PHYADDR;
+#elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT
+ phy_addr = XPAR_PCSPMA_SGMII_PHYADDR;
+#endif
+
+ xil_printf("Start PHY autonegotiation \r\n");
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ &control);
+
+ control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
+ control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
+#ifdef PCM_PMA_CORE_PRESENT
+ control &= IEEE_CTRL_ISOLATE_DISABLE;
+#endif
+
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ control);
+#ifdef PCM_PMA_CORE_PRESENT
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ xil_printf("Waiting for PHY to complete autonegotiation \r\n");
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ AxiEthernetUtilPhyDelay(1);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET,
+ &status);
+
+ }
+
+ xil_printf("Autonegotiation complete \r\n");
+
+ if (xaxiemacp->Config.Speed == XAE_SPEED_2500_MBPS)
+ return XAE_SPEED_2500_MBPS;
+
+#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 1);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ if ((temp & 0x0020) == 0x0020) {
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+ return 1000;
+ }
+ else {
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+ xil_printf("Link error, temp = %x\r\n", temp);
+ return 0;
+ }
+#elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
+ xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \r\n");
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ while(!(temp & 0x8000)) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ }
+ if((temp & 0x0C00) == 0x0800) {
+ return 1000;
+ }
+ else if((temp & 0x0C00) == 0x0400) {
+ return 100;
+ }
+ else if((temp & 0x0C00) == 0x0000) {
+ return 10;
+ } else {
+ xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Defaulting to Speed = 10 Mbps\r\n");
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &temp);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, 0x0100);
+ return 10;
+ }
+#endif
+#endif
+
+ /* Read PHY control and status registers is successful. */
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ &control);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET,
+ &status);
+ if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) && (status &
+ IEEE_STAT_AUTONEGOTIATE_CAPABLE)) {
+ xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_STATUS_REG_OFFSET,
+ &status);
+ }
+
+ xil_printf("autonegotiation complete \r\n");
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_PARTNER_ABILITIES_1_REG_OFFSET,
+ &partner_capabilities);
+ if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_PARTNER_ABILITIES_3_REG_OFFSET,
+ &partner_capabilities_1000);
+ if (partner_capabilities_1000 &
+ IEEE_AN3_ABILITY_MASK_1GBPS)
+ return 1000;
+ }
+
+ if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS)
+ return 100;
+ if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS)
+ return 10;
+
+ xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n",
+ __FUNCTION__);
+ return 10;
+ } else {
+ /* Update TEMAC speed accordingly */
+ if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
+
+ /* Get commanded link speed */
+ phylinkspeed = control &
+ IEEE_CTRL_1GBPS_LINKSPEED_MASK;
+
+ switch (phylinkspeed) {
+ case (IEEE_CTRL_LINKSPEED_1000M):
+ return 1000;
+ case (IEEE_CTRL_LINKSPEED_100M):
+ return 100;
+ case (IEEE_CTRL_LINKSPEED_10M):
+ return 10;
+ default:
+ xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n",
+ __FUNCTION__, phylinkspeed);
+ return 10;
+ }
+ } else {
+ return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10;
+ }
+ }
+}
+
+unsigned int get_phy_speed_TI_DP83867(XAxiEthernet *xaxiemacp, u32 phy_addr)
+{
+ u16 phy_val;
+ u16 control;
+
+ xil_printf("Start PHY autonegotiation \r\n");
+
+ /* Changing the PHY RX and TX DELAY settings. */
+ XAxiEthernet_PhyReadExtended(xaxiemacp, phy_addr, DP83867_R32_RGMIICTL1, &phy_val);
+ phy_val |= DP83867_RGMII_CLOCK_DELAY_CTRL_MASK;
+ XAxiEthernet_PhyWriteExtended(xaxiemacp, phy_addr, DP83867_R32_RGMIICTL1, phy_val);
+
+ XAxiEthernet_PhyReadExtended(xaxiemacp, phy_addr, DP83867_R86_RGMIIDCTL, &phy_val);
+ phy_val &= 0xFF00;
+ phy_val |= DP83867_RGMII_TX_CLOCK_DELAY_MASK;
+ phy_val |= DP83867_RGMII_RX_CLOCK_DELAY_MASK;
+ XAxiEthernet_PhyWriteExtended(xaxiemacp, phy_addr, DP83867_R86_RGMIIDCTL, phy_val);
+
+ /* Set advertised speeds for 10/100/1000Mbps modes. */
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
+ control |= IEEE_ASYMMETRIC_PAUSE_MASK;
+ control |= IEEE_PAUSE_MASK;
+ control |= ADVERTISE_100;
+ control |= ADVERTISE_10;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &control);
+ control |= ADVERTISE_1000;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, control);
+
+ return get_phy_negotiated_speed(xaxiemacp, phy_addr);
+}
+
+unsigned int get_phy_speed_TI_DP83867_SGMII(XAxiEthernet *xaxiemacp, u32 phy_addr)
+{
+ u16 control;
+ u16 temp;
+ u16 phyregtemp;
+
+ xil_printf("Start TI PHY autonegotiation \r\n");
+
+ /* Enable SGMII Clock */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR,
+ TI_PHY_REGCR_DEVAD_EN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR,
+ TI_PHY_SGMIITYPE);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR,
+ TI_PHY_REGCR_DEVAD_EN | TI_PHY_REGCR_DEVAD_DATAEN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR,
+ TI_PHY_SGMIICLK_EN);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ &control);
+ control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE | IEEE_CTRL_LINKSPEED_1000M |
+ IEEE_CTRL_FULL_DUPLEX);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ control);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, TI_PHY_CFGR2, &control);
+ control &= TI_PHY_CFGR2_MASK;
+ control |= (TI_PHY_CFG2_SPEEDOPT_10EN |
+ TI_PHY_CFG2_SGMII_AUTONEGEN |
+ TI_PHY_CFG2_SPEEDOPT_ENH |
+ TI_PHY_CFG2_SPEEDOPT_CNT |
+ TI_PHY_CFG2_SPEEDOPT_INTLOW);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_CFGR2, control);
+
+ /* Disable RGMII */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR,
+ TI_PHY_REGCR_DEVAD_EN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR,
+ DP83867_R32_RGMIICTL1);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR,
+ TI_PHY_REGCR_DEVAD_EN | TI_PHY_REGCR_DEVAD_DATAEN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR, 0);
+
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_PHYCTRL,
+ TI_PHY_CR_SGMII_EN);
+
+ xil_printf("Waiting for Link to be up \r\n");
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ while(!(temp & 0x4000)) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ }
+ xil_printf("Auto negotiation completed for TI PHY\n\r");
+
+ /* SW workaround for unstable link when RX_CTRL is not STRAP MODE 3 or 4 */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR, TI_PHY_REGCR_DEVAD_EN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR, TI_PHY_REGCFG4);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR, TI_PHY_REGCR_DATA);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, TI_PHY_ADDDR, (u16_t *)&phyregtemp);
+ phyregtemp &= ~(TI_PHY_CFG4RESVDBIT7);
+ phyregtemp |= TI_PHY_CFG4RESVDBIT8;
+ phyregtemp &= ~(TI_PHY_CFG4_AUTONEG_TIMER);
+ phyregtemp |= TI_PHY_CFG4_AUTONEG_TIMER;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR, TI_PHY_REGCR_DEVAD_EN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR, TI_PHY_REGCFG4);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR, TI_PHY_REGCR_DATA);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR, phyregtemp);
+
+ return get_phy_negotiated_speed(xaxiemacp, phy_addr);
+}
+
+unsigned int get_phy_speed_88E1116R(XAxiEthernet *xaxiemacp, u32 phy_addr)
+{
+ u16 phy_val;
+ u16 control;
+ u16 status;
+ u16 partner_capabilities;
+
+ xil_printf("Start PHY autonegotiation \r\n");
+
+ XAxiEthernet_PhyWrite(xaxiemacp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
+ control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, control);
+
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
+ control |= IEEE_ASYMMETRIC_PAUSE_MASK;
+ control |= IEEE_PAUSE_MASK;
+ control |= ADVERTISE_100;
+ control |= ADVERTISE_10;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ &control);
+ control |= ADVERTISE_1000;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ control);
+
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
+ &control);
+ control |= (7 << 12); /* max number of gigabit atphy_valts */
+ control |= (1 << 11); /* enable downshift */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
+ control);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
+ control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_RESET_MASK;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+ while (1) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ if (control & IEEE_CTRL_RESET_MASK)
+ continue;
+ else
+ break;
+ }
+
+ xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ AxiEthernetUtilPhyDelay(1);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2,
+ &phy_val);
+ if (phy_val & IEEE_AUTONEG_ERROR_MASK) {
+ xil_printf("Auto negotiation error \r\n");
+ }
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_STATUS_REG_OFFSET,
+ &status);
+ }
+
+ xil_printf("autonegotiation complete \r\n");
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_SPECIFIC_STATUS_REG,
+ &partner_capabilities);
+ if ( ((partner_capabilities >> 14) & 3) == 2)/* 1000Mbps */
+ return 1000;
+ else if ( ((partner_capabilities >> 14) & 3) == 1)/* 100Mbps */
+ return 100;
+ else /* 10Mbps */
+ return 10;
+}
+
+
+unsigned int get_phy_speed_88E1111 (XAxiEthernet *xaxiemacp, u32 phy_addr)
+{
+ u16 control;
+ int TimeOut;
+ u16 phy_val;
+
+ if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
+ XAE_PHY_TYPE_RGMII_2_0) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_EXT_PHY_SPECIFIC_CONTROL_REG, &phy_val);
+ phy_val |= PHY_88E1111_RGMII_RX_CLOCK_DELAYED_MASK;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
+ IEEE_EXT_PHY_SPECIFIC_CONTROL_REG, phy_val);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ &control);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ control | IEEE_CTRL_RESET_MASK);
+
+ TimeOut = RESET_TIMEOUT;
+ while (TimeOut) {
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_CONTROL_REG_OFFSET, &control);
+ if (!(control & IEEE_CTRL_RESET_MASK))
+ break;
+ TimeOut -= 1;
+ }
+
+ if (!TimeOut) {
+ xil_printf("%s: Phy Reset failed\n\r", __FUNCTION__);
+ return 0;
+ }
+ }
+
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ ADVERTISE_1000);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG,
+ ADVERTISE_100_AND_10);
+
+ return get_phy_negotiated_speed(xaxiemacp, phy_addr);
+}
+
+unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp)
+{
+ u16 phy_identifier;
+ u16 phy_model;
+ u8 phytype;
+
+#ifdef XPAR_AXIETHERNET_0_BASEADDR
+ u32 phy_addr = detect_phy(xaxiemacp);
+
+ /* Get the PHY Identifier and Model number */
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_IDENTIFIER_1_REG, &phy_identifier);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_IDENTIFIER_2_REG, &phy_model);
+
+/* Depending upon what manufacturer PHY is connected, a different mask is
+ * needed to determine the specific model number of the PHY. */
+ if (phy_identifier == MARVEL_PHY_IDENTIFIER) {
+ phy_model = phy_model & MARVEL_PHY_MODEL_NUM_MASK;
+
+ if (phy_model == MARVEL_PHY_88E1116R_MODEL) {
+ return get_phy_speed_88E1116R(xaxiemacp, phy_addr);
+ } else if (phy_model == MARVEL_PHY_88E1111_MODEL) {
+ return get_phy_speed_88E1111(xaxiemacp, phy_addr);
+ }
+ } else if (phy_identifier == TI_PHY_IDENTIFIER) {
+ phy_model = phy_model & TI_PHY_DP83867_MODEL;
+ phytype = XAxiEthernet_GetPhysicalInterface(xaxiemacp);
+
+ if (phy_model == TI_PHY_DP83867_MODEL && phytype == XAE_PHY_TYPE_SGMII) {
+ return get_phy_speed_TI_DP83867_SGMII(xaxiemacp, phy_addr);
+ }
+
+ if (phy_model == TI_PHY_DP83867_MODEL) {
+ return get_phy_speed_TI_DP83867(xaxiemacp, phy_addr);
+ }
+ }
+ else {
+ LWIP_DEBUGF(NETIF_DEBUG, ("XAxiEthernet get_IEEE_phy_speed: Detected PHY with unknown identifier/model.\r\n"));
+ }
+#endif
+#ifdef PCM_PMA_CORE_PRESENT
+ return get_phy_negotiated_speed(xaxiemacp, phy_addr);
+#endif
+}
+
+unsigned configure_IEEE_phy_speed(XAxiEthernet *xaxiemacp, unsigned speed)
+{
+ u16 control;
+ u32 phy_addr = detect_phy(xaxiemacp);
+ u16 phy_val;
+
+ if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
+ XAE_PHY_TYPE_RGMII_2_0) {
+ /* Setting Tx and Rx Delays for RGMII mode */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0x2);
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, &phy_val);
+ phy_val |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, phy_val);
+
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0x0);
+ }
+
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr,
+ IEEE_CONTROL_REG_OFFSET,
+ &control);
+ control &= ~IEEE_CTRL_LINKSPEED_1000M;
+ control &= ~IEEE_CTRL_LINKSPEED_100M;
+ control &= ~IEEE_CTRL_LINKSPEED_10M;
+
+ if (speed == 1000) {
+ control |= IEEE_CTRL_LINKSPEED_1000M;
+ }
+
+ else if (speed == 100) {
+ control |= IEEE_CTRL_LINKSPEED_100M;
+ /* Don't advertise PHY speed of 1000 Mbps */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
+ IEEE_1000_ADVERTISE_REG_OFFSET,
+ 0);
+ /* Don't advertise PHY speed of 10 Mbps */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
+ IEEE_AUTONEGO_ADVERTISE_REG,
+ ADVERTISE_100);
+
+ }
+ else if (speed == 10) {
+ control |= IEEE_CTRL_LINKSPEED_10M;
+ /* Don't advertise PHY speed of 1000 Mbps */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
+ IEEE_1000_ADVERTISE_REG_OFFSET,
+ 0);
+ /* Don't advertise PHY speed of 100 Mbps */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
+ IEEE_AUTONEGO_ADVERTISE_REG,
+ ADVERTISE_10);
+ }
+
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr,
+ IEEE_CONTROL_REG_OFFSET,
+ control | IEEE_CTRL_RESET_MASK);
+
+ if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
+ XAE_PHY_TYPE_SGMII) {
+ control &= (~PHY_R0_ISOLATE);
+ XAxiEthernet_PhyWrite(xaxiemacp,
+ XPAR_AXIETHERNET_0_PHYADDR,
+ IEEE_CONTROL_REG_OFFSET,
+ control | IEEE_CTRL_AUTONEGOTIATE_ENABLE);
+ }
+
+ {
+ volatile int wait;
+ for (wait=0; wait < 100000; wait++);
+ for (wait=0; wait < 100000; wait++);
+ }
+ return 0;
+}
+
+unsigned phy_setup_axiemac (XAxiEthernet *xaxiemacp)
+{
+ unsigned link_speed = 1000;
+
+ if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
+ XAE_PHY_TYPE_RGMII_1_3) {
+ ; /* Add PHY initialization code for RGMII 1.3 */
+ } else if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
+ XAE_PHY_TYPE_RGMII_2_0) {
+ ; /* Add PHY initialization code for RGMII 2.0 */
+ } else if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
+ XAE_PHY_TYPE_SGMII) {
+#ifdef CONFIG_LINKSPEED_AUTODETECT
+ u32 phy_wr_data = IEEE_CTRL_AUTONEGOTIATE_ENABLE |
+ IEEE_CTRL_LINKSPEED_1000M;
+ phy_wr_data &= (~PHY_R0_ISOLATE);
+
+ XAxiEthernet_PhyWrite(xaxiemacp,
+ XPAR_AXIETHERNET_0_PHYADDR,
+ IEEE_CONTROL_REG_OFFSET,
+ phy_wr_data);
+#endif
+ } else if (XAxiEthernet_GetPhysicalInterface(xaxiemacp) ==
+ XAE_PHY_TYPE_1000BASE_X) {
+ ; /* Add PHY initialization code for 1000 Base-X */
+ }
+/* set PHY <--> MAC data clock */
+#ifdef CONFIG_LINKSPEED_AUTODETECT
+ link_speed = get_IEEE_phy_speed(xaxiemacp);
+ xil_printf("auto-negotiated link speed: %d\r\n", link_speed);
+#elif defined(CONFIG_LINKSPEED1000)
+ link_speed = 1000;
+ configure_IEEE_phy_speed(xaxiemacp, link_speed);
+ xil_printf("link speed: %d\r\n", link_speed);
+#elif defined(CONFIG_LINKSPEED100)
+ link_speed = 100;
+ configure_IEEE_phy_speed(xaxiemacp, link_speed);
+ xil_printf("link speed: %d\r\n", link_speed);
+#elif defined(CONFIG_LINKSPEED10)
+ link_speed = 10;
+ configure_IEEE_phy_speed(xaxiemacp, link_speed);
+ xil_printf("link speed: %d\r\n", link_speed);
+#endif
+ return link_speed;
+}
+
+static void __attribute__ ((noinline)) AxiEthernetUtilPhyDelay(unsigned int Seconds)
+{
+#if defined (__MICROBLAZE__)
+ static int WarningFlag = 0;
+
+ /* If MB caches are disabled or do not exist, this delay loop could
+ * take minutes instead of seconds (e.g., 30x longer). Print a warning
+ * message for the user (once). If only MB had a built-in timer!
+ */
+ if (((mfmsr() & 0x20) == 0) && (!WarningFlag)) {
+ WarningFlag = 1;
+ }
+
+#define ITERS_PER_SEC (XPAR_CPU_CORE_CLOCK_FREQ_HZ / 6)
+ asm volatile ("\n"
+ "1: \n\t"
+ "addik r7, r0, %0 \n\t"
+ "2: \n\t"
+ "addik r7, r7, -1 \n\t"
+ "bneid r7, 2b \n\t"
+ "or r0, r0, r0 \n\t"
+ "bneid %1, 1b \n\t"
+ "addik %1, %1, -1 \n\t"
+ :: "i"(ITERS_PER_SEC), "d" (Seconds));
+#else
+ sleep(Seconds);
+#endif
+}
+
+void enable_sgmii_clock(XAxiEthernet *xaxiemacp)
+{
+ u16 phy_identifier;
+ u16 phy_model;
+ u8 phytype;
+
+ XAxiEthernet_PhySetMdioDivisor(xaxiemacp, XAE_MDIO_DIV_DFT);
+ u32 phy_addr = detect_phy(xaxiemacp);
+ /* Get the PHY Identifier and Model number */
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_IDENTIFIER_1_REG, &phy_identifier);
+ XAxiEthernet_PhyRead(xaxiemacp, phy_addr, PHY_IDENTIFIER_2_REG, &phy_model);
+
+ if (phy_identifier == TI_PHY_IDENTIFIER) {
+ phy_model = phy_model & TI_PHY_DP83867_MODEL;
+ phytype = XAxiEthernet_GetPhysicalInterface(xaxiemacp);
+
+ if (phy_model == TI_PHY_DP83867_MODEL && phytype == XAE_PHY_TYPE_SGMII) {
+ /* Enable SGMII Clock by switching to 6-wire mode */
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR,
+ TI_PHY_REGCR_DEVAD_EN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR,
+ TI_PHY_SGMIITYPE);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_REGCR,
+ TI_PHY_REGCR_DEVAD_EN | TI_PHY_REGCR_DEVAD_DATAEN);
+ XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, TI_PHY_ADDDR,
+ TI_PHY_SGMIICLK_EN);
+ }
+ }
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemac_ieee_reg.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemac_ieee_reg.h
new file mode 100644
index 0000000..4c240a9
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemac_ieee_reg.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2018 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XEMAC_IEEE_REGS_H_
+#define __XEMAC_IEEE_REGS_H_
+
+/* Advertisement control register. */
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
+
+
+#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \
+ ADVERTISE_10HALF | ADVERTISE_100HALF)
+#define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF)
+#define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF)
+
+#define ADVERTISE_1000 0x0300
+
+
+#define IEEE_CONTROL_REG_OFFSET 0
+#define IEEE_STATUS_REG_OFFSET 1
+#define IEEE_AUTONEGO_ADVERTISE_REG 4
+#define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5
+#define IEEE_PARTNER_ABILITIES_2_REG_OFFSET 8
+#define IEEE_PARTNER_ABILITIES_3_REG_OFFSET 10
+#define IEEE_1000_ADVERTISE_REG_OFFSET 9
+#define IEEE_MMD_ACCESS_CONTROL_REG 13
+#define IEEE_MMD_ACCESS_ADDRESS_DATA_REG 14
+#define IEEE_COPPER_SPECIFIC_CONTROL_REG 16
+#define IEEE_SPECIFIC_STATUS_REG 17
+#define IEEE_COPPER_SPECIFIC_STATUS_REG_2 19
+#define IEEE_EXT_PHY_SPECIFIC_CONTROL_REG 20
+#define IEEE_CONTROL_REG_MAC 21
+#define IEEE_PAGE_ADDRESS_REGISTER 22
+
+#define IEEE_CTRL_1GBPS_LINKSPEED_MASK 0x2040
+#define IEEE_CTRL_LINKSPEED_MASK 0x0040
+#define IEEE_CTRL_LINKSPEED_1000M 0x0040
+#define IEEE_CTRL_LINKSPEED_100M 0x2000
+#define IEEE_CTRL_LINKSPEED_10M 0x0000
+#define IEEE_CTRL_FULL_DUPLEX 0x100
+#define IEEE_CTRL_RESET_MASK 0x8000
+#define IEEE_CTRL_AUTONEGOTIATE_ENABLE 0x1000
+#define IEEE_STAT_AUTONEGOTIATE_CAPABLE 0x0008
+#define IEEE_STAT_AUTONEGOTIATE_COMPLETE 0x0020
+#define IEEE_STAT_AUTONEGOTIATE_RESTART 0x0200
+#define IEEE_STAT_LINK_STATUS 0x0004
+#define IEEE_STAT_1GBPS_EXTENSIONS 0x0100
+#define IEEE_AN1_ABILITY_MASK 0x1FE0
+#define IEEE_AN3_ABILITY_MASK_1GBPS 0x0C00
+#define IEEE_AN1_ABILITY_MASK_100MBPS 0x0380
+#define IEEE_AN1_ABILITY_MASK_10MBPS 0x0060
+#define IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK 0x0030
+
+#define IEEE_SPEED_MASK 0xC000
+#define IEEE_SPEED_1000 0x8000
+#define IEEE_SPEED_100 0x4000
+
+#define IEEE_ASYMMETRIC_PAUSE_MASK 0x0800
+#define IEEE_PAUSE_MASK 0x0400
+#define IEEE_AUTONEG_ERROR_MASK 0x8000
+
+#define IEEE_MMD_ACCESS_CTRL_DEVAD_MASK 0x1F
+#define IEEE_MMD_ACCESS_CTRL_PIDEVAD_MASK 0x801F
+#define IEEE_MMD_ACCESS_CTRL_NOPIDEVAD_MASK 0x401F
+
+#endif /* __XEMAC_IEEE_REGS_H_ */
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacliteif.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacliteif.c
new file mode 100644
index 0000000..41f4933
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacliteif.c
@@ -0,0 +1,854 @@
+/*
+ * Copyright (C) 2007 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwipopts.h"
+#include "xlwipconfig.h"
+
+#if !NO_SYS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "timers.h"
+#include "lwip/timeouts.h"
+#endif
+
+#include
+#include
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+#include "netif/etharp.h"
+#include "netif/xadapter.h"
+#include "netif/xemacliteif.h"
+#include "xstatus.h"
+
+#include "netif/xpqueue.h"
+
+#include "xlwipconfig.h"
+#include "xparameters.h"
+#if XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ == 1
+#include "xscugic.h"
+#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_DIST_BASEADDR
+#else
+#include "xintc.h"
+#endif
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'x'
+#define IFNAME1 'e'
+
+
+/* Advertisement control register. */
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
+
+
+#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \
+ ADVERTISE_10HALF | ADVERTISE_100HALF)
+#define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF)
+#define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF)
+
+#if XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ == 1
+#define EMACLITE_INTR_PRIORITY_SET_IN_GIC 0xA0
+#define TRIG_TYPE_RISING_EDGE_SENSITIVE 0x3
+#endif
+
+#define IEEE_CONTROL_REG_OFFSET 0
+#define IEEE_STATUS_REG_OFFSET 1
+#define IEEE_AUTONEGO_ADVERTISE_REG 4
+#define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5
+#define IEEE_PARTNER_ABILITIES_2_REG_OFFSET 8
+#define IEEE_PARTNER_ABILITIES_3_REG_OFFSET 10
+#define IEEE_1000_ADVERTISE_REG_OFFSET 9
+#define IEEE_CTRL_1GBPS_LINKSPEED_MASK 0x2040
+#define IEEE_CTRL_LINKSPEED_MASK 0x0040
+#define IEEE_CTRL_LINKSPEED_1000M 0x0040
+#define IEEE_CTRL_LINKSPEED_100M 0x2000
+#define IEEE_CTRL_LINKSPEED_10M 0x0000
+#define IEEE_CTRL_RESET_MASK 0x8000
+#define IEEE_CTRL_AUTONEGOTIATE_ENABLE 0x1000
+#define IEEE_STAT_AUTONEGOTIATE_CAPABLE 0x0008
+#define IEEE_STAT_AUTONEGOTIATE_COMPLETE 0x0020
+#define IEEE_STAT_AUTONEGOTIATE_RESTART 0x0200
+#define IEEE_STAT_1GBPS_EXTENSIONS 0x0100
+#define IEEE_AN1_ABILITY_MASK 0x1FE0
+#define IEEE_AN3_ABILITY_MASK_1GBPS 0x0C00
+#define IEEE_AN1_ABILITY_MASK_100MBPS 0x0380
+#define IEEE_AN1_ABILITY_MASK_10MBPS 0x0060
+
+#define PHY_DETECT_REG 1
+#define PHY_DETECT_MASK 0x1808
+
+/* Forward declarations. */
+static err_t xemacliteif_output(struct netif *netif, struct pbuf *p,
+ const ip_addr_t *ipaddr);
+unsigned get_IEEE_phy_speed_emaclite(XEmacLite *xemaclitep);
+unsigned configure_IEEE_phy_speed_emaclite(XEmacLite *xemaclitep, unsigned speed);
+
+/* The payload from multiple pbufs is assembled into a single contiguous
+ * area for transmission. Currently this is a global variable (it should really
+ * belong in the per netif structure), but that is ok since this can be used
+ * only in a protected context
+ */
+unsigned char xemac_tx_frame[XEL_MAX_FRAME_SIZE] __attribute__((aligned(64)));
+
+#if !NO_SYS
+unsigned int xInsideISR = 0;
+#endif
+
+#ifndef XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ
+#if XPAR_INTC_0_HAS_FAST == 1
+/*********** Function Prototypes *********************************************/
+/*
+ * Function prototypes of the functions used for registering Fast
+ * Interrupt Handlers
+ */
+static void XEmacLite_FastInterruptHandler(void)
+ __attribute__ ((fast_interrupt));
+
+
+/**************** Variable Declarations **************************************/
+
+/** Variables for Fast Interrupt handlers ***/
+XEmacLite *xemaclitep_fast;
+
+#endif
+#endif
+
+static void
+xemacif_recv_handler(void *arg) {
+ struct xemac_s *xemac = (struct xemac_s *)(arg);
+ xemacliteif_s *xemacliteif = (xemacliteif_s *)(xemac->state);
+ XEmacLite *instance = xemacliteif->instance;
+ struct pbuf *p;
+ int len = 0;
+ struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+
+#if XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ == 1
+#else
+ XIntc_AckIntr(xtopologyp->intc_baseaddr, 1 << xtopologyp->intc_emac_intr);
+#endif
+ p = pbuf_alloc(PBUF_RAW, XEL_MAX_FRAME_SIZE, PBUF_POOL);
+ if (!p) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ /* receive and just ignore the frame.
+ * we need to receive the frame because otherwise emaclite will
+ * not generate any other interrupts since it cannot receive,
+ * and we do not actively poll the emaclite
+ */
+ XEmacLite_Recv(instance, xemac_tx_frame);
+#if !NO_SYS
+ xInsideISR--;
+#endif
+ return;
+ }
+
+ /* receive the packet */
+ len = XEmacLite_Recv(instance, p->payload);
+
+ if (len == 0) {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ pbuf_free(p);
+#if !NO_SYS
+ xInsideISR--;
+#endif
+ return;
+ }
+
+ /* store it in the receive queue, where it'll be processed by xemacif input thread */
+ if (pq_enqueue(xemacliteif->recv_q, (void*)p) < 0) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ pbuf_free(p);
+#if !NO_SYS
+ xInsideISR--;
+#endif
+ return;
+ }
+
+#if !NO_SYS
+ sys_sem_signal(&xemac->sem_rx_data_available);
+ xInsideISR--;
+#endif
+}
+
+int transmit_packet(XEmacLite *instancep, void *packet, unsigned len)
+{
+ XStatus result = 0;
+
+ /* there is space for a buffer, so transfer */
+ result = XEmacLite_Send(instancep, packet, len);
+
+ if (result != XST_SUCCESS) {
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * this function is always called with interrupts off
+ * this function also assumes that there is space to send in the Emaclite buffer
+ */
+static err_t
+_unbuffered_low_level_output(XEmacLite *instancep, struct pbuf *p)
+{
+ struct pbuf *q;
+ int total_len = 0;
+
+#if ETH_PAD_SIZE
+ pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+ for(q = p, total_len = 0; q != NULL; q = q->next) {
+ /* Send the data from the pbuf to the interface, one pbuf at a
+ time. The size of the data in each pbuf is kept in the ->len
+ variable. */
+ memcpy(xemac_tx_frame + total_len, q->payload, q->len);
+ total_len += q->len;
+ }
+
+ if (transmit_packet(instancep, xemac_tx_frame, total_len) < 0) {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ }
+
+#if ETH_PAD_SIZE
+ pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+#if LINK_STATS
+ lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+
+ return ERR_OK;
+}
+
+/*
+ * low_level_output():
+ *
+ * Should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ */
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+ SYS_ARCH_DECL_PROTECT(lev);
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xemacliteif_s *xemacliteif = (xemacliteif_s *)(xemac->state);
+ XEmacLite *instance = xemacliteif->instance;
+ struct pbuf *q;
+
+ SYS_ARCH_PROTECT(lev);
+
+ /* check if space is available to send */
+ if (XEmacLite_TxBufferAvailable(instance) == TRUE) {
+ if (pq_qlength(xemacliteif->send_q)) { /* send backlog */
+ _unbuffered_low_level_output(instance, (struct pbuf *)pq_dequeue(xemacliteif->send_q));
+ } else { /* send current */
+ _unbuffered_low_level_output(instance, p);
+ SYS_ARCH_UNPROTECT(lev);
+ return ERR_OK;
+ }
+ }
+
+ /* if we cannot send the packet immediately, then make a copy of the whole packet
+ * into a separate pbuf and store it in send_q. We cannot enqueue the pbuf as is
+ * since parts of the pbuf may be modified inside lwIP.
+ */
+ q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_POOL);
+ if (!q) {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ SYS_ARCH_UNPROTECT(lev);
+ return ERR_MEM;
+ }
+
+ for (q->len = 0; p; p = p->next) {
+ memcpy(q->payload + q->len, p->payload, p->len);
+ q->len += p->len;
+ }
+ if (pq_enqueue(xemacliteif->send_q, (void *)q) < 0) {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ SYS_ARCH_UNPROTECT(lev);
+ return ERR_MEM;
+ }
+
+ SYS_ARCH_UNPROTECT(lev);
+
+ return ERR_OK;
+}
+
+static void
+xemacif_send_handler(void *arg) {
+ struct xemac_s *xemac = (struct xemac_s *)(arg);
+ xemacliteif_s *xemacliteif = (xemacliteif_s *)(xemac->state);
+ XEmacLite *instance = xemacliteif->instance;
+ struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+#if XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ == 1
+#else
+ XIntc_AckIntr(xtopologyp->intc_baseaddr, 1 << xtopologyp->intc_emac_intr);
+#endif
+
+ if (pq_qlength(xemacliteif->send_q) && (XEmacLite_TxBufferAvailable(instance) == TRUE)) {
+ struct pbuf *p = pq_dequeue(xemacliteif->send_q);
+ _unbuffered_low_level_output(instance, p);
+ pbuf_free(p);
+ }
+#if !NO_SYS
+ xInsideISR--;
+#endif
+}
+
+/*
+ * low_level_input():
+ *
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ */
+static struct pbuf *
+low_level_input(struct netif *netif)
+{
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xemacliteif_s *xemacliteif = (xemacliteif_s *)(xemac->state);
+
+ /* see if there is data to process */
+ if (pq_qlength(xemacliteif->recv_q) == 0)
+ return NULL;
+
+ /* return one packet from receive q */
+ return (struct pbuf *)pq_dequeue(xemacliteif->recv_q);
+}
+
+/*
+ * xemacliteif_output():
+ *
+ * This function is called by the TCP/IP stack when an IP packet
+ * should be sent. It calls the function called low_level_output() to
+ * do the actual transmission of the packet.
+ *
+ */
+
+err_t
+xemacliteif_output(struct netif *netif, struct pbuf *p,
+ const ip_addr_t *ipaddr)
+{
+ /* resolve hardware address, then send (or queue) packet */
+ return etharp_output(netif, p, ipaddr);
+}
+
+/*
+ * xemacliteif_input():
+ *
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.
+ *
+ * Returns the number of packets read (max 1 packet on success,
+ * 0 if there are no packets)
+ *
+ */
+int
+xemacliteif_input(struct netif *netif)
+{
+ struct eth_hdr *ethhdr;
+ struct pbuf *p;
+ SYS_ARCH_DECL_PROTECT(lev);
+
+#if !NO_SYS
+ while (1)
+#endif
+ {
+ SYS_ARCH_PROTECT(lev);
+ /* move received packet into a new pbuf */
+ p = low_level_input(netif);
+ SYS_ARCH_UNPROTECT(lev);
+
+ /* no packet could be read, silently ignore this */
+ if (p == NULL)
+ return 0;
+
+ /* points to packet payload, which starts with an Ethernet header */
+ ethhdr = p->payload;
+
+ #if LINK_STATS
+ lwip_stats.link.recv++;
+ #endif /* LINK_STATS */
+
+ switch (htons(ethhdr->type)) {
+ /* IP or ARP packet? */
+ case ETHTYPE_IP:
+ case ETHTYPE_ARP:
+ #if PPPOE_SUPPORT
+ /* PPPoE packet? */
+ case ETHTYPE_PPPOEDISC:
+ case ETHTYPE_PPPOE:
+ #endif /* PPPOE_SUPPORT */
+ /* full packet send to tcpip_thread to process */
+ if (netif->input(p, netif) != ERR_OK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xlltemacif_input: IP input error\r\n"));
+ pbuf_free(p);
+ p = NULL;
+ }
+ break;
+
+ default:
+ pbuf_free(p);
+ p = NULL;
+ break;
+ }
+ }
+
+ return 1;
+}
+
+#if !NO_SYS
+static void
+arp_timer(void *arg)
+{
+ etharp_tmr();
+ sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+#endif
+
+static XEmacLite_Config *
+xemaclite_lookup_config(unsigned base)
+{
+ XEmacLite_Config *CfgPtr = NULL;
+ int i;
+
+ for (i = 0; i < XPAR_XEMACLITE_NUM_INSTANCES; i++)
+ if (XEmacLite_ConfigTable[i].BaseAddress == base) {
+ CfgPtr = &XEmacLite_ConfigTable[i];
+ break;
+ }
+
+ return CfgPtr;
+}
+
+static err_t low_level_init(struct netif *netif)
+{
+ struct xemac_s *xemac;
+ XEmacLite_Config *config;
+ XEmacLite *xemaclitep;
+ struct xtopology_t *xtopologyp;
+ xemacliteif_s *xemacliteif;
+ unsigned link_speed = 1000;
+
+ xemaclitep = mem_malloc(sizeof *xemaclitep);
+#ifndef XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ
+#if XPAR_INTC_0_HAS_FAST == 1
+ xemaclitep_fast = xemaclitep;
+#endif
+#endif
+ if (xemaclitep == NULL) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
+ return ERR_MEM;
+ }
+
+ xemac = mem_malloc(sizeof *xemac);
+ if (xemac == NULL) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
+ return ERR_MEM;
+ }
+
+ xemacliteif = mem_malloc(sizeof *xemacliteif);
+ if (xemacliteif == NULL) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
+ return ERR_MEM;
+ }
+
+ /* obtain pointer to topology structure for this emac */
+ xemac->topology_index = xtopology_find_index((unsigned)(netif->state));
+ xtopologyp = &xtopology[xemac->topology_index];
+
+ /* obtain config of this emaclite */
+ config = xemaclite_lookup_config((unsigned)(netif->state));
+
+ /* maximum transfer unit */
+ netif->mtu = XEL_MTU_SIZE;
+
+ /* broadcast capability */
+ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+
+ /* initialize the mac */
+ XEmacLite_Initialize(xemaclitep, config->DeviceId);
+ xemaclitep->NextRxBufferToUse = 0;
+
+#if XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ == 1
+ XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
+ xtopologyp->intc_emac_intr,
+ (Xil_ExceptionHandler)XEmacLite_InterruptHandler,
+ xemaclitep);
+
+ XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
+ xtopologyp->intc_emac_intr,
+ EMACLITE_INTR_PRIORITY_SET_IN_GIC,
+ TRIG_TYPE_RISING_EDGE_SENSITIVE);
+
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
+ xtopologyp->intc_emac_intr);
+#else
+#if NO_SYS
+#if XPAR_INTC_0_HAS_FAST == 1
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xtopologyp->intc_emac_intr,
+ (XFastInterruptHandler)XEmacLite_FastInterruptHandler);
+#else
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xtopologyp->intc_emac_intr,
+ (XInterruptHandler)XEmacLite_InterruptHandler,
+ xemaclitep);
+#endif
+#else
+#if XPAR_INTC_0_HAS_FAST == 1
+ XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
+ xtopologyp->intc_emac_intr,
+ (XFastInterruptHandler)XEmacLite_FastInterruptHandler);
+
+ XIntc_EnableIntr(xtopologyp->intc_baseaddr, XIntc_In32(xtopologyp->intc_baseaddr +
+ XIN_IER_OFFSET) | (1 << xtopologyp->intc_emac_intr));
+#else
+
+ XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
+ xtopologyp->intc_emac_intr,
+ (XInterruptHandler)XEmacLite_InterruptHandler,
+ xemaclitep);
+ XIntc_EnableIntr(xtopologyp->intc_baseaddr, XIntc_In32(xtopologyp->intc_baseaddr +
+ XIN_IER_OFFSET) | (1 << xtopologyp->intc_emac_intr));
+#endif
+#endif
+#endif
+
+ /* set mac address */
+ XEmacLite_SetMacAddress(xemaclitep, (unsigned char*)(netif->hwaddr));
+
+ /* flush any frames already received */
+ XEmacLite_FlushReceive(xemaclitep);
+
+ /* set Rx, Tx interrupt handlers */
+ XEmacLite_SetRecvHandler(xemaclitep, (void *)(xemac), xemacif_recv_handler);
+ XEmacLite_SetSendHandler(xemaclitep, (void *)(xemac), xemacif_send_handler);
+
+ /* enable Rx, Tx interrupts */
+ XEmacLite_EnableInterrupts(xemaclitep);
+
+#if !NO_SYS
+ sys_sem_new(&xemac->sem_rx_data_available, 0);
+#endif
+
+ /* replace the state in netif (currently the base address of emaclite)
+ * with the xemacliteif instance pointer.
+ * this contains a pointer to the config table entry
+ */
+ xemac->type = xemac_type_xps_emaclite;
+ xemac->state = (void *)xemacliteif;
+ netif->state = (void *)xemac;
+
+ xemacliteif->instance = xemaclitep;
+ xemacliteif->recv_q = pq_create_queue();
+ if (!xemacliteif->recv_q)
+ return ERR_MEM;
+
+ xemacliteif->send_q = pq_create_queue();
+ if (!xemacliteif->send_q)
+ return ERR_MEM;
+
+ /* Initialize PHY */
+
+
+/* set PHY <--> MAC data clock */
+#ifdef CONFIG_LINKSPEED_AUTODETECT
+ link_speed = get_IEEE_phy_speed_emaclite(xemaclitep);
+ xil_printf("auto-negotiated link speed: %d\r\n", link_speed);
+#elif defined(CONFIG_LINKSPEED1000)
+ xil_printf("Link speed of 1000 Mbps not possible\r\n");
+#elif defined(CONFIG_LINKSPEED100)
+ link_speed = 100;
+ configure_IEEE_phy_speed_emaclite(xemaclitep, link_speed);
+ xil_printf("link speed: %d\r\n", link_speed);
+#elif defined(CONFIG_LINKSPEED10)
+ link_speed = 10;
+ configure_IEEE_phy_speed_emaclite(xemaclitep, link_speed);
+ xil_printf("link speed: %d\r\n", link_speed);
+#endif
+
+ return ERR_OK;
+}
+
+
+static int detect_phy_emaclite(XEmacLite *xemaclitep)
+{
+ u16 phy_reg;
+ u32 phy_addr;
+
+ for (phy_addr = 31; phy_addr > 0; phy_addr--) {
+ XEmacLite_PhyRead(xemaclitep, phy_addr, PHY_DETECT_REG, &phy_reg);
+
+ if ((phy_reg != 0xFFFF) &&
+ ((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+ /* Found a valid PHY address */
+ LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: PHY detected at address %d.\r\n", phy_addr));
+ LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: PHY detected.\r\n"));
+ return phy_addr;
+ }
+ }
+
+ LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: No PHY detected. Assuming a PHY at address 0\r\n"));
+
+ /* default to zero */
+ return 0;
+}
+
+unsigned get_IEEE_phy_speed_emaclite(XEmacLite *xemaclitep)
+{
+ u16 control;
+ u16 status;
+ u16 partner_capabilities;
+ u16 partner_capabilities_1000;
+ u16 phylinkspeed;
+ u32 phy_addr = detect_phy_emaclite(xemaclitep);
+
+ /* Don't advertise PHY speed of 1000 Mbps */
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_1000_ADVERTISE_REG_OFFSET,
+ 0);
+ /* Advertise PHY speed of 100 and 10 Mbps */
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_AUTONEGO_ADVERTISE_REG,
+ ADVERTISE_100_AND_10);
+
+ XEmacLite_PhyRead(xemaclitep, phy_addr,
+ IEEE_CONTROL_REG_OFFSET,
+ &control);
+ control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE |
+ IEEE_STAT_AUTONEGOTIATE_RESTART);
+
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_CONTROL_REG_OFFSET,
+ control);
+
+ /* Read PHY control and status registers is successful. */
+ XEmacLite_PhyRead(xemaclitep, phy_addr,
+ IEEE_CONTROL_REG_OFFSET,
+ &control);
+ XEmacLite_PhyRead(xemaclitep, phy_addr,
+ IEEE_STATUS_REG_OFFSET,
+ &status);
+
+ if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) &&
+ (status & IEEE_STAT_AUTONEGOTIATE_CAPABLE)) {
+
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ XEmacLite_PhyRead(xemaclitep, phy_addr,
+ IEEE_STATUS_REG_OFFSET,
+ &status);
+ }
+
+ XEmacLite_PhyRead(xemaclitep, phy_addr,
+ IEEE_PARTNER_ABILITIES_1_REG_OFFSET,
+ &partner_capabilities);
+
+ if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
+ XEmacLite_PhyRead(xemaclitep, phy_addr,
+ IEEE_PARTNER_ABILITIES_3_REG_OFFSET,
+ &partner_capabilities_1000);
+ if (partner_capabilities_1000 & IEEE_AN3_ABILITY_MASK_1GBPS) return 1000;
+ }
+
+ if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS) return 100;
+ if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS) return 10;
+
+ xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n",
+ __FUNCTION__);
+ return 10;
+
+
+ } else {
+
+ /* Update TEMAC speed accordingly */
+ if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
+
+ /* Get commanded link speed */
+ phylinkspeed = control & IEEE_CTRL_1GBPS_LINKSPEED_MASK;
+
+ switch (phylinkspeed) {
+ case (IEEE_CTRL_LINKSPEED_1000M):
+ return 1000;
+ case (IEEE_CTRL_LINKSPEED_100M):
+ return 100;
+ case (IEEE_CTRL_LINKSPEED_10M):
+ return 10;
+ default:
+ xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n",
+ __FUNCTION__, phylinkspeed);
+ return 10;
+ }
+
+ } else {
+
+ return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10;
+
+ }
+
+ }
+}
+
+unsigned configure_IEEE_phy_speed_emaclite(XEmacLite *xemaclitep, unsigned speed)
+{
+ u16 control;
+ u32 phy_addr = detect_phy_emaclite(xemaclitep);
+
+ XEmacLite_PhyRead(xemaclitep, phy_addr,
+ IEEE_CONTROL_REG_OFFSET,
+ &control);
+ control &= ~IEEE_CTRL_LINKSPEED_100M;
+ control &= ~IEEE_CTRL_LINKSPEED_10M;
+ if (speed == 100) {
+ control |= IEEE_CTRL_LINKSPEED_100M;
+ /* Don't advertise PHY speed of 1000 Mbps */
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_1000_ADVERTISE_REG_OFFSET,
+ 0);
+ /* Don't advertise PHY speed of 10 Mbps */
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_AUTONEGO_ADVERTISE_REG,
+ ADVERTISE_100);
+
+ }
+ else if (speed == 10) {
+ control |= IEEE_CTRL_LINKSPEED_10M;
+ /* Don't advertise PHY speed of 1000 Mbps */
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_1000_ADVERTISE_REG_OFFSET,
+ 0);
+ /* Don't advertise PHY speed of 100 Mbps */
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_AUTONEGO_ADVERTISE_REG,
+ ADVERTISE_10);
+ }
+
+ XEmacLite_PhyWrite(xemaclitep, phy_addr,
+ IEEE_CONTROL_REG_OFFSET,
+ control | IEEE_CTRL_RESET_MASK);
+ {
+ volatile int wait;
+ for (wait=0; wait < 100000; wait++);
+ for (wait=0; wait < 100000; wait++);
+ }
+ return 0;
+}
+
+/*
+ * xemacliteif_init():
+ *
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ */
+
+err_t
+xemacliteif_init(struct netif *netif)
+{
+#if LWIP_SNMP
+ /* ifType ethernetCsmacd(6) @see RFC1213 */
+ netif->link_type = 6;
+ /* your link speed here */
+ netif->link_speed = ;
+ netif->ts = 0;
+ netif->ifinoctets = 0;
+ netif->ifinucastpkts = 0;
+ netif->ifinnucastpkts = 0;
+ netif->ifindiscards = 0;
+ netif->ifoutoctets = 0;
+ netif->ifoutucastpkts = 0;
+ netif->ifoutnucastpkts = 0;
+ netif->ifoutdiscards = 0;
+#endif
+
+ netif->name[0] = IFNAME0;
+ netif->name[1] = IFNAME1;
+ netif->output = xemacliteif_output;
+ netif->linkoutput = low_level_output;
+
+ low_level_init(netif);
+
+#if !NO_SYS
+ sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+#endif
+
+ return ERR_OK;
+}
+
+#ifndef XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ
+#if XPAR_INTC_0_HAS_FAST == 1
+/****************** Fast Interrupt Handler **********************************/
+
+void XEmacLite_FastInterruptHandler (void)
+{
+ XEmacLite_InterruptHandler((void *)xemaclitep_fast);
+}
+#endif
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif.c
new file mode 100644
index 0000000..1bf3abb
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif.c
@@ -0,0 +1,795 @@
+/*
+ * Copyright (C) 2010 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include
+#include
+
+#include
+#include "lwipopts.h"
+#include "xlwipconfig.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/igmp.h"
+
+#include "netif/etharp.h"
+#include "netif/xemacpsif.h"
+#include "netif/xadapter.h"
+#include "netif/xpqueue.h"
+#include "xparameters.h"
+#include "xscugic.h"
+#include "xemacps.h"
+
+#if LWIP_IPV6
+#include "lwip/ethip6.h"
+#endif
+
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 't'
+#define IFNAME1 'e'
+
+#if LWIP_IGMP
+static err_t xemacpsif_mac_filter_update (struct netif *netif,
+ ip_addr_t *group, u8_t action);
+
+static u8_t xemacps_mcast_entry_mask = 0;
+#endif
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+static err_t xemacpsif_mld6_mac_filter_update (struct netif *netif,
+ ip_addr_t *group, u8_t action);
+
+static u8_t xemacps_mld6_mcast_entry_mask;
+#endif
+
+XEmacPs_Config *mac_config;
+struct netif *NetIf;
+
+#if !NO_SYS
+#if defined(__arm__) && !defined(ARMR5)
+int32_t lExpireCounter = 0;
+#define RESETRXTIMEOUT 10
+#endif
+#endif
+
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+extern volatile u32_t notifyinfo[4*XLWIP_CONFIG_N_TX_DESC];
+#endif
+
+/*
+ * this function is always called with interrupts off
+ * this function also assumes that there are available BD's
+ */
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+static err_t _unbuffered_low_level_output(xemacpsif_s *xemacpsif,
+ struct pbuf *p, u32_t block_till_tx_complete, u32_t *to_block_index )
+#else
+static err_t _unbuffered_low_level_output(xemacpsif_s *xemacpsif,
+ struct pbuf *p)
+#endif
+{
+ XStatus status = 0;
+ err_t err = ERR_MEM;
+
+#if ETH_PAD_SIZE
+ pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (block_till_tx_complete == 1) {
+ status = emacps_sgsend(xemacpsif, p, 1, to_block_index);
+ } else {
+ status = emacps_sgsend(xemacpsif, p, 0, to_block_index);
+ }
+#else
+ status = emacps_sgsend(xemacpsif, p);
+#endif
+ if (status != XST_SUCCESS) {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ } else {
+ err = ERR_OK;
+ }
+
+#if ETH_PAD_SIZE
+ pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+#if LINK_STATS
+ lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+
+ return err;
+
+}
+
+/*
+ * low_level_output():
+ *
+ * Should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ */
+
+static err_t low_level_output(struct netif *netif, struct pbuf *p)
+{
+ err_t err = ERR_MEM;
+ s32_t freecnt;
+ XEmacPs_BdRing *txring;
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ u32_t notfifyblocksleepcntr;
+ u32_t to_block_index;
+#endif
+
+ SYS_ARCH_DECL_PROTECT(lev);
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+
+ SYS_ARCH_PROTECT(lev);
+ /* check if space is available to send */
+ freecnt = is_tx_space_available(xemacpsif);
+ if (freecnt <= 5) {
+ txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+ process_sent_bds(xemacpsif, txring);
+ }
+
+ if (is_tx_space_available(xemacpsif)) {
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (netif_is_opt_block_tx_set(netif, NETIF_ENABLE_BLOCKING_TX_FOR_PACKET)) {
+ err = _unbuffered_low_level_output(xemacpsif, p, 1, &to_block_index);
+ } else {
+ err = _unbuffered_low_level_output(xemacpsif, p, 0, &to_block_index);
+ }
+#else
+ err = _unbuffered_low_level_output(xemacpsif, p);
+#endif
+ } else {
+#if LINK_STATS
+ lwip_stats.link.drop++;
+#endif
+ printf("pack dropped, no space\r\n");
+ SYS_ARCH_UNPROTECT(lev);
+ goto return_pack_dropped;
+ }
+ SYS_ARCH_UNPROTECT(lev);
+
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (netif_is_opt_block_tx_set(netif, NETIF_ENABLE_BLOCKING_TX_FOR_PACKET)) {
+ /* Wait for approx 1 second before timing out */
+ notfifyblocksleepcntr = 900000;
+ while(notifyinfo[to_block_index] == 1) {
+ usleep(1);
+ notfifyblocksleepcntr--;
+ if (notfifyblocksleepcntr <= 0) {
+ err = ERR_TIMEOUT;
+ break;
+ }
+ }
+ }
+ netif_clear_opt_block_tx(netif, NETIF_ENABLE_BLOCKING_TX_FOR_PACKET);
+#endif
+return_pack_dropped:
+ return err;
+}
+
+/*
+ * low_level_input():
+ *
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ */
+static struct pbuf * low_level_input(struct netif *netif)
+{
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+ struct pbuf *p;
+
+ /* see if there is data to process */
+ if (pq_qlength(xemacpsif->recv_q) == 0)
+ return NULL;
+
+ /* return one packet from receive q */
+ p = (struct pbuf *)pq_dequeue(xemacpsif->recv_q);
+ return p;
+}
+
+/*
+ * xemacpsif_output():
+ *
+ * This function is called by the TCP/IP stack when an IP packet
+ * should be sent. It calls the function called low_level_output() to
+ * do the actual transmission of the packet.
+ *
+ */
+
+static err_t xemacpsif_output(struct netif *netif, struct pbuf *p,
+ const ip_addr_t *ipaddr)
+{
+ /* resolve hardware address, then send (or queue) packet */
+ return etharp_output(netif, p, ipaddr);
+}
+
+/*
+ * xemacpsif_input():
+ *
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.
+ *
+ * Returns the number of packets read (max 1 packet on success,
+ * 0 if there are no packets)
+ *
+ */
+
+s32_t xemacpsif_input(struct netif *netif)
+{
+ struct eth_hdr *ethhdr;
+ struct pbuf *p;
+ SYS_ARCH_DECL_PROTECT(lev);
+
+#if !NO_SYS
+ while (1)
+#endif
+ {
+ /* move received packet into a new pbuf */
+ SYS_ARCH_PROTECT(lev);
+ p = low_level_input(netif);
+ SYS_ARCH_UNPROTECT(lev);
+
+ /* no packet could be read, silently ignore this */
+ if (p == NULL) {
+ return 0;
+ }
+
+ /* points to packet payload, which starts with an Ethernet header */
+ ethhdr = p->payload;
+
+ #if LINK_STATS
+ lwip_stats.link.recv++;
+ #endif /* LINK_STATS */
+
+ switch (htons(ethhdr->type)) {
+ /* IP or ARP packet? */
+ case ETHTYPE_IP:
+ case ETHTYPE_ARP:
+ #if LWIP_IPV6
+ /*IPv6 Packet?*/
+ case ETHTYPE_IPV6:
+ #endif
+ #if PPPOE_SUPPORT
+ /* PPPoE packet? */
+ case ETHTYPE_PPPOEDISC:
+ case ETHTYPE_PPPOE:
+ #endif /* PPPOE_SUPPORT */
+ /* full packet send to tcpip_thread to process */
+ if (netif->input(p, netif) != ERR_OK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_input: IP input error\r\n"));
+ pbuf_free(p);
+ p = NULL;
+ }
+ break;
+
+ default:
+ pbuf_free(p);
+ p = NULL;
+ break;
+ }
+ }
+
+ return 1;
+}
+
+#if !NO_SYS
+#if defined(__arm__) && !defined(ARMR5)
+void vTimerCallback( TimerHandle_t pxTimer )
+{
+ /* Do something if the pxTimer parameter is NULL */
+ configASSERT(pxTimer);
+
+ lExpireCounter++;
+ /* If the timer has expired 100 times then reset RX */
+ if(lExpireCounter >= RESETRXTIMEOUT) {
+ lExpireCounter = 0;
+ xemacpsif_resetrx_on_no_rxdata(NetIf);
+ }
+}
+#endif
+#endif
+
+static err_t low_level_init(struct netif *netif)
+{
+ UINTPTR mac_address = (UINTPTR)(netif->state);
+ struct xemac_s *xemac;
+ xemacpsif_s *xemacpsif;
+ u32 dmacrreg;
+
+ s32_t status = XST_SUCCESS;
+
+ NetIf = netif;
+
+ xemacpsif = mem_malloc(sizeof *xemacpsif);
+ if (xemacpsif == NULL) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
+ return ERR_MEM;
+ }
+
+ xemac = mem_malloc(sizeof *xemac);
+ if (xemac == NULL) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n"));
+ return ERR_MEM;
+ }
+
+ xemac->state = (void *)xemacpsif;
+ xemac->topology_index = xtopology_find_index(mac_address);
+ xemac->type = xemac_type_emacps;
+
+ xemacpsif->send_q = NULL;
+ xemacpsif->recv_q = pq_create_queue();
+ if (!xemacpsif->recv_q)
+ return ERR_MEM;
+
+ /* maximum transfer unit */
+#ifdef ZYNQMP_USE_JUMBO
+ netif->mtu = XEMACPS_MTU_JUMBO - XEMACPS_HDR_SIZE;
+#else
+ netif->mtu = XEMACPS_MTU - XEMACPS_HDR_SIZE;
+#endif
+
+#if LWIP_IGMP
+ netif->igmp_mac_filter = xemacpsif_mac_filter_update;
+#endif
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+ netif->mld_mac_filter = xemacpsif_mld6_mac_filter_update;
+#endif
+
+ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP |
+ NETIF_FLAG_LINK_UP;
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+ netif->flags |= NETIF_FLAG_MLD6;
+#endif
+
+#if LWIP_IGMP
+ netif->flags |= NETIF_FLAG_IGMP;
+#endif
+
+#if !NO_SYS
+ sys_sem_new(&xemac->sem_rx_data_available, 0);
+#endif
+ /* obtain config of this emac */
+ mac_config = (XEmacPs_Config *)xemacps_lookup_config((unsigned)(UINTPTR)netif->state);
+
+#if defined (__aarch64__) && (EL1_NONSECURE == 1)
+ /* Request device to indicate that this library is using it */
+ if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
+ Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_0, 1, 0, 100, 1, 0, 0);
+ }
+ if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
+ Xil_Smc(PM_REQUEST_DEVICE_SMC_FID, DEV_GEM_1, 1, 0, 100, 1, 0, 0);
+ }
+#endif
+
+ status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
+ mac_config->BaseAddress);
+ if (status != XST_SUCCESS) {
+ xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
+ }
+
+ /* initialize the mac */
+ init_emacps(xemacpsif, netif);
+
+ dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+ dmacrreg = dmacrreg | (0x00000010);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET, dmacrreg);
+#if !NO_SYS
+#if defined(__arm__) && !defined(ARMR5)
+ /* Freertos tick is 10ms by default; set period to the same */
+ xemac->xTimer = xTimerCreate("Timer", 10, pdTRUE, ( void * ) 1, vTimerCallback);
+ if (xemac->xTimer == NULL) {
+ xil_printf("In %s:Timer creation failed....\r\n", __func__);
+ } else {
+ if(xTimerStart(xemac->xTimer, 0) != pdPASS) {
+ xil_printf("In %s:Timer start failed....\r\n", __func__);
+ }
+ }
+#endif
+#endif
+ setup_isr(xemac);
+ init_dma(xemac);
+ start_emacps(xemacpsif);
+
+ /* replace the state in netif (currently the emac baseaddress)
+ * with the mac instance pointer.
+ */
+ netif->state = (void *)xemac;
+
+ return ERR_OK;
+}
+
+void HandleEmacPsError(struct xemac_s *xemac)
+{
+ xemacpsif_s *xemacpsif;
+ s32_t status = XST_SUCCESS;
+ u32 dmacrreg;
+
+ SYS_ARCH_DECL_PROTECT(lev);
+ SYS_ARCH_PROTECT(lev);
+
+ xemacpsif = (xemacpsif_s *)(xemac->state);
+ free_txrx_pbufs(xemacpsif);
+ status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config,
+ mac_config->BaseAddress);
+ if (status != XST_SUCCESS) {
+ xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__);
+ }
+ /* initialize the mac */
+ init_emacps_on_error(xemacpsif, NetIf);
+ dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET);
+ dmacrreg = dmacrreg | (0x01000000);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_DMACR_OFFSET, dmacrreg);
+ setup_isr(xemac);
+ init_dma(xemac);
+ start_emacps(xemacpsif);
+
+ SYS_ARCH_UNPROTECT(lev);
+}
+
+void HandleTxErrors(struct xemac_s *xemac)
+{
+ xemacpsif_s *xemacpsif;
+ u32 netctrlreg;
+
+ SYS_ARCH_DECL_PROTECT(lev);
+ SYS_ARCH_PROTECT(lev);
+ xemacpsif = (xemacpsif_s *)(xemac->state);
+ netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ netctrlreg = netctrlreg & (~XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, netctrlreg);
+ free_onlytx_pbufs(xemacpsif);
+
+ clean_dma_txdescs(xemac);
+ netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ netctrlreg = netctrlreg | (XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, netctrlreg);
+ SYS_ARCH_UNPROTECT(lev);
+}
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+static u8_t xemacpsif_ip6_addr_ismulticast(ip6_addr_t* ip_addr)
+{
+ if(ip6_addr_ismulticast_linklocal(ip_addr)||
+ ip6_addr_ismulticast_iflocal(ip_addr) ||
+ ip6_addr_ismulticast_adminlocal(ip_addr)||
+ ip6_addr_ismulticast_sitelocal(ip_addr) ||
+ ip6_addr_ismulticast_orglocal(ip_addr) ||
+ ip6_addr_ismulticast_global(ip_addr)) {
+ /*Return TRUE if IPv6 is Multicast type*/
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+static void xemacpsif_mld6_mac_hash_update (struct netif *netif, u8_t *ip_addr,
+ u8_t action)
+{
+ u8_t multicast_mac_addr[6];
+ struct xemac_s *xemac = (struct xemac_s *) (netif->state);
+ xemacpsif_s *xemacpsif = (xemacpsif_s *) (xemac->state);
+ XEmacPs_BdRing *txring;
+ txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+
+ multicast_mac_addr[0] = LL_IP6_MULTICAST_ADDR_0;
+ multicast_mac_addr[1] = LL_IP6_MULTICAST_ADDR_1;
+ multicast_mac_addr[2] = ip_addr[12];
+ multicast_mac_addr[3] = ip_addr[13];
+ multicast_mac_addr[4] = ip_addr[14];
+ multicast_mac_addr[5] = ip_addr[15];
+
+ /* Wait till all sent packets are acknowledged from HW */
+ while(txring->HwCnt);
+
+ SYS_ARCH_DECL_PROTECT(lev);
+
+ SYS_ARCH_PROTECT(lev);
+
+ /* Stop Ethernet */
+ XEmacPs_Stop(&xemacpsif->emacps);
+
+ if (action == NETIF_ADD_MAC_FILTER) {
+ /* Set Mulitcast mac address in hash table */
+ XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
+
+ } else if (action == NETIF_DEL_MAC_FILTER) {
+ /* Remove Mulitcast mac address in hash table */
+ XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
+ }
+
+ /* Reset DMA */
+ reset_dma(xemac);
+
+ /* Start Ethernet */
+ XEmacPs_Start(&xemacpsif->emacps);
+
+ SYS_ARCH_UNPROTECT(lev);
+}
+
+static err_t xemacpsif_mld6_mac_filter_update (struct netif *netif, ip_addr_t *group,
+ u8_t action)
+{
+ u8_t temp_mask;
+ unsigned int i;
+ u8_t * ip_addr = (u8_t *) group;
+
+ if(!(xemacpsif_ip6_addr_ismulticast((ip6_addr_t*) ip_addr))) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: The requested MAC address is not a multicast address.\r\n", __func__)); LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast address add operation failure !!\r\n"));
+ return ERR_ARG;
+ }
+ if (action == NETIF_ADD_MAC_FILTER) {
+ for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+ temp_mask = (0x01) << i;
+ if ((xemacps_mld6_mcast_entry_mask & temp_mask) == temp_mask) {
+ continue;
+ }
+ xemacps_mld6_mcast_entry_mask |= temp_mask;
+
+ /* Update mac address in hash table */
+ xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: Multicast MAC address successfully added.\r\n", __func__));
+
+ return ERR_OK;
+ }
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: No multicast address registers left.\r\n", __func__));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast MAC address add operation failure !!\r\n"));
+ return ERR_MEM;
+ } else if (action == NETIF_DEL_MAC_FILTER) {
+ for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+ temp_mask = (0x01) << i;
+ if ((xemacps_mld6_mcast_entry_mask & temp_mask) != temp_mask) {
+ continue;
+ }
+ xemacps_mld6_mcast_entry_mask &= (~temp_mask);
+
+ /* Update mac address in hash table */
+ xemacpsif_mld6_mac_hash_update(netif, ip_addr, action);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: Multicast MAC address successfully removed.\r\n", __func__));
+
+ return ERR_OK;
+ }
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: No multicast address registers present with\r\n", __func__));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("the requested Multicast MAC address.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast MAC address removal failure!!.\r\n"));
+ return ERR_MEM;
+ }
+ return ERR_ARG;
+}
+#endif
+
+#if LWIP_IGMP
+static void xemacpsif_mac_hash_update (struct netif *netif, u8_t *ip_addr,
+ u8_t action)
+{
+ u8_t multicast_mac_addr[6];
+ struct xemac_s *xemac = (struct xemac_s *) (netif->state);
+ xemacpsif_s *xemacpsif = (xemacpsif_s *) (xemac->state);
+ XEmacPs_BdRing *txring;
+ txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+
+ multicast_mac_addr[0] = 0x01;
+ multicast_mac_addr[1] = 0x00;
+ multicast_mac_addr[2] = 0x5E;
+ multicast_mac_addr[3] = ip_addr[1] & 0x7F;
+ multicast_mac_addr[4] = ip_addr[2];
+ multicast_mac_addr[5] = ip_addr[3];
+
+ /* Wait till all sent packets are acknowledged from HW */
+ while(txring->HwCnt);
+
+ SYS_ARCH_DECL_PROTECT(lev);
+
+ SYS_ARCH_PROTECT(lev);
+
+ /* Stop Ethernet */
+ XEmacPs_Stop(&xemacpsif->emacps);
+
+ if (action == IGMP_ADD_MAC_FILTER) {
+ /* Set Mulitcast mac address in hash table */
+ XEmacPs_SetHash(&xemacpsif->emacps, multicast_mac_addr);
+
+ } else if (action == IGMP_DEL_MAC_FILTER) {
+ /* Remove Mulitcast mac address in hash table */
+ XEmacPs_DeleteHash(&xemacpsif->emacps, multicast_mac_addr);
+ }
+
+ /* Reset DMA */
+ reset_dma(xemac);
+
+ /* Start Ethernet */
+ XEmacPs_Start(&xemacpsif->emacps);
+
+ SYS_ARCH_UNPROTECT(lev);
+}
+
+static err_t xemacpsif_mac_filter_update (struct netif *netif, ip_addr_t *group,
+ u8_t action)
+{
+ u8_t temp_mask;
+ unsigned int i;
+ u8_t * ip_addr = (u8_t *) group;
+
+ if ((ip_addr[0] < 224) && (ip_addr[0] > 239)) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: The requested MAC address is not a multicast address.\r\n", __func__));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast address add operation failure !!\r\n"));
+
+ return ERR_ARG;
+ }
+
+ if (action == IGMP_ADD_MAC_FILTER) {
+
+ for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+ temp_mask = (0x01) << i;
+ if ((xemacps_mcast_entry_mask & temp_mask) == temp_mask) {
+ continue;
+ }
+ xemacps_mcast_entry_mask |= temp_mask;
+
+ /* Update mac address in hash table */
+ xemacpsif_mac_hash_update(netif, ip_addr, action);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: Multicast MAC address successfully added.\r\n", __func__));
+
+ return ERR_OK;
+ }
+ if (i == XEMACPS_MAX_MAC_ADDR) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: No multicast address registers left.\r\n", __func__));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast MAC address add operation failure !!\r\n"));
+
+ return ERR_MEM;
+ }
+ } else if (action == IGMP_DEL_MAC_FILTER) {
+ for (i = 0; i < XEMACPS_MAX_MAC_ADDR; i++) {
+ temp_mask = (0x01) << i;
+ if ((xemacps_mcast_entry_mask & temp_mask) != temp_mask) {
+ continue;
+ }
+ xemacps_mcast_entry_mask &= (~temp_mask);
+
+ /* Update mac address in hash table */
+ xemacpsif_mac_hash_update(netif, ip_addr, action);
+
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: Multicast MAC address successfully removed.\r\n", __func__));
+
+ return ERR_OK;
+ }
+ if (i == XEMACPS_MAX_MAC_ADDR) {
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("%s: No multicast address registers present with\r\n", __func__));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("the requested Multicast MAC address.\r\n"));
+ LWIP_DEBUGF(NETIF_DEBUG,
+ ("Multicast MAC address removal failure!!.\r\n"));
+
+ return ERR_MEM;
+ }
+ }
+ return ERR_OK;
+}
+#endif
+
+/*
+ * xemacpsif_init():
+ *
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ */
+
+err_t xemacpsif_init(struct netif *netif)
+{
+#if LWIP_SNMP
+ /* ifType ethernetCsmacd(6) @see RFC1213 */
+ netif->link_type = 6;
+ /* your link speed here */
+ netif->link_speed = ;
+ netif->ts = 0;
+ netif->ifinoctets = 0;
+ netif->ifinucastpkts = 0;
+ netif->ifinnucastpkts = 0;
+ netif->ifindiscards = 0;
+ netif->ifoutoctets = 0;
+ netif->ifoutucastpkts = 0;
+ netif->ifoutnucastpkts = 0;
+ netif->ifoutdiscards = 0;
+#endif
+
+ netif->name[0] = IFNAME0;
+ netif->name[1] = IFNAME1;
+ netif->output = xemacpsif_output;
+ netif->linkoutput = low_level_output;
+#if LWIP_IPV6
+ netif->output_ip6 = ethip6_output;
+#endif
+
+ low_level_init(netif);
+ return ERR_OK;
+}
+
+/*
+ * xemacpsif_resetrx_on_no_rxdata():
+ *
+ * Should be called by the user at regular intervals, typically
+ * from a timer (100 msecond). This is to provide a SW workaround
+ * for the HW bug (SI #692601). Please refer to the function header
+ * for the function resetrx_on_no_rxdata in xemacpsif_dma.c to
+ * know more about the SI.
+ *
+ */
+
+void xemacpsif_resetrx_on_no_rxdata(struct netif *netif)
+{
+ struct xemac_s *xemac = (struct xemac_s *)(netif->state);
+ xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+
+ resetrx_on_no_rxdata(xemacpsif);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_dma.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_dma.c
new file mode 100644
index 0000000..2da3566
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_dma.c
@@ -0,0 +1,930 @@
+/*
+ * Copyright (C) 2010 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwipopts.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/inet_chksum.h"
+
+#include "netif/xadapter.h"
+#include "netif/xemacpsif.h"
+#include "xstatus.h"
+
+#include "xlwipconfig.h"
+#include "xparameters.h"
+#include "xparameters_ps.h"
+#include "xil_exception.h"
+#include "xil_mmu.h"
+#if defined (ARMR5)
+#include "xreg_cortexr5.h"
+#endif
+#ifdef CONFIG_XTRACE
+#include "xtrace.h"
+#endif
+#if !NO_SYS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "timers.h"
+#endif
+
+
+#define INTC_BASE_ADDR XPAR_SCUGIC_0_CPU_BASEADDR
+#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
+
+/* Byte alignment of BDs */
+#define BD_ALIGNMENT (XEMACPS_DMABD_MINIMUM_ALIGNMENT*2)
+
+/* A max of 4 different ethernet interfaces are supported */
+static UINTPTR tx_pbufs_storage[4*XLWIP_CONFIG_N_TX_DESC];
+static UINTPTR rx_pbufs_storage[4*XLWIP_CONFIG_N_RX_DESC];
+
+static s32_t emac_intr_num;
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+volatile u32_t notifyinfo[4*XLWIP_CONFIG_N_TX_DESC];
+#endif
+
+/******************************************************************************
+ * Each BD is of 8 bytes of size and the BDs (BD chain) need to be put
+ * at uncached memory location. If they are not put at uncached
+ * locations, the user needs to flush or invalidate for each BD/packet.
+ * However, the flush or invalidate can happen over a cache line which can
+ * span multiple BDs. This means a flush or invalidate of one BD can actually
+ * flush/invalidate multiple BDs adjacent to the targeted BD.Assuming that
+ * the user and hardware both update the BD fields, this operation from user
+ * can potentially overwrite the updates done by hardware or user.
+ * To avoid this, it is always safe to put the BD chains for Rx and tx side
+ * at uncached memory location.
+ *
+ * The Xilinx standalone BSP for Cortex A9 implements only primary page tables.
+ * Each table entry corresponds to 1 MB of address map. This means, if a memory
+ * region has to be made uncached, the minimum granularity will be of 1 MB.
+ *
+ * The implementation below allocates a 1 MB of u8 array aligned to 1 MB.
+ * This ensures that this array is put at 1 MB aligned memory (e.g. 0x1200000)
+ * and accupies memory of 1 MB. The init_dma function then changes 1 MB of this
+ * region to make it uncached (strongly ordered).
+ * This increases the bss section of the program significantly and can be a
+ * wastage of memory. The reason beings, BDs will hardly occupy few KBs of
+ * memory and the rest of 1 MB of memory will be unused.
+ *
+ * If a program uses other peripherals that have DMAs/bus masters and need
+ * uncached memory, they may also end of following the same approach. This
+ * definitely aggravates the memory wastage issue. To avoid all this, the user
+ * can create a new 1 MB section in the linker script and reserve it for such
+ * use cases that need uncached memory location. They can then have their own
+ * memory allocation logic in their application that allocates uncached memory
+ * from this 1 MB location. For such a case, changes need to be done in this
+ * file and appropriate uncached memory allocated through other means can be
+ * used.
+ *
+ * The present implementation here allocates 1 MB of uncached memory. It
+ * reserves of 64 KB of memory for each BD chain. 64 KB of memory means 8192 of
+ * BDs for each BD chain which is more than enough for any application.
+ * Assuming that both emac0 and emac1 are present, 256 KB of memory is allocated
+ * for BDs. The rest 768 KB of memory is just unused.
+ *********************************************************************************/
+
+#if defined __aarch64__
+u8_t bd_space[0x200000] __attribute__ ((aligned (0x200000)));
+#else
+u8_t bd_space[0x100000] __attribute__ ((aligned (0x100000)));
+#endif
+static volatile u32_t bd_space_index = 0;
+static volatile u32_t bd_space_attr_set = 0;
+
+#if !NO_SYS
+long xInsideISR = 0;
+#endif
+
+#define XEMACPS_BD_TO_INDEX(ringptr, bdptr) \
+ (((UINTPTR)bdptr - (UINTPTR)(ringptr)->BaseBdAddr) / (ringptr)->Separation)
+
+
+s32_t is_tx_space_available(xemacpsif_s *emac)
+{
+ XEmacPs_BdRing *txring;
+ s32_t freecnt = 0;
+
+ txring = &(XEmacPs_GetTxRing(&emac->emacps));
+
+ /* tx space is available as long as there are valid BD's */
+ freecnt = XEmacPs_BdRingGetFreeCnt(txring);
+ return freecnt;
+}
+
+
+static inline
+u32_t get_base_index_txpbufsstorage (xemacpsif_s *xemacpsif)
+{
+ u32_t index;
+#ifdef XPAR_XEMACPS_0_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+ index = 0;
+ }
+#endif
+#ifdef XPAR_XEMACPS_1_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) {
+ index = XLWIP_CONFIG_N_TX_DESC;
+ }
+#endif
+#ifdef XPAR_XEMACPS_2_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) {
+ index = 2 * XLWIP_CONFIG_N_TX_DESC;
+ }
+#endif
+#ifdef XPAR_XEMACPS_3_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_3_BASEADDR) {
+ index = 3 * XLWIP_CONFIG_N_TX_DESC;
+ }
+#endif
+ return index;
+}
+
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+static inline
+u32_t get_base_index_tasknotifyinfo (xemacpsif_s *xemacpsif)
+{
+ u32_t index;
+#ifdef XPAR_XEMACPS_0_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+ index = 0;
+ }
+#endif
+#ifdef XPAR_XEMACPS_1_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) {
+ index = XLWIP_CONFIG_N_TX_DESC;
+ }
+#endif
+#ifdef XPAR_XEMACPS_2_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) {
+ index = 2 * XLWIP_CONFIG_N_TX_DESC;
+ }
+#endif
+#ifdef XPAR_XEMACPS_3_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_3_BASEADDR) {
+ index = 3 * XLWIP_CONFIG_N_TX_DESC;
+ }
+#endif
+ return index;
+}
+#endif
+
+static inline
+u32_t get_base_index_rxpbufsstorage (xemacpsif_s *xemacpsif)
+{
+ u32_t index;
+#ifdef XPAR_XEMACPS_0_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+ index = 0;
+ }
+#endif
+#ifdef XPAR_XEMACPS_1_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) {
+ index = XLWIP_CONFIG_N_RX_DESC;
+ }
+#endif
+#ifdef XPAR_XEMACPS_2_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) {
+ index = 2 * XLWIP_CONFIG_N_RX_DESC;
+ }
+#endif
+#ifdef XPAR_XEMACPS_3_BASEADDR
+ if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_3_BASEADDR) {
+ index = 3 * XLWIP_CONFIG_N_RX_DESC;
+ }
+#endif
+ return index;
+}
+
+void process_sent_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *txring)
+{
+ XEmacPs_Bd *txbdset;
+ XEmacPs_Bd *curbdpntr;
+ s32_t n_bds;
+ XStatus status;
+ s32_t n_pbufs_freed = 0;
+ u32_t bdindex;
+ struct pbuf *p;
+ u32 *temp;
+ u32_t index;
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ u32_t tx_task_notifier_index;
+#endif
+
+ index = get_base_index_txpbufsstorage (xemacpsif);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ tx_task_notifier_index = get_base_index_tasknotifyinfo (xemacpsif);
+#endif
+
+ while (1) {
+ /* obtain processed BD's */
+ n_bds = XEmacPs_BdRingFromHwTx(txring,
+ XLWIP_CONFIG_N_TX_DESC, &txbdset);
+ if (n_bds == 0) {
+ return;
+ }
+ /* free the processed BD's */
+ n_pbufs_freed = n_bds;
+ curbdpntr = txbdset;
+ while (n_pbufs_freed > 0) {
+ bdindex = XEMACPS_BD_TO_INDEX(txring, curbdpntr);
+ temp = (u32 *)curbdpntr;
+ *temp = 0;
+ temp++;
+ if (bdindex == (XLWIP_CONFIG_N_TX_DESC - 1)) {
+ *temp = 0xC0000000;
+ } else {
+ *temp = 0x80000000;
+ }
+ dsb();
+ p = (struct pbuf *)tx_pbufs_storage[index + bdindex];
+ if (p != NULL) {
+ pbuf_free(p);
+ }
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ notifyinfo[tx_task_notifier_index + bdindex] = 0;
+#endif
+ tx_pbufs_storage[index + bdindex] = 0;
+ curbdpntr = XEmacPs_BdRingNext(txring, curbdpntr);
+ n_pbufs_freed--;
+ dsb();
+ }
+
+ status = XEmacPs_BdRingFree(txring, n_bds, txbdset);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Failure while freeing in Tx Done ISR\r\n"));
+ }
+ }
+ return;
+}
+
+void emacps_send_handler(void *arg)
+{
+ struct xemac_s *xemac;
+ xemacpsif_s *xemacpsif;
+ XEmacPs_BdRing *txringptr;
+ u32_t regval;
+#if !NO_SYS
+ xInsideISR++;
+#endif
+ xemac = (struct xemac_s *)(arg);
+ xemacpsif = (xemacpsif_s *)(xemac->state);
+ txringptr = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+ regval = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_TXSR_OFFSET);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,XEMACPS_TXSR_OFFSET, regval);
+
+ /* If Transmit done interrupt is asserted, process completed BD's */
+ process_sent_bds(xemacpsif, txringptr);
+#if !NO_SYS
+ xInsideISR--;
+#endif
+}
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p,
+ u32_t block_till_tx_complete, u32_t *to_block_index)
+#else
+XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p)
+#endif
+{
+ struct pbuf *q;
+ s32_t n_pbufs;
+ XEmacPs_Bd *txbdset, *txbd, *last_txbd = NULL;
+ XEmacPs_Bd *temp_txbd;
+ XStatus status;
+ XEmacPs_BdRing *txring;
+ u32_t bdindex = 0;
+ u32_t index;
+ u32_t max_fr_size;
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ u32_t tx_task_notifier_index;
+#endif
+
+ txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps));
+
+ index = get_base_index_txpbufsstorage (xemacpsif);
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ tx_task_notifier_index = get_base_index_tasknotifyinfo (xemacpsif);
+#endif
+
+ /* first count the number of pbufs */
+ for (q = p, n_pbufs = 0; q != NULL; q = q->next)
+ n_pbufs++;
+
+ /* obtain as many BD's */
+ status = XEmacPs_BdRingAlloc(txring, n_pbufs, &txbdset);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n"));
+ return XST_FAILURE;
+ }
+
+ for(q = p, txbd = txbdset; q != NULL; q = q->next) {
+ bdindex = XEMACPS_BD_TO_INDEX(txring, txbd);
+ if (tx_pbufs_storage[index + bdindex] != 0) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n"));
+ return XST_FAILURE;
+ }
+
+ /* Send the data from the pbuf to the interface, one pbuf at a
+ time. The size of the data in each pbuf is kept in the ->len
+ variable. */
+ if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((UINTPTR)q->payload, (UINTPTR)q->len);
+ }
+
+ XEmacPs_BdSetAddressTx(txbd, (UINTPTR)q->payload);
+
+#ifdef ZYNQMP_USE_JUMBO
+ max_fr_size = MAX_FRAME_SIZE_JUMBO - 18;
+#else
+ max_fr_size = XEMACPS_MAX_FRAME_SIZE - 18;
+#endif
+ if (q->len > max_fr_size)
+ XEmacPs_BdSetLength(txbd, max_fr_size & 0x3FFF);
+ else
+ XEmacPs_BdSetLength(txbd, q->len & 0x3FFF);
+
+ tx_pbufs_storage[index + bdindex] = (UINTPTR)q;
+
+ pbuf_ref(q);
+ last_txbd = txbd;
+ XEmacPs_BdClearLast(txbd);
+ txbd = XEmacPs_BdRingNext(txring, txbd);
+ }
+#if LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE
+ if (block_till_tx_complete == 1) {
+ notifyinfo[tx_task_notifier_index + bdindex] = 1;
+ *to_block_index = tx_task_notifier_index + bdindex;
+ }
+#endif
+ XEmacPs_BdSetLast(last_txbd);
+ /* For fragmented packets, remember the 1st BD allocated for the 1st
+ packet fragment. The used bit for this BD should be cleared at the end
+ after clearing out used bits for other fragments. For packets without
+ just remember the allocated BD. */
+ temp_txbd = txbdset;
+ txbd = txbdset;
+ txbd = XEmacPs_BdRingNext(txring, txbd);
+ q = p->next;
+ for(; q != NULL; q = q->next) {
+ XEmacPs_BdClearTxUsed(txbd);
+ txbd = XEmacPs_BdRingNext(txring, txbd);
+ }
+ XEmacPs_BdClearTxUsed(temp_txbd);
+ dsb();
+
+ status = XEmacPs_BdRingToHw(txring, n_pbufs, txbdset);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n"));
+ return XST_FAILURE;
+ }
+ /* Start transmit */
+ XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET,
+ (XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK));
+ return status;
+}
+
+void setup_rx_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *rxring)
+{
+ XEmacPs_Bd *rxbd;
+ XStatus status;
+ struct pbuf *p;
+ u32_t freebds;
+ u32_t bdindex;
+ u32 *temp;
+ u32_t index;
+
+ index = get_base_index_rxpbufsstorage (xemacpsif);
+
+ freebds = XEmacPs_BdRingGetFreeCnt (rxring);
+ while (freebds > 0) {
+ freebds--;
+#ifdef ZYNQMP_USE_JUMBO
+ p = pbuf_alloc(PBUF_RAW, MAX_FRAME_SIZE_JUMBO, PBUF_POOL);
+#else
+ p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL);
+#endif
+ if (!p) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ printf("unable to alloc pbuf in recv_handler\r\n");
+ return;
+ }
+ status = XEmacPs_BdRingAlloc(rxring, 1, &rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("setup_rx_bds: Error allocating RxBD\r\n"));
+ pbuf_free(p);
+ return;
+ }
+ status = XEmacPs_BdRingToHw(rxring, 1, rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error committing RxBD to hardware: "));
+ if (status == XST_DMA_SG_LIST_ERROR) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with XEmacPs_BdRingAlloc()\r\n"));
+ }
+ else {
+ LWIP_DEBUGF(NETIF_DEBUG, ("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n"));
+ }
+
+ pbuf_free(p);
+ XEmacPs_BdRingUnAlloc(rxring, 1, rxbd);
+ return;
+ }
+#ifdef ZYNQMP_USE_JUMBO
+ if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+ }
+#else
+ if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+ }
+#endif
+ bdindex = XEMACPS_BD_TO_INDEX(rxring, rxbd);
+ temp = (u32 *)rxbd;
+ temp++;
+ /* Status field should be cleared first to avoid drops */
+ *temp = 0;
+ dsb();
+
+ /* Set high address when required */
+#ifdef __aarch64__
+ XEmacPs_BdWrite(rxbd, XEMACPS_BD_ADDR_HI_OFFSET,
+ (((UINTPTR)p->payload) & ULONG64_HI_MASK) >> 32U);
+#endif
+ /* Set address field; add WRAP bit on last descriptor */
+ if (bdindex == (XLWIP_CONFIG_N_RX_DESC - 1)) {
+ XEmacPs_BdWrite(rxbd, XEMACPS_BD_ADDR_OFFSET, ((UINTPTR)p->payload | XEMACPS_RXBUF_WRAP_MASK));
+ } else {
+ XEmacPs_BdWrite(rxbd, XEMACPS_BD_ADDR_OFFSET, (UINTPTR)p->payload);
+ }
+
+ rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
+ }
+}
+
+void emacps_recv_handler(void *arg)
+{
+ struct pbuf *p;
+ XEmacPs_Bd *rxbdset, *curbdptr;
+ struct xemac_s *xemac;
+ xemacpsif_s *xemacpsif;
+ XEmacPs_BdRing *rxring;
+ volatile s32_t bd_processed;
+ s32_t rx_bytes, k;
+ u32_t bdindex;
+ u32_t regval;
+ u32_t index;
+ u32_t gigeversion;
+
+ xemac = (struct xemac_s *)(arg);
+ xemacpsif = (xemacpsif_s *)(xemac->state);
+ rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps);
+
+#if !NO_SYS
+ xInsideISR++;
+#endif
+
+ gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
+ index = get_base_index_rxpbufsstorage (xemacpsif);
+ /*
+ * If Reception done interrupt is asserted, call RX call back function
+ * to handle the processed BDs and then raise the according flag.
+ */
+ regval = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET, regval);
+ if (gigeversion <= 2) {
+ resetrx_on_no_rxdata(xemacpsif);
+ }
+
+ while(1) {
+
+ bd_processed = XEmacPs_BdRingFromHwRx(rxring, XLWIP_CONFIG_N_RX_DESC, &rxbdset);
+ if (bd_processed <= 0) {
+ break;
+ }
+
+ for (k = 0, curbdptr=rxbdset; k < bd_processed; k++) {
+
+ bdindex = XEMACPS_BD_TO_INDEX(rxring, curbdptr);
+ p = (struct pbuf *)rx_pbufs_storage[index + bdindex];
+
+ /*
+ * Adjust the buffer size to the actual number of bytes received.
+ */
+#ifdef ZYNQMP_USE_JUMBO
+ rx_bytes = XEmacPs_GetRxFrameSize(&xemacpsif->emacps, curbdptr);
+#else
+ rx_bytes = XEmacPs_BdGetLength(curbdptr);
+#endif
+ pbuf_realloc(p, rx_bytes);
+
+ /* Invalidate RX frame before queuing to handle
+ * L1 cache prefetch conditions on any architecture.
+ */
+ if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((UINTPTR)p->payload, rx_bytes);
+ }
+
+ /* store it in the receive queue,
+ * where it'll be processed by a different handler
+ */
+ if (pq_enqueue(xemacpsif->recv_q, (void*)p) < 0) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ pbuf_free(p);
+ }
+ curbdptr = XEmacPs_BdRingNext( rxring, curbdptr);
+ }
+ /* free up the BD's */
+ XEmacPs_BdRingFree(rxring, bd_processed, rxbdset);
+ setup_rx_bds(xemacpsif, rxring);
+ }
+#if !NO_SYS
+ sys_sem_signal(&xemac->sem_rx_data_available);
+ xInsideISR--;
+#endif
+
+ return;
+}
+
+void clean_dma_txdescs(struct xemac_s *xemac)
+{
+ XEmacPs_Bd bdtemplate;
+ XEmacPs_BdRing *txringptr;
+ xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+
+ txringptr = &XEmacPs_GetTxRing(&xemacpsif->emacps);
+
+ XEmacPs_BdClear(&bdtemplate);
+ XEmacPs_BdSetStatus(&bdtemplate, XEMACPS_TXBUF_USED_MASK);
+
+ /*
+ * Create the TxBD ring
+ */
+ XEmacPs_BdRingCreate(txringptr, (UINTPTR) xemacpsif->tx_bdspace,
+ (UINTPTR) xemacpsif->tx_bdspace, BD_ALIGNMENT,
+ XLWIP_CONFIG_N_TX_DESC);
+ XEmacPs_BdRingClone(txringptr, &bdtemplate, XEMACPS_SEND);
+}
+
+XStatus init_dma(struct xemac_s *xemac)
+{
+ XEmacPs_Bd bdtemplate;
+ XEmacPs_BdRing *rxringptr, *txringptr;
+ XEmacPs_Bd *rxbd;
+ struct pbuf *p;
+ XStatus status;
+ s32_t i;
+ u32_t bdindex;
+ volatile UINTPTR tempaddress;
+ u32_t index;
+ u32_t gigeversion;
+ XEmacPs_Bd *bdtxterminate = NULL;
+ XEmacPs_Bd *bdrxterminate = NULL;
+ u32 *temp;
+
+ xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+ struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
+
+ index = get_base_index_rxpbufsstorage (xemacpsif);
+ gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
+ /*
+ * The BDs need to be allocated in uncached memory. Hence the 1 MB
+ * address range allocated for Bd_Space is made uncached
+ * by setting appropriate attributes in the translation table.
+ * The Bd_Space is aligned to 1MB and has a size of 1 MB. This ensures
+ * a reserved uncached area used only for BDs.
+ */
+ if (bd_space_attr_set == 0) {
+#if defined (ARMR5)
+ Xil_SetTlbAttributes((s32_t)bd_space, STRONG_ORDERD_SHARED | PRIV_RW_USER_RW); // addr, attr
+#else
+#if defined __aarch64__
+ Xil_SetTlbAttributes((u64)bd_space, NORM_NONCACHE | INNER_SHAREABLE);
+#else
+ Xil_SetTlbAttributes((s32_t)bd_space, DEVICE_MEMORY); // addr, attr
+#endif
+#endif
+ bd_space_attr_set = 1;
+ }
+
+ rxringptr = &XEmacPs_GetRxRing(&xemacpsif->emacps);
+ txringptr = &XEmacPs_GetTxRing(&xemacpsif->emacps);
+ LWIP_DEBUGF(NETIF_DEBUG, ("rxringptr: 0x%08x\r\n", rxringptr));
+ LWIP_DEBUGF(NETIF_DEBUG, ("txringptr: 0x%08x\r\n", txringptr));
+
+ /* Allocate 64k for Rx and Tx bds each to take care of extreme cases */
+ tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
+ xemacpsif->rx_bdspace = (void *)tempaddress;
+ bd_space_index += 0x10000;
+ tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
+ xemacpsif->tx_bdspace = (void *)tempaddress;
+ bd_space_index += 0x10000;
+ if (gigeversion > 2) {
+ tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
+ bdrxterminate = (XEmacPs_Bd *)tempaddress;
+ bd_space_index += 0x10000;
+ tempaddress = (UINTPTR)&(bd_space[bd_space_index]);
+ bdtxterminate = (XEmacPs_Bd *)tempaddress;
+ bd_space_index += 0x10000;
+ }
+
+ LWIP_DEBUGF(NETIF_DEBUG, ("rx_bdspace: %p \r\n", xemacpsif->rx_bdspace));
+ LWIP_DEBUGF(NETIF_DEBUG, ("tx_bdspace: %p \r\n", xemacpsif->tx_bdspace));
+
+ if (!xemacpsif->rx_bdspace || !xemacpsif->tx_bdspace) {
+ xil_printf("%s@%d: Error: Unable to allocate memory for TX/RX buffer descriptors",
+ __FILE__, __LINE__);
+ return ERR_IF;
+ }
+
+ /*
+ * Setup RxBD space.
+ *
+ * Setup a BD template for the Rx channel. This template will be copied to
+ * every RxBD. We will not have to explicitly set these again.
+ */
+ XEmacPs_BdClear(&bdtemplate);
+
+ /*
+ * Create the RxBD ring
+ */
+
+ status = XEmacPs_BdRingCreate(rxringptr, (UINTPTR) xemacpsif->rx_bdspace,
+ (UINTPTR) xemacpsif->rx_bdspace, BD_ALIGNMENT,
+ XLWIP_CONFIG_N_RX_DESC);
+
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error setting up RxBD space\r\n"));
+ return ERR_IF;
+ }
+
+ status = XEmacPs_BdRingClone(rxringptr, &bdtemplate, XEMACPS_RECV);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error initializing RxBD space\r\n"));
+ return ERR_IF;
+ }
+
+ XEmacPs_BdClear(&bdtemplate);
+ XEmacPs_BdSetStatus(&bdtemplate, XEMACPS_TXBUF_USED_MASK);
+ /*
+ * Create the TxBD ring
+ */
+ status = XEmacPs_BdRingCreate(txringptr, (UINTPTR) xemacpsif->tx_bdspace,
+ (UINTPTR) xemacpsif->tx_bdspace, BD_ALIGNMENT,
+ XLWIP_CONFIG_N_TX_DESC);
+
+ if (status != XST_SUCCESS) {
+ return ERR_IF;
+ }
+
+ /* We reuse the bd template, as the same one will work for both rx and tx. */
+ status = XEmacPs_BdRingClone(txringptr, &bdtemplate, XEMACPS_SEND);
+ if (status != XST_SUCCESS) {
+ return ERR_IF;
+ }
+
+ /*
+ * Allocate RX descriptors, 1 RxBD at a time.
+ */
+ for (i = 0; i < XLWIP_CONFIG_N_RX_DESC; i++) {
+#ifdef ZYNQMP_USE_JUMBO
+ p = pbuf_alloc(PBUF_RAW, MAX_FRAME_SIZE_JUMBO, PBUF_POOL);
+#else
+ p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL);
+#endif
+ if (!p) {
+#if LINK_STATS
+ lwip_stats.link.memerr++;
+ lwip_stats.link.drop++;
+#endif
+ printf("unable to alloc pbuf in init_dma\r\n");
+ return ERR_IF;
+ }
+ status = XEmacPs_BdRingAlloc(rxringptr, 1, &rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("init_dma: Error allocating RxBD\r\n"));
+ pbuf_free(p);
+ return ERR_IF;
+ }
+ /* Enqueue to HW */
+ status = XEmacPs_BdRingToHw(rxringptr, 1, rxbd);
+ if (status != XST_SUCCESS) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Error: committing RxBD to HW\r\n"));
+ pbuf_free(p);
+ XEmacPs_BdRingUnAlloc(rxringptr, 1, rxbd);
+ return ERR_IF;
+ }
+
+ bdindex = XEMACPS_BD_TO_INDEX(rxringptr, rxbd);
+ temp = (u32 *)rxbd;
+ *temp = 0;
+ if (bdindex == (XLWIP_CONFIG_N_RX_DESC - 1)) {
+ *temp = 0x00000002;
+ }
+ temp++;
+ *temp = 0;
+ dsb();
+#ifdef ZYNQMP_USE_JUMBO
+ if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)MAX_FRAME_SIZE_JUMBO);
+ }
+#else
+ if (xemacpsif->emacps.Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((UINTPTR)p->payload, (UINTPTR)XEMACPS_MAX_FRAME_SIZE);
+ }
+#endif
+ XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
+
+ rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
+ }
+ XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
+ if (gigeversion > 2) {
+ XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 1, XEMACPS_SEND);
+ }else {
+ XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 0, XEMACPS_SEND);
+ }
+ if (gigeversion > 2)
+ {
+ /*
+ * This version of GEM supports priority queuing and the current
+ * driver is using tx priority queue 1 and normal rx queue for
+ * packet transmit and receive. The below code ensure that the
+ * other queue pointers are parked to known state for avoiding
+ * the controller to malfunction by fetching the descriptors
+ * from these queues.
+ */
+ XEmacPs_BdClear(bdrxterminate);
+ XEmacPs_BdSetAddressRx(bdrxterminate, (XEMACPS_RXBUF_NEW_MASK |
+ XEMACPS_RXBUF_WRAP_MASK));
+ XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_RXQ1BASE_OFFSET),
+ (UINTPTR)bdrxterminate);
+ XEmacPs_BdClear(bdtxterminate);
+ XEmacPs_BdSetStatus(bdtxterminate, (XEMACPS_TXBUF_USED_MASK |
+ XEMACPS_TXBUF_WRAP_MASK));
+ XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_TXQBASE_OFFSET),
+ (UINTPTR)bdtxterminate);
+ }
+#if !NO_SYS
+ xPortInstallInterruptHandler(xtopologyp->scugic_emac_intr,
+ ( Xil_InterruptHandler ) XEmacPs_IntrHandler,
+ (void *)&xemacpsif->emacps);
+#else
+ /*
+ * Connect the device driver handler that will be called when an
+ * interrupt for the device occurs, the handler defined above performs
+ * the specific interrupt processing for the device.
+ */
+ XScuGic_RegisterHandler(INTC_BASE_ADDR, xtopologyp->scugic_emac_intr,
+ (Xil_ExceptionHandler)XEmacPs_IntrHandler,
+ (void *)&xemacpsif->emacps);
+#endif
+ /*
+ * Enable the interrupt for emacps.
+ */
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, (u32) xtopologyp->scugic_emac_intr);
+ emac_intr_num = (u32) xtopologyp->scugic_emac_intr;
+ return 0;
+}
+
+/*
+ * resetrx_on_no_rxdata():
+ *
+ * It is called at regular intervals through the API xemacpsif_resetrx_on_no_rxdata
+ * called by the user.
+ * The EmacPs has a HW bug (SI# 692601) on the Rx path for heavy Rx traffic.
+ * Under heavy Rx traffic because of the HW bug there are times when the Rx path
+ * becomes unresponsive. The workaround for it is to check for the Rx path for
+ * traffic (by reading the stats registers regularly). If the stats register
+ * does not increment for sometime (proving no Rx traffic), the function resets
+ * the Rx data path.
+ *
+ */
+
+void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif)
+{
+ u32_t regctrl;
+ u32_t tempcntr;
+ u32_t gigeversion;
+
+ gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
+ if (gigeversion == 2) {
+ tempcntr = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET);
+ if ((!tempcntr) && (!(xemacpsif->last_rx_frms_cntr))) {
+ regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, regctrl);
+ regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET);
+ regctrl |= (XEMACPS_NWCTRL_RXEN_MASK);
+ XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl);
+ }
+ xemacpsif->last_rx_frms_cntr = tempcntr;
+ }
+}
+
+void free_txrx_pbufs(xemacpsif_s *xemacpsif)
+{
+ s32_t index;
+ s32_t index1;
+ struct pbuf *p;
+
+ index1 = get_base_index_txpbufsstorage (xemacpsif);
+
+ for (index = index1; index < (index1 + XLWIP_CONFIG_N_TX_DESC); index++) {
+ if (tx_pbufs_storage[index] != 0) {
+ p = (struct pbuf *)tx_pbufs_storage[index];
+ pbuf_free(p);
+ tx_pbufs_storage[index] = 0;
+ }
+ }
+
+ index1 = get_base_index_rxpbufsstorage(xemacpsif);
+ for (index = index1; index < (index1 + XLWIP_CONFIG_N_RX_DESC); index++) {
+ p = (struct pbuf *)rx_pbufs_storage[index];
+ pbuf_free(p);
+
+ }
+}
+
+void free_onlytx_pbufs(xemacpsif_s *xemacpsif)
+{
+ s32_t index;
+ s32_t index1;
+ struct pbuf *p;
+
+ index1 = get_base_index_txpbufsstorage (xemacpsif);
+ for (index = index1; index < (index1 + XLWIP_CONFIG_N_TX_DESC); index++) {
+ if (tx_pbufs_storage[index] != 0) {
+ p = (struct pbuf *)tx_pbufs_storage[index];
+ pbuf_free(p);
+ tx_pbufs_storage[index] = 0;
+ }
+ }
+}
+
+/* reset Tx and Rx DMA pointers after XEmacPs_Stop */
+void reset_dma(struct xemac_s *xemac)
+{
+ u8 txqueuenum;
+ u32_t gigeversion;
+ xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
+ XEmacPs_BdRing *txringptr = &XEmacPs_GetTxRing(&xemacpsif->emacps);
+ XEmacPs_BdRing *rxringptr = &XEmacPs_GetRxRing(&xemacpsif->emacps);
+
+ XEmacPs_BdRingPtrReset(txringptr, xemacpsif->tx_bdspace);
+ XEmacPs_BdRingPtrReset(rxringptr, xemacpsif->rx_bdspace);
+
+ gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
+ if (gigeversion > 2) {
+ txqueuenum = 1;
+ } else {
+ txqueuenum = 0;
+ }
+
+ XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
+ XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, txqueuenum, XEMACPS_SEND);
+}
+
+void emac_disable_intr(void)
+{
+ XScuGic_DisableIntr(INTC_DIST_BASE_ADDR, emac_intr_num);
+}
+
+void emac_enable_intr(void)
+{
+ XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, emac_intr_num);
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_hw.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_hw.c
new file mode 100644
index 0000000..a1fdeda
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_hw.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2010 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/xemacpsif.h"
+#include "lwipopts.h"
+
+#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1 || \
+ XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
+#define PCM_PMA_CORE_PRESENT
+#else
+#undef PCM_PMA_CORE_PRESENT
+#endif
+
+u32_t link_speed = 100;
+extern XEmacPs_Config XEmacPs_ConfigTable[];
+extern u32_t phymapemac0[32];
+extern u32_t phymapemac1[32];
+extern u32_t phyaddrforemac;
+extern enum ethernet_link_status eth_link_status;
+
+#if !NO_SYS
+extern long xInsideISR;
+#endif
+
+XEmacPs_Config *xemacps_lookup_config(unsigned mac_base)
+{
+ XEmacPs_Config *cfgptr = NULL;
+ s32_t i;
+
+ for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
+ if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) {
+ cfgptr = &XEmacPs_ConfigTable[i];
+ break;
+ }
+ }
+
+ return (cfgptr);
+}
+
+void init_emacps(xemacpsif_s *xemacps, struct netif *netif)
+{
+ XEmacPs *xemacpsp;
+ s32_t status = XST_SUCCESS;
+ u32_t i;
+ u32_t phyfoundforemac0 = FALSE;
+ u32_t phyfoundforemac1 = FALSE;
+
+ xemacpsp = &xemacps->emacps;
+
+#ifdef ZYNQMP_USE_JUMBO
+ XEmacPs_SetOptions(xemacpsp, XEMACPS_JUMBO_ENABLE_OPTION);
+#endif
+
+#ifdef LWIP_IGMP
+ XEmacPs_SetOptions(xemacpsp, XEMACPS_MULTICAST_OPTION);
+#endif
+
+ /* set mac address */
+ status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
+ if (status != XST_SUCCESS) {
+ xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
+ }
+
+ XEmacPs_SetMdioDivisor(xemacpsp, MDC_DIV_224);
+
+/* Please refer to file header comments for the file xemacpsif_physpeed.c
+ * to know more about the PHY programming sequence.
+ * For PCS PMA core, phy_setup_emacps is called with the predefined PHY address
+ * exposed through xaparemeters.h
+ * For RGMII case, assuming multiple PHYs can be present on the MDIO bus,
+ * detect_phy is called to get the addresses of the PHY present on
+ * a particular MDIO bus (emac0 or emac1). This address map is populated
+ * in phymapemac0 or phymapemac1.
+ * phy_setup_emacps is then called for each PHY present on the MDIO bus.
+ */
+#ifdef PCM_PMA_CORE_PRESENT
+#ifdef XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT
+ link_speed = phy_setup_emacps(xemacpsp, XPAR_PCSPMA_1000BASEX_PHYADDR);
+#elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT
+ link_speed = phy_setup_emacps(xemacpsp, XPAR_PCSPMA_SGMII_PHYADDR);
+#endif
+#else
+ detect_phy(xemacpsp);
+ for (i = 31; i > 0; i--) {
+ if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+ if (phymapemac0[i] == TRUE) {
+ link_speed = phy_setup_emacps(xemacpsp, i);
+ phyfoundforemac0 = TRUE;
+ phyaddrforemac = i;
+ }
+ } else {
+ if (phymapemac1[i] == TRUE) {
+ link_speed = phy_setup_emacps(xemacpsp, i);
+ phyfoundforemac1 = TRUE;
+ phyaddrforemac = i;
+ }
+ }
+ }
+ /* If no PHY was detected, use broadcast PHY address of 0 */
+ if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) {
+ if (phyfoundforemac0 == FALSE)
+ link_speed = phy_setup_emacps(xemacpsp, 0);
+ } else {
+ if (phyfoundforemac1 == FALSE)
+ link_speed = phy_setup_emacps(xemacpsp, 0);
+ }
+#endif
+
+ if (link_speed == XST_FAILURE) {
+ eth_link_status = ETH_LINK_DOWN;
+ xil_printf("Phy setup failure %s \n\r",__func__);
+ return;
+ } else {
+ eth_link_status = ETH_LINK_UP;
+ }
+
+ XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
+ /* Setting the operating speed of the MAC needs a delay. */
+ {
+ volatile s32_t wait;
+ for (wait=0; wait < 20000; wait++);
+ }
+}
+
+void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif)
+{
+ XEmacPs *xemacpsp;
+ s32_t status = XST_SUCCESS;
+
+ xemacpsp = &xemacps->emacps;
+
+ /* set mac address */
+ status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1);
+ if (status != XST_SUCCESS) {
+ xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__);
+ }
+
+ XEmacPs_SetOperatingSpeed(xemacpsp, link_speed);
+
+ /* Setting the operating speed of the MAC needs a delay. */
+ {
+ volatile s32_t wait;
+ for (wait=0; wait < 20000; wait++);
+ }
+}
+
+void setup_isr (struct xemac_s *xemac)
+{
+ xemacpsif_s *xemacpsif;
+
+ xemacpsif = (xemacpsif_s *)(xemac->state);
+ /*
+ * Setup callbacks
+ */
+ XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMASEND,
+ (void *) emacps_send_handler,
+ (void *) xemac);
+
+ XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMARECV,
+ (void *) emacps_recv_handler,
+ (void *) xemac);
+
+ XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_ERROR,
+ (void *) emacps_error_handler,
+ (void *) xemac);
+}
+
+void start_emacps (xemacpsif_s *xemacps)
+{
+ /* start the temac */
+ XEmacPs_Start(&xemacps->emacps);
+}
+
+void restart_emacps_transmitter (xemacpsif_s *xemacps) {
+ u32_t Reg;
+ Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg = Reg & (~XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+
+ Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET);
+ Reg = Reg | (XEMACPS_NWCTRL_TXEN_MASK);
+ XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress,
+ XEMACPS_NWCTRL_OFFSET, Reg);
+}
+
+void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord)
+{
+ struct xemac_s *xemac;
+ xemacpsif_s *xemacpsif;
+ XEmacPs_BdRing *rxring;
+ XEmacPs_BdRing *txring;
+#if !NO_SYS
+ xInsideISR++;
+#endif
+
+ xemac = (struct xemac_s *)(arg);
+ xemacpsif = (xemacpsif_s *)(xemac->state);
+ rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps);
+ txring = &XEmacPs_GetTxRing(&xemacpsif->emacps);
+
+ if (ErrorWord != 0) {
+ switch (Direction) {
+ case XEMACPS_RECV:
+ if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n"));
+ HandleEmacPsError(xemac);
+ }
+ if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n"));
+ emacps_recv_handler(arg);
+ setup_rx_bds(xemacpsif, rxring);
+ }
+ if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n"));
+ emacps_recv_handler(arg);
+ setup_rx_bds(xemacpsif, rxring);
+ }
+ break;
+ case XEMACPS_SEND:
+ if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n"));
+ HandleEmacPsError(xemac);
+ }
+ if (ErrorWord & XEMACPS_TXSR_URUN_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n"));
+ HandleTxErrors(xemac);
+ }
+ if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n"));
+ HandleTxErrors(xemac);
+ }
+ if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n"));
+ HandleTxErrors(xemac);
+ }
+ if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) {
+ LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n"));
+ process_sent_bds(xemacpsif, txring);
+ }
+ break;
+ }
+ }
+#if !NO_SYS
+ xInsideISR--;
+#endif
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_hw.h b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_hw.h
new file mode 100644
index 0000000..64f7771
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_hw.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __XEMACPSIF_HW_H_
+#define __XEMACPSIF_HW_H_
+
+#include "netif/xemacpsif.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+XEmacPs_Config * lookup_config(unsigned mac_base);
+
+void init_emacps(xemacpsif_s *xemacpsif, struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c
new file mode 100644
index 0000000..069020a
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c
@@ -0,0 +1,1037 @@
+/*
+ * Copyright (C) 2010 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+/*****************************************************************************
+* This file xemacpsif_physpeed.c implements functionalities to:
+* - Detect the available PHYs connected to a MAC
+* - Negotiate speed
+* - Configure speed
+* - Configure the SLCR registers for the negotiated speed
+*
+* In a typical use case, users of the APIs implemented in this file need to
+* do the following.
+* - Call the API detect_phy. It probes for the available PHYs connected to a MAC.
+* The MACs can be Emac0 (XPAR_XEMACPS_0_BASEADDR, 0xE000B000) or Emac1
+* (XPAR_XEMACPS_0_BASEADDR, 0xE000C000). It populates an array to notify
+* about the detected PHYs. The array phymapemac0 is used for Emac0 and
+* phymapemac1 is for Emac1.
+* - The users need to parse the corresponding arrays, phymapemac0 or phymapemac1
+* to know the available PHYs for a MAC. The users then need to call
+* phy_setup_emacps to setup the PHYs for proper speed setting. The API
+* phy_setup_emacps should be called with the PHY address for which the speed
+* needs to be negotiated or configured. In a specific use case, if 2 PHYs are
+* connected to Emac0 with addresses of 7 and 11, then users get these address
+* details from phymapemac0 (after calling detect_phy) and then call
+* phy_setup_emacps twice, with ab address of 7 and 11.
+* - Points to note: The MAC can operate at only one speed. If a MAC is connected
+* to multiple PHYs, then all PHYs must negotiate and configured for the same
+* speed.
+* - This file implements static functions to set proper SLCR clocks. As stated
+* above, all PHYs connected to a PHY must operate at same speed and the SLCR
+* clock will be setup accordingly.
+*
+* This file implements the following PHY types.
+* - The standard RGMII.
+* - It provides support for GMII to RGMII converter Xilinx IP. This Xilinx IP
+* sits on the MDIO bus with a predefined PHY address. This IP exposes register
+* that needs to be programmed with the negotiated speed.
+* For example, in a typical design, the Emac0 or Emac1 exposes GMII interface.
+* The user can then use the Xilinx IP that converts GMII to RGMII.
+* The external PHY (most typically Marvell 88E1116R) negotiates for speed
+* with the remote PHY. The implementation in this file then programs the
+* Xilinx IP with this negotiated speed. The Xilinx IP has a predefined IP
+* address exposed through xparameters.h
+* - The SGMII and 1000 BaseX PHY interfaces.
+* If the PHY interface is SGMII or 1000 BaseX a separate "get_IEEE_phy_speed"
+* is used which is different from standard RGMII "get_IEEE_phy_speed".
+* The 1000 BaseX always operates at 1000 Mbps. The SGMII interface can
+* negotiate speed accordingly.
+* For SGMII or 1000 BaseX interfaces, the detect_phy should not be called.
+* The phy addresses for these interfaces are fixed at the design time.
+*
+* Point to note:
+* A MAC can not be connected to PHYs where there is a mix between
+* SGMII or 1000 Basex or GMII/MII/RGMII.
+* In a typical multiple PHY designs, it is expected that the PHYs connected
+* will be RGMII or GMII.
+*
+* The users can choose not to negotiate speed from lwip settings GUI.
+* If they opt to choose a particular PHY speed, then the PHY will hard code
+* the speed to operate only at the corresponding speed. It will not advertise
+* any other speeds. It is users responsibility to ensure that the remote PHY
+* supports the speed programmed through the lwip gui.
+*
+* The following combination of MDIO/PHY are supported:
+* - Multiple PHYs connected to the MDIO bus of a MAC. If Emac0 MDIO is connected
+* to single/multiple PHYs, it is supported. Similarly Emac1 MDIO connected to
+* single/multiple PHYs is supported.
+* - A design where both the interfaces are present and are connected to their own
+* MDIO bus is supported.
+*
+* The following MDIO/PHY setup is not supported:
+* - A design has both the MACs present. MDIO bus is available only for one MAC
+* (Emac0 or Emac1). This MDIO bus has multiple PHYs available for both the
+* MACs. The negotiated speed for PHYs sitting on the MDIO bus of one MAC will
+* not be see for the other MAC and hence the speed/SLCR settings of the other
+* MAC cannot be programmed. Hence this kind of design will not work for
+* this implementation.
+*
+********************************************************************************/
+
+#include "netif/xemacpsif.h"
+#include "lwipopts.h"
+#include "xparameters_ps.h"
+#include "xparameters.h"
+#include "xemac_ieee_reg.h"
+
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
+
+#define PHY_DETECT_REG 1
+#define PHY_IDENTIFIER_1_REG 2
+#define PHY_IDENTIFIER_2_REG 3
+#define PHY_DETECT_MASK 0x1808
+#define PHY_MARVELL_IDENTIFIER 0x0141
+#define PHY_TI_IDENTIFIER 0x2000
+#define PHY_REALTEK_IDENTIFIER 0x001c
+#define PHY_XILINX_PCS_PMA_ID1 0x0174
+#define PHY_XILINX_PCS_PMA_ID2 0x0C00
+
+#define XEMACPS_GMII2RGMII_SPEED1000_FD 0x140
+#define XEMACPS_GMII2RGMII_SPEED100_FD 0x2100
+#define XEMACPS_GMII2RGMII_SPEED10_FD 0x100
+#define XEMACPS_GMII2RGMII_REG_NUM 0x10
+
+#define PHY_REGCR 0x0D
+#define PHY_ADDAR 0x0E
+#define PHY_RGMIIDCTL 0x86
+#define PHY_RGMIICTL 0x32
+#define PHY_STS 0x11
+#define PHY_TI_CR 0x10
+#define PHY_TI_CFG4 0x31
+
+#define PHY_REGCR_ADDR 0x001F
+#define PHY_REGCR_DATA 0x401F
+#define PHY_TI_CRVAL 0x5048
+#define PHY_TI_CFG4RESVDBIT7 0x80
+
+/* Frequency setting */
+#define SLCR_LOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x4)
+#define SLCR_UNLOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x8)
+#define SLCR_GEM0_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x140)
+#define SLCR_GEM1_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x144)
+#define SLCR_GEM_SRCSEL_EMIO 0x40
+#define SLCR_LOCK_KEY_VALUE 0x767B
+#define SLCR_UNLOCK_KEY_VALUE 0xDF0D
+#define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214)
+#define EMACPS_SLCR_DIV_MASK 0xFC0FC0FF
+
+#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1 || \
+ XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
+#define PCM_PMA_CORE_PRESENT
+#else
+#undef PCM_PMA_CORE_PRESENT
+#endif
+
+#ifdef PCM_PMA_CORE_PRESENT
+#define IEEE_CTRL_RESET 0x9140
+#define IEEE_CTRL_ISOLATE_DISABLE 0xFBFF
+#endif
+
+u32_t phymapemac0[32];
+u32_t phymapemac1[32];
+
+#if defined (PCM_PMA_CORE_PRESENT) || defined (CONFIG_LINKSPEED_AUTODETECT)
+static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr);
+#endif
+static void SetUpSLCRDivisors(UINTPTR mac_baseaddr, s32_t speed);
+#if defined (CONFIG_LINKSPEED1000) || defined (CONFIG_LINKSPEED100) \
+ || defined (CONFIG_LINKSPEED10)
+static u32_t configure_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr, u32_t speed);
+#endif
+
+#ifdef PCM_PMA_CORE_PRESENT
+u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
+{
+ u32_t link_speed;
+ u16_t regval;
+ u16_t phy_id;
+
+ if(phy_addr == 0) {
+ for (phy_addr = 31; phy_addr > 0; phy_addr--) {
+ XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
+ &phy_id);
+
+ if (phy_id == PHY_XILINX_PCS_PMA_ID1) {
+ XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_2_REG,
+ &phy_id);
+ if (phy_id == PHY_XILINX_PCS_PMA_ID2) {
+ /* Found a valid PHY address */
+ LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
+ phy_addr));
+ break;
+ }
+ }
+ }
+ }
+
+ link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr);
+ if (link_speed == 1000)
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
+ else if (link_speed == 100)
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
+ else
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
+
+ xil_printf("link speed for phy address %d: %d\r\n", phy_addr, link_speed);
+ return link_speed;
+}
+
+static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
+{
+ u16_t temp;
+ u16_t control;
+ u16_t status;
+ u16_t partner_capabilities;
+
+ xil_printf("Start PHY autonegotiation \r\n");
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
+ control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
+ control &= IEEE_CTRL_ISOLATE_DISABLE;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+
+ xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ sleep(1);
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET,
+ &status);
+ }
+ xil_printf("autonegotiation complete \r\n");
+
+#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 1);
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ if ((temp & 0x0020) == 0x0020) {
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+ return 1000;
+ }
+ else {
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+ xil_printf("Link error, temp = %x\r\n", temp);
+ return 0;
+ }
+#elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
+ xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \r\n");
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ while(!(temp & 0x8000)) {
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
+ }
+ if((temp & 0x0C00) == 0x0800) {
+ return 1000;
+ }
+ else if((temp & 0x0C00) == 0x0400) {
+ return 100;
+ }
+ else if((temp & 0x0C00) == 0x0000) {
+ return 10;
+ } else {
+ xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Defaulting to Speed = 10 Mbps\r\n");
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &temp);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, 0x0100);
+ return 10;
+ }
+#endif
+
+}
+
+#else /*PCM_PMA_CORE_PRESENT not defined, GMII/RGMII case*/
+void detect_phy(XEmacPs *xemacpsp)
+{
+ u16_t phy_reg;
+ u32_t phy_addr;
+ u32_t emacnum;
+
+ if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR)
+ emacnum = 0;
+ else
+ emacnum = 1;
+ for (phy_addr = 31; phy_addr > 0; phy_addr--) {
+ XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_DETECT_REG,
+ &phy_reg);
+
+ if ((phy_reg != 0xFFFF) &&
+ ((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+ /* Found a valid PHY address */
+ LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
+ phy_addr));
+ if (emacnum == 0)
+ phymapemac0[phy_addr] = TRUE;
+ else
+ phymapemac1[phy_addr] = TRUE;
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
+ &phy_reg);
+ if ((phy_reg != PHY_MARVELL_IDENTIFIER) &&
+ (phy_reg != PHY_TI_IDENTIFIER) &&
+ (phy_reg != PHY_REALTEK_IDENTIFIER)) {
+ xil_printf("WARNING: Not a Marvell or TI or Realtek Ethernet PHY. Please verify the initialization sequence\r\n");
+ }
+ }
+ }
+}
+
+u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
+{
+ u32_t link_speed;
+ u32_t conv_present = 0;
+ u32_t convspeeddupsetting = 0;
+ u32_t convphyaddr = 0;
+
+#ifdef XPAR_GMII2RGMIICON_0N_ETH0_ADDR
+ convphyaddr = XPAR_GMII2RGMIICON_0N_ETH0_ADDR;
+ conv_present = 1;
+#endif
+#ifdef XPAR_GMII2RGMIICON_0N_ETH1_ADDR
+ convphyaddr = XPAR_GMII2RGMIICON_0N_ETH1_ADDR;
+ conv_present = 1;
+#endif
+
+#ifdef CONFIG_LINKSPEED_AUTODETECT
+ link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr);
+ if (link_speed == 1000) {
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
+ convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
+ } else if (link_speed == 100) {
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
+ convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
+ } else if (link_speed != XST_FAILURE){
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
+ convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
+ } else {
+ xil_printf("Phy setup error \r\n");
+ return XST_FAILURE;
+ }
+#elif defined(CONFIG_LINKSPEED1000)
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
+ link_speed = 1000;
+ configure_IEEE_phy_speed(xemacpsp, phy_addr, link_speed);
+ convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
+ sleep(1);
+#elif defined(CONFIG_LINKSPEED100)
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
+ link_speed = 100;
+ configure_IEEE_phy_speed(xemacpsp, phy_addr, link_speed);
+ convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
+ sleep(1);
+#elif defined(CONFIG_LINKSPEED10)
+ SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
+ link_speed = 10;
+ configure_IEEE_phy_speed(xemacpsp, phy_addr, link_speed);
+ convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
+ sleep(1);
+#endif
+ if (conv_present) {
+ XEmacPs_PhyWrite(xemacpsp, convphyaddr,
+ XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting);
+ }
+
+ xil_printf("link speed for phy address %d: %d\r\n", phy_addr, link_speed);
+ return link_speed;
+}
+
+#if defined CONFIG_LINKSPEED_AUTODETECT
+static u32_t get_TI_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
+{
+ u16_t control;
+ u16_t status;
+ u16_t status_speed;
+ u32_t timeout_counter = 0;
+ u32_t phyregtemp;
+ u32_t RetStatus;
+
+ xil_printf("Start PHY autonegotiation \r\n");
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, 0x1F, (u16_t *)&phyregtemp);
+ phyregtemp |= 0x4000;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, 0x1F, phyregtemp);
+ RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, 0x1F, (u16_t *)&phyregtemp);
+ if (RetStatus != XST_SUCCESS) {
+ xil_printf("Error during sw reset \n\r");
+ return XST_FAILURE;
+ }
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, 0, (u16_t *)&phyregtemp);
+ phyregtemp |= 0x8000;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, phyregtemp);
+
+ /*
+ * Delay
+ */
+ sleep(1);
+
+ RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, 0, (u16_t *)&phyregtemp);
+ if (RetStatus != XST_SUCCESS) {
+ xil_printf("Error during reset \n\r");
+ return XST_FAILURE;
+ }
+
+ /* FIFO depth */
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_TI_CR, PHY_TI_CRVAL);
+ RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_TI_CR, (u16_t *)&phyregtemp);
+ if (RetStatus != XST_SUCCESS) {
+ xil_printf("Error writing to 0x10 \n\r");
+ return XST_FAILURE;
+ }
+
+ /* TX/RX tuning */
+ /* Write to PHY_RGMIIDCTL */
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIIDCTL);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
+ RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, 0xA8);
+ if (RetStatus != XST_SUCCESS) {
+ xil_printf("Error in tuning");
+ return XST_FAILURE;
+ }
+
+ /* Read PHY_RGMIIDCTL */
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIIDCTL);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
+ RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
+ if (RetStatus != XST_SUCCESS) {
+ xil_printf("Error in tuning");
+ return XST_FAILURE;
+ }
+
+ /* Write PHY_RGMIICTL */
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIICTL);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
+ RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, 0xD3);
+ if (RetStatus != XST_SUCCESS) {
+ xil_printf("Error in tuning");
+ return XST_FAILURE;
+ }
+
+ /* Read PHY_RGMIICTL */
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIICTL);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
+ RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
+ if (RetStatus != XST_SUCCESS) {
+ xil_printf("Error in tuning");
+ return XST_FAILURE;
+ }
+
+ /* SW workaround for unstable link when RX_CTRL is not STRAP MODE 3 or 4 */
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_TI_CFG4);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
+ RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
+ phyregtemp &= ~(PHY_TI_CFG4RESVDBIT7);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_TI_CFG4);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
+ RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, phyregtemp);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
+ control |= IEEE_ASYMMETRIC_PAUSE_MASK;
+ control |= IEEE_PAUSE_MASK;
+ control |= ADVERTISE_100;
+ control |= ADVERTISE_10;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ &control);
+ control |= ADVERTISE_1000;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
+ control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
+
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ sleep(1);
+ timeout_counter++;
+
+ if (timeout_counter == 30) {
+ xil_printf("Auto negotiation error \r\n");
+ return XST_FAILURE;
+ }
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ }
+ xil_printf("autonegotiation complete \r\n");
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_STS, &status_speed);
+ if ((status_speed & 0xC000) == 0x8000) {
+ return 1000;
+ } else if ((status_speed & 0xC000) == 0x4000) {
+ return 100;
+ } else {
+ return 10;
+ }
+
+ return XST_SUCCESS;
+}
+
+static u32_t get_Marvell_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
+{
+ u16_t temp;
+ u16_t control;
+ u16_t status;
+ u16_t status_speed;
+ u32_t timeout_counter = 0;
+ u32_t temp_speed;
+
+ xil_printf("Start PHY autonegotiation \r\n");
+
+ XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
+ control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control);
+
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
+ control |= IEEE_ASYMMETRIC_PAUSE_MASK;
+ control |= IEEE_PAUSE_MASK;
+ control |= ADVERTISE_100;
+ control |= ADVERTISE_10;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ &control);
+ control |= ADVERTISE_1000;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ control);
+
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
+ &control);
+ control |= (7 << 12); /* max number of gigabit attempts */
+ control |= (1 << 11); /* enable downshift */
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
+ control);
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
+ control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_RESET_MASK;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+
+ while (1) {
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ if (control & IEEE_CTRL_RESET_MASK)
+ continue;
+ else
+ break;
+ }
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
+
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ sleep(1);
+ XEmacPs_PhyRead(xemacpsp, phy_addr,
+ IEEE_COPPER_SPECIFIC_STATUS_REG_2, &temp);
+ timeout_counter++;
+
+ if (timeout_counter == 30) {
+ xil_printf("Auto negotiation error \r\n");
+ return XST_FAILURE;
+ }
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ }
+ xil_printf("autonegotiation complete \r\n");
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr,IEEE_SPECIFIC_STATUS_REG,
+ &status_speed);
+ if (status_speed & 0x400) {
+ temp_speed = status_speed & IEEE_SPEED_MASK;
+
+ if (temp_speed == IEEE_SPEED_1000)
+ return 1000;
+ else if(temp_speed == IEEE_SPEED_100)
+ return 100;
+ else
+ return 10;
+ }
+
+ return XST_SUCCESS;
+}
+
+static u32_t get_Realtek_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
+{
+ u16_t control;
+ u16_t status;
+ u16_t status_speed;
+ u32_t timeout_counter = 0;
+ u32_t temp_speed;
+
+ xil_printf("Start PHY autonegotiation \r\n");
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
+ control |= IEEE_ASYMMETRIC_PAUSE_MASK;
+ control |= IEEE_PAUSE_MASK;
+ control |= ADVERTISE_100;
+ control |= ADVERTISE_10;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ &control);
+ control |= ADVERTISE_1000;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
+ control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
+ control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control |= IEEE_CTRL_RESET_MASK;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
+
+ while (1) {
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ if (control & IEEE_CTRL_RESET_MASK)
+ continue;
+ else
+ break;
+ }
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+
+ xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
+
+ while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+ sleep(1);
+ timeout_counter++;
+
+ if (timeout_counter == 30) {
+ xil_printf("Auto negotiation error \r\n");
+ return XST_FAILURE;
+ }
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
+ }
+ xil_printf("autonegotiation complete \r\n");
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr,IEEE_SPECIFIC_STATUS_REG,
+ &status_speed);
+ if (status_speed & 0x400) {
+ temp_speed = status_speed & IEEE_SPEED_MASK;
+
+ if (temp_speed == IEEE_SPEED_1000)
+ return 1000;
+ else if(temp_speed == IEEE_SPEED_100)
+ return 100;
+ else
+ return 10;
+ }
+
+ return XST_FAILURE;
+}
+
+static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
+{
+ u16_t phy_identity;
+ u32_t RetStatus;
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
+ &phy_identity);
+ if (phy_identity == PHY_TI_IDENTIFIER) {
+ RetStatus = get_TI_phy_speed(xemacpsp, phy_addr);
+ } else if (phy_identity == PHY_REALTEK_IDENTIFIER) {
+ RetStatus = get_Realtek_phy_speed(xemacpsp, phy_addr);
+ } else {
+ RetStatus = get_Marvell_phy_speed(xemacpsp, phy_addr);
+ }
+
+ return RetStatus;
+}
+#endif
+
+#if defined (CONFIG_LINKSPEED1000) || defined (CONFIG_LINKSPEED100) \
+ || defined (CONFIG_LINKSPEED10)
+static u32_t configure_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr, u32_t speed)
+{
+ u16_t control;
+ u16_t autonereg;
+
+ XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
+ control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control);
+
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+ autonereg |= IEEE_ASYMMETRIC_PAUSE_MASK;
+ autonereg |= IEEE_PAUSE_MASK;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
+ control &= ~IEEE_CTRL_LINKSPEED_1000M;
+ control &= ~IEEE_CTRL_LINKSPEED_100M;
+ control &= ~IEEE_CTRL_LINKSPEED_10M;
+
+ if (speed == 1000) {
+ control |= IEEE_CTRL_LINKSPEED_1000M;
+
+ /* Don't advertise PHY speed of 100 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+ autonereg &= (~ADVERTISE_100);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+
+ /* Don't advertise PHY speed of 10 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+ autonereg &= (~ADVERTISE_10);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+
+ /* Advertise PHY speed of 1000 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
+ autonereg |= ADVERTISE_1000;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
+ }
+
+ else if (speed == 100) {
+ control |= IEEE_CTRL_LINKSPEED_100M;
+
+ /* Don't advertise PHY speed of 1000 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
+ autonereg &= (~ADVERTISE_1000);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
+
+ /* Don't advertise PHY speed of 10 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+ autonereg &= (~ADVERTISE_10);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+
+ /* Advertise PHY speed of 100 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+ autonereg |= ADVERTISE_100;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+ }
+
+ else if (speed == 10) {
+ control |= IEEE_CTRL_LINKSPEED_10M;
+
+ /* Don't advertise PHY speed of 1000 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
+ autonereg &= (~ADVERTISE_1000);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
+
+ /* Don't advertise PHY speed of 100 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+ autonereg &= (~ADVERTISE_100);
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+
+ /* Advertise PHY speed of 10 Mbps */
+ XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
+ autonereg |= ADVERTISE_10;
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
+ }
+
+ XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET,
+ control | IEEE_CTRL_RESET_MASK);
+ {
+ volatile s32_t wait;
+ for (wait=0; wait < 100000; wait++);
+ }
+ return 0;
+}
+#endif
+#endif /*PCM_PMA_CORE_PRESENT*/
+
+static void SetUpSLCRDivisors(UINTPTR mac_baseaddr, s32_t speed)
+{
+ volatile UINTPTR slcrBaseAddress;
+ u32_t SlcrDiv0 = 0;
+ u32_t SlcrDiv1 = 0;
+ u32_t SlcrTxClkCntrl;
+ u32_t gigeversion;
+ volatile UINTPTR CrlApbBaseAddr;
+ u32_t CrlApbDiv0 = 0;
+ u32_t CrlApbDiv1 = 0;
+ u32_t CrlApbGemCtrl;
+#if defined (__aarch64__) && (EL1_NONSECURE == 1)
+ u32_t ClkId;
+#endif
+
+ gigeversion = ((Xil_In32(mac_baseaddr + 0xFC)) >> 16) & 0xFFF;
+ if (gigeversion == 2) {
+
+ Xil_Out32(SLCR_UNLOCK_ADDR, SLCR_UNLOCK_KEY_VALUE);
+
+ if (mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR) {
+ slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
+ } else {
+ slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
+ }
+
+ if(Xil_In32(slcrBaseAddress) &
+ SLCR_GEM_SRCSEL_EMIO) {
+ return;
+ }
+
+ if (speed == 1000) {
+ if (mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR) {
+#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
+ SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
+ SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
+#endif
+ } else {
+#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
+ SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
+ SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
+#endif
+ }
+ } else if (speed == 100) {
+ if (mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR) {
+#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
+ SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
+ SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
+#endif
+ } else {
+#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
+ SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
+ SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
+#endif
+ }
+ } else {
+ if (mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR) {
+#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
+ SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
+ SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
+#endif
+ } else {
+#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
+ SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
+ SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
+#endif
+ }
+ }
+
+ if (SlcrDiv0 != 0 && SlcrDiv1 != 0) {
+ SlcrTxClkCntrl = Xil_In32(slcrBaseAddress);
+ SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
+ SlcrTxClkCntrl |= (SlcrDiv1 << 20);
+ SlcrTxClkCntrl |= (SlcrDiv0 << 8);
+ Xil_Out32(slcrBaseAddress, SlcrTxClkCntrl);
+ Xil_Out32(SLCR_LOCK_ADDR, SLCR_LOCK_KEY_VALUE);
+ } else {
+ xil_printf("Clock Divisors incorrect - Please check\r\n");
+ }
+ } else if (gigeversion == GEM_VERSION_ZYNQMP) {
+ /* Setup divisors in CRL_APB for Zynq Ultrascale+ MPSoC */
+ if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+ CrlApbBaseAddr = CRL_APB_GEM0_REF_CTRL;
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+ CrlApbBaseAddr = CRL_APB_GEM1_REF_CTRL;
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+ CrlApbBaseAddr = CRL_APB_GEM2_REF_CTRL;
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+ CrlApbBaseAddr = CRL_APB_GEM3_REF_CTRL;
+ }
+
+ if (speed == 1000) {
+ if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1;
+#endif
+ }
+ } else if (speed == 100) {
+ if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1;
+#endif
+ }
+ } else {
+ if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1;
+#endif
+ } else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
+#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0
+ CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0;
+ CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1;
+#endif
+ }
+ }
+
+ if (CrlApbDiv0 != 0 && CrlApbDiv1 != 0) {
+ #if defined (__aarch64__) && (EL1_NONSECURE == 1)
+ XSmc_OutVar RegRead;
+ RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
+ 0, 0, 0, 0, 0, 0);
+ CrlApbGemCtrl = RegRead.Arg0 >> 32;
+ #else
+ CrlApbGemCtrl = Xil_In32(CrlApbBaseAddr);
+ #endif
+ CrlApbGemCtrl &= ~CRL_APB_GEM_DIV0_MASK;
+ CrlApbGemCtrl |= CrlApbDiv0 << CRL_APB_GEM_DIV0_SHIFT;
+ CrlApbGemCtrl &= ~CRL_APB_GEM_DIV1_MASK;
+ CrlApbGemCtrl |= CrlApbDiv1 << CRL_APB_GEM_DIV1_SHIFT;
+ #if defined (__aarch64__) && (EL1_NONSECURE == 1)
+ Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(CrlApbBaseAddr) | ((u64)(0xFFFFFFFF) << 32),
+ (u64)CrlApbGemCtrl, 0, 0, 0, 0, 0);
+ do {
+ RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
+ 0, 0, 0, 0, 0, 0);
+ } while((RegRead.Arg0 >> 32) != CrlApbGemCtrl);
+ #else
+ Xil_Out32(CrlApbBaseAddr, CrlApbGemCtrl);
+ #endif
+ } else {
+ xil_printf("Clock Divisors incorrect - Please check\r\n");
+ }
+ } else if (gigeversion == GEM_VERSION_VERSAL) {
+ /* Setup divisors in CRL for Versal */
+ if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+ CrlApbBaseAddr = VERSAL_CRL_GEM0_REF_CTRL;
+#if defined (__aarch64__) && (EL1_NONSECURE == 1)
+ ClkId = CLK_GEM0_REF;
+#endif
+ } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+ CrlApbBaseAddr = VERSAL_CRL_GEM1_REF_CTRL;
+#if defined (__aarch64__) && (EL1_NONSECURE == 1)
+ ClkId = CLK_GEM1_REF;
+#endif
+ }
+
+ if (speed == 1000) {
+ if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+#ifdef XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
+ CrlApbDiv0 = XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
+#endif
+ } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+#ifdef XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
+ CrlApbDiv0 = XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
+#endif
+ }
+ } else if (speed == 100) {
+ if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+#ifdef XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
+ CrlApbDiv0 = XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
+#endif
+ } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+#ifdef XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
+ CrlApbDiv0 = XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
+#endif
+ }
+ } else {
+ if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
+#ifdef XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
+ CrlApbDiv0 = XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
+#endif
+ } else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
+#ifdef XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
+ CrlApbDiv0 = XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
+#endif
+ }
+ }
+
+ if (CrlApbDiv0 != 0) {
+#if defined (__aarch64__) && (EL1_NONSECURE == 1)
+ Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)CrlApbDiv0 << 32) | ClkId), 0, 0, 0, 0, 0, 0);
+#else
+ CrlApbGemCtrl = Xil_In32(CrlApbBaseAddr);
+ CrlApbGemCtrl &= ~VERSAL_CRL_GEM_DIV_MASK;
+ CrlApbGemCtrl |= CrlApbDiv0 << VERSAL_CRL_APB_GEM_DIV_SHIFT;
+
+ Xil_Out32(CrlApbBaseAddr, CrlApbGemCtrl);
+#endif
+ } else {
+ xil_printf("Clock Divisors incorrect - Please check\r\n");
+ }
+ }
+
+ return;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xpqueue.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xpqueue.c
new file mode 100644
index 0000000..b5a773e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xpqueue.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2007 - 2019 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include
+
+#include "netif/xpqueue.h"
+#include "xil_printf.h"
+
+#define NUM_QUEUES 2
+
+pq_queue_t pq_queue[NUM_QUEUES];
+
+pq_queue_t *
+pq_create_queue()
+{
+ static int i;
+ pq_queue_t *q = NULL;
+
+ if (i >= NUM_QUEUES) {
+ xil_printf("ERR: Max Queues allocated\n\r");
+ return q;
+ }
+
+ q = &pq_queue[i++];
+
+ if (!q)
+ return q;
+
+ q->head = q->tail = q->len = 0;
+
+ return q;
+}
+
+int
+pq_enqueue(pq_queue_t *q, void *p)
+{
+ if (q->len == PQ_QUEUE_SIZE)
+ return -1;
+
+ q->data[q->head] = p;
+ q->head = (q->head + 1)%PQ_QUEUE_SIZE;
+ q->len++;
+
+ return 0;
+}
+
+void*
+pq_dequeue(pq_queue_t *q)
+{
+ int ptail;
+
+ if (q->len == 0)
+ return NULL;
+
+ ptail = q->tail;
+ q->tail = (q->tail + 1)%PQ_QUEUE_SIZE;
+ q->len--;
+
+ return q->data[ptail];
+}
+
+int
+pq_qlength(pq_queue_t *q)
+{
+ return q->len;
+}
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xtopology_g.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xtopology_g.c
new file mode 100644
index 0000000..128583e
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/netif/xtopology_g.c
@@ -0,0 +1,15 @@
+#include "netif/xtopology.h"
+#include "xparameters.h"
+
+struct xtopology_t xtopology[] = {
+ {
+ 0xE000B000,
+ xemac_type_emacps,
+ 0x0,
+ 0x0,
+ 0xF8F00100,
+ 0x36,
+ },
+};
+
+int xtopology_n_emacs = 1;
diff --git a/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/sys_arch.c b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/sys_arch.c
new file mode 100644
index 0000000..8a0cbd4
--- /dev/null
+++ b/2.FW/Zynq/proj_cal/Vitis/calboard_bsp/ps7_cortexa9_0/libsrc/lwip211_v1_7/src/contrib/ports/xilinx/sys_arch.c
@@ -0,0 +1,622 @@
+/* sys_arch.c -
+ * provide sys_arch functionality as required for lwIP
+ * most of this functionality is obtained from FreeRTOS
+ * this file acts as a wrapper around the FreeRTOS functions
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (C) 2007 - 2021 Xilinx, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels