Add Zynq project files
This commit is contained in:
Jeremy Shen
@@ -0,0 +1,78 @@
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[2]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[4]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[5]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[6]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[7]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[8]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[9]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[10]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[11]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[12]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[13]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[14]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[15]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[16]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[17]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[18]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[20]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[21]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[22]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[23]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[24]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[25]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[26]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[27]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[28]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[29]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[30]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[31]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {EMIO_0_tri_io[32]}]
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set_property PACKAGE_PIN AB21 [get_ports {EMIO_0_tri_io[0]}]
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set_property PACKAGE_PIN W20 [get_ports {EMIO_0_tri_io[1]}]
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set_property PACKAGE_PIN Y20 [get_ports {EMIO_0_tri_io[2]}]
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set_property PACKAGE_PIN AE18 [get_ports {EMIO_0_tri_io[3]}]
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set_property PACKAGE_PIN AF18 [get_ports {EMIO_0_tri_io[4]}]
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set_property PACKAGE_PIN AF19 [get_ports {EMIO_0_tri_io[5]}]
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set_property PACKAGE_PIN AE21 [get_ports {EMIO_0_tri_io[6]}]
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set_property PACKAGE_PIN AE20 [get_ports {EMIO_0_tri_io[7]}]
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set_property PACKAGE_PIN AD18 [get_ports {EMIO_0_tri_io[8]}]
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set_property PACKAGE_PIN AD19 [get_ports {EMIO_0_tri_io[9]}]
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set_property PACKAGE_PIN AA22 [get_ports {EMIO_0_tri_io[10]}]
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set_property PACKAGE_PIN AB25 [get_ports {EMIO_0_tri_io[11]}]
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set_property PACKAGE_PIN AD23 [get_ports {EMIO_0_tri_io[12]}]
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set_property PACKAGE_PIN AD20 [get_ports {EMIO_0_tri_io[13]}]
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set_property PACKAGE_PIN AD21 [get_ports {EMIO_0_tri_io[14]}]
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set_property PACKAGE_PIN AC23 [get_ports {EMIO_0_tri_io[15]}]
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set_property PACKAGE_PIN AA25 [get_ports {EMIO_0_tri_io[16]}]
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set_property PACKAGE_PIN AD24 [get_ports {EMIO_0_tri_io[17]}]
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set_property PACKAGE_PIN AC24 [get_ports {EMIO_0_tri_io[18]}]
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set_property PACKAGE_PIN AC21 [get_ports {EMIO_0_tri_io[19]}]
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set_property PACKAGE_PIN AC22 [get_ports {EMIO_0_tri_io[20]}]
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set_property PACKAGE_PIN AF20 [get_ports {EMIO_0_tri_io[21]}]
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set_property PACKAGE_PIN AD10 [get_ports {EMIO_0_tri_io[22]}]
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set_property PACKAGE_PIN AA12 [get_ports {EMIO_0_tri_io[23]}]
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set_property PACKAGE_PIN AF12 [get_ports {EMIO_0_tri_io[24]}]
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set_property PACKAGE_PIN AA13 [get_ports {EMIO_0_tri_io[25]}]
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set_property PACKAGE_PIN AE12 [get_ports {EMIO_0_tri_io[26]}]
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set_property PACKAGE_PIN AE13 [get_ports {EMIO_0_tri_io[27]}]
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set_property PACKAGE_PIN AF13 [get_ports {EMIO_0_tri_io[28]}]
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set_property PACKAGE_PIN AE11 [get_ports {EMIO_0_tri_io[29]}]
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set_property PACKAGE_PIN AF10 [get_ports {EMIO_0_tri_io[30]}]
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set_property PACKAGE_PIN AE10 [get_ports {EMIO_0_tri_io[31]}]
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set_property PACKAGE_PIN W13 [get_ports {EMIO_0_tri_io[32]}]
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@@ -0,0 +1,399 @@
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_0]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_1]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_2]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_3]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_4]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_5]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_6]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_7]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_8]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_9]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_10]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_11]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_12]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_13]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_14]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_15]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_16]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_17]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_18]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_19]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_20]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_21]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_22]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_23]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_24]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_25]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_28]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_29]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_30]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_26]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_27]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_31]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_i_32]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_0]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_1]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_2]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_4]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_5]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_7]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_8]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_9]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_3]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_6]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_11]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_14]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_15]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_17]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_18]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_10]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_12]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_13]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_16]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_19]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_20]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_21]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_22]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_23]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_24]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_25]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_26]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_27]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_28]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_29]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_30]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_31]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_o_32]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_0]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_1]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_2]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_3]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_4]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_5]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_6]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_7]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_8]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_9]
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set_property MARK_DEBUG true [get_nets EMIO_0_tri_t_10]
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets [list system_i/processing_system7_0/inst/FCLK_CLK0]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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set_property port_width 1 [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list EMIO_0_tri_i_0]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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set_property port_width 1 [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list EMIO_0_tri_i_1]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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set_property port_width 1 [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list EMIO_0_tri_i_2]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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set_property port_width 1 [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list EMIO_0_tri_i_3]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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set_property port_width 1 [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list EMIO_0_tri_i_4]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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set_property port_width 1 [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list EMIO_0_tri_i_5]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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set_property port_width 1 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list EMIO_0_tri_i_6]]
|
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create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
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set_property port_width 1 [get_debug_ports u_ila_0/probe7]
|
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connect_debug_port u_ila_0/probe7 [get_nets [list EMIO_0_tri_i_7]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list EMIO_0_tri_i_8]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list EMIO_0_tri_i_9]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list EMIO_0_tri_i_10]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list EMIO_0_tri_i_11]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list EMIO_0_tri_i_12]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list EMIO_0_tri_i_13]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list EMIO_0_tri_i_14]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list EMIO_0_tri_i_15]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list EMIO_0_tri_i_16]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list EMIO_0_tri_i_17]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list EMIO_0_tri_i_18]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list EMIO_0_tri_i_19]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list EMIO_0_tri_i_20]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list EMIO_0_tri_i_21]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list EMIO_0_tri_i_22]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list EMIO_0_tri_i_23]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list EMIO_0_tri_i_24]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list EMIO_0_tri_i_25]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list EMIO_0_tri_i_26]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list EMIO_0_tri_i_27]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list EMIO_0_tri_i_28]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list EMIO_0_tri_i_29]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list EMIO_0_tri_i_30]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list EMIO_0_tri_i_31]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list EMIO_0_tri_i_32]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list EMIO_0_tri_o_0]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list EMIO_0_tri_o_1]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list EMIO_0_tri_o_2]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||
connect_debug_port u_ila_0/probe36 [get_nets [list EMIO_0_tri_o_3]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list EMIO_0_tri_o_4]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
||||
connect_debug_port u_ila_0/probe38 [get_nets [list EMIO_0_tri_o_5]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
||||
connect_debug_port u_ila_0/probe39 [get_nets [list EMIO_0_tri_o_6]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
||||
connect_debug_port u_ila_0/probe40 [get_nets [list EMIO_0_tri_o_7]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
||||
connect_debug_port u_ila_0/probe41 [get_nets [list EMIO_0_tri_o_8]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list EMIO_0_tri_o_9]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
||||
connect_debug_port u_ila_0/probe43 [get_nets [list EMIO_0_tri_o_10]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
||||
connect_debug_port u_ila_0/probe44 [get_nets [list EMIO_0_tri_o_11]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
||||
connect_debug_port u_ila_0/probe45 [get_nets [list EMIO_0_tri_o_12]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
||||
connect_debug_port u_ila_0/probe46 [get_nets [list EMIO_0_tri_o_13]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list EMIO_0_tri_o_14]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list EMIO_0_tri_o_15]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
||||
connect_debug_port u_ila_0/probe49 [get_nets [list EMIO_0_tri_o_16]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list EMIO_0_tri_o_17]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
||||
connect_debug_port u_ila_0/probe51 [get_nets [list EMIO_0_tri_o_18]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
||||
connect_debug_port u_ila_0/probe52 [get_nets [list EMIO_0_tri_o_19]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
||||
connect_debug_port u_ila_0/probe53 [get_nets [list EMIO_0_tri_o_20]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
||||
connect_debug_port u_ila_0/probe54 [get_nets [list EMIO_0_tri_o_21]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
||||
connect_debug_port u_ila_0/probe55 [get_nets [list EMIO_0_tri_o_22]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
||||
connect_debug_port u_ila_0/probe56 [get_nets [list EMIO_0_tri_o_23]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
||||
connect_debug_port u_ila_0/probe57 [get_nets [list EMIO_0_tri_o_24]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
||||
connect_debug_port u_ila_0/probe58 [get_nets [list EMIO_0_tri_o_25]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
||||
connect_debug_port u_ila_0/probe59 [get_nets [list EMIO_0_tri_o_26]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
||||
connect_debug_port u_ila_0/probe60 [get_nets [list EMIO_0_tri_o_27]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
||||
connect_debug_port u_ila_0/probe61 [get_nets [list EMIO_0_tri_o_28]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
||||
connect_debug_port u_ila_0/probe62 [get_nets [list EMIO_0_tri_o_29]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
||||
connect_debug_port u_ila_0/probe63 [get_nets [list EMIO_0_tri_o_30]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
||||
connect_debug_port u_ila_0/probe64 [get_nets [list EMIO_0_tri_o_31]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
|
||||
connect_debug_port u_ila_0/probe65 [get_nets [list EMIO_0_tri_o_32]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
|
||||
connect_debug_port u_ila_0/probe66 [get_nets [list EMIO_0_tri_t_0]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
|
||||
connect_debug_port u_ila_0/probe67 [get_nets [list EMIO_0_tri_t_1]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
|
||||
connect_debug_port u_ila_0/probe68 [get_nets [list EMIO_0_tri_t_2]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
|
||||
connect_debug_port u_ila_0/probe69 [get_nets [list EMIO_0_tri_t_3]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
|
||||
connect_debug_port u_ila_0/probe70 [get_nets [list EMIO_0_tri_t_4]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe71]
|
||||
connect_debug_port u_ila_0/probe71 [get_nets [list EMIO_0_tri_t_5]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe72]
|
||||
connect_debug_port u_ila_0/probe72 [get_nets [list EMIO_0_tri_t_6]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe73]
|
||||
connect_debug_port u_ila_0/probe73 [get_nets [list EMIO_0_tri_t_7]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe74]
|
||||
connect_debug_port u_ila_0/probe74 [get_nets [list EMIO_0_tri_t_8]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe75]
|
||||
connect_debug_port u_ila_0/probe75 [get_nets [list EMIO_0_tri_t_9]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe76]
|
||||
connect_debug_port u_ila_0/probe76 [get_nets [list EMIO_0_tri_t_10]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets u_ila_0_FCLK_CLK0]
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.674141",
|
||||
"Default View_TopLeft":"-50,-455",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port DDR -pg 1 -lvl 4 -x 1180 -y -90 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 4 -x 1180 -y -60 -defaultsOSRD
|
||||
preplace port EMIO_0 -pg 1 -lvl 4 -x 1180 -y -120 -defaultsOSRD
|
||||
preplace inst processing_system7_0 -pg 1 -lvl 2 -x 500 -y -40 -defaultsOSRD
|
||||
preplace inst dna_port_read_0 -pg 1 -lvl 1 -x 120 -y 120 -defaultsOSRD
|
||||
preplace inst mydna_read_v1_0_0 -pg 1 -lvl 1 -x 120 -y -230 -defaultsOSRD
|
||||
preplace inst ps7_0_axi_periph -pg 1 -lvl 3 -x 1010 -y 80 -defaultsOSRD
|
||||
preplace inst rst_ps7_0_100M -pg 1 -lvl 2 -x 500 -y -240 -defaultsOSRD
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 -20 20 300 80 830
|
||||
preplace netloc processing_system7_0_FCLK_RESET0_N 1 1 2 310 70 690
|
||||
preplace netloc rst_ps7_0_100M_interconnect_aresetn 1 2 1 870 -220n
|
||||
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 3 -30 200 260 190 840
|
||||
preplace netloc dna_port_read_0_dna_port 1 0 2 -20 -330 270
|
||||
preplace netloc mydna_read_v1_0_0_start_vld 1 0 2 -10 10 260
|
||||
preplace netloc dna_port_read_0_read_vld 1 0 2 -10 0 250
|
||||
preplace netloc processing_system7_0_DDR 1 2 2 860J -90 NJ
|
||||
preplace netloc ps7_0_axi_periph_M00_AXI 1 0 4 -40 40 280J 200 NJ 200 1150
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 2 2 NJ -50 1150J
|
||||
preplace netloc processing_system7_0_M_AXI_GP0 1 2 1 850J -30n
|
||||
preplace netloc processing_system7_0_GPIO_0 1 2 2 850J -120 NJ
|
||||
levelinfo -pg 1 -90 120 500 1010 1180
|
||||
pagesize -pg 1 -db -bbox -sgen -90 -340 1290 210
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_axi4_cnt":"2",
|
||||
"da_clkrst_cnt":"2",
|
||||
"da_ps7_cnt":"1"
|
||||
}
|
||||
@@ -0,0 +1,99 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2023/01/29 15:52:48
|
||||
// Design Name:
|
||||
// Module Name: dna_port_read
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module dna_port_read(
|
||||
input clk,
|
||||
input rst_n,
|
||||
input start_vld,
|
||||
output read_vld,
|
||||
output[56:0] dna_port
|
||||
);
|
||||
|
||||
localparam CNT0 = 90;
|
||||
|
||||
wire read_vld;
|
||||
reg[56:0] dna_port;
|
||||
|
||||
reg[7:0] cnt0;
|
||||
wire add_cnt0;
|
||||
wire end_cnt0;
|
||||
reg start_flag;
|
||||
|
||||
wire dna_out;
|
||||
wire dna_read;
|
||||
wire dna_shift;
|
||||
|
||||
DNA_PORT #(
|
||||
.SIM_DNA_VALUE(57'h000000000000000) // Specifies a sample 57-bit DNA value for simulation
|
||||
)
|
||||
DNA_PORT_inst (
|
||||
.DOUT(dna_out), // 1-bit output: DNA output data.
|
||||
.CLK(clk), // 1-bit input: Clock input.
|
||||
.DIN(1'b0), // 1-bit input: User data input pin.
|
||||
.READ(dna_read), // 1-bit input: Active high load DNA, active low read input.
|
||||
.SHIFT(dna_shift) // 1-bit input: Active high shift enable input.
|
||||
);
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n == 1'b0)begin
|
||||
start_flag <= 0;
|
||||
end
|
||||
else if(start_vld == 1'b1)begin
|
||||
start_flag <= 1;
|
||||
end
|
||||
else if(end_cnt0)begin
|
||||
start_flag <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n == 1'b0)begin
|
||||
cnt0 <= 8'd0;
|
||||
end
|
||||
else if(add_cnt0)begin
|
||||
if(end_cnt0)begin
|
||||
cnt0 <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
cnt0 <= cnt0 + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign add_cnt0 = start_flag;
|
||||
assign end_cnt0 = add_cnt0 && cnt0 == CNT0 -1;
|
||||
|
||||
assign dna_read = (cnt0 > 8'd0 && cnt0 <= 8'd9) ? 1'b1 : 1'b0;
|
||||
assign dna_shift = (cnt0 > 8'd9 && cnt0 <= 8'd66) ? 1'b1 : 1'b0;
|
||||
|
||||
assign read_vld = (cnt0 > 8'd85 && cnt0 <= 8'd89) ? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n == 1'b0)begin
|
||||
dna_port <= 57'd0;
|
||||
end
|
||||
else if(dna_shift)begin
|
||||
dna_port <= {dna_port[55:0],dna_out};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,84 @@
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module mydna_read_v1_0 #
|
||||
(
|
||||
// Users to add parameters here
|
||||
|
||||
// User parameters ends
|
||||
// Do not modify the parameters beyond this line
|
||||
|
||||
|
||||
// Parameters of Axi Slave Bus Interface S00_AXI
|
||||
parameter integer C_S00_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_S00_AXI_ADDR_WIDTH = 4
|
||||
)
|
||||
(
|
||||
// Users to add ports here
|
||||
output wire start_vld,
|
||||
input wire read_vld,
|
||||
input wire[56:0] dna_port,
|
||||
// User ports ends
|
||||
// Do not modify the ports beyond this line
|
||||
|
||||
|
||||
// Ports of Axi Slave Bus Interface S00_AXI
|
||||
input wire s00_axi_aclk,
|
||||
input wire s00_axi_aresetn,
|
||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
|
||||
input wire [2 : 0] s00_axi_awprot,
|
||||
input wire s00_axi_awvalid,
|
||||
output wire s00_axi_awready,
|
||||
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
|
||||
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
|
||||
input wire s00_axi_wvalid,
|
||||
output wire s00_axi_wready,
|
||||
output wire [1 : 0] s00_axi_bresp,
|
||||
output wire s00_axi_bvalid,
|
||||
input wire s00_axi_bready,
|
||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
|
||||
input wire [2 : 0] s00_axi_arprot,
|
||||
input wire s00_axi_arvalid,
|
||||
output wire s00_axi_arready,
|
||||
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
|
||||
output wire [1 : 0] s00_axi_rresp,
|
||||
output wire s00_axi_rvalid,
|
||||
input wire s00_axi_rready
|
||||
);
|
||||
// Instantiation of Axi Bus Interface S00_AXI
|
||||
mydna_read_v1_0_S00_AXI # (
|
||||
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
|
||||
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
|
||||
) mydna_read_v1_0_S00_AXI_inst (
|
||||
|
||||
.start_vld(start_vld),
|
||||
.read_vld(read_vld),
|
||||
.dna_port(dna_port),
|
||||
.S_AXI_ACLK(s00_axi_aclk),
|
||||
.S_AXI_ARESETN(s00_axi_aresetn),
|
||||
.S_AXI_AWADDR(s00_axi_awaddr),
|
||||
.S_AXI_AWPROT(s00_axi_awprot),
|
||||
.S_AXI_AWVALID(s00_axi_awvalid),
|
||||
.S_AXI_AWREADY(s00_axi_awready),
|
||||
.S_AXI_WDATA(s00_axi_wdata),
|
||||
.S_AXI_WSTRB(s00_axi_wstrb),
|
||||
.S_AXI_WVALID(s00_axi_wvalid),
|
||||
.S_AXI_WREADY(s00_axi_wready),
|
||||
.S_AXI_BRESP(s00_axi_bresp),
|
||||
.S_AXI_BVALID(s00_axi_bvalid),
|
||||
.S_AXI_BREADY(s00_axi_bready),
|
||||
.S_AXI_ARADDR(s00_axi_araddr),
|
||||
.S_AXI_ARPROT(s00_axi_arprot),
|
||||
.S_AXI_ARVALID(s00_axi_arvalid),
|
||||
.S_AXI_ARREADY(s00_axi_arready),
|
||||
.S_AXI_RDATA(s00_axi_rdata),
|
||||
.S_AXI_RRESP(s00_axi_rresp),
|
||||
.S_AXI_RVALID(s00_axi_rvalid),
|
||||
.S_AXI_RREADY(s00_axi_rready)
|
||||
);
|
||||
|
||||
// Add user logic here
|
||||
|
||||
// User logic ends
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,421 @@
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module mydna_read_v1_0_S00_AXI #
|
||||
(
|
||||
// Users to add parameters here
|
||||
|
||||
// User parameters ends
|
||||
// Do not modify the parameters beyond this line
|
||||
|
||||
// Width of S_AXI data bus
|
||||
parameter integer C_S_AXI_DATA_WIDTH = 32,
|
||||
// Width of S_AXI address bus
|
||||
parameter integer C_S_AXI_ADDR_WIDTH = 4
|
||||
)
|
||||
(
|
||||
// Users to add ports here
|
||||
output wire start_vld,
|
||||
input wire read_vld,
|
||||
input wire[56:0] dna_port,
|
||||
// User ports ends
|
||||
// Do not modify the ports beyond this line
|
||||
|
||||
// Global Clock Signal
|
||||
input wire S_AXI_ACLK,
|
||||
// Global Reset Signal. This Signal is Active LOW
|
||||
input wire S_AXI_ARESETN,
|
||||
// Write address (issued by master, acceped by Slave)
|
||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
|
||||
// Write channel Protection type. This signal indicates the
|
||||
// privilege and security level of the transaction, and whether
|
||||
// the transaction is a data access or an instruction access.
|
||||
input wire [2 : 0] S_AXI_AWPROT,
|
||||
// Write address valid. This signal indicates that the master signaling
|
||||
// valid write address and control information.
|
||||
input wire S_AXI_AWVALID,
|
||||
// Write address ready. This signal indicates that the slave is ready
|
||||
// to accept an address and associated control signals.
|
||||
output wire S_AXI_AWREADY,
|
||||
// Write data (issued by master, acceped by Slave)
|
||||
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
|
||||
// Write strobes. This signal indicates which byte lanes hold
|
||||
// valid data. There is one write strobe bit for each eight
|
||||
// bits of the write data bus.
|
||||
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
|
||||
// Write valid. This signal indicates that valid write
|
||||
// data and strobes are available.
|
||||
input wire S_AXI_WVALID,
|
||||
// Write ready. This signal indicates that the slave
|
||||
// can accept the write data.
|
||||
output wire S_AXI_WREADY,
|
||||
// Write response. This signal indicates the status
|
||||
// of the write transaction.
|
||||
output wire [1 : 0] S_AXI_BRESP,
|
||||
// Write response valid. This signal indicates that the channel
|
||||
// is signaling a valid write response.
|
||||
output wire S_AXI_BVALID,
|
||||
// Response ready. This signal indicates that the master
|
||||
// can accept a write response.
|
||||
input wire S_AXI_BREADY,
|
||||
// Read address (issued by master, acceped by Slave)
|
||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
|
||||
// Protection type. This signal indicates the privilege
|
||||
// and security level of the transaction, and whether the
|
||||
// transaction is a data access or an instruction access.
|
||||
input wire [2 : 0] S_AXI_ARPROT,
|
||||
// Read address valid. This signal indicates that the channel
|
||||
// is signaling valid read address and control information.
|
||||
input wire S_AXI_ARVALID,
|
||||
// Read address ready. This signal indicates that the slave is
|
||||
// ready to accept an address and associated control signals.
|
||||
output wire S_AXI_ARREADY,
|
||||
// Read data (issued by slave)
|
||||
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
|
||||
// Read response. This signal indicates the status of the
|
||||
// read transfer.
|
||||
output wire [1 : 0] S_AXI_RRESP,
|
||||
// Read valid. This signal indicates that the channel is
|
||||
// signaling the required read data.
|
||||
output wire S_AXI_RVALID,
|
||||
// Read ready. This signal indicates that the master can
|
||||
// accept the read data and response information.
|
||||
input wire S_AXI_RREADY
|
||||
);
|
||||
|
||||
reg[56:0] dna_port_reg;
|
||||
|
||||
// AXI4LITE signals
|
||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
|
||||
reg axi_awready;
|
||||
reg axi_wready;
|
||||
reg [1 : 0] axi_bresp;
|
||||
reg axi_bvalid;
|
||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
|
||||
reg axi_arready;
|
||||
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
|
||||
reg [1 : 0] axi_rresp;
|
||||
reg axi_rvalid;
|
||||
|
||||
// Example-specific design signals
|
||||
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
// ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
// ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
// ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
|
||||
localparam integer OPT_MEM_ADDR_BITS = 1;
|
||||
//----------------------------------------------
|
||||
//-- Signals for user logic register space example
|
||||
//------------------------------------------------
|
||||
//-- Number of Slave Registers 4
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
|
||||
wire slv_reg_rden;
|
||||
wire slv_reg_wren;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
|
||||
integer byte_index;
|
||||
reg aw_en;
|
||||
|
||||
// I/O Connections assignments
|
||||
|
||||
assign S_AXI_AWREADY = axi_awready;
|
||||
assign S_AXI_WREADY = axi_wready;
|
||||
assign S_AXI_BRESP = axi_bresp;
|
||||
assign S_AXI_BVALID = axi_bvalid;
|
||||
assign S_AXI_ARREADY = axi_arready;
|
||||
assign S_AXI_RDATA = axi_rdata;
|
||||
assign S_AXI_RRESP = axi_rresp;
|
||||
assign S_AXI_RVALID = axi_rvalid;
|
||||
// Implement axi_awready generation
|
||||
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
// de-asserted when reset is low.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_awready <= 1'b0;
|
||||
aw_en <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
||||
begin
|
||||
// slave is ready to accept write address when
|
||||
// there is a valid write address and write data
|
||||
// on the write address and data bus. This design
|
||||
// expects no outstanding transactions.
|
||||
axi_awready <= 1'b1;
|
||||
aw_en <= 1'b0;
|
||||
end
|
||||
else if (S_AXI_BREADY && axi_bvalid)
|
||||
begin
|
||||
aw_en <= 1'b1;
|
||||
axi_awready <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
axi_awready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_awaddr latching
|
||||
// This process is used to latch the address when both
|
||||
// S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_awaddr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
||||
begin
|
||||
// Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_wready generation
|
||||
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
// de-asserted when reset is low.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_wready <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
|
||||
begin
|
||||
// slave is ready to accept write data when
|
||||
// there is a valid write address and write data
|
||||
// on the write address and data bus. This design
|
||||
// expects no outstanding transactions.
|
||||
axi_wready <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
axi_wready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement memory mapped register select and write logic generation
|
||||
// The write data is accepted and written to memory mapped registers when
|
||||
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
// select byte enables of slave registers while writing.
|
||||
// These registers are cleared when reset (active low) is applied.
|
||||
// Slave register write enable is asserted when valid address and data are available
|
||||
// and the slave is ready to accept the write address and write data.
|
||||
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
slv_reg0 <= 0;
|
||||
slv_reg1 <= 0;
|
||||
slv_reg2 <= 0;
|
||||
slv_reg3 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (slv_reg_wren)
|
||||
begin
|
||||
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
||||
2'h0:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 0
|
||||
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
2'h1:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 1
|
||||
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
2'h2:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 2
|
||||
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
2'h3:
|
||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
||||
// Respective byte enables are asserted as per write strobes
|
||||
// Slave register 3
|
||||
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
||||
end
|
||||
default : begin
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
slv_reg0 <= 32'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement write response logic generation
|
||||
// The write response and response valid signals are asserted by the slave
|
||||
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
// This marks the acceptance of address and indicates the status of
|
||||
// write transaction.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_bvalid <= 0;
|
||||
axi_bresp <= 2'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
|
||||
begin
|
||||
// indicates a valid write response is available
|
||||
axi_bvalid <= 1'b1;
|
||||
axi_bresp <= 2'b0; // 'OKAY' response
|
||||
end // work error responses in future
|
||||
else
|
||||
begin
|
||||
if (S_AXI_BREADY && axi_bvalid)
|
||||
//check if bready is asserted while bvalid is high)
|
||||
//(there is a possibility that bready is always asserted high)
|
||||
begin
|
||||
axi_bvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_arready generation
|
||||
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
// S_AXI_ARVALID is asserted. axi_awready is
|
||||
// de-asserted when reset (active low) is asserted.
|
||||
// The read address is also latched when S_AXI_ARVALID is
|
||||
// asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_arready <= 1'b0;
|
||||
axi_araddr <= 32'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (~axi_arready && S_AXI_ARVALID)
|
||||
begin
|
||||
// indicates that the slave has acceped the valid read address
|
||||
axi_arready <= 1'b1;
|
||||
// Read address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
axi_arready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement axi_arvalid generation
|
||||
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
// data are available on the axi_rdata bus at this instance. The
|
||||
// assertion of axi_rvalid marks the validity of read data on the
|
||||
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
// is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
// cleared to zero on reset (active low).
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_rvalid <= 0;
|
||||
axi_rresp <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
|
||||
begin
|
||||
// Valid read data is available at the read data bus
|
||||
axi_rvalid <= 1'b1;
|
||||
axi_rresp <= 2'b0; // 'OKAY' response
|
||||
end
|
||||
else if (axi_rvalid && S_AXI_RREADY)
|
||||
begin
|
||||
// Read data is accepted by the master
|
||||
axi_rvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Implement memory mapped register select and read logic generation
|
||||
// Slave register read enable is asserted when valid address is available
|
||||
// and the slave is ready to accept the read address.
|
||||
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
|
||||
always @(*)
|
||||
begin
|
||||
// Address decoding for reading registers
|
||||
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
||||
2'h0 : reg_data_out <= slv_reg0;
|
||||
2'h1 : reg_data_out <= {7'd0,dna_port_reg[56:32]};
|
||||
2'h2 : reg_data_out <= dna_port_reg[31:0];
|
||||
2'h3 : reg_data_out <= slv_reg3;
|
||||
default : reg_data_out <= 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Output register or memory read data
|
||||
always @( posedge S_AXI_ACLK )
|
||||
begin
|
||||
if ( S_AXI_ARESETN == 1'b0 )
|
||||
begin
|
||||
axi_rdata <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// When there is a valid read address (S_AXI_ARVALID) with
|
||||
// acceptance of read address by the slave (axi_arready),
|
||||
// output the read dada
|
||||
if (slv_reg_rden)
|
||||
begin
|
||||
axi_rdata <= reg_data_out; // register read data
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Add user logic here
|
||||
assign start_vld = slv_reg0[0];
|
||||
|
||||
//dna_port_logic
|
||||
always @( * )begin
|
||||
if(read_vld == 1'b1)begin
|
||||
dna_port_reg <= dna_port;
|
||||
end
|
||||
else begin
|
||||
dna_port_reg <= dna_port_reg;
|
||||
end
|
||||
end
|
||||
// User logic ends
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user