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Add Zynq project files

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This commit is contained in:
Jeremy Shen
2026-05-25 18:12:01 +08:00
parent e61e9d48ad
commit 74cd2ae192
2326 changed files with 850853 additions and 23 deletions
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2.FW/Zynq/proj_cal/Vitis/FSBL/.cproject
+180
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@@ -0,0 +1,180 @@
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2.FW/Zynq/proj_cal/Vitis/FSBL/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>FSBL</name>
<comment>Created by SDK v2018.3. FSBL_bsp - ps7_cortexa9_0</comment>
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<project>FSBL_bsp</project>
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2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/FSBL.elf.size
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text data bss dec hex filename
81496 10160 74712 166368 289e0 FSBL.elf
2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/Xilinx.spec
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*startfile:
crti%O%s crtbegin%O%s
2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/makefile
+65
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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include src/subdir.mk
-include subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
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endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
ELFSIZE += \
FSBL.elf.size \
# All Target
all: pre-build main-build
# Main-build Target
main-build: FSBL.elf secondary-outputs
# Tool invocations
FSBL.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: ARM v7 gcc linker'
arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../FSBL_bsp/ps7_cortexa9_0/lib -o "FSBL.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo 'Finished building target: $@'
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FSBL.elf.size: FSBL.elf
@echo 'Invoking: ARM v7 Print Size'
arm-none-eabi-size FSBL.elf |tee "FSBL.elf.size"
@echo 'Finished building: $@'
@echo ' '
# Other Targets
clean:
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-@echo ' '
pre-build:
-a9-linaro-pre-build-step
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2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/objects.mk
+8
View File
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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS := -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group
2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/sources.mk
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@@ -0,0 +1,20 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
LD_SRCS :=
OBJ_SRCS :=
S_SRCS :=
C_SRCS :=
S_UPPER_SRCS :=
O_SRCS :=
EXECUTABLES :=
OBJS :=
S_UPPER_DEPS :=
C_DEPS :=
ELFSIZE :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
2.FW/Zynq/proj_cal/Vitis/FSBL/Debug/src/subdir.mk
+78
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@@ -0,0 +1,78 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
LD_SRCS += \
../src/lscript.ld
C_SRCS += \
../src/fsbl_hooks.c \
../src/image_mover.c \
../src/main.c \
../src/md5.c \
../src/nand.c \
../src/nor.c \
../src/pcap.c \
E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c \
../src/qspi.c \
../src/rsa.c \
../src/sd.c
S_UPPER_SRCS += \
../src/fsbl_handoff.S
OBJS += \
./src/fsbl_handoff.o \
./src/fsbl_hooks.o \
./src/image_mover.o \
./src/main.o \
./src/md5.o \
./src/nand.o \
./src/nor.o \
./src/pcap.o \
./src/ps7_init.o \
./src/qspi.o \
./src/rsa.o \
./src/sd.o
S_UPPER_DEPS += \
./src/fsbl_handoff.d
C_DEPS += \
./src/fsbl_hooks.d \
./src/image_mover.d \
./src/main.d \
./src/md5.d \
./src/nand.d \
./src/nor.d \
./src/pcap.d \
./src/ps7_init.d \
./src/qspi.d \
./src/rsa.d \
./src/sd.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.S
@echo 'Building file: $<'
@echo 'Invoking: ARM v7 gcc compiler'
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
src/%.o: ../src/%.c
@echo 'Building file: $<'
@echo 'Invoking: ARM v7 gcc compiler'
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
src/ps7_init.o: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c
@echo 'Building file: $<'
@echo 'Invoking: ARM v7 gcc compiler'
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
2.FW/Zynq/proj_cal/Vitis/FSBL/src/Xilinx.spec
+2
View File
@@ -0,0 +1,2 @@
*startfile:
crti%O%s crtbegin%O%s
2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl.h
+559
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@@ -0,0 +1,559 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file fsbl.h
*
* Contains the function prototypes, defines and macros for the
* First Stage Boot Loader (FSBL) functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 03/04/11 Initial release
* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
* xparameters.h file
* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
* Added the debug levels
* 4.00a sgd 02/28/13 Removed DDR initialization check
* Removed DDR ECC initialization code
* Modified hand off address check to 1MB
* Added RSA authentication support
* Removed LPBK_DLY_ADJ register setting code as we use
* divisor 8
* Removed check for Fabric is already initialized
*
* CR's fixed and description
* 689026: FSBL doesn't hold PL resets active during
* bit download
* Resolution: PL resets are released just before
* handoff
*
* 689077: FSBL hangs at Handoff clearing the
* TX UART buffer
* Resolution: STDOUT_BASEADDRESS macro value changes
* based UART select, hence used STDOUT_BASEADDRESS
* as UART base address
*
* 695578: FSBL failed to load standalone application
* in secure bootmode
* Resolution: Application will be placed at load address
* instead of DDR temporary address
*
* 699475: FSBL functionality is broken and its
* not able to boot in QSPI/NAND bootmode
* Resolution: New flags are added DevCfg driver
* for handling loopback
* XDCFG_CONCURRENT_NONSEC_READ_WRITE
* XDCFG_CONCURRENT_SECURE_READ_WRITE
*
* 683145: Define stack area for FIQ, UNDEF modes
* in linker file
* Resolution: FSBL linker modified to create stack area
* for FIQ, UNDEF
*
* 705664: FSBL fails to decrypt the bitstream when
* the image is AES encrypted using non-zero key value
* Resolution: Fabric cleaning will not be done
* for AES-E-Fuse encryption
*
* Watchdog disabled for AES E-Fuse encryption
*
* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
* Added QSPI Flash Size > 128Mbit support
* QSPI Dual Stack support
* Added Md5 checksum support
*
* CR's fixed and description
* 692045 FSBL: Linker script of FSBL has PHDR workaround,
* this needs to be fixed
* Resolution: Removed PHDR from Linker file
*
* 704287 FSBL: fsbl.h file has a few error codes that
* are not used by FSBL, that needs to be removed
* Resolution: Removed unused error codes
*
* 704379 FSBL: Check if DDR is in proper state before
* handoff
* Resolution: Added DDR initialization check
*
* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
* the debug level is FSBL_DEBUG only.
*
* 710128 FSBL: Linux boot failing without load attribute
* set for Linux partitions in BIF
* Resolution: FSBL will load partitions with valid load
* address and stop loading if any invalid load address
*
* 708728 Issues seen while making HP interconnect
* 32 bit wide
* Resolution: ps7_post_config function generated by PCW
* will be called after Bit stream download
* Added MMC support
* 6.00a kc 07/31/2013 CR's fixed and description
* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
* for authenticating the Partition images
* Resolution: FSBL now uses the PPK left by Boot ROM in
* OCM for authencating the SPK
*
* 724165 Partition Header used by FSBL is not
* authenticated
* Resolution: FSBL now authenticates the partition header
*
* 691150 ps7_init does not check for peripheral
* initialization failures or timeout on polls
* Resolution: Return value of ps7_init() is now checked
* by FSBL and prints the error string
*
* 708316 PS7_init.tcl file should have Error mechanism
* for all mask_poll
* Resolution: Return value of ps7_init() is now checked
* by FSBL and prints the error string
*
* 732062 FSBL fails to build if UART not available
* Resolution: Added define to call xil_printf only
* if uart is defined
*
* 722979 Provide customer-friendly changelogs in FSBL
* Resolution: Added CR description for all the files
*
* 732865 Backward compatibility for ps7_init function
* Resolution: Added a new define for ps7_init success
* and value is defined based on ps7_init define
*
* Fix for CR#739711 - FSBL not able to read Large
* QSPI (512M) in IO Mode
* Resolution: Modified the address calculation
* algorithm in dual parallel mode for QSPI
*
* 7.00a kc 10/18/13 Integrated SD/MMC driver
* 10/23/13 Support for armcc compiler added
* 741003 FSBL has to check the HMAC error status after
* decryption
* Resolution: Added code for checking the error status
* after PCAP completion
* 739968 FSBL should do the QSPI config settings for
* Dual parallel configuration in IO mode
* Resolution: Added QSPI config settings in qspi.c
* 724620 FSBL: How to handle PCAP_MODE after bitstream
* configuration.
* Resolution: PCAP_MODE and PCAP_PR bits are now cleared
* after PCAP transfer completion
* 726178 In the 14.6 FSBL function FabricInit() PROG_B
* is kept active for 5mS.
* Resolution: PROG_B is now kept active for 5mS only incase
* if efuse is the aes key source.
* 755245 FSBL does not load partition if eMMC has only
* one partition
* Resolution: Changed the if condition for MMC
* 12/04/13 764382 FSBL: How to handle PCAP_MODE after bitstream
* configuration
* Resolution: Reverted back the changes of 724620. PCAP_MODE
* and PCAP_PR bits are not changed
* 8.00a kc 01/16/13 767798 Fsbl MD5 Checksum failiure for encrypted images
* Resolution: For checksum enabled partitions, total
* total partition image length is copied now.
* 761895 FSBL should authenticate image only if
* partition owner was not set to u-boot
* Resolution: Partition owner check added in
* image_mover.c
* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
* Resolution: Function argument is updated from value
* to pointer to reflect updated value
* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
* unless FSBL* and FSBL are identical in length
* Resolution: PPK is set only once now.
* 785778 - FSBL takes 8 seconds to
* authenticate (RSA) a bitstream on zc706
* Resolution: Data Caches are enabled only for
* authentication.
* 791245 - Use of xilrsa in fsbl
* Resolution: Rsa library is removed from fsbl source
* and xilrsa is used from BSP
* 10.00a kc 07/15/14 804595 Zynq FSBL - Issues with
* fallback image offset handling using MD5
* Resolution: Updated the checksum offset to add with
* image base address
* 782309 Fallback support for AES
* encryption with E-Fuse - Enhancement
* Resolution: Same as 773866
* 809336 Minor code cleanup
* Resolution Minor code changes
* kc 08/27/14 820356 - FSBL compilation fails with IAR compiler
* Resolution: Change of __asm__ to __asm
* 11.00a kv 10/08/14 826030 - FSBL:LinearBootDeviceFlag is not initialized
* in IO mode case.Due to which the variable is
* remaining in unknown state.
* Resolution: LinearBootDeviceFlag is initialized 0
* in main.c
* 12.00a ssc 12/11/14 839182 - FSBL -In the file sd.c, f_mount is called with
* two arguments but f_mount is expecting the 3 arguments
* from build 2015.1_1210_1, causing compilation error.
* Resolution: Arguments for f_mount in InitSD() are
* changed as per new signature.
* 13.00a ssc 04/10/15 846899 - FSBL -In the file pcap.c, to clear DMA done
* count, devcfg.INT_STS register is written to, which is
* not correct.
* Resolution: Corresponding fields in the devcfg.STATUS
* register are written to, for clearing DMA done count.
* 14.00a gan 01/13/16 869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
* read command from LQSPI_CFG register instead of hard
* coded read command (0x6B).
* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
* Fabric Initialization sequence is modified to check
* the PL power before sequence starts and checking INIT_B
* reset status twice in case of failure.
* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
* In pcap.c, check pl power through MCTRL register
* for 3.0 and later versions of silicon.
* 17.00a bsv 27/03/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
* to enable level shifters in jtag boot mode.
* 18.00a ka 10/29/18 Fix for CR# 1006294 Added macro for FORCE_USE_AES_EXCLUDE
*
* </pre>
*
* </pre>
*
* @note
*
* Flags in FSBL
*
* FSBL_PERF
*
* This Flag can be set at compilation time. This flag is set for
* measuring the performance of FSBL.That is the time taken to execute is
* measured.when this flag is set.Execution time with reference to
* global timer is taken here
*
* Total Execution time is the time taken for executing FSBL till handoff
* to any application .
* If there is a bitstream in the partition header then the
* execution time includes the copying of the bitstream to DDR
* (in case of SD/NAND bootmode)
* and programming the devcfg dma is accounted.
*
* FSBL provides two debug levels
* DEBUG GENERAL - fsbl_printf under this category will appear only when the
* FSBL_DEBUG flag is set during compilation
* DEBUG_INFO - fsbl_printf under this category will appear when the
* FSBL_DEBUG_INFO flag is set during compilation
* For a more detailed output log can be used.
* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
* RSA functions
* These macros are input to the fsbl_printf function
*
* DEBUG LEVELS
* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
* that are with the DEBUG_GENERAL argument are shown
* FSBL_DEBUG_INFO is level 2, when this flag is set during the
* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
*
* DEFAULT LEVEL
* By default no print messages will appear.
*
* NON_PS_INSTANTIATED_BITSTREAM
*
* FSBL will not enable the level shifters for a NON PS instantiated
* Bitstream.This flag can be set during compilation for a NON PS instantiated
* bitstream
*
* ECC_ENABLE
* This flag will be defined in the ps7_init.h file when ECC is enabled
* in the DDR configuration (XPS GUI)
*
* RSA_SUPPORT
* This flag is used to enable authentication feature
* Default this macro disabled, reason to avoid increase in code size
*
* MMC_SUPPORT
* This flag is used to enable MMC support feature
*
* JTAG_ENABLE_LEVEL_SHIFTERS
* FSBL will not enable the level shifters for jtag boot mode. This flag can be
* set during compilation for jtag boot mode to enable level shifters.
*
* FORCE_USE_AES_EXCLUDE
* Defining this flag will exclude the feature, forcing every partition to be
* encrypted when EFUSE_SEC_EN bit is set.
* This flag can be set/unset during compilation.
* By deafult this flag is unset/undefined which enables the above feature
* Note : Changing the default behaviour is not recommended from
* Security perspective.
*
*******************************************************************************/
#ifndef XIL_FSBL_H
#define XIL_FSBL_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xparameters.h"
#include "xpseudo_asm.h"
#include "xil_printf.h"
#include "pcap.h"
#include "fsbl_debug.h"
#include "ps7_init.h"
#ifdef FSBL_PERF
#include "xtime_l.h"
#include <stdio.h>
#endif
/************************** Constant Definitions *****************************/
/*
* SDK release version
*/
#define SDK_RELEASE_YEAR 2018
#define SDK_RELEASE_QUARTER 3
#define WORD_LENGTH_SHIFT 2
/*
* On a Successful handoff to an application FSBL sets this SUCCESS code
*/
#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
/*
* Backward compatibility for ps7_init
*/
#ifdef NEW_PS7_ERR_CODE
#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
#else
#define FSBL_PS7_INIT_SUCCESS (1)
#endif
/*
* ERROR CODES
* The following are the Error codes that FSBL uses
* If the Debug prints are enabled only then the error codes will be
* seen on the com port.Without the debug prints enabled no error codes will
* be visible.There are not saved in any register
* Boot Mode States used for error and status output
* Error codes are defined below
*/
#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
#define NO_DDR 0xA008 /**< DDR missing */
#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
#define PARTITION_LOAD_FAIL 0xA013 /**< Partition load fail*/
/*
* FSBL Exception error codes
*/
#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
/*
* FSBL hook routine failures
*/
#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
download hook failed */
#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
download hook failed */
/*
* Watchdog related Error codes
*/
#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
/*
* SLCR Registers
*/
#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
/*
* Efuse Status Register
*/
#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
/*
* PS reset control register define
*/
#define PS_RST_MASK 0x1 /**< PS software reset */
/*
* SLCR BOOT Mode Register defines
*/
#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
/*
* Boot Modes
*/
#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
#define SD_MODE 0x00000005 /**< SD Boot Mode */
#define MMC_MODE 0x00000006 /**< MMC Boot Device */
#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
/*
* Golden image offset
*/
#define GOLDEN_IMAGE_OFFSET 0x8000
/*
* Silicon Version
*/
#define SILICON_VERSION_1 0
#define SILICON_VERSION_2 1
#define SILICON_VERSION_3 2
#define SILICON_VERSION_3_1 3
/*
* DDR start address for storing the data temporarily(1M)
* Need to finalize correct logic
*/
#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
#else
/*
* In case of PL DDR, this macros defined based PL DDR address
*/
#define DDR_START_ADDR 0x00
#define DDR_END_ADDR 0x00
#endif
#define DDR_TEMP_START_ADDR DDR_START_ADDR
/*
* DDR test pattern
*/
#define DDR_TEST_PATTERN 0xAA55AA55
#define DDR_TEST_OFFSET 0x100000
/*
*
*/
#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
#define LQSPI_CFG_OFFSET 0xA0
#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
/*
* These are the SLCR lock and unlock macros
*/
#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
#define IMAGE_HEADER_CHECKSUM_COUNT 10
/* Boot ROM Image defines */
#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
/* Reboot status register defines:
* 0xF0000000 for FSBL fallback mask to notify Boot Rom
* 0x60000000 for FSBL to mark that FSBL has not handoff yet
* 0x00FFFFFF for user application to use across soft reset
*/
#define FSBL_FAIL_MASK 0xF0000000
#define FSBL_IN_MASK 0x60000000
/* The address that holds the base address for the image Boot ROM found */
#define BASEADDR_HOLDER 0xFFFFFFF8
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
void OutputStatus(u32 State);
void FsblFallback(void);
int FsblSetNextPartition(int Num);
void *(memcpy_rom)(void * s1, const void * s2, u32 n);
char *strcpy_rom(char *Dest, const char *Src);
void ClearFSBLIn(void);
void MarkFSBLIn(void);
void FsblHandoff(u32 FsblStartAddr);
u32 GetResetReason(void);
#ifdef FSBL_PERF
void FsblGetGlobalTime (XTime * tCur);
void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
#endif
void GetSiliconVersion(void);
void FsblHandoffExit(u32 FsblStartAddr);
void FsblHandoffJtagExit();
/************************** Variable Definitions *****************************/
extern int SkipPartition;
/***************** Macros (Inline Functions) Definitions *********************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_debug.h
+78
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@@ -0,0 +1,78 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file fsbl_debug.h
*
* This file contains the debug verbose information for FSBL print functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 3.00a mb 01/09/12 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef _FSBL_DEBUG_H
#define _FSBL_DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
#define DEBUG_GENERAL 0x00000001 /* general debug messages */
#define DEBUG_INFO 0x00000002 /* More debug information */
#if defined (FSBL_DEBUG_INFO)
#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
#elif defined (FSBL_DEBUG)
#define fsbl_dbg_current_types (DEBUG_GENERAL)
#else
#define fsbl_dbg_current_types 0
#endif
#ifdef STDOUT_BASEADDRESS
#define fsbl_printf(type,...) \
if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
#else
#define fsbl_printf(type, ...)
#endif
#ifdef __cplusplus
}
#endif
#endif /* _FSBL_DEBUG_H */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_handoff.S
+217
View File
@@ -0,0 +1,217 @@
#ifdef __GNUC__
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file handoff.S
*
* Contains the code that does the handoff to the loaded application. This
* code lives high in the ROM.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date.word Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 03/01/10 Initial release
* 7.00a kc 10/23/13 Added support for armcc compiler
* </pre>
*
* @note
* Assumes that the starting address of the FSBL is provided by the calling routine
* in R0.
*
******************************************************************************/
.globl FsblHandoffJtagExit
.globl FsblHandoffExit
.section .handoff,"axS"
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
FsblHandoffJtagExit:
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
dsb
isb /* make sure it completes */
ldr r4, =0
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
isb /* make sure it completes */
Loop:
wfe
b Loop
FsblHandoffExit:
mov lr, r0 /* move the destination address into link register */
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
dsb
isb /* make sure it completes */
ldr r4, =0
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
isb /* make sure it completes */
bx lr /* force the switch, destination should have been in r0 */
.Ldone: b .Ldone /* Paranoia: we should never get here */
.end
#elif defined (__IASMARM__)
PUBLIC FsblHandoffJtagExit
PUBLIC FsblHandoffExit
SECTION .handoff:CODE:NOROOT(2)
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
FsblHandoffJtagExit
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
Loop
wfe
b Loop
FsblHandoffExit
mov lr, r0 ;/* move the destination address into link register */
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
bx lr ;/* force the switch, destination should have been in r0 */
.Ldone
b .Ldone ;/* Paranoia: we should never get here */
END
#else
EXPORT FsblHandoffJtagExit
EXPORT FsblHandoffExit
AREA |.handoff|,CODE
;/***************************** Include Files *********************************/
;/************************** Constant Definitions *****************************/
;/**************************** Type Definitions *******************************/
;/***************** Macros (Inline Functions) Definitions *********************/
;/************************** Function Prototypes ******************************/
;/************************** Variable Definitions *****************************/
FsblHandoffJtagExit
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
Loop
wfe
b Loop
FsblHandoffExit
mov lr, r0 ;/* move the destination address into link register */
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
bx lr ;/* force the switch, destination should have been in r0 */
Ldone b Ldone ;/* Paranoia: we should never get here */
END
#endif
2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.c
+160
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@@ -0,0 +1,160 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************
*
* @file fsbl_hooks.c
*
* This file provides functions that serve as user hooks. The user can add the
* additional functionality required into these routines. This would help retain
* the normal FSBL flow unchanged.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 3.00a np 08/03/12 Initial release
* </pre>
*
* @note
*
******************************************************************************/
#include "fsbl.h"
#include "xstatus.h"
#include "fsbl_hooks.h"
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/******************************************************************************
* This function is the hook which will be called before the bitstream download.
* The user can add all the customized code required to be executed before the
* bitstream download to this routine.
*
* @param None
*
* @return
* - XST_SUCCESS to indicate success
* - XST_FAILURE.to indicate failure
*
****************************************************************************/
u32 FsblHookBeforeBitstreamDload(void)
{
u32 Status;
Status = XST_SUCCESS;
/*
* User logic to be added here. Errors to be stored in the status variable
* and returned
*/
fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
return (Status);
}
/******************************************************************************
* This function is the hook which will be called after the bitstream download.
* The user can add all the customized code required to be executed after the
* bitstream download to this routine.
*
* @param None
*
* @return
* - XST_SUCCESS to indicate success
* - XST_FAILURE.to indicate failure
*
****************************************************************************/
u32 FsblHookAfterBitstreamDload(void)
{
u32 Status;
Status = XST_SUCCESS;
/*
* User logic to be added here.
* Errors to be stored in the status variable and returned
*/
fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
return (Status);
}
/******************************************************************************
* This function is the hook which will be called before the FSBL does a handoff
* to the application. The user can add all the customized code required to be
* executed before the handoff to this routine.
*
* @param None
*
* @return
* - XST_SUCCESS to indicate success
* - XST_FAILURE.to indicate failure
*
****************************************************************************/
u32 FsblHookBeforeHandoff(void)
{
u32 Status;
Status = XST_SUCCESS;
/*
* User logic to be added here.
* Errors to be stored in the status variable and returned
*/
fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
return (Status);
}
/******************************************************************************
* This function is the hook which will be called in case FSBL fall back
*
* @param None
*
* @return None
*
****************************************************************************/
void FsblHookFallback(void)
{
/*
* User logic to be added here.
* Errors to be stored in the status variable and returned
*/
fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
while(1);
}
2.FW/Zynq/proj_cal/Vitis/FSBL/src/fsbl_hooks.h
+77
View File
@@ -0,0 +1,77 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file fsbl_hooks.h
*
* Contains the function prototypes, defines and macros required by fsbl_hooks.c
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 3.00a np/mb 10/08/12 Initial release
* Corrected the prototype
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef FSBL_HOOKS_H_
#define FSBL_HOOKS_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "fsbl.h"
/************************** Function Prototypes ******************************/
/* FSBL hook function which is called before bitstream download */
u32 FsblHookBeforeBitstreamDload(void);
/* FSBL hook function which is called after bitstream download */
u32 FsblHookAfterBitstreamDload(void);
/* FSBL hook function which is called before handoff to the application */
u32 FsblHookBeforeHandoff(void);
/* FSBL hook function which is called in FSBL fallback */
void FsblHookFallback(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.c
+1348
View File
File diff suppressed because it is too large Load Diff
2.FW/Zynq/proj_cal/Vitis/FSBL/src/image_mover.h
+157
View File
@@ -0,0 +1,157 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file image_mover.h
*
* This file contains the interface for moving the image from FLASH to OCM
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 03/04/11 Initial release
* 2.00a jz 06/04/11 partition header expands to 12 words
* 5.00a kc 07/30/13 Added defines for image header information
* 8.00a kc 01/16/13 Added defines for partition owner attribute
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___IMAGE_MOVER_H___
#define ___IMAGE_MOVER_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "fsbl.h"
/************************** Constant Definitions *****************************/
#define PARTITION_NUMBER_SHIFT 24
#define MAX_PARTITION_NUMBER (0xE)
/* Boot Image Header defines */
#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */
#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */
#define IMAGE_HEADER_SIZE (64)
#define IMAGE_HEADER_TABLE_SIZE (64)
#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \
TOTAL_IMAGE_HEADER_SIZE + \
TOTAL_PARTITION_HEADER_SIZE + 64)
/* Partition Header defines */
#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */
#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */
#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */
#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */
#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */
#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */
#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */
#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */
#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */
#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */
#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/
/* Attribute word defines */
#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */
#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */
#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */
#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */
#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */
#define ATTRIBUTE_PARTITION_OWNER_MASK 0x30000 /* Partition Owner */
#define ATTRIBUTE_PARTITION_OWNER_FSBL 0x00000 /* FSBL Partition Owner */
/**************************** Type Definitions *******************************/
typedef u32 (*ImageMoverType)( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthBytes);
typedef struct StructPartHeader {
u32 ImageWordLen; /* 0x0 */
u32 DataWordLen; /* 0x4 */
u32 PartitionWordLen; /* 0x8 */
u32 LoadAddr; /* 0xC */
u32 ExecAddr; /* 0x10 */
u32 PartitionStart; /* 0x14 */
u32 PartitionAttr; /* 0x18 */
u32 SectionCount; /* 0x1C */
u32 CheckSumOffset; /* 0x20 */
u32 Pads1[1];
u32 ACOffset; /* 0x28 */
u32 Pads2[4];
u32 CheckSum; /* 0x3C */
}PartHeader;
struct HeaderArray {
u32 Fields[16];
};
/***************** Macros (Inline Functions) Definitions *********************/
#define MoverIn32 Xil_In32
#define MoverOut32 Xil_Out32
/************************** Function Prototypes ******************************/
u32 LoadBootImage(void);
u32 GetPartitionHeaderInfo(u32 ImageBaseAddress);
u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header);
u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H);
u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset);
u32 GetImageHeaderAndSignature(u32 ImageAddress, u32 *Offset);
u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength);
u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header);
u32 IsEmptyHeader(struct HeaderArray *H);
u32 IsLastPartition(struct HeaderArray *H);
void HeaderDump(PartHeader *Header);
u32 GetPartitionCount(PartHeader *Header);
u32 ValidateHeader(PartHeader *Header);
u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___IMAGE_MOVER_H___ */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/lscript.ld
+309
View File
@@ -0,0 +1,309 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
SECTIONS
{
.text : {
*(.vectors)
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ram_0_S_AXI_BASEADDR
.init : {
KEEP (*(.init))
} > ps7_ram_0_S_AXI_BASEADDR
.fini : {
KEEP (*(.fini))
} > ps7_ram_0_S_AXI_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.got : {
*(.got)
} > ps7_ram_0_S_AXI_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ram_0_S_AXI_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ram_0_S_AXI_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > ps7_ram_0_S_AXI_BASEADDR
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ram_0_S_AXI_BASEADDR
.mmu_tbl (ALIGN(0x4000)): {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.rsa_ac : {
. = ALIGN(64);
__rsa_ac_start = .;
. += _RSA_AC_SIZE;
__rsa_ac_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.bss (NOLOAD) : {
__bss_start = .;
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
__bss_end__ = .;
} > ps7_ram_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ram_0_S_AXI_BASEADDR
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _STACK_SIZE;
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ram_1_S_AXI_BASEADDR
_end = .;
}
2.FW/Zynq/proj_cal/Vitis/FSBL/src/main.c
+1543
View File
File diff suppressed because it is too large Load Diff
2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.c
+484
View File
@@ -0,0 +1,484 @@
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
* All rights reserved.
*
* This package is an SSL implementation written
* by Eric Young (eay@cryptsoft.com).
* The implementation was written so as to conform with Netscapes SSL.
*
* This library is free for commercial and non-commercial use as long as
* the following conditions are aheared to. The following conditions
* apply to all code found in this distribution, be it the RC4, RSA,
* lhash, DES, etc., code; not just the SSL code. The SSL documentation
* included with this distribution is covered by the same copyright terms
* except that the holder is Tim Hudson (tjh@cryptsoft.com).
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed.
* If this package is used in a product, Eric Young should be given attribution
* as the author of the parts of the library used.
* This can be in the form of a textual message at program startup or
* in documentation (online or textual) provided with the package.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* "This product includes cryptographic software written by
* Eric Young (eay@cryptsoft.com)"
* The word 'cryptographic' can be left out if the rouines from the library
* being used are not cryptographic related :-).
* 4. If you include any Windows specific code (or a derivative thereof) from
* the apps directory (application code) you must include an acknowledgement:
* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
*
* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The licence and distribution terms for any publically available version or
* derivative of this code cannot be changed. i.e. this code cannot simply be
* copied and put under another distribution licence
* [including the GNU Public Licence.]
*/
/*****************************************************************************/
/**
*
* @file md5.c
*
* Contains code to calculate checksum using md5 algorithm
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00a sgd 05/17/13 Initial release
*
*
* </pre>
*
* @note
*
******************************************************************************/
/****************************** Include Files *********************************/
#include "md5.h"
/******************************************************************************/
/**
*
* This function sets the memory
*
* @param dest
*
* @param ch
*
* @param count
*
* @return None
*
* @note None
*
****************************************************************************/
inline void * MD5Memset( void *dest, int ch, u32 count )
{
register char *dst8 = (char*)dest;
while( count-- )
*dst8++ = ch;
return dest;
}
/******************************************************************************/
/**
*
* This function copy the memory
*
* @param dest
*
* @param ch
*
* @param count
*
* @return None
*
* @note None
*
****************************************************************************/
inline void * MD5Memcpy( void *dest, const void *src,
u32 count, boolean doByteSwap )
{
register char * dst8 = (char*)dest;
register char * src8 = (char*)src;
if( doByteSwap == FALSE ) {
while( count-- )
*dst8++ = *src8++;
} else {
count /= sizeof( u32 );
while( count-- ) {
dst8[ 0 ] = src8[ 3 ];
dst8[ 1 ] = src8[ 2 ];
dst8[ 2 ] = src8[ 1 ];
dst8[ 3 ] = src8[ 0 ];
dst8 += 4;
src8 += 4;
}
}
return dest;
}
/******************************************************************************/
/**
*
* This function is the core of the MD5 algorithm,
* this alters an existing MD5 hash to
* reflect the addition of 16 longwords of new data. MD5Update blocks
* the data and converts bytes into longwords for this routine.
*
* Use binary integer part of the sine of integers (Radians) as constants.
* Calculated as:
*
* for( i = 0; i < 63; i++ )
* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
*
* Following number is the per-round shift amount.
*
* @param dest
*
* @param ch
*
* @param count
*
* @return None
*
* @note None
*
****************************************************************************/
void MD5Transform( u32 *buffer, u32 *intermediate )
{
register u32 a, b, c, d;
a = buffer[ 0 ];
b = buffer[ 1 ];
c = buffer[ 2 ];
d = buffer[ 3 ];
MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
buffer[ 0 ] += a;
buffer[ 1 ] += b;
buffer[ 2 ] += c;
buffer[ 3 ] += d;
}
/******************************************************************************/
/**
*
* This function Start MD5 accumulation
* Set bit count to 0 and buffer to mysterious initialization constants
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
inline void MD5Init( MD5Context *context )
{
context->buffer[ 0 ] = 0x67452301;
context->buffer[ 1 ] = 0xefcdab89;
context->buffer[ 2 ] = 0x98badcfe;
context->buffer[ 3 ] = 0x10325476;
context->bits[ 0 ] = 0;
context->bits[ 1 ] = 0;
}
/******************************************************************************/
/**
*
* This function updates context to reflect the concatenation of another
* buffer full of bytes
*
* @param
*
* @param
*
* @param
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
inline void MD5Update( MD5Context *context, u8 *buffer,
u32 len, boolean doByteSwap )
{
register u32 temp;
register u8 * p;
/*
* Update bitcount
*/
temp = context->bits[ 0 ];
if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
/*
* Carry from low to high
*/
context->bits[ 1 ]++;
}
context->bits[ 1 ] += len >> 29;
/*
* Bytes already in shsInfo->data
*/
temp = ( temp >> 3 ) & 0x3f;
/*
* Handle any leading odd-sized chunks
*/
if( temp ) {
p = (u8 *)context->intermediate + temp;
temp = MD5_SIGNATURE_BYTE_SIZE - temp;
if( len < temp ) {
MD5Memcpy( p, buffer, len, doByteSwap );
return;
}
MD5Memcpy( p, buffer, temp, doByteSwap );
MD5Transform( context->buffer, (u32 *)context->intermediate );
buffer += temp;
len -= temp;
}
/*
* Process data in 64-byte, 512 bit, chunks
*/
while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
doByteSwap );
MD5Transform( context->buffer, (u32 *)context->intermediate );
buffer += MD5_SIGNATURE_BYTE_SIZE;
len -= MD5_SIGNATURE_BYTE_SIZE;
}
/*
* Handle any remaining bytes of data
*/
MD5Memcpy( context->intermediate, buffer, len, doByteSwap );
}
/******************************************************************************/
/**
*
* This function final wrap-up - pad to 64-byte boundary with the bit pattern
* 1 0* (64-bit count of bits processed, MSB-first
*
* @param
*
* @param
*
* @param
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
inline void MD5Final( MD5Context *context, u8 *digest,
boolean doByteSwap )
{
u32 count;
u8 * p;
/*
* Compute number of bytes mod 64
*/
count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
/*
* Set the first char of padding to 0x80. This is safe since there is
* always at least one byte free
*/
p = context->intermediate + count;
*p++ = 0x80;
/*
* Bytes of padding needed to make 64 bytes
*/
count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
/*
* Pad out to 56 mod 64
*/
if( count < 8 ) {
/*
* Two lots of padding: Pad the first block to 64 bytes
*/
MD5Memset( p, 0, count );
MD5Transform( context->buffer, (u32 *)context->intermediate );
/*
* Now fill the next block with 56 bytes
*/
MD5Memset( context->intermediate, 0, 56 );
} else {
/*
* Pad block to 56 bytes
*/
MD5Memset( p, 0, count - 8 );
}
/*
* Append length in bits and transform
*/
( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
MD5Transform( context->buffer, (u32 *)context->intermediate );
/*
* Now return the digest
*/
MD5Memcpy( digest, context->buffer, 16, doByteSwap );
}
/******************************************************************************/
/**
*
* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
* 'input'. 'digest' must have enough space to hold 16 bytes
*
* @param
*
* @param
*
* @param
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
{
MD5Context context;
MD5Init( &context );
MD5Update( &context, input, len, doByteSwap );
MD5Final( &context, digest, doByteSwap );
}
2.FW/Zynq/proj_cal/Vitis/FSBL/src/md5.h
+116
View File
@@ -0,0 +1,116 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file md5.h
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00a sgd 05/17/13 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___MD5_H___
#define ___MD5_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define MD5_SIGNATURE_BYTE_SIZE 64
/**************************** Type Definitions *******************************/
typedef u8 boolean;
typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
struct MD5Context
{
u32 buffer[ 4 ];
u32 bits[ 2 ];
signature intermediate;
};
typedef struct MD5Context MD5Context;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* The four core functions - F1 is optimized somewhat
*/
#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
#define F2( x, y, z ) F1( z, x, y )
#define F3( x, y, z ) ( x ^ y ^ z )
#define F4( x, y, z ) ( y ^ ( x | ~z ) )
/*
* This is the central step in the MD5 algorithm
*/
#define MD5_STEP( f, w, x, y, z, data, s ) \
( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
/************************** Function Prototypes ******************************/
void * MD5Memset( void *dest, int ch, u32 count );
void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
void MD5Transform( u32 *buffer, u32 *intermediate );
void MD5Init( MD5Context *context );
void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___MD5_H___ */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.c
+291
View File
@@ -0,0 +1,291 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nand.c
*
* Contains code for the NAND FLASH functionality. Bad Block management
* is simple: skip the bad blocks and keep going.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 2.00a mb 25/05/12 fsbl changes for standalone bsp based
* 3.00a sgd 30/01/13 Code cleanup
* 5.00a sgd 17/05/13 Support for Multi Boot
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "fsbl.h"
#ifdef XPAR_PS7_NAND_0_BASEADDR
#include "nand.h"
#include "xnandps_bbm.h"
/************************** Constant Definitions *****************************/
#define NAND_DEVICE_ID XPAR_XNANDPS_0_DEVICE_ID
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
u64 Offset,
u32 Length);
/************************** Variable Definitions *****************************/
extern u32 FlashReadBaseAddress;
extern u32 FlashOffsetAddress;
XNandPs *NandInstPtr;
XNandPs NandInstance; /* XNand Instance. */
/******************************************************************************/
/**
*
* This function initializes the controller for the NAND FLASH interface.
*
* @param none
*
* @return
* - XST_SUCCESS if the controller initializes correctly
* - XST_FAILURE if the controller fails to initializes correctly
*
* @note none.
*
****************************************************************************/
u32 InitNand(void)
{
u32 Status;
XNandPs_Config *ConfigPtr;
/*
* Set up pointers to instance and the config structure
*/
NandInstPtr = &NandInstance;
/*
* Initialize the flash driver.
*/
ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE_ID);
if (ConfigPtr == NULL) {
fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r");
return XST_FAILURE;
}
Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr,
ConfigPtr->SmcBase,ConfigPtr->FlashBase);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_GENERAL,"NAND intialization failed \n \r");
return XST_FAILURE;
}
/*
* Set up base address for access
*/
FlashReadBaseAddress = XPS_NAND_BASEADDR;
fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n",
NandInstPtr->Geometry.FlashWidth);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n",
Status);
return XST_FAILURE;
}
/*
* set up the FLASH access pointers
*/
fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r");
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function provides the NAND FLASH interface for the Simplified header
* functionality. This function handles bad blocks.
*
* The source address is the absolute good address, bad blocks are skipped
* without incrementing the source address.
*
* @param SourceAddress is address in FLASH data space, absolute good address
* @param DestinationAddress is address in OCM data space
*
* @return XST_SUCCESS if the transfer completes correctly
* XST_FAILURE if the transfer fails to completes correctly
*
* @note none.
*
****************************************************************************/
u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
u32 ActLen;
u32 BlockOffset;
u32 Block;
u32 Status;
u32 BytesLeft = LengthBytes;
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
u8 *BufPtr = (u8 *)DestinationAddress;
u32 ReadLen;
u32 BlockReadLen;
u32 Offset;
u32 TmpAddress = 0 ;
u32 BlockCount = 0;
u32 BadBlocks = 0;
/*
* First get bad blocks before the source address
*/
while (TmpAddress < SourceAddress) {
while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) ==
XST_SUCCESS) {
BlockCount ++;
BadBlocks ++;
}
TmpAddress += BlockSize;
BlockCount ++;
}
Offset = SourceAddress + BadBlocks * BlockSize;
/*
* Calculate the actual length including bad blocks
*/
ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes);
/*
* Check if the actual length cross flash size
*/
if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) {
return XST_FAILURE;
}
while (BytesLeft > 0) {
BlockOffset = Offset & (BlockSize - 1);
Block = (Offset & ~(BlockSize - 1))/BlockSize;
BlockReadLen = BlockSize - BlockOffset;
Status = XNandPs_IsBlockBad(NandInstPtr, Block);
if (Status == XST_SUCCESS) {
/* Move to next block */
Offset += BlockReadLen;
continue;
}
/*
* Check if we cross block boundary
*/
if (BytesLeft < BlockReadLen) {
ReadLen = BytesLeft;
} else {
ReadLen = BlockReadLen;
}
/*
* Read from the NAND flash
*/
Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL);
if (Status != XST_SUCCESS) {
return Status;
}
BytesLeft -= ReadLen;
Offset += ReadLen;
BufPtr += ReadLen;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function returns the length including bad blocks from a given offset and
* length.
*
* @param NandInstPtr is the pointer to the XNandPs instance.
* @param Offset is the flash data address to read from.
* @param Length is number of bytes to read.
*
* @return
* - Return actual length including bad blocks.
*
* @note None.
*
******************************************************************************/
static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
u64 Offset,
u32 Length)
{
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
u32 CurBlockLen;
u32 CurBlock;
u32 Status;
u32 TempLen = 0;
u32 ActLen = 0;
while (TempLen < Length) {
CurBlockLen = BlockSize - (Offset & (BlockSize - 1));
CurBlock = (Offset & ~(BlockSize - 1))/BlockSize;
/*
* Check if the block is bad
*/
Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock);
if (Status != XST_SUCCESS) {
/* Good Block */
TempLen += CurBlockLen;
}
ActLen += CurBlockLen;
Offset += CurBlockLen;
if (Offset >= NandInstPtr->Geometry.DeviceSize) {
break;
}
}
return ActLen;
}
#endif
2.FW/Zynq/proj_cal/Vitis/FSBL/src/nand.h
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nand.h
*
* This file contains the interface for the NAND FLASH functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 2.00a mb 30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___NAND_H___
#define ___NAND_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#ifdef XPAR_PS7_NAND_0_BASEADDR
#include "xnandps.h"
#include "xnandps_bbm.h"
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
u32 InitNand(void);
u32 NandAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthWords);
#endif
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___NAND_H___ */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.c
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nor.c
*
* Contains code for the NOR FLASH functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 2.00a mb 25/05/12 mio init removed
* 3.00a sgd 30/01/13 Code cleanup
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "fsbl.h"
#include "nor.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u32 FlashReadBaseAddress;
/******************************************************************************/
/******************************************************************************/
/**
*
* This function initializes the controller for the NOR FLASH interface.
*
* @param None
*
* @return None
*
* @note None.
*
****************************************************************************/
void InitNor(void)
{
/*
* Set up the base address for access
*/
FlashReadBaseAddress = XPS_NOR_BASEADDR;
}
/******************************************************************************/
/**
*
* This function provides the NOR FLASH interface for the Simplified header
* functionality.
*
* @param SourceAddress is address in FLASH data space
* @param DestinationAddress is address in OCM data space
* @param LengthBytes is the data length to transfer in bytes
*
* @return
* - XST_SUCCESS if the write completes correctly
* - XST_FAILURE if the write fails to completes correctly
*
* @note None.
*
****************************************************************************/
u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
u32 Data;
u32 Count;
u32 *SourceAddr;
u32 *DestAddr;
u32 LengthWords;
/*
* check for non-word tail
* add bytes to cover the end
*/
if ((LengthBytes%4) != 0){
LengthBytes += (4 - (LengthBytes & 0x00000003));
}
LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
DestAddr = (u32 *)(DestinationAddress);
/*
* Word transfers, endianism isn't an issue
*/
for (Count=0; Count < LengthWords; Count++){
Data = Xil_In32((u32)(SourceAddr++));
Xil_Out32((u32)(DestAddr++), Data);
}
return XST_SUCCESS;
}
2.FW/Zynq/proj_cal/Vitis/FSBL/src/nor.h
+83
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nor.h
*
* This file contains the interface for the NOR FLASH functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___NOR_H___
#define ___NOR_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void InitNor(void);
u32 NorAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthBytes);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___NOR_H___ */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.c
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@@ -0,0 +1,812 @@
/*****************************************************************************
*
* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file pcap.c
*
* Contains code for enabling and accessing the PCAP
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 02/10/10 Initial release
* 2.00a jz 05/28/11 Add SD support
* 2.00a mb 25/05/12 using the EDK provided devcfg driver
* Nand/SD encryption and review comments
* 3.00a mb 16/08/12 Added the poll function
* Removed the FPGA_RST_CTRL define
* Added the flag for NON PS instantiated bitstream
* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
* fabric_init()
* Fix for CR#689026 - FSBL doesn't hold PL resets active
* during bit download
* Fix for CR#699475 - FSBL functionality is broken and
* its not able to boot in QSPI/NAND
* bootmode
* Fix for CR#705664 - FSBL fails to decrypt the
* bitstream when the image is AES
* encrypted using non-zero key value
* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
* changelogs in FSBL
* 7.00a kc 10/25/13 Fix for CR#724620 - How to handle PCAP_MODE after
* bitstream configuration
* Fix for CR#726178 - FabricInit() PROG_B is kept active
* for 5mS.
* Fix for CR#731839 - FSBL has to check the
* HMAC error status after decryption
* 12/04/13 Fix for CR#764382 - How to handle PCAP_MODE after
* bitstream configuration - PCAP_MODE
* and PCAP_PR bits are not modified
* 8.00a kc 2/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
* is not proper
* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
* 13.00a ssc 04/10/15 Fix for CR#846899 - Corrected logic to clear
* DMA done count
* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
* In pcap.c/pcap.h/main.h,
* Fabric Initialization sequence
* is modified to check the PL power
* before sequence starts and checking
* INIT_B reset status twice in case
* of failure.
* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
* In pcap.c, check pl power
* through MCTRL register for
* 3.0 and later versions of silicon.
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "pcap.h"
#include "nand.h" /* For NAND geometry information */
#include "fsbl.h"
#include "image_mover.h" /* For MoveImage */
#include "xparameters.h"
#include "xil_exception.h"
#include "xdevcfg.h"
#include "sleep.h"
#include "xtime_l.h"
#ifdef XPAR_XWDTPS_0_BASEADDR
#include "xwdtps.h"
#endif
/************************** Constant Definitions *****************************/
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are only defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
/************************** Variable Definitions *****************************/
/* Devcfg driver instance */
static XDcfg DcfgInstance;
XDcfg *DcfgInstPtr;
extern u32 Silicon_Version;
#ifdef XPAR_XWDTPS_0_BASEADDR
extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
#endif
/******************************************************************************/
/**
*
* This function transfer data using PCAP
*
* @param SourceDataPtr is a pointer to where the data is read from
* @param DestinationDataPtr is a pointer to where the data is written to
* @param SourceLength is the length of the data to be moved in words
* @param DestinationLength is the length of the data to be moved in words
* @param SecureTransfer indicated the encryption key location, 0 for
* non-encrypted
*
* @return
* - XST_SUCCESS if the transfer is successful
* - XST_FAILURE if the transfer fails
*
* @note None
*
****************************************************************************/
u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
{
u32 Status;
u32 IntrStsReg;
u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
/*
* Check for secure transfer
*/
if (SecureTransfer) {
PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
}
#ifdef FSBL_PERF
XTime tXferCur = 0;
FsblGetGlobalTime(&tXferCur);
#endif
/*
* Clear the PCAP status registers
*/
Status = ClearPcapStatus();
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
return XST_FAILURE;
}
#ifdef XPAR_XWDTPS_0_BASEADDR
/*
* Prevent WDT reset
*/
XWdtPs_RestartWdt(&Watchdog);
#endif
/*
* PCAP single DMA transfer setup
*/
SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
/*
* Transfer using Device Configuration
*/
Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
SourceLength,
(u8 *)DestinationDataPtr,
DestinationLength, PcapTransferType);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
return XST_FAILURE;
}
/*
* Dump the PCAP registers
*/
PcapDumpRegisters();
/*
* Poll for the DMA done
*/
Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
/*
* Check for errors
*/
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
return XST_FAILURE;
}
/*
* For Performance measurement
*/
#ifdef FSBL_PERF
XTime tXferEnd = 0;
fsbl_printf(DEBUG_GENERAL,"Time taken is ");
FsblMeasurePerfTime(tXferCur,tXferEnd);
#endif
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function loads PL partition using PCAP
*
* @param SourceDataPtr is a pointer to where the data is read from
* @param DestinationDataPtr is a pointer to where the data is written to
* @param SourceLength is the length of the data to be moved in words
* @param DestinationLength is the length of the data to be moved in words
* @param SecureTransfer indicated the encryption key location, 0 for
* non-encrypted
*
* @return
* - XST_SUCCESS if the transfer is successful
* - XST_FAILURE if the transfer fails
*
* @note None
*
****************************************************************************/
u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
{
u32 Status;
u32 IntrStsReg;
u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
/*
* Check for secure transfer
*/
if (SecureTransfer) {
PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
}
#ifdef FSBL_PERF
XTime tXferCur = 0;
FsblGetGlobalTime(&tXferCur);
#endif
/*
* Clear the PCAP status registers
*/
Status = ClearPcapStatus();
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
return XST_FAILURE;
}
/*
* For Bitstream case destination address will be 0xFFFFFFFF
*/
DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
/*
* New Bitstream download initialization sequence
*/
Status = FabricInit();
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#ifdef XPAR_XWDTPS_0_BASEADDR
/*
* Prevent WDT reset
*/
XWdtPs_RestartWdt(&Watchdog);
#endif
/*
* PCAP single DMA transfer setup
*/
SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
/*
* Transfer using Device Configuration
*/
Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
SourceLength,
(u8 *)DestinationDataPtr,
DestinationLength, PcapTransferType);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
return XST_FAILURE;
}
/*
* Dump the PCAP registers
*/
PcapDumpRegisters();
/*
* Poll for the DMA done
*/
Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
/*
* Poll for FPGA Done
*/
Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
/*
* Check for errors
*/
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
return XST_FAILURE;
}
/*
* For Performance measurement
*/
#ifdef FSBL_PERF
XTime tXferEnd = 0;
fsbl_printf(DEBUG_GENERAL,"Time taken is ");
FsblMeasurePerfTime(tXferCur,tXferEnd);
#endif
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function Initializes the PCAP driver.
*
* @param none
*
* @return
* - XST_SUCCESS if the pcap driver initialization is successful
* - XST_FAILURE if the pcap driver initialization fails
*
* @note none
*
****************************************************************************/
int InitPcap(void)
{
XDcfg_Config *ConfigPtr;
int Status = XST_SUCCESS;
DcfgInstPtr = &DcfgInstance;
/*
* Initialize the Device Configuration Interface driver.
*/
ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
ConfigPtr->BaseAddr);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function programs the Fabric for use.
*
* @param None
*
* @return
* - XST_SUCCESS if the Fabric initialization is successful
* - XST_FAILURE if the Fabric initialization fails
* @note None
*
****************************************************************************/
u32 FabricInit(void)
{
u32 PcapReg;
u32 PcapCtrlRegVal;
u32 StatusReg;
u32 MctrlReg;
u32 PcfgInit;
u32 TimerExpired=0;
XTime tCur=0;
XTime tEnd=0;
/*
* Set Level Shifters DT618760 - PS to PL enabling
*/
Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n",
Xil_In32(PS_LVL_SHFTR_EN));
/*
* Get DEVCFG controller settings
*/
PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
/*
* Check the PL power status
*/
if(Silicon_Version >= SILICON_VERSION_3)
{
MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr);
if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) !=
XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK)
{
fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n");
return XST_FAILURE;
}
}
/*
* Setting PCFG_PROG_B signal to high
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Setting PCFG_PROG_B signal to low
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Polling the PCAP_INIT status for Reset or timeout
*/
XTime_GetTime(&tCur);
do
{
PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
XDCFG_STATUS_PCFG_INIT_MASK);
if(PcfgInit == 0)
{
break;
}
XTime_GetTime(&tEnd);
if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
{
TimerExpired = 1;
}
} while(!TimerExpired);
if(TimerExpired == 1)
{
TimerExpired = 0;
/*
* Came here due to expiration and PCAP_INIT is set.
* Retry PCFG_PROG_B High -> Low again
*/
/*
* Setting PCFG_PROG_B signal to high
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Setting PCFG_PROG_B signal to low
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Polling the PCAP_INIT status for Reset or timeout (second iteration)
*/
XTime_GetTime(&tCur);
do
{
PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
XDCFG_STATUS_PCFG_INIT_MASK);
if(PcfgInit == 0)
{
break;
}
XTime_GetTime(&tEnd);
if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
{
TimerExpired = 1;
}
} while(!TimerExpired);
if(TimerExpired == 1)
{
/*
* Came here due to PCAP_INIT is not getting reset
* for PCFG_PROG_B signal High -> Low
*/
fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n");
return XST_FAILURE;
}
}
/*
* Setting PCFG_PROG_B signal to high
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Polling the PCAP_INIT status for Set
*/
while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
XDCFG_STATUS_PCFG_INIT_MASK));
/*
* Get Device configuration status
*/
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg);
fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function Clears the PCAP status registers.
*
* @param None
*
* @return
* - XST_SUCCESS if the pcap status registers are cleared
* - XST_FAILURE if errors are there
* - XST_DEVICE_BUSY if Pcap device is busy
* @note None
*
****************************************************************************/
u32 ClearPcapStatus(void)
{
u32 StatusReg;
u32 IntStatusReg;
/*
* Clear it all, so if Boot ROM comes back, it can proceed
*/
XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
/*
* Get PCAP Interrupt Status Register
*/
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
IntStatusReg);
return XST_FAILURE;
}
/*
* Read the PCAP status register for DMA status
*/
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg);
/*
* If the queue is full, return w/ XST_DEVICE_BUSY
*/
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
return XST_DEVICE_BUSY;
}
fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
/*
* There are unacknowledged DMA commands outstanding
*/
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
XDCFG_IXR_DMA_DONE_MASK){
/*
* Error state, transfer cannot occur
*/
fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
return XST_FAILURE;
}
else {
/*
* clear out the status
*/
XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
}
}
if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg |
XDCFG_STATUS_DMA_DONE_CNT_MASK);
}
fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function prints PCAP register status.
*
* @param none
*
* @return none
*
* @note none
*
****************************************************************************/
void PcapDumpRegisters (void) {
fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
}
/******************************************************************************/
/**
*
* This function Polls for the DMA done or FPGA done.
*
* @param none
*
* @return
* - XST_SUCCESS if polling for DMA/FPGA done is successful
* - XST_FAILURE if polling for DMA/FPGA done fails
*
* @note none
*
****************************************************************************/
int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
{
int Count = MaxCount;
u32 IntrStsReg = 0;
/*
* poll for the DMA done
*/
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
while ((IntrStsReg & MaskValue) !=
MaskValue) {
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
Count -=1;
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
IntrStsReg);
PcapDumpRegisters();
return XST_FAILURE;
}
if(!Count) {
fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
return XST_FAILURE;
}
if (Count > (MAX_COUNT-100)) {
fsbl_printf(DEBUG_GENERAL,".");
}
}
fsbl_printf(DEBUG_GENERAL,"\n\r");
XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
return XST_SUCCESS;
}
2.FW/Zynq/proj_cal/Vitis/FSBL/src/pcap.h
+104
View File
@@ -0,0 +1,104 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file pcap.h
*
* This file contains the interface for intiializing and accessing the PCAP
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 02/10/10 Initial release
* 2.00a mb 16/08/12 Added the macros and function prototypes
* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
* Fabric Initialization sequence is modified to check
* the PL power before sequence starts and checking INIT_B
* reset status twice in case of failure.
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___PCAP_H___
#define ___PCAP_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xdevcfg.h"
/************************** Function Prototypes ******************************/
/* Multiboot register offset mask */
#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF
#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000
/*Miscellaneous Control Register mask*/
#define XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK 0x00000100
#define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000)
#define PCAP_LAST_TRANSFER 1
#define MAX_COUNT 1000000000
#define LVL_PL_PS 0x0000000F
#define LVL_PS_PL 0x0000000A
/* Fix for #672779 */
#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
int InitPcap(void);
void PcapDumpRegisters(void);
u32 ClearPcapStatus(void);
u32 FabricInit(void);
int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
u32 DestinationLength, u32 Flags);
u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
u32 DestinationLength, u32 Flags);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___PCAP_H___ */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.c
+877
View File
@@ -0,0 +1,877 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file qspi.c
*
* Contains code for the QSPI FLASH functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
* are set
* 4.00a sg 02/28/13 Cleanup
* Removed LPBK_DLY_ADJ register setting code as we use
* divisor 8
* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
* Dual Stack support
* Fix for CR:721674 - FSBL- Failed to boot from Dual
* stacked QSPI
* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
* changelogs in FSBL
* Fix for CR#739711 - FSBL not able to read Large QSPI
* (512M) in IO Mode
* 7.00a kc 10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
* settings for Dual parallel
* configuration in IO mode
* 14.0 gan 01/13/16 Fix for CR#869081 - (2016.1)FSBL picks the qspi read
* command from LQSPI_CFG register
* instead of hard coded read
* command (0x6B).
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "qspi.h"
#include "image_mover.h"
#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
#include "xqspips_hw.h"
#include "xqspips.h"
/************************** Constant Definitions *****************************/
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
/*
* The following constants define the commands which may be sent to the FLASH
* device.
*/
#define QUAD_READ_CMD 0x6B
#define READ_ID_CMD 0x9F
#define WRITE_ENABLE_CMD 0x06
#define BANK_REG_RD 0x16
#define BANK_REG_WR 0x17
/* Bank register is called Extended Address Reg in Micron */
#define EXTADD_REG_RD 0xC8
#define EXTADD_REG_WR 0xC5
#define COMMAND_OFFSET 0 /* FLASH instruction */
#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
#define DATA_OFFSET 4 /* Start of Data for Read/Write */
#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
reads */
#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
quad reads */
#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
/*
* The following constants specify the extra bytes which are sent to the
* FLASH on the QSPI interface, that are not data, but control information
* which includes the command and address
*/
#define OVERHEAD_SIZE 4
/*
* The following constants specify the max amount of data and the size of the
* the buffer required to hold the data and overhead to transfer the data to
* and from the FLASH.
*/
#define DATA_SIZE 4096
/*
* The following defines are for dual flash interface.
*/
#define LQSPI_CR_FAST_READ 0x0000000B
#define LQSPI_CR_FAST_DUAL_READ 0x0000003B
#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
address and return data */
#define SINGLE_QSPI_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_READ)
#define SINGLE_QSPI_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_DUAL_READ)
#define SINGLE_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define DUAL_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define DUAL_STACK_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_READ)
#define DUAL_STACK_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_DUAL_READ)
#define DUAL_STACK_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define SINGLE_QSPI_IO_CONFIG_FAST_READ (LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_READ)
#define SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ (LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_DUAL_READ)
#define SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define QSPI_BUSWIDTH_ONE 0U
#define QSPI_BUSWIDTH_TWO 1U
#define QSPI_BUSWIDTH_FOUR 2U
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
XQspiPs QspiInstance;
XQspiPs *QspiInstancePtr;
u32 QspiFlashSize;
u32 QspiFlashMake;
extern u32 FlashReadBaseAddress;
extern u8 LinearBootDeviceFlag;
/*
* The following variables are used to read and write to the eeprom and they
* are global to avoid having large buffers on the stack
*/
u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
/******************************************************************************/
/**
*
* This function initializes the controller for the QSPI interface.
*
* @param None
*
* @return None
*
* @note None
*
****************************************************************************/
u32 InitQspi(void)
{
XQspiPs_Config *QspiConfig;
int Status;
u32 ConfigCmd;
QspiInstancePtr = &QspiInstance;
/*
* Set up the base address for access
*/
FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
/*
* Initialize the QSPI driver so that it's ready to use
*/
QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
if (NULL == QspiConfig) {
return XST_FAILURE;
}
Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
QspiConfig->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Set Manual Chip select options and drive HOLD_B pin high.
*/
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
XQSPIPS_HOLD_B_DRIVE_OPTION);
/*
* Set the prescaler for QSPI clock
*/
XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
/*
* Assert the FLASH chip select.
*/
XQspiPs_SetSlaveSelect(QspiInstancePtr);
/*
* Read Flash ID and extract Manufacture and Size information
*/
Status = FlashReadID();
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (XPAR_XQSPIPS_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) {
fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
/*
* For Flash size <128Mbit controller configured in linear mode
*/
if (QspiFlashSize <= FLASH_SIZE_16MB) {
LinearBootDeviceFlag = 1;
/*
* Enable linear mode
*/
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
XQSPIPS_HOLD_B_DRIVE_OPTION);
switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
case QSPI_BUSWIDTH_ONE:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_READ;
}
break;
case QSPI_BUSWIDTH_TWO:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_DUAL_READ;
}
break;
case QSPI_BUSWIDTH_FOUR:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_QUAD_READ;
}
break;
}
/*
* Single linear read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
} else {
switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
case QSPI_BUSWIDTH_ONE:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_READ;
}
break;
case QSPI_BUSWIDTH_TWO:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ;
}
break;
case QSPI_BUSWIDTH_FOUR:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ;
}
break;
}
/*
* Single flash IO read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
}
}
if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
/*
* For Single Flash size <128Mbit controller configured in linear mode
*/
if (QspiFlashSize <= FLASH_SIZE_16MB) {
/*
* Setting linear access flag
*/
LinearBootDeviceFlag = 1;
/*
* Enable linear mode
*/
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
XQSPIPS_HOLD_B_DRIVE_OPTION);
/*
* Dual linear read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_FAST_QUAD_READ);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
} else {
/*
* Dual flash IO read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
}
/*
* Total flash size is two time of single flash size
*/
QspiFlashSize = 2 * QspiFlashSize;
}
/*
* It is expected to same flash size for both chip selection
*/
if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
QspiFlashSize = 2 * QspiFlashSize;
/*
* Enable two flash memories on separate buses
*/
switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
case QSPI_BUSWIDTH_ONE:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
ConfigCmd = DUAL_STACK_CONFIG_FAST_READ;
}
break;
case QSPI_BUSWIDTH_TWO:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
ConfigCmd = DUAL_STACK_CONFIG_FAST_DUAL_READ;
}
break;
case QSPI_BUSWIDTH_FOUR:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
ConfigCmd = DUAL_STACK_CONFIG_FAST_QUAD_READ;
}
break;
}
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
}
return XST_SUCCESS;
}
/******************************************************************************
*
* This function reads serial FLASH ID connected to the SPI interface.
* It then deduces the make and size of the flash and obtains the
* connection mode to point to corresponding parameters in the flash
* configuration table. The flash driver will function based on this and
* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
* Winbond 128Mbit
*
* @param none
*
* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
u32 FlashReadID(void)
{
u32 Status;
/*
* Read ID in Auto mode.
*/
WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
RD_ID_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
ReadBuffer[2],
ReadBuffer[3]);
/*
* Deduce flash make
*/
if (ReadBuffer[1] == MICRON_ID) {
QspiFlashMake = MICRON_ID;
fsbl_printf(DEBUG_INFO, "MICRON ");
} else if(ReadBuffer[1] == SPANSION_ID) {
QspiFlashMake = SPANSION_ID;
fsbl_printf(DEBUG_INFO, "SPANSION ");
} else if(ReadBuffer[1] == WINBOND_ID) {
QspiFlashMake = WINBOND_ID;
fsbl_printf(DEBUG_INFO, "WINBOND ");
} else if(ReadBuffer[1] == MACRONIX_ID) {
QspiFlashMake = MACRONIX_ID;
fsbl_printf(DEBUG_INFO, "MACRONIX ");
} else if(ReadBuffer[0] == ISSI_ID) {
QspiFlashMake = ISSI_ID;
fsbl_printf(DEBUG_INFO, "ISSI ");
}
/*
* Deduce flash Size
*/
if (ReadBuffer[2] == FLASH_SIZE_ID_8M) {
QspiFlashSize = FLASH_SIZE_8M;
fsbl_printf(DEBUG_INFO, "8M Bits\r\n");
} else if (ReadBuffer[2] == FLASH_SIZE_ID_16M) {
QspiFlashSize = FLASH_SIZE_16M;
fsbl_printf(DEBUG_INFO, "16M Bits\r\n");
} else if (ReadBuffer[2] == FLASH_SIZE_ID_32M) {
QspiFlashSize = FLASH_SIZE_32M;
fsbl_printf(DEBUG_INFO, "32M Bits\r\n");
} else if (ReadBuffer[2] == FLASH_SIZE_ID_64M) {
QspiFlashSize = FLASH_SIZE_64M;
fsbl_printf(DEBUG_INFO, "64M Bits\r\n");
} else if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
QspiFlashSize = FLASH_SIZE_128M;
fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
} else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
QspiFlashSize = FLASH_SIZE_256M;
fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M)
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) {
QspiFlashSize = FLASH_SIZE_512M;
fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G)
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) {
QspiFlashSize = FLASH_SIZE_1G;
fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
}
return XST_SUCCESS;
}
/******************************************************************************
*
* This function reads from the serial FLASH connected to the
* QSPI interface.
*
* @param Address contains the address to read data from in the FLASH.
* @param ByteCount contains the number of bytes to read.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void FlashRead(u32 Address, u32 ByteCount)
{
/*
* Setup the write command with the specified address and data for the
* FLASH
*/
u32 LqspiCrReg;
u8 ReadCommand;
LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK);
WriteBuffer[COMMAND_OFFSET] = ReadCommand;
WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
ByteCount += DUMMY_SIZE;
/*
* Send the read command to the FLASH to read the specified number
* of bytes from the FLASH, send the read command and address and
* receive the specified number of bytes of data in the data buffer
*/
XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
ByteCount + OVERHEAD_SIZE);
}
/******************************************************************************/
/**
*
* This function provides the QSPI FLASH interface for the Simplified header
* functionality.
*
* @param SourceAddress is address in FLASH data space
* @param DestinationAddress is address in DDR data space
* @param LengthBytes is the length of the data in Bytes
*
* @return
* - XST_SUCCESS if the write completes correctly
* - XST_FAILURE if the write fails to completes correctly
*
* @note none.
*
****************************************************************************/
u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
u8 *BufferPtr;
u32 Length = 0;
u32 BankSel = 0;
u32 LqspiCrReg;
u32 Status;
u8 BankSwitchFlag = 1;
/*
* Linear access check
*/
if (LinearBootDeviceFlag == 1) {
/*
* Check for non-word tail, add bytes to cover the end
*/
if ((LengthBytes%4) != 0){
LengthBytes += (4 - (LengthBytes & 0x00000003));
}
memcpy((void*)DestinationAddress,
(const void*)(SourceAddress + FlashReadBaseAddress),
(size_t)LengthBytes);
} else {
/*
* Non Linear access
*/
BufferPtr = (u8*)DestinationAddress;
/*
* Dual parallel connection actual flash is half
*/
if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
SourceAddress = SourceAddress/2;
}
while(LengthBytes > 0) {
/*
* Local of DATA_SIZE size used for read/write buffer
*/
if(LengthBytes > DATA_SIZE) {
Length = DATA_SIZE;
} else {
Length = LengthBytes;
}
/*
* Dual stack connection
*/
if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
/*
* Get the current LQSPI configuration value
*/
LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
/*
* Select lower or upper Flash based on sector address
*/
if (SourceAddress >= (QspiFlashSize/2)) {
/*
* Set selection to U_PAGE
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
/*
* Subtract first flash size when accessing second flash
*/
SourceAddress = SourceAddress - (QspiFlashSize/2);
fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
/*
* Assert the FLASH chip select.
*/
XQspiPs_SetSlaveSelect(QspiInstancePtr);
}
}
/*
* Select bank
*/
if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
BankSel = SourceAddress/FLASH_SIZE_16MB;
fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel);
Status = SendBankSelect(BankSel);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
return XST_FAILURE;
}
BankSwitchFlag = 0;
}
/*
* If data to be read spans beyond the current bank, then
* calculate length in current bank else no change in length
*/
if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
/*
* In dual parallel mode, check should be for half
* the length.
*/
if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
{
Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
/*
* Above length calculated is for single flash
* Length should be doubled since dual parallel
*/
Length = Length * 2;
BankSwitchFlag = 1;
}
} else {
if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
{
Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
BankSwitchFlag = 1;
}
}
/*
* Copying the image to local buffer
*/
FlashRead(SourceAddress, Length);
/*
* Moving the data from local buffer to DDR destination address
*/
memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
/*
* Updated the variables
*/
LengthBytes -= Length;
/*
* For Dual parallel connection address increment should be half
*/
if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
SourceAddress += Length/2;
} else {
SourceAddress += Length;
}
BufferPtr = (u8*)((u32)BufferPtr + Length);
}
/*
* Reset Bank selection to zero
*/
Status = SendBankSelect(0);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
return XST_FAILURE;
}
if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
/*
* Reset selection to L_PAGE
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
/*
* Assert the FLASH chip select.
*/
XQspiPs_SetSlaveSelect(QspiInstancePtr);
}
}
return XST_SUCCESS;
}
/******************************************************************************
*
* This functions selects the current bank
*
* @param BankSel is the bank to be selected in the flash device(s).
*
* @return XST_SUCCESS if bank selected
* XST_FAILURE if selection failed
* @note None.
*
******************************************************************************/
u32 SendBankSelect(u8 BankSel)
{
u32 Status;
/*
* bank select commands for Micron and Spansion are different
* Macronix bank select is same as Micron
*/
if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
/*
* For micron command WREN should be sent first
* except for some specific feature set
*/
WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
WRITE_ENABLE_CMD_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
if (QspiFlashMake == SPANSION_ID) {
WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
/*
* For testing - Read bank to verify
*/
if (QspiFlashMake == SPANSION_ID) {
WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
if (ReadBuffer[1] != BankSel) {
fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
ReadBuffer[1]);
return XST_FAILURE;
}
return XST_SUCCESS;
}
#endif
2.FW/Zynq/proj_cal/Vitis/FSBL/src/qspi.h
+133
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@@ -0,0 +1,133 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file qspi.h
*
* This file contains the interface for the QSPI FLASH functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
* Dual Stack support
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___QSPI_H___
#define ___QSPI_H___
#include "fsbl.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "fsbl.h"
/************************** Constant Definitions *****************************/
#define SINGLE_FLASH_CONNECTION 0
#define DUAL_STACK_CONNECTION 1
#define DUAL_PARALLEL_CONNECTION 2
#define FLASH_SIZE_16MB 0x1000000
/*
* Bank mask
*/
#define BANKMASK 0xF000000
/*
* Identification of Flash
* Micron:
* Byte 0 is Manufacturer ID;
* Byte 1 is first byte of Device ID - 0xBB or 0xBA
* Byte 2 is second byte of Device ID describes flash size:
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
* Spansion:
* Byte 0 is Manufacturer ID;
* Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
* Byte 2 is second byte of Device ID describes flash size:
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
*/
#define MICRON_ID 0x20
#define SPANSION_ID 0x01
#define WINBOND_ID 0xEF
#define MACRONIX_ID 0xC2
#define ISSI_ID 0x9D
#define FLASH_SIZE_ID_8M 0x14
#define FLASH_SIZE_ID_16M 0x15
#define FLASH_SIZE_ID_32M 0x16
#define FLASH_SIZE_ID_64M 0x17
#define FLASH_SIZE_ID_128M 0x18
#define FLASH_SIZE_ID_256M 0x19
#define FLASH_SIZE_ID_512M 0x20
#define FLASH_SIZE_ID_1G 0x21
/* Macronix size constants are different for 512M and 1G */
#define MACRONIX_FLASH_SIZE_ID_512M 0x1A
#define MACRONIX_FLASH_SIZE_ID_1G 0x1B
/*
* Size in bytes
*/
#define FLASH_SIZE_8M 0x0100000
#define FLASH_SIZE_16M 0x0200000
#define FLASH_SIZE_32M 0x0400000
#define FLASH_SIZE_64M 0x0800000
#define FLASH_SIZE_128M 0x1000000
#define FLASH_SIZE_256M 0x2000000
#define FLASH_SIZE_512M 0x4000000
#define FLASH_SIZE_1G 0x8000000
/************************** Function Prototypes ******************************/
u32 InitQspi(void);
u32 QspiAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthBytes);
u32 FlashReadID(void);
u32 SendBankSelect(u8 BankSel);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___QSPI_H___ */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/rsa.c
+357
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@@ -0,0 +1,357 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file rsa.c
*
* Contains code for the RSA authentication
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.00a sgd 02/28/13 Initial release
* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
* Fix for CR#724165 - Partition Header used by FSBL is
* not authenticated
* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
* by Boot ROM for authenticating
* the Partition images
* Fix for CR#722979 - Provide customer-friendly
* changelogs in FSBL
* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
* fallback unless FSBL* and FSBL are
* identical in length
* Fix for CR#791245 - Use of xilrsa in FSBL
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#ifdef RSA_SUPPORT
#include "fsbl.h"
#include "rsa.h"
#include "xilrsa.h"
#ifdef XPAR_XWDTPS_0_BASEADDR
#include "xwdtps.h"
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef XPAR_XWDTPS_0_BASEADDR
extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
#endif
/************************** Variable Definitions *****************************/
static u8 *PpkModular;
static u8 *PpkModularEx;
static u32 PpkExp;
static u32 PpkAlreadySet=0;
extern u32 FsblLength;
void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
{
#ifdef FSBL_DEBUG_RSA
int Index;
fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
for (Index=0;Index<Len;Index++)
{
fsbl_printf(DEBUG_INFO, "%02x",Buf[Index]);
if ((Index+1)%16 == 0){
fsbl_printf(DEBUG_INFO, "\r\n");
}
}
fsbl_printf(DEBUG_INFO, "\r\n %s END\r\n",Str);
#endif
return;
}
/*****************************************************************************/
/**
*
* This function is used to set ppk pointer to ppk in OCM
*
* @param None
*
* @return
*
* @note None
*
******************************************************************************/
void SetPpk(void )
{
u32 PadSize;
u8 *PpkPtr;
/*
* Set PPK only if is not already set
*/
if(PpkAlreadySet == 0)
{
/*
* Set PpkPtr to PPK in OCM
*/
/*
* Skip FSBL Length
*/
PpkPtr = (u8 *)(FsblLength);
/*
* Skip to 64 byte Boundary
*/
PadSize = ((u32)PpkPtr % 64);
if(PadSize != 0)
{
PpkPtr += (64 - PadSize);
}
/*
* Increment the pointer by authentication Header size
*/
PpkPtr += RSA_HEADER_SIZE;
/*
* Increment the pointer by Magic word size
*/
PpkPtr += RSA_MAGIC_WORD_SIZE;
/*
* Set pointer to PPK
*/
PpkModular = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_SIZE;
PpkModularEx = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
PpkExp = *((u32 *)PpkPtr);
/*
* Setting variable to avoid resetting PPK pointers
*/
PpkAlreadySet=1;
}
return;
}
/*****************************************************************************/
/**
*
* This function Authenticate Partition Signature
*
* @param Partition header pointer
*
* @return
* - XST_SUCCESS if Authentication passed
* - XST_FAILURE if Authentication failed
*
* @note None
*
******************************************************************************/
u32 AuthenticatePartition(u8 *Buffer, u32 Size)
{
u8 DecryptSignature[256];
u8 HashSignature[32];
u8 *SpkModular;
u8 *SpkModularEx;
u32 SpkExp;
u8 *SignaturePtr;
u32 Status;
#ifdef XPAR_XWDTPS_0_BASEADDR
/*
* Prevent WDT reset
*/
XWdtPs_RestartWdt(&Watchdog);
#endif
/*
* Point to Authentication Certificate
*/
SignaturePtr = (u8 *)(Buffer + Size - RSA_SIGNATURE_SIZE);
/*
* Increment the pointer by authentication Header size
*/
SignaturePtr += RSA_HEADER_SIZE;
/*
* Increment the pointer by Magic word size
*/
SignaturePtr += RSA_MAGIC_WORD_SIZE;
/*
* Increment the pointer beyond the PPK
*/
SignaturePtr += RSA_PPK_MODULAR_SIZE;
SignaturePtr += RSA_PPK_MODULAR_EXT_SIZE;
SignaturePtr += RSA_PPK_EXPO_SIZE;
/*
* Calculate Hash Signature
*/
sha_256((u8 *)SignaturePtr, (RSA_SPK_MODULAR_EXT_SIZE +
RSA_SPK_EXPO_SIZE + RSA_SPK_MODULAR_SIZE),
HashSignature);
FsblPrintArray(HashSignature, 32, "SPK Hash Calculated");
/*
* Extract SPK signature
*/
SpkModular = (u8 *)SignaturePtr;
SignaturePtr += RSA_SPK_MODULAR_SIZE;
SpkModularEx = (u8 *)SignaturePtr;
SignaturePtr += RSA_SPK_MODULAR_EXT_SIZE;
SpkExp = *((u32 *)SignaturePtr);
SignaturePtr += RSA_SPK_EXPO_SIZE;
/*
* Decrypt SPK Signature
*/
rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
(RSA_NUMBER)SignaturePtr,
(u32)PpkExp,
(RSA_NUMBER)PpkModular,
(RSA_NUMBER)PpkModularEx);
FsblPrintArray(DecryptSignature, RSA_SPK_SIGNATURE_SIZE,
"SPK Decrypted Hash");
Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Partition SPK Signature "
"Authentication failed\r\n");
return XST_FAILURE;
}
SignaturePtr += RSA_SPK_SIGNATURE_SIZE;
/*
* Decrypt Partition Signature
*/
rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
(RSA_NUMBER)SignaturePtr,
(u32)SpkExp,
(RSA_NUMBER)SpkModular,
(RSA_NUMBER)SpkModularEx);
FsblPrintArray(DecryptSignature, RSA_PARTITION_SIGNATURE_SIZE,
"Partition Decrypted Hash");
/*
* Partition Authentication
* Calculate Hash Signature
*/
sha_256((u8 *)Buffer,
(Size - RSA_PARTITION_SIGNATURE_SIZE),
HashSignature);
FsblPrintArray(HashSignature, 32,
"Partition Hash Calculated");
Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Partition Signature "
"Authentication failed\r\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function recreates the and check signature
*
* @param Partition signature
* @param Partition hash value which includes boot header, partition data
* @return
* - XST_SUCCESS if check passed
* - XST_FAILURE if check failed
*
* @note None
*
******************************************************************************/
u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash)
{
u8 T_padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
u8 * pad_ptr = signature + 256;
u32 pad = 256 - 3 - 19 - 32;
u32 ii;
/*
* Re-Create PKCS#1v1.5 Padding
* MSB ----------------------------------------------------LSB
* 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
*/
if (*--pad_ptr != 0x00 || *--pad_ptr != 0x01) {
return XST_FAILURE;
}
for (ii = 0; ii < pad; ii++) {
if (*--pad_ptr != 0xFF) {
return XST_FAILURE;
}
}
if (*--pad_ptr != 0x00) {
return XST_FAILURE;
}
for (ii = 0; ii < sizeof(T_padding); ii++) {
if (*--pad_ptr != T_padding[ii]) {
return XST_FAILURE;
}
}
for (ii = 0; ii < 32; ii++) {
if (*--pad_ptr != hash[ii])
return XST_FAILURE;
}
return XST_SUCCESS;
}
#endif
2.FW/Zynq/proj_cal/Vitis/FSBL/src/rsa.h
+76
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file rsa.h
*
* This file contains the RSA algorithm functions
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.00a sg 02/28/13 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___RSA_H___
#define ___RSA_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#define RSA_PPK_MODULAR_SIZE 256
#define RSA_PPK_MODULAR_EXT_SIZE 256
#define RSA_PPK_EXPO_SIZE 64
#define RSA_SPK_MODULAR_SIZE 256
#define RSA_SPK_MODULAR_EXT_SIZE 256
#define RSA_SPK_EXPO_SIZE 64
#define RSA_SPK_SIGNATURE_SIZE 256
#define RSA_PARTITION_SIGNATURE_SIZE 256
#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */
#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
void SetPpk(void );
u32 AuthenticatePartition(u8 *Buffer, u32 Size);
u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);
#ifdef __cplusplus
}
#endif
#endif /* ___RSA_H___ */
2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.c
+187
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file sd.c
*
* Contains code for the SD card FLASH functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 04/28/11 Initial release
* 7.00a kc 10/18/13 Integrated SD/MMC driver
* 12.00a ssc 12/11/14 Fix for CR# 839182
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "fsbl.h"
#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
#ifndef XPAR_PS7_SD_0_S_AXI_BASEADDR
#define XPAR_PS7_SD_0_S_AXI_BASEADDR XPAR_XSDPS_0_BASEADDR
#endif
#include "xstatus.h"
#include "ff.h"
#include "sd.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u32 FlashReadBaseAddress;
static FIL fil; /* File object */
static FATFS fatfs;
static char buffer[32];
static char *boot_file = buffer;
/******************************************************************************/
/******************************************************************************/
/**
*
* This function initializes the controller for the SD FLASH interface.
*
* @param filename of the file that is to be used
*
* @return
* - XST_SUCCESS if the controller initializes correctly
* - XST_FAILURE if the controller fails to initializes correctly
*
* @note None.
*
****************************************************************************/
u32 InitSD(const char *filename)
{
FRESULT rc;
TCHAR *path = "0:/"; /* Logical drive number is 0 */
/* Register volume work area, initialize device */
rc = f_mount(&fatfs, path, 0);
fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc);
if (rc != FR_OK) {
return XST_FAILURE;
}
strcpy_rom(buffer, filename);
boot_file = (char *)buffer;
FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR;
rc = f_open(&fil, boot_file, FA_READ);
if (rc) {
fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function provides the SD FLASH interface for the Simplified header
* functionality.
*
* @param SourceAddress is address in FLASH data space
* @param DestinationAddress is address in OCM data space
* @param LengthBytes is the number of bytes to move
*
* @return
* - XST_SUCCESS if the write completes correctly
* - XST_FAILURE if the write fails to completes correctly
*
* @note None.
*
****************************************************************************/
u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
FRESULT rc; /* Result code */
UINT br;
rc = f_lseek(&fil, SourceAddress);
if (rc) {
fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress);
return XST_FAILURE;
}
rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br);
if (rc) {
fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc);
}
return XST_SUCCESS;
} /* End of SDAccess */
/******************************************************************************/
/**
*
* This function closes the file object
*
* @param None
*
* @return None.
*
* @note None.
*
****************************************************************************/
void ReleaseSD(void) {
f_close(&fil);
return;
}
#endif
2.FW/Zynq/proj_cal/Vitis/FSBL/src/sd.h
+75
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/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file sd.h
*
* This file contains the interface for the Secure Digital (SD) card
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a bh 03/10/11 Initial release
* 7.00a kc 10/18/13 Integrated SD/MMC driver
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___SD_H___
#define ___SD_H___
#ifdef __cplusplus
extern "C" {
#endif
/************************** Function Prototypes ******************************/
#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
u32 InitSD(const char *);
u32 SDAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthWords);
void ReleaseSD(void);
#endif
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___SD_H___ */