Migrate to Vitis2023.2 version
This commit is contained in:
Jeremy Shen
@@ -0,0 +1,4 @@
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CompileFlags:
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Add: [-Wno-unknown-warning-option, -U__linux__, -U__clang__]
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Remove: [-m*, -f*]
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@@ -0,0 +1,80 @@
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# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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cmake_minimum_required(VERSION 3.15)
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set(APP_NAME fsbl)
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project(${APP_NAME})
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||||
include_directories(${CMAKE_BINARY_DIR}/include)
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include(${CMAKE_CURRENT_SOURCE_DIR}/UserConfig.cmake)
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find_package(common)
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enable_language(C ASM)
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collect(PROJECT_LIB_DEPS xiltimer;xilffs;xilrsa)
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collect(PROJECT_LIB_DEPS xilffs)
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collect(PROJECT_LIB_DEPS xilrsa)
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collect(PROJECT_LIB_DEPS xil)
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collect(PROJECT_LIB_DEPS xilstandalone)
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collect(PROJECT_LIB_DEPS gcc)
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collect(PROJECT_LIB_DEPS c)
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||||
|
||||
list (APPEND _deps ${USER_LINK_LIBRARIES})
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collector_list (_deps PROJECT_LIB_DEPS)
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||||
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||||
if(CMAKE_EXPORT_COMPILE_COMMANDS)
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||||
set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES})
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set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES})
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endif()
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||||
collector_create (PROJECT_LIB_HEADERS "${CMAKE_CURRENT_SOURCE_DIR}")
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collector_create (PROJECT_LIB_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}")
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collect (PROJECT_LIB_HEADERS fsbl_debug.h)
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collect (PROJECT_LIB_HEADERS fsbl.h)
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collect (PROJECT_LIB_HEADERS fsbl_hooks.h)
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collect (PROJECT_LIB_HEADERS image_mover.h)
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collect (PROJECT_LIB_HEADERS md5.h)
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collect (PROJECT_LIB_HEADERS nand.h)
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collect (PROJECT_LIB_HEADERS nor.h)
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collect (PROJECT_LIB_HEADERS pcap.h)
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collect (PROJECT_LIB_HEADERS qspi.h)
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collect (PROJECT_LIB_HEADERS rsa.h)
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collect (PROJECT_LIB_HEADERS sd.h)
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collect (PROJECT_LIB_HEADERS ps7_init.h)
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collect (PROJECT_LIB_SOURCES fsbl_hooks.c)
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collect (PROJECT_LIB_SOURCES image_mover.c)
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collect (PROJECT_LIB_SOURCES main.c)
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collect (PROJECT_LIB_SOURCES md5.c)
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collect (PROJECT_LIB_SOURCES nand.c)
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collect (PROJECT_LIB_SOURCES nor.c)
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collect (PROJECT_LIB_SOURCES pcap.c)
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collect (PROJECT_LIB_SOURCES qspi.c)
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collect (PROJECT_LIB_SOURCES rsa.c)
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collect (PROJECT_LIB_SOURCES sd.c)
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collect (PROJECT_LIB_SOURCES ps7_init.c)
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collector_list (_sources PROJECT_LIB_SOURCES)
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collector_list (_headers PROJECT_LIB_HEADERS)
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string(APPEND CMAKE_C_FLAGS ${USER_COMPILE_OPTIONS})
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string(APPEND CMAKE_CXX_FLAGS ${USER_COMPILE_OPTIONS})
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string(APPEND CMAKE_C_LINK_FLAGS ${USER_LINK_OPTIONS})
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string(APPEND CMAKE_CXX_LINK_FLAGS ${USER_LINK_OPTIONS})
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set_source_files_properties(${_sources} OBJECT_DEPENDS "${CMAKE_LIBRARY_PATH}/*.a")
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add_executable(${APP_NAME}.elf fsbl_handoff.S ${_sources})
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set_target_properties(${APP_NAME}.elf PROPERTIES LINK_DEPENDS ${CMAKE_SOURCE_DIR}/lscript.ld)
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target_link_libraries(${APP_NAME}.elf -Os -Wl,--gc-sections -n -T\"${CMAKE_SOURCE_DIR}/lscript.ld\" -L\"${CMAKE_LIBRARY_PATH}/\" -L\"${USER_LINK_DIRECTORIES}/\" -Wl,--start-group ${_deps} -Wl,--end-group)
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target_compile_definitions(${APP_NAME}.elf PUBLIC ${USER_COMPILE_DEFINITIONS})
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target_include_directories(${APP_NAME}.elf PUBLIC ${USER_INCLUDE_DIRECTORIES})
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print_elf_size(CMAKE_SIZE ${APP_NAME})
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@@ -0,0 +1,157 @@
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# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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cmake_minimum_required(VERSION 3.16)
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### USER SETTINGS START ###
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# Below settings can be customized
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||||
# User need to edit it manually as per their needs.
|
||||
### DO NOT ADD OR REMOVE VARIABLES FROM THIS SECTION ###
|
||||
# -----------------------------------------
|
||||
# Add any compiler definitions, they will be added as extra definitions
|
||||
# Example adding VERBOSE=1 will pass -DVERBOSE=1 to the compiler.
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set(USER_COMPILE_DEFINITIONS
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""
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)
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|
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# Undefine any previously specified compiler definitions, either built in or provided with a -D option
|
||||
# Example adding MY_SYMBOL will pass -UMY_SYMBOL to the compiler.
|
||||
set(USER_UNDEFINED_SYMBOLS
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"__clang__"
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)
|
||||
|
||||
|
||||
# Add any directories below, they will be added as extra include directories.
|
||||
# Example 1: Adding /proj/data/include will pass -I/proj/data/include
|
||||
# Example 2: Adding ../../common/include will consider the path as relative to this component directory.
|
||||
# Example 3: Adding ${CMAKE_SOURCE_DIR}/data/include to add data/include from this project.
|
||||
|
||||
set(USER_INCLUDE_DIRECTORIES
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)
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||||
|
||||
# -----------------------------------------
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|
||||
# Turn on all optional warnings (-Wall)
|
||||
set(USER_COMPILE_WARNINGS_ALL -Wall)
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|
||||
# Enable extra warning flags (-Wextra)
|
||||
set(USER_COMPILE_WARNINGS_EXTRA -Wextra)
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||||
|
||||
# Make all warnings into hard errors (-Werror)
|
||||
set(USER_COMPILE_WARNINGS_AS_ERRORS )
|
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|
||||
# Check the code for syntax errors, but don't do anything beyond that. (-fsyntax-only)
|
||||
set(USER_COMPILE_WARNINGS_CHECK_SYNTAX_ONLY )
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||||
|
||||
# Issue all the mandatory diagnostics listed in the C standard (-pedantic)
|
||||
set(USER_COMPILE_WARNINGS_PEDANTIC )
|
||||
|
||||
# Issue all the mandatory diagnostics, and make all mandatory diagnostics into errors. (-pedantic-errors)
|
||||
set(USER_COMPILE_WARNINGS_PEDANTIC_AS_ERRORS )
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|
||||
# Suppress all warnings (-w)
|
||||
set(USER_COMPILE_WARNINGS_INHIBIT_ALL )
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|
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# -----------------------------------------
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||||
|
||||
# Optimization level "-O0" [None] , "-O1" [Optimize] , "-O2" [Optimize More], "-O3" [Optimize Most] or "-Os" [Optimize Size]
|
||||
set(USER_COMPILE_OPTIMIZATION_LEVEL -O0)
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|
||||
# Other flags related to optimization
|
||||
set(USER_COMPILE_OPTIMIZATION_OTHER_FLAGS )
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||||
|
||||
# -----------------------------------------
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||||
|
||||
# Debug level "" [None], "-g1" [Minimum], "g2" [Default], "g3" [Maximim]
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||||
set(USER_COMPILE_DEBUG_LEVEL -g3)
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|
||||
# Other flags releated to debugging
|
||||
set(USER_COMPILE_DEBUG_OTHER_FLAGS )
|
||||
|
||||
# -----------------------------------------
|
||||
|
||||
# Enable Profiling (-pg) (This feature is not supported currently)
|
||||
# set(USER_COMPILE_PROFILING_ENABLE )
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||||
|
||||
# -----------------------------------------
|
||||
|
||||
# Verbose (-v)
|
||||
set(USER_COMPILE_VERBOSE )
|
||||
|
||||
# Support ANSI_PROGRAM (-ansi)
|
||||
set(USER_COMPILE_ANSI )
|
||||
|
||||
# Add any compiler options that are not covered by the above variables, they will be added as extra compiler options
|
||||
# To enable profiling -pg [ for gprof ] or -p [ for prof information ]
|
||||
set(USER_COMPILE_OTHER_FLAGS )
|
||||
|
||||
# -----------------------------------------
|
||||
|
||||
# Linker options
|
||||
# Do not use the standard system startup files when linking.
|
||||
# The standard system libraries are used normally, unless -nostdlib or -nodefaultlibs is used. (-nostartfiles)
|
||||
set(USER_LINK_NO_START_FILES )
|
||||
|
||||
# Do not use the standard system libraries when linking. (-nodefaultlibs)
|
||||
set(USER_LINK_NO_DEFAULT_LIBS )
|
||||
|
||||
# Do not use the standard system startup files or libraries when linking. (-nostdlib)
|
||||
set(USER_LINK_NO_STDLIB )
|
||||
|
||||
# Omit all symbol information (-s)
|
||||
set(USER_LINK_OMIT_ALL_SYMBOL_INFO )
|
||||
|
||||
|
||||
# -----------------------------------------
|
||||
|
||||
# Add any libraries to be linked below, they will be added as extra libraries.
|
||||
# User need to update USER_LINK_DIRECTORIES below with these library paths.
|
||||
set(USER_LINK_LIBRARIES
|
||||
)
|
||||
|
||||
# Add any directories to look for the libraries to be linked.
|
||||
# Example 1: Adding /proj/compression/lib will pass -L/proj/compression/lib to the linker.
|
||||
# Example adding Adding ../../common/lib will consider the path as relative to this directory. and will pass the path to -L option.
|
||||
set(USER_LINK_DIRECTORIES
|
||||
)
|
||||
|
||||
# -----------------------------------------
|
||||
|
||||
set(USER_LINKER_SCRIPT "${CMAKE_SOURCE_DIR}/lscript.ld")
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||||
|
||||
# Add linker options to be passed, they will be added as extra linker options
|
||||
# Example : adding -s will pass -s to the linker.
|
||||
set(USER_LINK_OTHER_FLAGS
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||||
)
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||||
|
||||
# -----------------------------------------
|
||||
|
||||
### END OF USER SETTINGS SECTION ###
|
||||
### DO NOT EDIT BEYOND THIS LINE ###
|
||||
|
||||
set(USER_COMPILE_OPTIONS
|
||||
" ${USER_COMPILE_WARNINGS_ALL}"
|
||||
" ${USER_COMPILE_WARNINGS_EXTRA}"
|
||||
" ${USER_COMPILE_WARNINGS_AS_ERRORS}"
|
||||
" ${USER_COMPILE_WARNINGS_CHECK_SYNTAX_ONLY}"
|
||||
" ${USER_COMPILE_WARNINGS_PEDANTIC}"
|
||||
" ${USER_COMPILE_WARNINGS_PEDANTIC_AS_ERRORS}"
|
||||
" ${USER_COMPILE_WARNINGS_INHIBIT_ALL}"
|
||||
" ${USER_COMPILE_OPTIMIZATION_LEVEL}"
|
||||
" ${USER_COMPILE_OPTIMIZATION_OTHER_FLAGS}"
|
||||
" ${USER_COMPILE_DEBUG_LEVEL}"
|
||||
" ${USER_COMPILE_DEBUG_OTHER_FLAGS}"
|
||||
" ${USER_COMPILE_VERBOSE}"
|
||||
" ${USER_COMPILE_ANSI}"
|
||||
" ${USER_COMPILE_OTHER_FLAGS}"
|
||||
)
|
||||
foreach(entry ${USER_UNDEFINED_SYMBOLS})
|
||||
list(APPEND USER_COMPILE_OPTIONS " -U${entry}")
|
||||
endforeach()
|
||||
|
||||
set(USER_LINK_OPTIONS
|
||||
" ${USER_LINKER_NO_START_FILES}"
|
||||
" ${USER_LINKER_NO_DEFAULT_LIBS}"
|
||||
" ${USER_LINKER_NO_STDLIB}"
|
||||
" ${USER_LINKER_OMIT_ALL_SYMBOL_INFO}"
|
||||
" ${USER_LINK_OTHER_FLAGS}"
|
||||
)
|
||||
@@ -0,0 +1,13 @@
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set(DDR ps7_ddr_0)
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||||
set(ps7_ddr_0 "0x100000;0x3ff00000")
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||||
set(ps7_ram_0 "0x0;0x30000")
|
||||
set(ps7_ram_1 "0xffff0000;0xfe00")
|
||||
set(TOTAL_MEM_CONTROLLERS "ps7_ddr_0;ps7_ram_0;ps7_ram_1")
|
||||
set(MEMORY_SECTION "MEMORY
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||||
{
|
||||
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3ff00000
|
||||
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
|
||||
ps7_ram_1 : ORIGIN = 0xffff0000, LENGTH = 0xfe00
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||||
}")
|
||||
set(STACK_SIZE 0x2000)
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||||
set(HEAP_SIZE 0x2000)
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||||
@@ -0,0 +1,3 @@
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domain_path: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp
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app_src_dir: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/sw_apps/zynq_fsbl
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template: zynq_fsbl
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@@ -0,0 +1,431 @@
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# This is the CMakeCache file.
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||||
# For build in directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/build
|
||||
# It was generated by CMake: /data/xilinx/Vitis/2023.2/tps/lnx64/cmake-3.24.2/bin/cmake
|
||||
# You can edit this file to change values found and used by cmake.
|
||||
# If you do not want to change any of the values, simply exit the editor.
|
||||
# If you do want to change a value, simply edit, save, and exit the editor.
|
||||
# The syntax for the file is as follows:
|
||||
# KEY:TYPE=VALUE
|
||||
# KEY is the name of a variable in the cache.
|
||||
# TYPE is a hint to GUIs for the type of VALUE, DO NOT EDIT TYPE!.
|
||||
# VALUE is the current value for the KEY.
|
||||
|
||||
########################
|
||||
# EXTERNAL cache entries
|
||||
########################
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||||
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||||
//Path to a program.
|
||||
CMAKE_ADDR2LINE:FILEPATH=/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-addr2line
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||||
|
||||
//Archiver
|
||||
CMAKE_AR:FILEPATH=arm-none-eabi-ar
|
||||
|
||||
//A wrapper around 'ar' adding the appropriate '--plugin' option
|
||||
// for the GCC compiler
|
||||
CMAKE_ASM_COMPILER_AR:FILEPATH=/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc-ar
|
||||
|
||||
//A wrapper around 'ranlib' adding the appropriate '--plugin' option
|
||||
// for the GCC compiler
|
||||
CMAKE_ASM_COMPILER_RANLIB:FILEPATH=/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc-ranlib
|
||||
|
||||
//ASMFLAGS
|
||||
CMAKE_ASM_FLAGS:STRING= -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -MMD -MP -specs=/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/Xilinx.spec -I/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include
|
||||
|
||||
//Flags used by the ASM compiler during DEBUG builds.
|
||||
CMAKE_ASM_FLAGS_DEBUG:STRING=-g
|
||||
|
||||
//Flags used by the ASM compiler during MINSIZEREL builds.
|
||||
CMAKE_ASM_FLAGS_MINSIZEREL:STRING=-Os -DNDEBUG
|
||||
|
||||
//Additional ASM FLAGS for release
|
||||
CMAKE_ASM_FLAGS_RELEASE:STRING=-DNDEBUG
|
||||
|
||||
//Flags used by the ASM compiler during RELWITHDEBINFO builds.
|
||||
CMAKE_ASM_FLAGS_RELWITHDEBINFO:STRING=-O2 -g -DNDEBUG
|
||||
|
||||
//Choose the type of build, options are: None Debug Release RelWithDebInfo
|
||||
// MinSizeRel ...
|
||||
CMAKE_BUILD_TYPE:STRING=
|
||||
|
||||
//Enable/Disable color output during build.
|
||||
CMAKE_COLOR_MAKEFILE:BOOL=ON
|
||||
|
||||
//A wrapper around 'ar' adding the appropriate '--plugin' option
|
||||
// for the GCC compiler
|
||||
CMAKE_CXX_COMPILER_AR:FILEPATH=/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc-ar
|
||||
|
||||
//A wrapper around 'ranlib' adding the appropriate '--plugin' option
|
||||
// for the GCC compiler
|
||||
CMAKE_CXX_COMPILER_RANLIB:FILEPATH=/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc-ranlib
|
||||
|
||||
//CXXFLAGS
|
||||
CMAKE_CXX_FLAGS:STRING= -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -MMD -MP -specs=/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/Xilinx.spec -I/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include
|
||||
|
||||
//Flags used by the CXX compiler during DEBUG builds.
|
||||
CMAKE_CXX_FLAGS_DEBUG:STRING=-g
|
||||
|
||||
//Flags used by the CXX compiler during MINSIZEREL builds.
|
||||
CMAKE_CXX_FLAGS_MINSIZEREL:STRING=-Os -DNDEBUG
|
||||
|
||||
//Additional CXXFLAGS for release
|
||||
CMAKE_CXX_FLAGS_RELEASE:STRING=-DNDEBUG
|
||||
|
||||
//Flags used by the CXX compiler during RELWITHDEBINFO builds.
|
||||
CMAKE_CXX_FLAGS_RELWITHDEBINFO:STRING=-O2 -g -DNDEBUG
|
||||
|
||||
//A wrapper around 'ar' adding the appropriate '--plugin' option
|
||||
// for the GCC compiler
|
||||
CMAKE_C_COMPILER_AR:FILEPATH=/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc-ar
|
||||
|
||||
//A wrapper around 'ranlib' adding the appropriate '--plugin' option
|
||||
// for the GCC compiler
|
||||
CMAKE_C_COMPILER_RANLIB:FILEPATH=/data/xilinx/Vitis/2023.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin/arm-none-eabi-gcc-ranlib
|
||||
|
||||
//CFLAGS
|
||||
CMAKE_C_FLAGS:STRING= -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -MMD -MP -specs=/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/Xilinx.spec -I/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include
|
||||
|
||||
//Flags used by the C compiler during DEBUG builds.
|
||||
CMAKE_C_FLAGS_DEBUG:STRING=-g
|
||||
|
||||
//Flags used by the C compiler during MINSIZEREL builds.
|
||||
CMAKE_C_FLAGS_MINSIZEREL:STRING=-Os -DNDEBUG
|
||||
|
||||
//Additional CFLAGS for release
|
||||
CMAKE_C_FLAGS_RELEASE:STRING=-DNDEBUG
|
||||
|
||||
//Flags used by the C compiler during RELWITHDEBINFO builds.
|
||||
CMAKE_C_FLAGS_RELWITHDEBINFO:STRING=-O2 -g -DNDEBUG
|
||||
|
||||
//Path to a program.
|
||||
CMAKE_DLLTOOL:FILEPATH=CMAKE_DLLTOOL-NOTFOUND
|
||||
|
||||
//Flags used by the linker during all build types.
|
||||
CMAKE_EXE_LINKER_FLAGS:STRING=
|
||||
|
||||
//Flags used by the linker during DEBUG builds.
|
||||
CMAKE_EXE_LINKER_FLAGS_DEBUG:STRING=
|
||||
|
||||
//Flags used by the linker during MINSIZEREL builds.
|
||||
CMAKE_EXE_LINKER_FLAGS_MINSIZEREL:STRING=
|
||||
|
||||
//Flags used by the linker during RELEASE builds.
|
||||
CMAKE_EXE_LINKER_FLAGS_RELEASE:STRING=
|
||||
|
||||
//Flags used by the linker during RELWITHDEBINFO builds.
|
||||
CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO:STRING=
|
||||
|
||||
//Value Computed by CMake.
|
||||
CMAKE_FIND_PACKAGE_REDIRECTS_DIR:STATIC=/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/build/CMakeFiles/pkgRedirects
|
||||
|
||||
//No help, variable specified on the command line.
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|
||||
#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER)
|
||||
# define COMPILER_ID "IntelLLVM"
|
||||
#if defined(_MSC_VER)
|
||||
# define SIMULATE_ID "MSVC"
|
||||
#endif
|
||||
#if defined(__GNUC__)
|
||||
# define SIMULATE_ID "GNU"
|
||||
#endif
|
||||
/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and
|
||||
* later. Look for 6 digit vs. 8 digit version number to decide encoding.
|
||||
* VVVV is no smaller than the current year when a version is released.
|
||||
*/
|
||||
#if __INTEL_LLVM_COMPILER < 1000000L
|
||||
# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10)
|
||||
#else
|
||||
# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100)
|
||||
#endif
|
||||
#if defined(_MSC_VER)
|
||||
/* _MSC_VER = VVRR */
|
||||
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
#endif
|
||||
#if defined(__GNUC__)
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
|
||||
#elif defined(__GNUG__)
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUG__)
|
||||
#endif
|
||||
#if defined(__GNUC_MINOR__)
|
||||
# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
|
||||
#endif
|
||||
#if defined(__GNUC_PATCHLEVEL__)
|
||||
# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
|
||||
#endif
|
||||
|
||||
#elif defined(__PATHCC__)
|
||||
# define COMPILER_ID "PathScale"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__PATHCC__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__)
|
||||
# if defined(__PATHCC_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__)
|
||||
# define COMPILER_ID "Embarcadero"
|
||||
# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF)
|
||||
# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF)
|
||||
# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF)
|
||||
|
||||
#elif defined(__BORLANDC__)
|
||||
# define COMPILER_ID "Borland"
|
||||
/* __BORLANDC__ = 0xVRR */
|
||||
# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8)
|
||||
# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF)
|
||||
|
||||
#elif defined(__WATCOMC__) && __WATCOMC__ < 1200
|
||||
# define COMPILER_ID "Watcom"
|
||||
/* __WATCOMC__ = VVRR */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
|
||||
# if (__WATCOMC__ % 10) > 0
|
||||
# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
|
||||
# endif
|
||||
|
||||
#elif defined(__WATCOMC__)
|
||||
# define COMPILER_ID "OpenWatcom"
|
||||
/* __WATCOMC__ = VVRP + 1100 */
|
||||
# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
|
||||
# if (__WATCOMC__ % 10) > 0
|
||||
# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
|
||||
# endif
|
||||
|
||||
#elif defined(__SUNPRO_C)
|
||||
# define COMPILER_ID "SunPro"
|
||||
# if __SUNPRO_C >= 0x5100
|
||||
/* __SUNPRO_C = 0xVRRP */
|
||||
# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>12)
|
||||
# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xFF)
|
||||
# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF)
|
||||
# else
|
||||
/* __SUNPRO_CC = 0xVRP */
|
||||
# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>8)
|
||||
# define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xF)
|
||||
# define COMPILER_VERSION_PATCH HEX(__SUNPRO_C & 0xF)
|
||||
# endif
|
||||
|
||||
#elif defined(__HP_cc)
|
||||
# define COMPILER_ID "HP"
|
||||
/* __HP_cc = VVRRPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__HP_cc/10000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__HP_cc/100 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__HP_cc % 100)
|
||||
|
||||
#elif defined(__DECC)
|
||||
# define COMPILER_ID "Compaq"
|
||||
/* __DECC_VER = VVRRTPPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__DECC_VER/10000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__DECC_VER/100000 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__DECC_VER % 10000)
|
||||
|
||||
#elif defined(__IBMC__) && defined(__COMPILER_VER__)
|
||||
# define COMPILER_ID "zOS"
|
||||
/* __IBMC__ = VRP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10)
|
||||
|
||||
#elif defined(__open_xl__) && defined(__clang__)
|
||||
# define COMPILER_ID "IBMClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__open_xl_release__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__)
|
||||
# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__)
|
||||
|
||||
|
||||
#elif defined(__ibmxl__) && defined(__clang__)
|
||||
# define COMPILER_ID "XLClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__)
|
||||
# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__)
|
||||
|
||||
|
||||
#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800
|
||||
# define COMPILER_ID "XL"
|
||||
/* __IBMC__ = VRP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10)
|
||||
|
||||
#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800
|
||||
# define COMPILER_ID "VisualAge"
|
||||
/* __IBMC__ = VRP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__IBMC__ % 10)
|
||||
|
||||
#elif defined(__NVCOMPILER)
|
||||
# define COMPILER_ID "NVHPC"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__)
|
||||
# if defined(__NVCOMPILER_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(__PGI)
|
||||
# define COMPILER_ID "PGI"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__PGIC__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__)
|
||||
# if defined(__PGIC_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(_CRAYC)
|
||||
# define COMPILER_ID "Cray"
|
||||
# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR)
|
||||
# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR)
|
||||
|
||||
#elif defined(__TI_COMPILER_VERSION__)
|
||||
# define COMPILER_ID "TI"
|
||||
/* __TI_COMPILER_VERSION__ = VVVRRRPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000)
|
||||
# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000)
|
||||
|
||||
#elif defined(__CLANG_FUJITSU)
|
||||
# define COMPILER_ID "FujitsuClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
|
||||
# define COMPILER_VERSION_INTERNAL_STR __clang_version__
|
||||
|
||||
|
||||
#elif defined(__FUJITSU)
|
||||
# define COMPILER_ID "Fujitsu"
|
||||
# if defined(__FCC_version__)
|
||||
# define COMPILER_VERSION __FCC_version__
|
||||
# elif defined(__FCC_major__)
|
||||
# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
|
||||
# endif
|
||||
# if defined(__fcc_version)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__fcc_version)
|
||||
# elif defined(__FCC_VERSION)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION)
|
||||
# endif
|
||||
|
||||
|
||||
#elif defined(__ghs__)
|
||||
# define COMPILER_ID "GHS"
|
||||
/* __GHS_VERSION_NUMBER = VVVVRP */
|
||||
# ifdef __GHS_VERSION_NUMBER
|
||||
# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10)
|
||||
# endif
|
||||
|
||||
#elif defined(__TINYC__)
|
||||
# define COMPILER_ID "TinyCC"
|
||||
|
||||
#elif defined(__BCC__)
|
||||
# define COMPILER_ID "Bruce"
|
||||
|
||||
#elif defined(__SCO_VERSION__)
|
||||
# define COMPILER_ID "SCO"
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && !defined(__clang__)
|
||||
# define COMPILER_ID "ARMCC"
|
||||
#if __ARMCC_VERSION >= 1000000
|
||||
/* __ARMCC_VERSION = VRRPPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
|
||||
#else
|
||||
/* __ARMCC_VERSION = VRPPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
|
||||
#endif
|
||||
|
||||
|
||||
#elif defined(__clang__) && defined(__apple_build_version__)
|
||||
# define COMPILER_ID "AppleClang"
|
||||
# if defined(_MSC_VER)
|
||||
# define SIMULATE_ID "MSVC"
|
||||
# endif
|
||||
# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
|
||||
# if defined(_MSC_VER)
|
||||
/* _MSC_VER = VVRR */
|
||||
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
# endif
|
||||
# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
|
||||
|
||||
#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
|
||||
# define COMPILER_ID "ARMClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION % 10000)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
|
||||
|
||||
#elif defined(__clang__)
|
||||
# define COMPILER_ID "Clang"
|
||||
# if defined(_MSC_VER)
|
||||
# define SIMULATE_ID "MSVC"
|
||||
# endif
|
||||
# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
|
||||
# if defined(_MSC_VER)
|
||||
/* _MSC_VER = VVRR */
|
||||
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
# endif
|
||||
|
||||
#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__))
|
||||
# define COMPILER_ID "LCC"
|
||||
# define COMPILER_VERSION_MAJOR DEC(1)
|
||||
# if defined(__LCC__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__LCC__- 100)
|
||||
# endif
|
||||
# if defined(__LCC_MINOR__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__)
|
||||
# endif
|
||||
# if defined(__GNUC__) && defined(__GNUC_MINOR__)
|
||||
# define SIMULATE_ID "GNU"
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
|
||||
# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
|
||||
# if defined(__GNUC_PATCHLEVEL__)
|
||||
# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
|
||||
# endif
|
||||
# endif
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
# define COMPILER_ID "GNU"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__GNUC__)
|
||||
# if defined(__GNUC_MINOR__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
|
||||
# endif
|
||||
# if defined(__GNUC_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(_MSC_VER)
|
||||
# define COMPILER_ID "MSVC"
|
||||
/* _MSC_VER = VVRR */
|
||||
# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
# if defined(_MSC_FULL_VER)
|
||||
# if _MSC_VER >= 1400
|
||||
/* _MSC_FULL_VER = VVRRPPPPP */
|
||||
# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
|
||||
# else
|
||||
/* _MSC_FULL_VER = VVRRPPPP */
|
||||
# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
|
||||
# endif
|
||||
# endif
|
||||
# if defined(_MSC_BUILD)
|
||||
# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
|
||||
# endif
|
||||
|
||||
#elif defined(_ADI_COMPILER)
|
||||
# define COMPILER_ID "ADSP"
|
||||
#if defined(__VERSIONNUM__)
|
||||
/* __VERSIONNUM__ = 0xVVRRPPTT */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF)
|
||||
# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF)
|
||||
# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF)
|
||||
# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF)
|
||||
#endif
|
||||
|
||||
#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
|
||||
# define COMPILER_ID "IAR"
|
||||
# if defined(__VER__) && defined(__ICCARM__)
|
||||
# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
|
||||
# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
|
||||
# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__))
|
||||
# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
|
||||
# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
|
||||
# endif
|
||||
|
||||
#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC)
|
||||
# define COMPILER_ID "SDCC"
|
||||
# if defined(__SDCC_VERSION_MAJOR)
|
||||
# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR)
|
||||
# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR)
|
||||
# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH)
|
||||
# else
|
||||
/* SDCC = VRP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(SDCC/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(SDCC % 10)
|
||||
# endif
|
||||
|
||||
|
||||
/* These compilers are either not known or too old to define an
|
||||
identification macro. Try to identify the platform and guess that
|
||||
it is the native compiler. */
|
||||
#elif defined(__hpux) || defined(__hpua)
|
||||
# define COMPILER_ID "HP"
|
||||
|
||||
#else /* unknown compiler */
|
||||
# define COMPILER_ID ""
|
||||
#endif
|
||||
|
||||
/* Construct the string literal in pieces to prevent the source from
|
||||
getting matched. Store it in a pointer rather than an array
|
||||
because some compilers will just produce instructions to fill the
|
||||
array rather than assigning a pointer to a static array. */
|
||||
char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
|
||||
#ifdef SIMULATE_ID
|
||||
char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
|
||||
#endif
|
||||
|
||||
#ifdef __QNXNTO__
|
||||
char const* qnxnto = "INFO" ":" "qnxnto[]";
|
||||
#endif
|
||||
|
||||
#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
|
||||
char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
|
||||
#endif
|
||||
|
||||
#define STRINGIFY_HELPER(X) #X
|
||||
#define STRINGIFY(X) STRINGIFY_HELPER(X)
|
||||
|
||||
/* Identify known platforms by name. */
|
||||
#if defined(__linux) || defined(__linux__) || defined(linux)
|
||||
# define PLATFORM_ID "Linux"
|
||||
|
||||
#elif defined(__MSYS__)
|
||||
# define PLATFORM_ID "MSYS"
|
||||
|
||||
#elif defined(__CYGWIN__)
|
||||
# define PLATFORM_ID "Cygwin"
|
||||
|
||||
#elif defined(__MINGW32__)
|
||||
# define PLATFORM_ID "MinGW"
|
||||
|
||||
#elif defined(__APPLE__)
|
||||
# define PLATFORM_ID "Darwin"
|
||||
|
||||
#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
|
||||
# define PLATFORM_ID "Windows"
|
||||
|
||||
#elif defined(__FreeBSD__) || defined(__FreeBSD)
|
||||
# define PLATFORM_ID "FreeBSD"
|
||||
|
||||
#elif defined(__NetBSD__) || defined(__NetBSD)
|
||||
# define PLATFORM_ID "NetBSD"
|
||||
|
||||
#elif defined(__OpenBSD__) || defined(__OPENBSD)
|
||||
# define PLATFORM_ID "OpenBSD"
|
||||
|
||||
#elif defined(__sun) || defined(sun)
|
||||
# define PLATFORM_ID "SunOS"
|
||||
|
||||
#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
|
||||
# define PLATFORM_ID "AIX"
|
||||
|
||||
#elif defined(__hpux) || defined(__hpux__)
|
||||
# define PLATFORM_ID "HP-UX"
|
||||
|
||||
#elif defined(__HAIKU__)
|
||||
# define PLATFORM_ID "Haiku"
|
||||
|
||||
#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
|
||||
# define PLATFORM_ID "BeOS"
|
||||
|
||||
#elif defined(__QNX__) || defined(__QNXNTO__)
|
||||
# define PLATFORM_ID "QNX"
|
||||
|
||||
#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
|
||||
# define PLATFORM_ID "Tru64"
|
||||
|
||||
#elif defined(__riscos) || defined(__riscos__)
|
||||
# define PLATFORM_ID "RISCos"
|
||||
|
||||
#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
|
||||
# define PLATFORM_ID "SINIX"
|
||||
|
||||
#elif defined(__UNIX_SV__)
|
||||
# define PLATFORM_ID "UNIX_SV"
|
||||
|
||||
#elif defined(__bsdos__)
|
||||
# define PLATFORM_ID "BSDOS"
|
||||
|
||||
#elif defined(_MPRAS) || defined(MPRAS)
|
||||
# define PLATFORM_ID "MP-RAS"
|
||||
|
||||
#elif defined(__osf) || defined(__osf__)
|
||||
# define PLATFORM_ID "OSF1"
|
||||
|
||||
#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv)
|
||||
# define PLATFORM_ID "SCO_SV"
|
||||
|
||||
#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
|
||||
# define PLATFORM_ID "ULTRIX"
|
||||
|
||||
#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
|
||||
# define PLATFORM_ID "Xenix"
|
||||
|
||||
#elif defined(__WATCOMC__)
|
||||
# if defined(__LINUX__)
|
||||
# define PLATFORM_ID "Linux"
|
||||
|
||||
# elif defined(__DOS__)
|
||||
# define PLATFORM_ID "DOS"
|
||||
|
||||
# elif defined(__OS2__)
|
||||
# define PLATFORM_ID "OS2"
|
||||
|
||||
# elif defined(__WINDOWS__)
|
||||
# define PLATFORM_ID "Windows3x"
|
||||
|
||||
# elif defined(__VXWORKS__)
|
||||
# define PLATFORM_ID "VxWorks"
|
||||
|
||||
# else /* unknown platform */
|
||||
# define PLATFORM_ID
|
||||
# endif
|
||||
|
||||
#elif defined(__INTEGRITY)
|
||||
# if defined(INT_178B)
|
||||
# define PLATFORM_ID "Integrity178"
|
||||
|
||||
# else /* regular Integrity */
|
||||
# define PLATFORM_ID "Integrity"
|
||||
# endif
|
||||
|
||||
# elif defined(_ADI_COMPILER)
|
||||
# define PLATFORM_ID "ADSP"
|
||||
|
||||
#else /* unknown platform */
|
||||
# define PLATFORM_ID
|
||||
|
||||
#endif
|
||||
|
||||
/* For windows compilers MSVC and Intel we can determine
|
||||
the architecture of the compiler being used. This is because
|
||||
the compilers do not have flags that can change the architecture,
|
||||
but rather depend on which compiler is being used
|
||||
*/
|
||||
#if defined(_WIN32) && defined(_MSC_VER)
|
||||
# if defined(_M_IA64)
|
||||
# define ARCHITECTURE_ID "IA64"
|
||||
|
||||
# elif defined(_M_ARM64EC)
|
||||
# define ARCHITECTURE_ID "ARM64EC"
|
||||
|
||||
# elif defined(_M_X64) || defined(_M_AMD64)
|
||||
# define ARCHITECTURE_ID "x64"
|
||||
|
||||
# elif defined(_M_IX86)
|
||||
# define ARCHITECTURE_ID "X86"
|
||||
|
||||
# elif defined(_M_ARM64)
|
||||
# define ARCHITECTURE_ID "ARM64"
|
||||
|
||||
# elif defined(_M_ARM)
|
||||
# if _M_ARM == 4
|
||||
# define ARCHITECTURE_ID "ARMV4I"
|
||||
# elif _M_ARM == 5
|
||||
# define ARCHITECTURE_ID "ARMV5I"
|
||||
# else
|
||||
# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
|
||||
# endif
|
||||
|
||||
# elif defined(_M_MIPS)
|
||||
# define ARCHITECTURE_ID "MIPS"
|
||||
|
||||
# elif defined(_M_SH)
|
||||
# define ARCHITECTURE_ID "SHx"
|
||||
|
||||
# else /* unknown architecture */
|
||||
# define ARCHITECTURE_ID ""
|
||||
# endif
|
||||
|
||||
#elif defined(__WATCOMC__)
|
||||
# if defined(_M_I86)
|
||||
# define ARCHITECTURE_ID "I86"
|
||||
|
||||
# elif defined(_M_IX86)
|
||||
# define ARCHITECTURE_ID "X86"
|
||||
|
||||
# else /* unknown architecture */
|
||||
# define ARCHITECTURE_ID ""
|
||||
# endif
|
||||
|
||||
#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
|
||||
# if defined(__ICCARM__)
|
||||
# define ARCHITECTURE_ID "ARM"
|
||||
|
||||
# elif defined(__ICCRX__)
|
||||
# define ARCHITECTURE_ID "RX"
|
||||
|
||||
# elif defined(__ICCRH850__)
|
||||
# define ARCHITECTURE_ID "RH850"
|
||||
|
||||
# elif defined(__ICCRL78__)
|
||||
# define ARCHITECTURE_ID "RL78"
|
||||
|
||||
# elif defined(__ICCRISCV__)
|
||||
# define ARCHITECTURE_ID "RISCV"
|
||||
|
||||
# elif defined(__ICCAVR__)
|
||||
# define ARCHITECTURE_ID "AVR"
|
||||
|
||||
# elif defined(__ICC430__)
|
||||
# define ARCHITECTURE_ID "MSP430"
|
||||
|
||||
# elif defined(__ICCV850__)
|
||||
# define ARCHITECTURE_ID "V850"
|
||||
|
||||
# elif defined(__ICC8051__)
|
||||
# define ARCHITECTURE_ID "8051"
|
||||
|
||||
# elif defined(__ICCSTM8__)
|
||||
# define ARCHITECTURE_ID "STM8"
|
||||
|
||||
# else /* unknown architecture */
|
||||
# define ARCHITECTURE_ID ""
|
||||
# endif
|
||||
|
||||
#elif defined(__ghs__)
|
||||
# if defined(__PPC64__)
|
||||
# define ARCHITECTURE_ID "PPC64"
|
||||
|
||||
# elif defined(__ppc__)
|
||||
# define ARCHITECTURE_ID "PPC"
|
||||
|
||||
# elif defined(__ARM__)
|
||||
# define ARCHITECTURE_ID "ARM"
|
||||
|
||||
# elif defined(__x86_64__)
|
||||
# define ARCHITECTURE_ID "x64"
|
||||
|
||||
# elif defined(__i386__)
|
||||
# define ARCHITECTURE_ID "X86"
|
||||
|
||||
# else /* unknown architecture */
|
||||
# define ARCHITECTURE_ID ""
|
||||
# endif
|
||||
|
||||
#elif defined(__TI_COMPILER_VERSION__)
|
||||
# if defined(__TI_ARM__)
|
||||
# define ARCHITECTURE_ID "ARM"
|
||||
|
||||
# elif defined(__MSP430__)
|
||||
# define ARCHITECTURE_ID "MSP430"
|
||||
|
||||
# elif defined(__TMS320C28XX__)
|
||||
# define ARCHITECTURE_ID "TMS320C28x"
|
||||
|
||||
# elif defined(__TMS320C6X__) || defined(_TMS320C6X)
|
||||
# define ARCHITECTURE_ID "TMS320C6x"
|
||||
|
||||
# else /* unknown architecture */
|
||||
# define ARCHITECTURE_ID ""
|
||||
# endif
|
||||
|
||||
# elif defined(__ADSPSHARC__)
|
||||
# define ARCHITECTURE_ID "SHARC"
|
||||
|
||||
# elif defined(__ADSPBLACKFIN__)
|
||||
# define ARCHITECTURE_ID "Blackfin"
|
||||
|
||||
#else
|
||||
# define ARCHITECTURE_ID
|
||||
#endif
|
||||
|
||||
/* Convert integer to decimal digit literals. */
|
||||
#define DEC(n) \
|
||||
('0' + (((n) / 10000000)%10)), \
|
||||
('0' + (((n) / 1000000)%10)), \
|
||||
('0' + (((n) / 100000)%10)), \
|
||||
('0' + (((n) / 10000)%10)), \
|
||||
('0' + (((n) / 1000)%10)), \
|
||||
('0' + (((n) / 100)%10)), \
|
||||
('0' + (((n) / 10)%10)), \
|
||||
('0' + ((n) % 10))
|
||||
|
||||
/* Convert integer to hex digit literals. */
|
||||
#define HEX(n) \
|
||||
('0' + ((n)>>28 & 0xF)), \
|
||||
('0' + ((n)>>24 & 0xF)), \
|
||||
('0' + ((n)>>20 & 0xF)), \
|
||||
('0' + ((n)>>16 & 0xF)), \
|
||||
('0' + ((n)>>12 & 0xF)), \
|
||||
('0' + ((n)>>8 & 0xF)), \
|
||||
('0' + ((n)>>4 & 0xF)), \
|
||||
('0' + ((n) & 0xF))
|
||||
|
||||
/* Construct a string literal encoding the version number. */
|
||||
#ifdef COMPILER_VERSION
|
||||
char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]";
|
||||
|
||||
/* Construct a string literal encoding the version number components. */
|
||||
#elif defined(COMPILER_VERSION_MAJOR)
|
||||
char const info_version[] = {
|
||||
'I', 'N', 'F', 'O', ':',
|
||||
'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[',
|
||||
COMPILER_VERSION_MAJOR,
|
||||
# ifdef COMPILER_VERSION_MINOR
|
||||
'.', COMPILER_VERSION_MINOR,
|
||||
# ifdef COMPILER_VERSION_PATCH
|
||||
'.', COMPILER_VERSION_PATCH,
|
||||
# ifdef COMPILER_VERSION_TWEAK
|
||||
'.', COMPILER_VERSION_TWEAK,
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
']','\0'};
|
||||
#endif
|
||||
|
||||
/* Construct a string literal encoding the internal version number. */
|
||||
#ifdef COMPILER_VERSION_INTERNAL
|
||||
char const info_version_internal[] = {
|
||||
'I', 'N', 'F', 'O', ':',
|
||||
'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_',
|
||||
'i','n','t','e','r','n','a','l','[',
|
||||
COMPILER_VERSION_INTERNAL,']','\0'};
|
||||
#elif defined(COMPILER_VERSION_INTERNAL_STR)
|
||||
char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]";
|
||||
#endif
|
||||
|
||||
/* Construct a string literal encoding the version number components. */
|
||||
#ifdef SIMULATE_VERSION_MAJOR
|
||||
char const info_simulate_version[] = {
|
||||
'I', 'N', 'F', 'O', ':',
|
||||
's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[',
|
||||
SIMULATE_VERSION_MAJOR,
|
||||
# ifdef SIMULATE_VERSION_MINOR
|
||||
'.', SIMULATE_VERSION_MINOR,
|
||||
# ifdef SIMULATE_VERSION_PATCH
|
||||
'.', SIMULATE_VERSION_PATCH,
|
||||
# ifdef SIMULATE_VERSION_TWEAK
|
||||
'.', SIMULATE_VERSION_TWEAK,
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
']','\0'};
|
||||
#endif
|
||||
|
||||
/* Construct the string literal in pieces to prevent the source from
|
||||
getting matched. Store it in a pointer rather than an array
|
||||
because some compilers will just produce instructions to fill the
|
||||
array rather than assigning a pointer to a static array. */
|
||||
char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]";
|
||||
char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]";
|
||||
|
||||
|
||||
|
||||
#if !defined(__STDC__) && !defined(__clang__)
|
||||
# if defined(_MSC_VER) || defined(__ibmxl__) || defined(__IBMC__)
|
||||
# define C_VERSION "90"
|
||||
# else
|
||||
# define C_VERSION
|
||||
# endif
|
||||
#elif __STDC_VERSION__ > 201710L
|
||||
# define C_VERSION "23"
|
||||
#elif __STDC_VERSION__ >= 201710L
|
||||
# define C_VERSION "17"
|
||||
#elif __STDC_VERSION__ >= 201000L
|
||||
# define C_VERSION "11"
|
||||
#elif __STDC_VERSION__ >= 199901L
|
||||
# define C_VERSION "99"
|
||||
#else
|
||||
# define C_VERSION "90"
|
||||
#endif
|
||||
const char* info_language_standard_default =
|
||||
"INFO" ":" "standard_default[" C_VERSION "]";
|
||||
|
||||
const char* info_language_extensions_default = "INFO" ":" "extensions_default["
|
||||
#if (defined(__clang__) || defined(__GNUC__) || defined(__xlC__) || \
|
||||
defined(__TI_COMPILER_VERSION__)) && \
|
||||
!defined(__STRICT_ANSI__)
|
||||
"ON"
|
||||
#else
|
||||
"OFF"
|
||||
#endif
|
||||
"]";
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef ID_VOID_MAIN
|
||||
void main() {}
|
||||
#else
|
||||
# if defined(__CLASSIC_C__)
|
||||
int main(argc, argv) int argc; char *argv[];
|
||||
# else
|
||||
int main(int argc, char* argv[])
|
||||
# endif
|
||||
{
|
||||
int require = 0;
|
||||
require += info_compiler[argc];
|
||||
require += info_platform[argc];
|
||||
require += info_arch[argc];
|
||||
#ifdef COMPILER_VERSION_MAJOR
|
||||
require += info_version[argc];
|
||||
#endif
|
||||
#ifdef COMPILER_VERSION_INTERNAL
|
||||
require += info_version_internal[argc];
|
||||
#endif
|
||||
#ifdef SIMULATE_ID
|
||||
require += info_simulate[argc];
|
||||
#endif
|
||||
#ifdef SIMULATE_VERSION_MAJOR
|
||||
require += info_simulate_version[argc];
|
||||
#endif
|
||||
#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
|
||||
require += info_cray[argc];
|
||||
#endif
|
||||
require += info_language_standard_default[argc];
|
||||
require += info_language_extensions_default[argc];
|
||||
(void)argv;
|
||||
return require;
|
||||
}
|
||||
#endif
|
||||
Executable
BIN
Binary file not shown.
+826
@@ -0,0 +1,826 @@
|
||||
/* This source file must have a .cpp extension so that all C++ compilers
|
||||
recognize the extension without flags. Borland does not know .cxx for
|
||||
example. */
|
||||
#ifndef __cplusplus
|
||||
# error "A C compiler has been selected for C++."
|
||||
#endif
|
||||
|
||||
#if !defined(__has_include)
|
||||
/* If the compiler does not have __has_include, pretend the answer is
|
||||
always no. */
|
||||
# define __has_include(x) 0
|
||||
#endif
|
||||
|
||||
|
||||
/* Version number components: V=Version, R=Revision, P=Patch
|
||||
Version date components: YYYY=Year, MM=Month, DD=Day */
|
||||
|
||||
#if defined(__COMO__)
|
||||
# define COMPILER_ID "Comeau"
|
||||
/* __COMO_VERSION__ = VRR */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__COMO_VERSION__ / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__COMO_VERSION__ % 100)
|
||||
|
||||
#elif defined(__INTEL_COMPILER) || defined(__ICC)
|
||||
# define COMPILER_ID "Intel"
|
||||
# if defined(_MSC_VER)
|
||||
# define SIMULATE_ID "MSVC"
|
||||
# endif
|
||||
# if defined(__GNUC__)
|
||||
# define SIMULATE_ID "GNU"
|
||||
# endif
|
||||
/* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later,
|
||||
except that a few beta releases use the old format with V=2021. */
|
||||
# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111
|
||||
# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10)
|
||||
# if defined(__INTEL_COMPILER_UPDATE)
|
||||
# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE)
|
||||
# else
|
||||
# define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER % 10)
|
||||
# endif
|
||||
# else
|
||||
# define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER)
|
||||
# define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE)
|
||||
/* The third version component from --version is an update index,
|
||||
but no macro is provided for it. */
|
||||
# define COMPILER_VERSION_PATCH DEC(0)
|
||||
# endif
|
||||
# if defined(__INTEL_COMPILER_BUILD_DATE)
|
||||
/* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */
|
||||
# define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE)
|
||||
# endif
|
||||
# if defined(_MSC_VER)
|
||||
/* _MSC_VER = VVRR */
|
||||
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
# endif
|
||||
# if defined(__GNUC__)
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
|
||||
# elif defined(__GNUG__)
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUG__)
|
||||
# endif
|
||||
# if defined(__GNUC_MINOR__)
|
||||
# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
|
||||
# endif
|
||||
# if defined(__GNUC_PATCHLEVEL__)
|
||||
# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER)
|
||||
# define COMPILER_ID "IntelLLVM"
|
||||
#if defined(_MSC_VER)
|
||||
# define SIMULATE_ID "MSVC"
|
||||
#endif
|
||||
#if defined(__GNUC__)
|
||||
# define SIMULATE_ID "GNU"
|
||||
#endif
|
||||
/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and
|
||||
* later. Look for 6 digit vs. 8 digit version number to decide encoding.
|
||||
* VVVV is no smaller than the current year when a version is released.
|
||||
*/
|
||||
#if __INTEL_LLVM_COMPILER < 1000000L
|
||||
# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 10)
|
||||
#else
|
||||
# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER % 100)
|
||||
#endif
|
||||
#if defined(_MSC_VER)
|
||||
/* _MSC_VER = VVRR */
|
||||
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
#endif
|
||||
#if defined(__GNUC__)
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
|
||||
#elif defined(__GNUG__)
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUG__)
|
||||
#endif
|
||||
#if defined(__GNUC_MINOR__)
|
||||
# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
|
||||
#endif
|
||||
#if defined(__GNUC_PATCHLEVEL__)
|
||||
# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
|
||||
#endif
|
||||
|
||||
#elif defined(__PATHCC__)
|
||||
# define COMPILER_ID "PathScale"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__PATHCC__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__)
|
||||
# if defined(__PATHCC_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__)
|
||||
# define COMPILER_ID "Embarcadero"
|
||||
# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF)
|
||||
# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF)
|
||||
# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__ & 0xFFFF)
|
||||
|
||||
#elif defined(__BORLANDC__)
|
||||
# define COMPILER_ID "Borland"
|
||||
/* __BORLANDC__ = 0xVRR */
|
||||
# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8)
|
||||
# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF)
|
||||
|
||||
#elif defined(__WATCOMC__) && __WATCOMC__ < 1200
|
||||
# define COMPILER_ID "Watcom"
|
||||
/* __WATCOMC__ = VVRR */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
|
||||
# if (__WATCOMC__ % 10) > 0
|
||||
# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
|
||||
# endif
|
||||
|
||||
#elif defined(__WATCOMC__)
|
||||
# define COMPILER_ID "OpenWatcom"
|
||||
/* __WATCOMC__ = VVRP + 1100 */
|
||||
# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
|
||||
# if (__WATCOMC__ % 10) > 0
|
||||
# define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
|
||||
# endif
|
||||
|
||||
#elif defined(__SUNPRO_CC)
|
||||
# define COMPILER_ID "SunPro"
|
||||
# if __SUNPRO_CC >= 0x5100
|
||||
/* __SUNPRO_CC = 0xVRRP */
|
||||
# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>12)
|
||||
# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xFF)
|
||||
# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF)
|
||||
# else
|
||||
/* __SUNPRO_CC = 0xVRP */
|
||||
# define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>8)
|
||||
# define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xF)
|
||||
# define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC & 0xF)
|
||||
# endif
|
||||
|
||||
#elif defined(__HP_aCC)
|
||||
# define COMPILER_ID "HP"
|
||||
/* __HP_aCC = VVRRPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__HP_aCC/10000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__HP_aCC/100 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__HP_aCC % 100)
|
||||
|
||||
#elif defined(__DECCXX)
|
||||
# define COMPILER_ID "Compaq"
|
||||
/* __DECCXX_VER = VVRRTPPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__DECCXX_VER/10000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__DECCXX_VER/100000 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__DECCXX_VER % 10000)
|
||||
|
||||
#elif defined(__IBMCPP__) && defined(__COMPILER_VER__)
|
||||
# define COMPILER_ID "zOS"
|
||||
/* __IBMCPP__ = VRP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10)
|
||||
|
||||
#elif defined(__open_xl__) && defined(__clang__)
|
||||
# define COMPILER_ID "IBMClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__open_xl_release__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__)
|
||||
# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__)
|
||||
|
||||
|
||||
#elif defined(__ibmxl__) && defined(__clang__)
|
||||
# define COMPILER_ID "XLClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__)
|
||||
# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__)
|
||||
|
||||
|
||||
#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800
|
||||
# define COMPILER_ID "XL"
|
||||
/* __IBMCPP__ = VRP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10)
|
||||
|
||||
#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800
|
||||
# define COMPILER_ID "VisualAge"
|
||||
/* __IBMCPP__ = VRP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10)
|
||||
|
||||
#elif defined(__NVCOMPILER)
|
||||
# define COMPILER_ID "NVHPC"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__)
|
||||
# if defined(__NVCOMPILER_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(__PGI)
|
||||
# define COMPILER_ID "PGI"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__PGIC__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__)
|
||||
# if defined(__PGIC_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(_CRAYC)
|
||||
# define COMPILER_ID "Cray"
|
||||
# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR)
|
||||
# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR)
|
||||
|
||||
#elif defined(__TI_COMPILER_VERSION__)
|
||||
# define COMPILER_ID "TI"
|
||||
/* __TI_COMPILER_VERSION__ = VVVRRRPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000)
|
||||
# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000)
|
||||
|
||||
#elif defined(__CLANG_FUJITSU)
|
||||
# define COMPILER_ID "FujitsuClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
|
||||
# define COMPILER_VERSION_INTERNAL_STR __clang_version__
|
||||
|
||||
|
||||
#elif defined(__FUJITSU)
|
||||
# define COMPILER_ID "Fujitsu"
|
||||
# if defined(__FCC_version__)
|
||||
# define COMPILER_VERSION __FCC_version__
|
||||
# elif defined(__FCC_major__)
|
||||
# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
|
||||
# endif
|
||||
# if defined(__fcc_version)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__fcc_version)
|
||||
# elif defined(__FCC_VERSION)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION)
|
||||
# endif
|
||||
|
||||
|
||||
#elif defined(__ghs__)
|
||||
# define COMPILER_ID "GHS"
|
||||
/* __GHS_VERSION_NUMBER = VVVVRP */
|
||||
# ifdef __GHS_VERSION_NUMBER
|
||||
# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10)
|
||||
# endif
|
||||
|
||||
#elif defined(__SCO_VERSION__)
|
||||
# define COMPILER_ID "SCO"
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && !defined(__clang__)
|
||||
# define COMPILER_ID "ARMCC"
|
||||
#if __ARMCC_VERSION >= 1000000
|
||||
/* __ARMCC_VERSION = VRRPPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
|
||||
#else
|
||||
/* __ARMCC_VERSION = VRPPPP */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
|
||||
#endif
|
||||
|
||||
|
||||
#elif defined(__clang__) && defined(__apple_build_version__)
|
||||
# define COMPILER_ID "AppleClang"
|
||||
# if defined(_MSC_VER)
|
||||
# define SIMULATE_ID "MSVC"
|
||||
# endif
|
||||
# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
|
||||
# if defined(_MSC_VER)
|
||||
/* _MSC_VER = VVRR */
|
||||
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
# endif
|
||||
# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
|
||||
|
||||
#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
|
||||
# define COMPILER_ID "ARMClang"
|
||||
# define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
|
||||
# define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION % 10000)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
|
||||
|
||||
#elif defined(__clang__)
|
||||
# define COMPILER_ID "Clang"
|
||||
# if defined(_MSC_VER)
|
||||
# define SIMULATE_ID "MSVC"
|
||||
# endif
|
||||
# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
|
||||
# if defined(_MSC_VER)
|
||||
/* _MSC_VER = VVRR */
|
||||
# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
# endif
|
||||
|
||||
#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__))
|
||||
# define COMPILER_ID "LCC"
|
||||
# define COMPILER_VERSION_MAJOR DEC(1)
|
||||
# if defined(__LCC__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__LCC__- 100)
|
||||
# endif
|
||||
# if defined(__LCC_MINOR__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__)
|
||||
# endif
|
||||
# if defined(__GNUC__) && defined(__GNUC_MINOR__)
|
||||
# define SIMULATE_ID "GNU"
|
||||
# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
|
||||
# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
|
||||
# if defined(__GNUC_PATCHLEVEL__)
|
||||
# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
|
||||
# endif
|
||||
# endif
|
||||
|
||||
#elif defined(__GNUC__) || defined(__GNUG__)
|
||||
# define COMPILER_ID "GNU"
|
||||
# if defined(__GNUC__)
|
||||
# define COMPILER_VERSION_MAJOR DEC(__GNUC__)
|
||||
# else
|
||||
# define COMPILER_VERSION_MAJOR DEC(__GNUG__)
|
||||
# endif
|
||||
# if defined(__GNUC_MINOR__)
|
||||
# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
|
||||
# endif
|
||||
# if defined(__GNUC_PATCHLEVEL__)
|
||||
# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
|
||||
# endif
|
||||
|
||||
#elif defined(_MSC_VER)
|
||||
# define COMPILER_ID "MSVC"
|
||||
/* _MSC_VER = VVRR */
|
||||
# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
|
||||
# if defined(_MSC_FULL_VER)
|
||||
# if _MSC_VER >= 1400
|
||||
/* _MSC_FULL_VER = VVRRPPPPP */
|
||||
# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
|
||||
# else
|
||||
/* _MSC_FULL_VER = VVRRPPPP */
|
||||
# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
|
||||
# endif
|
||||
# endif
|
||||
# if defined(_MSC_BUILD)
|
||||
# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
|
||||
# endif
|
||||
|
||||
#elif defined(_ADI_COMPILER)
|
||||
# define COMPILER_ID "ADSP"
|
||||
#if defined(__VERSIONNUM__)
|
||||
/* __VERSIONNUM__ = 0xVVRRPPTT */
|
||||
# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF)
|
||||
# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF)
|
||||
# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF)
|
||||
# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF)
|
||||
#endif
|
||||
|
||||
#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
|
||||
# define COMPILER_ID "IAR"
|
||||
# if defined(__VER__) && defined(__ICCARM__)
|
||||
# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
|
||||
# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
|
||||
# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
|
||||
# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__))
|
||||
# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
|
||||
# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
|
||||
# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
|
||||
# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
|
||||
# endif
|
||||
|
||||
|
||||
/* These compilers are either not known or too old to define an
|
||||
identification macro. Try to identify the platform and guess that
|
||||
it is the native compiler. */
|
||||
#elif defined(__hpux) || defined(__hpua)
|
||||
# define COMPILER_ID "HP"
|
||||
|
||||
#else /* unknown compiler */
|
||||
# define COMPILER_ID ""
|
||||
#endif
|
||||
|
||||
/* Construct the string literal in pieces to prevent the source from
|
||||
getting matched. Store it in a pointer rather than an array
|
||||
because some compilers will just produce instructions to fill the
|
||||
array rather than assigning a pointer to a static array. */
|
||||
char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
|
||||
#ifdef SIMULATE_ID
|
||||
char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
|
||||
#endif
|
||||
|
||||
#ifdef __QNXNTO__
|
||||
char const* qnxnto = "INFO" ":" "qnxnto[]";
|
||||
#endif
|
||||
|
||||
#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
|
||||
char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
|
||||
#endif
|
||||
|
||||
#define STRINGIFY_HELPER(X) #X
|
||||
#define STRINGIFY(X) STRINGIFY_HELPER(X)
|
||||
|
||||
/* Identify known platforms by name. */
|
||||
#if defined(__linux) || defined(__linux__) || defined(linux)
|
||||
# define PLATFORM_ID "Linux"
|
||||
|
||||
#elif defined(__MSYS__)
|
||||
# define PLATFORM_ID "MSYS"
|
||||
|
||||
#elif defined(__CYGWIN__)
|
||||
# define PLATFORM_ID "Cygwin"
|
||||
|
||||
#elif defined(__MINGW32__)
|
||||
# define PLATFORM_ID "MinGW"
|
||||
|
||||
#elif defined(__APPLE__)
|
||||
# define PLATFORM_ID "Darwin"
|
||||
|
||||
#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
|
||||
# define PLATFORM_ID "Windows"
|
||||
|
||||
#elif defined(__FreeBSD__) || defined(__FreeBSD)
|
||||
# define PLATFORM_ID "FreeBSD"
|
||||
|
||||
#elif defined(__NetBSD__) || defined(__NetBSD)
|
||||
# define PLATFORM_ID "NetBSD"
|
||||
|
||||
#elif defined(__OpenBSD__) || defined(__OPENBSD)
|
||||
# define PLATFORM_ID "OpenBSD"
|
||||
|
||||
#elif defined(__sun) || defined(sun)
|
||||
# define PLATFORM_ID "SunOS"
|
||||
|
||||
#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
|
||||
# define PLATFORM_ID "AIX"
|
||||
|
||||
#elif defined(__hpux) || defined(__hpux__)
|
||||
# define PLATFORM_ID "HP-UX"
|
||||
|
||||
#elif defined(__HAIKU__)
|
||||
# define PLATFORM_ID "Haiku"
|
||||
|
||||
#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
|
||||
# define PLATFORM_ID "BeOS"
|
||||
|
||||
#elif defined(__QNX__) || defined(__QNXNTO__)
|
||||
# define PLATFORM_ID "QNX"
|
||||
|
||||
#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
|
||||
# define PLATFORM_ID "Tru64"
|
||||
|
||||
#elif defined(__riscos) || defined(__riscos__)
|
||||
# define PLATFORM_ID "RISCos"
|
||||
|
||||
#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
|
||||
# define PLATFORM_ID "SINIX"
|
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|
||||
}
|
||||
]
|
||||
@@ -0,0 +1,557 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file fsbl.h
|
||||
*
|
||||
* Contains the function prototypes, defines and macros for the
|
||||
* First Stage Boot Loader (FSBL) functionality
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jz 03/04/11 Initial release
|
||||
* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
|
||||
* xparameters.h file
|
||||
* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
|
||||
* Added the debug levels
|
||||
* 4.00a sgd 02/28/13 Removed DDR initialization check
|
||||
* Removed DDR ECC initialization code
|
||||
* Modified hand off address check to 1MB
|
||||
* Added RSA authentication support
|
||||
* Removed LPBK_DLY_ADJ register setting code as we use
|
||||
* divisor 8
|
||||
* Removed check for Fabric is already initialized
|
||||
*
|
||||
* CR's fixed and description
|
||||
* 689026: FSBL doesn't hold PL resets active during
|
||||
* bit download
|
||||
* Resolution: PL resets are released just before
|
||||
* handoff
|
||||
*
|
||||
* 689077: FSBL hangs at Handoff clearing the
|
||||
* TX UART buffer
|
||||
* Resolution: STDOUT_BASEADDRESS macro value changes
|
||||
* based UART select, hence used STDOUT_BASEADDRESS
|
||||
* as UART base address
|
||||
*
|
||||
* 695578: FSBL failed to load standalone application
|
||||
* in secure bootmode
|
||||
* Resolution: Application will be placed at load address
|
||||
* instead of DDR temporary address
|
||||
*
|
||||
* 699475: FSBL functionality is broken and its
|
||||
* not able to boot in QSPI/NAND bootmode
|
||||
* Resolution: New flags are added DevCfg driver
|
||||
* for handling loopback
|
||||
* XDCFG_CONCURRENT_NONSEC_READ_WRITE
|
||||
* XDCFG_CONCURRENT_SECURE_READ_WRITE
|
||||
*
|
||||
* 683145: Define stack area for FIQ, UNDEF modes
|
||||
* in linker file
|
||||
* Resolution: FSBL linker modified to create stack area
|
||||
* for FIQ, UNDEF
|
||||
*
|
||||
* 705664: FSBL fails to decrypt the bitstream when
|
||||
* the image is AES encrypted using non-zero key value
|
||||
* Resolution: Fabric cleaning will not be done
|
||||
* for AES-E-Fuse encryption
|
||||
*
|
||||
* Watchdog disabled for AES E-Fuse encryption
|
||||
*
|
||||
* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
|
||||
* Added QSPI Flash Size > 128Mbit support
|
||||
* QSPI Dual Stack support
|
||||
* Added Md5 checksum support
|
||||
*
|
||||
* CR's fixed and description
|
||||
* 692045 FSBL: Linker script of FSBL has PHDR workaround,
|
||||
* this needs to be fixed
|
||||
* Resolution: Removed PHDR from Linker file
|
||||
*
|
||||
* 704287 FSBL: fsbl.h file has a few error codes that
|
||||
* are not used by FSBL, that needs to be removed
|
||||
* Resolution: Removed unused error codes
|
||||
*
|
||||
* 704379 FSBL: Check if DDR is in proper state before
|
||||
* handoff
|
||||
* Resolution: Added DDR initialization check
|
||||
*
|
||||
* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
|
||||
* the debug level is FSBL_DEBUG only.
|
||||
*
|
||||
* 710128 FSBL: Linux boot failing without load attribute
|
||||
* set for Linux partitions in BIF
|
||||
* Resolution: FSBL will load partitions with valid load
|
||||
* address and stop loading if any invalid load address
|
||||
*
|
||||
* 708728 Issues seen while making HP interconnect
|
||||
* 32 bit wide
|
||||
* Resolution: ps7_post_config function generated by PCW
|
||||
* will be called after Bit stream download
|
||||
* Added MMC support
|
||||
* 6.00a kc 07/31/2013 CR's fixed and description
|
||||
* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
|
||||
* for authenticating the Partition images
|
||||
* Resolution: FSBL now uses the PPK left by Boot ROM in
|
||||
* OCM for authencating the SPK
|
||||
*
|
||||
* 724165 Partition Header used by FSBL is not
|
||||
* authenticated
|
||||
* Resolution: FSBL now authenticates the partition header
|
||||
*
|
||||
* 691150 ps7_init does not check for peripheral
|
||||
* initialization failures or timeout on polls
|
||||
* Resolution: Return value of ps7_init() is now checked
|
||||
* by FSBL and prints the error string
|
||||
*
|
||||
* 708316 PS7_init.tcl file should have Error mechanism
|
||||
* for all mask_poll
|
||||
* Resolution: Return value of ps7_init() is now checked
|
||||
* by FSBL and prints the error string
|
||||
*
|
||||
* 732062 FSBL fails to build if UART not available
|
||||
* Resolution: Added define to call xil_printf only
|
||||
* if uart is defined
|
||||
*
|
||||
* 722979 Provide customer-friendly changelogs in FSBL
|
||||
* Resolution: Added CR description for all the files
|
||||
*
|
||||
* 732865 Backward compatibility for ps7_init function
|
||||
* Resolution: Added a new define for ps7_init success
|
||||
* and value is defined based on ps7_init define
|
||||
*
|
||||
* Fix for CR#739711 - FSBL not able to read Large
|
||||
* QSPI (512M) in IO Mode
|
||||
* Resolution: Modified the address calculation
|
||||
* algorithm in dual parallel mode for QSPI
|
||||
*
|
||||
* 7.00a kc 10/18/13 Integrated SD/MMC driver
|
||||
* 10/23/13 Support for armcc compiler added
|
||||
* 741003 FSBL has to check the HMAC error status after
|
||||
* decryption
|
||||
* Resolution: Added code for checking the error status
|
||||
* after PCAP completion
|
||||
* 739968 FSBL should do the QSPI config settings for
|
||||
* Dual parallel configuration in IO mode
|
||||
* Resolution: Added QSPI config settings in qspi.c
|
||||
* 724620 FSBL: How to handle PCAP_MODE after bitstream
|
||||
* configuration.
|
||||
* Resolution: PCAP_MODE and PCAP_PR bits are now cleared
|
||||
* after PCAP transfer completion
|
||||
* 726178 In the 14.6 FSBL function FabricInit() PROG_B
|
||||
* is kept active for 5mS.
|
||||
* Resolution: PROG_B is now kept active for 5ms only in case
|
||||
* if efuse is the aes key source.
|
||||
* 755245 FSBL does not load partition if eMMC has only
|
||||
* one partition
|
||||
* Resolution: Changed the if condition for MMC
|
||||
* 12/04/13 764382 FSBL: How to handle PCAP_MODE after bitstream
|
||||
* configuration
|
||||
* Resolution: Reverted back the changes of 724620. PCAP_MODE
|
||||
* and PCAP_PR bits are not changed
|
||||
* 8.00a kc 01/16/13 767798 Fsbl MD5 Checksum failiure for encrypted images
|
||||
* Resolution: For checksum enabled partitions, total
|
||||
* total partition image length is copied now.
|
||||
* 761895 FSBL should authenticate image only if
|
||||
* partition owner was not set to u-boot
|
||||
* Resolution: Partition owner check added in
|
||||
* image_mover.c
|
||||
* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
|
||||
* Resolution: Function argument is updated from value
|
||||
* to pointer to reflect updated value
|
||||
* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
|
||||
* unless FSBL* and FSBL are identical in length
|
||||
* Resolution: PPK is set only once now.
|
||||
* 785778 - FSBL takes 8 seconds to
|
||||
* authenticate (RSA) a bitstream on zc706
|
||||
* Resolution: Data Caches are enabled only for
|
||||
* authentication.
|
||||
* 791245 - Use of xilrsa in fsbl
|
||||
* Resolution: Rsa library is removed from fsbl source
|
||||
* and xilrsa is used from BSP
|
||||
* 10.00a kc 07/15/14 804595 Zynq FSBL - Issues with
|
||||
* fallback image offset handling using MD5
|
||||
* Resolution: Updated the checksum offset to add with
|
||||
* image base address
|
||||
* 782309 Fallback support for AES
|
||||
* encryption with E-Fuse - Enhancement
|
||||
* Resolution: Same as 773866
|
||||
* 809336 Minor code cleanup
|
||||
* Resolution Minor code changes
|
||||
* kc 08/27/14 820356 - FSBL compilation fails with IAR compiler
|
||||
* Resolution: Change of __asm__ to __asm
|
||||
* 11.00a kv 10/08/14 826030 - FSBL:LinearBootDeviceFlag is not initialized
|
||||
* in IO mode case.Due to which the variable is
|
||||
* remaining in unknown state.
|
||||
* Resolution: LinearBootDeviceFlag is initialized 0
|
||||
* in main.c
|
||||
* 12.00a ssc 12/11/14 839182 - FSBL -In the file sd.c, f_mount is called with
|
||||
* two arguments but f_mount is expecting the 3 arguments
|
||||
* from build 2015.1_1210_1, causing compilation error.
|
||||
* Resolution: Arguments for f_mount in InitSD() are
|
||||
* changed as per new signature.
|
||||
* 13.00a ssc 04/10/15 846899 - FSBL -In the file pcap.c, to clear DMA done
|
||||
* count, devcfg.INT_STS register is written to, which is
|
||||
* not correct.
|
||||
* Resolution: Corresponding fields in the devcfg.STATUS
|
||||
* register are written to, for clearing DMA done count.
|
||||
* 14.00a gan 01/13/16 869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
|
||||
* read command from LQSPI_CFG register instead of hard
|
||||
* coded read command (0x6B).
|
||||
* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
|
||||
* Fabric Initialization sequence is modified to check
|
||||
* the PL power before sequence starts and checking INIT_B
|
||||
* reset status twice in case of failure.
|
||||
* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
|
||||
* In pcap.c, check pl power through MCTRL register
|
||||
* for 3.0 and later versions of silicon.
|
||||
* 17.00a bsv 27/03/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
|
||||
* to enable level shifters in jtag boot mode.
|
||||
* 18.00a ka 10/29/18 Fix for CR# 1006294 Added macro for FORCE_USE_AES_EXCLUDE
|
||||
* 19.0 vns 03/18/22 Fixed CR#1125470, added FsblPrintArray() prototype
|
||||
* 20.0 ng 12/08/22 Updated SDK release version
|
||||
* 21.0 skd 02/10/22 SDK release version updated
|
||||
* 21.1 ng 07/13/23 Add SDT support
|
||||
* 21.2 ng 07/25/23 Fixed DDR address support in SDT
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* Flags in FSBL
|
||||
*
|
||||
* FSBL_PERF
|
||||
*
|
||||
* This Flag can be set at compilation time. This flag is set for
|
||||
* measuring the performance of FSBL.That is the time taken to execute is
|
||||
* measured.when this flag is set.Execution time with reference to
|
||||
* global timer is taken here
|
||||
*
|
||||
* Total Execution time is the time taken for executing FSBL till handoff
|
||||
* to any application .
|
||||
* If there is a bitstream in the partition header then the
|
||||
* execution time includes the copying of the bitstream to DDR
|
||||
* (in case of SD/NAND bootmode)
|
||||
* and programming the devcfg dma is accounted.
|
||||
*
|
||||
* FSBL provides two debug levels
|
||||
* DEBUG GENERAL - fsbl_printf under this category will appear only when the
|
||||
* FSBL_DEBUG flag is set during compilation
|
||||
* DEBUG_INFO - fsbl_printf under this category will appear when the
|
||||
* FSBL_DEBUG_INFO flag is set during compilation
|
||||
* For a more detailed output log can be used.
|
||||
* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
|
||||
* RSA functions
|
||||
* These macros are input to the fsbl_printf function
|
||||
*
|
||||
* DEBUG LEVELS
|
||||
* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
|
||||
* that are with the DEBUG_GENERAL argument are shown
|
||||
* FSBL_DEBUG_INFO is level 2, when this flag is set during the
|
||||
* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
|
||||
*
|
||||
* DEFAULT LEVEL
|
||||
* By default no print messages will appear.
|
||||
*
|
||||
* NON_PS_INSTANTIATED_BITSTREAM
|
||||
*
|
||||
* FSBL will not enable the level shifters for a NON PS instantiated
|
||||
* Bitstream.This flag can be set during compilation for a NON PS instantiated
|
||||
* bitstream
|
||||
*
|
||||
* ECC_ENABLE
|
||||
* This flag will be defined in the ps7_init.h file when ECC is enabled
|
||||
* in the DDR configuration (XPS GUI)
|
||||
*
|
||||
* RSA_SUPPORT
|
||||
* This flag is used to enable authentication feature
|
||||
* Default this macro disabled, reason to avoid increase in code size
|
||||
*
|
||||
* MMC_SUPPORT
|
||||
* This flag is used to enable MMC support feature
|
||||
*
|
||||
* JTAG_ENABLE_LEVEL_SHIFTERS
|
||||
* FSBL will not enable the level shifters for jtag boot mode. This flag can be
|
||||
* set during compilation for jtag boot mode to enable level shifters.
|
||||
*
|
||||
* FORCE_USE_AES_EXCLUDE
|
||||
* Defining this flag will exclude the feature, forcing every partition to be
|
||||
* encrypted when EFUSE_SEC_EN bit is set.
|
||||
* This flag can be set/unset during compilation.
|
||||
* By default this flag is unset/undefined which enables the above feature
|
||||
* Note : Changing the default behaviour is not recommended from
|
||||
* Security perspective.
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef XIL_FSBL_H
|
||||
#define XIL_FSBL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xil_io.h"
|
||||
#include "xparameters.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xil_printf.h"
|
||||
#include "pcap.h"
|
||||
#include "fsbl_debug.h"
|
||||
#include "ps7_init.h"
|
||||
#ifdef FSBL_PERF
|
||||
#ifndef SDT
|
||||
#include "xtime_l.h"
|
||||
#else
|
||||
#include "xiltimer.h"
|
||||
#endif
|
||||
#include <stdio.h>
|
||||
#endif
|
||||
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
/*
|
||||
* SDK release version
|
||||
*/
|
||||
#define SDK_RELEASE_YEAR 2023
|
||||
#define SDK_RELEASE_QUARTER 2
|
||||
|
||||
#define WORD_LENGTH_SHIFT 2
|
||||
|
||||
/*
|
||||
* On a Successful handoff to an application FSBL sets this SUCCESS code
|
||||
*/
|
||||
#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
|
||||
|
||||
/*
|
||||
* Backward compatibility for ps7_init
|
||||
*/
|
||||
#ifdef NEW_PS7_ERR_CODE
|
||||
#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
|
||||
#else
|
||||
#define FSBL_PS7_INIT_SUCCESS (1)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ERROR CODES
|
||||
* The following are the Error codes that FSBL uses
|
||||
* If the Debug prints are enabled only then the error codes will be
|
||||
* seen on the com port.Without the debug prints enabled no error codes will
|
||||
* be visible.There are not saved in any register
|
||||
* Boot Mode States used for error and status output
|
||||
* Error codes are defined below
|
||||
*/
|
||||
#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
|
||||
#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
|
||||
#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
|
||||
#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
|
||||
#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
|
||||
#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
|
||||
#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
|
||||
#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
|
||||
#define NO_DDR 0xA008 /**< DDR missing */
|
||||
#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
|
||||
#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
|
||||
#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
|
||||
#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
|
||||
#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
|
||||
#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
|
||||
#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
|
||||
#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
|
||||
#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
|
||||
#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
|
||||
#define PARTITION_LOAD_FAIL 0xA013 /**< Partition load fail*/
|
||||
/*
|
||||
* FSBL Exception error codes
|
||||
*/
|
||||
#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
|
||||
#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
|
||||
#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
|
||||
#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
|
||||
#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
|
||||
#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
|
||||
|
||||
/*
|
||||
* FSBL hook routine failures
|
||||
*/
|
||||
#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
|
||||
#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
|
||||
download hook failed */
|
||||
#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
|
||||
download hook failed */
|
||||
|
||||
/*
|
||||
* Watchdog related Error codes
|
||||
*/
|
||||
#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
|
||||
#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
|
||||
|
||||
/*
|
||||
* SLCR Registers
|
||||
*/
|
||||
#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
|
||||
#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
|
||||
#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
|
||||
#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
|
||||
#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
|
||||
#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
|
||||
#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
|
||||
|
||||
/*
|
||||
* Efuse Status Register
|
||||
*/
|
||||
#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
|
||||
#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
|
||||
|
||||
/*
|
||||
* PS reset control register define
|
||||
*/
|
||||
#define PS_RST_MASK 0x1 /**< PS software reset */
|
||||
|
||||
/*
|
||||
* SLCR BOOT Mode Register defines
|
||||
*/
|
||||
#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
|
||||
|
||||
/*
|
||||
* Boot Modes
|
||||
*/
|
||||
#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
|
||||
#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
|
||||
#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
|
||||
#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
|
||||
#define SD_MODE 0x00000005 /**< SD Boot Mode */
|
||||
#define MMC_MODE 0x00000006 /**< MMC Boot Device */
|
||||
|
||||
#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
|
||||
#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
|
||||
|
||||
/*
|
||||
* Golden image offset
|
||||
*/
|
||||
#define GOLDEN_IMAGE_OFFSET 0x8000
|
||||
|
||||
/*
|
||||
* Silicon Version
|
||||
*/
|
||||
#define SILICON_VERSION_1 0
|
||||
#define SILICON_VERSION_2 1
|
||||
#define SILICON_VERSION_3 2
|
||||
#define SILICON_VERSION_3_1 3
|
||||
|
||||
/*
|
||||
* In case of PL DDR, this macros defined based PL DDR address
|
||||
*/
|
||||
#if !defined(XPAR_PS7_DDR_0_S_AXI_BASEADDR) && !defined(XPAR_PS7_DDR_0_BASEADDRESS)
|
||||
#define DDR_START_ADDR 0x00
|
||||
#define DDR_END_ADDR 0x00
|
||||
#else
|
||||
/*
|
||||
* DDR start address for storing the data temporarily(1M)
|
||||
* Need to finalize correct logic
|
||||
*/
|
||||
#ifndef SDT
|
||||
#if defined(XPAR_PS7_DDR_0_S_AXI_BASEADDR)
|
||||
#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
|
||||
#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
|
||||
#endif
|
||||
#else
|
||||
#if defined(XPAR_PS7_DDR_0_BASEADDRESS)
|
||||
#define DDR_START_ADDR XPAR_PS7_DDR_0_BASEADDRESS
|
||||
#define DDR_END_ADDR XPAR_PS7_DDR_0_HIGHADDRESS
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define DDR_TEMP_START_ADDR DDR_START_ADDR
|
||||
/*
|
||||
* DDR test pattern
|
||||
*/
|
||||
#define DDR_TEST_PATTERN 0xAA55AA55
|
||||
#define DDR_TEST_OFFSET 0x100000
|
||||
/*
|
||||
*
|
||||
*/
|
||||
#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
|
||||
#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
|
||||
#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
|
||||
#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
|
||||
#define LQSPI_CFG_OFFSET 0xA0
|
||||
#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
|
||||
|
||||
/*
|
||||
* These are the SLCR lock and unlock macros
|
||||
*/
|
||||
#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
|
||||
#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
|
||||
|
||||
#define IMAGE_HEADER_CHECKSUM_COUNT 10
|
||||
|
||||
/* Boot ROM Image defines */
|
||||
#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
|
||||
#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
|
||||
#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
|
||||
#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
|
||||
#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
|
||||
#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
|
||||
#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
|
||||
#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
|
||||
#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
|
||||
#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
|
||||
#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
|
||||
#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
|
||||
|
||||
/* Reboot status register defines:
|
||||
* 0xF0000000 for FSBL fallback mask to notify Boot Rom
|
||||
* 0x60000000 for FSBL to mark that FSBL has not handoff yet
|
||||
* 0x00FFFFFF for user application to use across soft reset
|
||||
*/
|
||||
#define FSBL_FAIL_MASK 0xF0000000
|
||||
#define FSBL_IN_MASK 0x60000000
|
||||
|
||||
/* The address that holds the base address for the image Boot ROM found */
|
||||
#define BASEADDR_HOLDER 0xFFFFFFF8
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void OutputStatus(u32 State);
|
||||
void FsblFallback(void);
|
||||
|
||||
int FsblSetNextPartition(int Num);
|
||||
void *(memcpy_rom)(void * s1, const void * s2, u32 n);
|
||||
char *strcpy_rom(char *Dest, const char *Src);
|
||||
|
||||
void ClearFSBLIn(void);
|
||||
void MarkFSBLIn(void);
|
||||
void FsblHandoff(u32 FsblStartAddr);
|
||||
u32 GetResetReason(void);
|
||||
|
||||
#ifdef FSBL_PERF
|
||||
void FsblGetGlobalTime (XTime * tCur);
|
||||
void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
|
||||
#endif
|
||||
void GetSiliconVersion(void);
|
||||
void FsblHandoffExit(u32 FsblStartAddr);
|
||||
void FsblHandoffJtagExit();
|
||||
void FsblPrintArray (u8 *Buf, u32 Len, char *Str);
|
||||
/************************** Variable Definitions *****************************/
|
||||
extern int SkipPartition;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
@@ -0,0 +1,56 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file fsbl_debug.h
|
||||
*
|
||||
* This file contains the debug verbose information for FSBL print functionality
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 3.00a mb 01/09/12 Initial release
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _FSBL_DEBUG_H
|
||||
#define _FSBL_DEBUG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define DEBUG_GENERAL 0x00000001 /* general debug messages */
|
||||
#define DEBUG_INFO 0x00000002 /* More debug information */
|
||||
|
||||
#if defined (FSBL_DEBUG_INFO)
|
||||
#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
|
||||
#elif defined (FSBL_DEBUG)
|
||||
#define fsbl_dbg_current_types (DEBUG_GENERAL)
|
||||
#else
|
||||
#define fsbl_dbg_current_types 0
|
||||
#endif
|
||||
|
||||
#ifdef STDOUT_BASEADDRESS
|
||||
#define fsbl_printf(type,...) \
|
||||
if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
|
||||
#else
|
||||
#define fsbl_printf(type, ...)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSBL_DEBUG_H */
|
||||
@@ -0,0 +1,194 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file handoff.S
|
||||
*
|
||||
* Contains the code that does the handoff to the loaded application. This
|
||||
* code lives high in the ROM.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date.word Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 03/01/10 Initial release
|
||||
* 7.00a kc 10/23/13 Added support for armcc compiler
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
* Assumes that the starting address of the FSBL is provided by the calling routine
|
||||
* in R0.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifdef __GNUC__
|
||||
.globl FsblHandoffJtagExit
|
||||
|
||||
.globl FsblHandoffExit
|
||||
|
||||
.section .handoff,"axS"
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
FsblHandoffJtagExit:
|
||||
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
|
||||
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
|
||||
|
||||
dsb
|
||||
isb /* make sure it completes */
|
||||
|
||||
ldr r4, =0
|
||||
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
|
||||
|
||||
isb /* make sure it completes */
|
||||
Loop:
|
||||
wfe
|
||||
b Loop
|
||||
|
||||
FsblHandoffExit:
|
||||
mov lr, r0 /* move the destination address into link register */
|
||||
|
||||
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
|
||||
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
|
||||
|
||||
dsb
|
||||
isb /* make sure it completes */
|
||||
|
||||
ldr r4, =0
|
||||
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
|
||||
|
||||
isb /* make sure it completes */
|
||||
|
||||
|
||||
bx lr /* force the switch, destination should have been in r0 */
|
||||
|
||||
.Ldone: b .Ldone /* Paranoia: we should never get here */
|
||||
.end
|
||||
|
||||
#elif defined (__IASMARM__)
|
||||
|
||||
PUBLIC FsblHandoffJtagExit
|
||||
|
||||
PUBLIC FsblHandoffExit
|
||||
|
||||
SECTION .handoff:CODE:NOROOT(2)
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
FsblHandoffJtagExit
|
||||
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
|
||||
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
|
||||
|
||||
dsb
|
||||
isb ;/* make sure it completes */
|
||||
|
||||
ldr r4, =0
|
||||
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
|
||||
|
||||
isb ;/* make sure it completes */
|
||||
Loop
|
||||
wfe
|
||||
b Loop
|
||||
|
||||
FsblHandoffExit
|
||||
mov lr, r0 ;/* move the destination address into link register */
|
||||
|
||||
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
|
||||
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
|
||||
|
||||
dsb
|
||||
isb ;/* make sure it completes */
|
||||
|
||||
ldr r4, =0
|
||||
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
|
||||
|
||||
isb ;/* make sure it completes */
|
||||
|
||||
|
||||
bx lr ;/* force the switch, destination should have been in r0 */
|
||||
|
||||
.Ldone
|
||||
b .Ldone ;/* Paranoia: we should never get here */
|
||||
|
||||
END
|
||||
|
||||
|
||||
#else
|
||||
EXPORT FsblHandoffJtagExit
|
||||
|
||||
EXPORT FsblHandoffExit
|
||||
|
||||
AREA |.handoff|,CODE
|
||||
|
||||
;/***************************** Include Files *********************************/
|
||||
|
||||
;/************************** Constant Definitions *****************************/
|
||||
|
||||
;/**************************** Type Definitions *******************************/
|
||||
|
||||
;/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
;/************************** Function Prototypes ******************************/
|
||||
|
||||
;/************************** Variable Definitions *****************************/
|
||||
|
||||
|
||||
FsblHandoffJtagExit
|
||||
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
|
||||
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
|
||||
|
||||
dsb
|
||||
isb ;/* make sure it completes */
|
||||
|
||||
ldr r4, =0
|
||||
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
|
||||
|
||||
isb ;/* make sure it completes */
|
||||
Loop
|
||||
wfe
|
||||
b Loop
|
||||
|
||||
FsblHandoffExit
|
||||
mov lr, r0 ;/* move the destination address into link register */
|
||||
|
||||
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
|
||||
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
|
||||
|
||||
dsb
|
||||
isb ;/* make sure it completes */
|
||||
|
||||
ldr r4, =0
|
||||
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
|
||||
|
||||
isb ;/* make sure it completes */
|
||||
|
||||
|
||||
bx lr ;/* force the switch, destination should have been in r0 */
|
||||
|
||||
Ldone b Ldone ;/* Paranoia: we should never get here */
|
||||
END
|
||||
#endif
|
||||
@@ -0,0 +1,138 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* @file fsbl_hooks.c
|
||||
*
|
||||
* This file provides functions that serve as user hooks. The user can add the
|
||||
* additional functionality required into these routines. This would help retain
|
||||
* the normal FSBL flow unchanged.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 3.00a np 08/03/12 Initial release
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include "fsbl.h"
|
||||
#include "xstatus.h"
|
||||
#include "fsbl_hooks.h"
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* This function is the hook which will be called before the bitstream download.
|
||||
* The user can add all the customized code required to be executed before the
|
||||
* bitstream download to this routine.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS to indicate success
|
||||
* - XST_FAILURE.to indicate failure
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 FsblHookBeforeBitstreamDload(void)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
Status = XST_SUCCESS;
|
||||
|
||||
/*
|
||||
* User logic to be added here. Errors to be stored in the status variable
|
||||
* and returned
|
||||
*/
|
||||
fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
|
||||
|
||||
return (Status);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* This function is the hook which will be called after the bitstream download.
|
||||
* The user can add all the customized code required to be executed after the
|
||||
* bitstream download to this routine.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS to indicate success
|
||||
* - XST_FAILURE.to indicate failure
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 FsblHookAfterBitstreamDload(void)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
Status = XST_SUCCESS;
|
||||
|
||||
/*
|
||||
* User logic to be added here.
|
||||
* Errors to be stored in the status variable and returned
|
||||
*/
|
||||
fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
|
||||
|
||||
return (Status);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* This function is the hook which will be called before the FSBL does a handoff
|
||||
* to the application. The user can add all the customized code required to be
|
||||
* executed before the handoff to this routine.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS to indicate success
|
||||
* - XST_FAILURE.to indicate failure
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 FsblHookBeforeHandoff(void)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
Status = XST_SUCCESS;
|
||||
|
||||
/*
|
||||
* User logic to be added here.
|
||||
* Errors to be stored in the status variable and returned
|
||||
*/
|
||||
fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
|
||||
|
||||
return (Status);
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* This function is the hook which will be called in case FSBL fall back
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
****************************************************************************/
|
||||
void FsblHookFallback(void)
|
||||
{
|
||||
/*
|
||||
* User logic to be added here.
|
||||
* Errors to be stored in the status variable and returned
|
||||
*/
|
||||
fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,55 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file fsbl_hooks.h
|
||||
*
|
||||
* Contains the function prototypes, defines and macros required by fsbl_hooks.c
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 3.00a np/mb 10/08/12 Initial release
|
||||
* Corrected the prototype
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef FSBL_HOOKS_H_
|
||||
#define FSBL_HOOKS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "fsbl.h"
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/* FSBL hook function which is called before bitstream download */
|
||||
u32 FsblHookBeforeBitstreamDload(void);
|
||||
|
||||
/* FSBL hook function which is called after bitstream download */
|
||||
u32 FsblHookAfterBitstreamDload(void);
|
||||
|
||||
/* FSBL hook function which is called before handoff to the application */
|
||||
u32 FsblHookBeforeHandoff(void);
|
||||
|
||||
/* FSBL hook function which is called in FSBL fallback */
|
||||
void FsblHookFallback(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,137 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file image_mover.h
|
||||
*
|
||||
* This file contains the interface for moving the image from FLASH to OCM
|
||||
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jz 03/04/11 Initial release
|
||||
* 2.00a jz 06/04/11 partition header expands to 12 words
|
||||
* 5.00a kc 07/30/13 Added defines for image header information
|
||||
* 8.00a kc 01/16/13 Added defines for partition owner attribute
|
||||
* 9.0 vns 03/21/22 Deleted GetImageHeaderAndSignature() and added
|
||||
* GetNAuthImageHeader()
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___IMAGE_MOVER_H___
|
||||
#define ___IMAGE_MOVER_H___
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "fsbl.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define PARTITION_NUMBER_SHIFT 24
|
||||
#define MAX_PARTITION_NUMBER (0xE)
|
||||
|
||||
/* Boot Image Header defines */
|
||||
#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */
|
||||
#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */
|
||||
#define IMAGE_HEADER_SIZE (64)
|
||||
#define IMAGE_HEADER_TABLE_SIZE (64)
|
||||
#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
|
||||
#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
|
||||
#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \
|
||||
TOTAL_IMAGE_HEADER_SIZE + \
|
||||
TOTAL_PARTITION_HEADER_SIZE + 64)
|
||||
|
||||
/* Partition Header defines */
|
||||
#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */
|
||||
#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */
|
||||
#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */
|
||||
#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */
|
||||
#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */
|
||||
#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */
|
||||
#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */
|
||||
#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */
|
||||
#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */
|
||||
#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */
|
||||
#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/
|
||||
|
||||
/* Attribute word defines */
|
||||
#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */
|
||||
#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */
|
||||
#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */
|
||||
#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */
|
||||
#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */
|
||||
#define ATTRIBUTE_PARTITION_OWNER_MASK 0x30000 /* Partition Owner */
|
||||
|
||||
#define ATTRIBUTE_PARTITION_OWNER_FSBL 0x00000 /* FSBL Partition Owner */
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
typedef u32 (*ImageMoverType)( u32 SourceAddress,
|
||||
u32 DestinationAddress,
|
||||
u32 LengthBytes);
|
||||
|
||||
typedef struct StructPartHeader {
|
||||
u32 ImageWordLen; /* 0x0 */
|
||||
u32 DataWordLen; /* 0x4 */
|
||||
u32 PartitionWordLen; /* 0x8 */
|
||||
u32 LoadAddr; /* 0xC */
|
||||
u32 ExecAddr; /* 0x10 */
|
||||
u32 PartitionStart; /* 0x14 */
|
||||
u32 PartitionAttr; /* 0x18 */
|
||||
u32 SectionCount; /* 0x1C */
|
||||
u32 CheckSumOffset; /* 0x20 */
|
||||
u32 Pads1[1];
|
||||
u32 ACOffset; /* 0x28 */
|
||||
u32 Pads2[4];
|
||||
u32 CheckSum; /* 0x3C */
|
||||
}PartHeader;
|
||||
|
||||
struct HeaderArray {
|
||||
u32 Fields[16];
|
||||
};
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
#define MoverIn32 Xil_In32
|
||||
#define MoverOut32 Xil_Out32
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
u32 LoadBootImage(void);
|
||||
u32 GetPartitionHeaderInfo(u32 ImageBaseAddress);
|
||||
u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header);
|
||||
u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H);
|
||||
u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset);
|
||||
u32 GetNAuthImageHeader(u32 ImageAddress);
|
||||
u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength);
|
||||
u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header);
|
||||
u32 IsEmptyHeader(struct HeaderArray *H);
|
||||
u32 IsLastPartition(struct HeaderArray *H);
|
||||
void HeaderDump(PartHeader *Header);
|
||||
u32 GetPartitionCount(PartHeader *Header);
|
||||
u32 ValidateHeader(PartHeader *Header);
|
||||
u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* ___IMAGE_MOVER_H___ */
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
#ifndef @DRVNAME@_EXAMPLE_H
|
||||
#define @DRVNAME@_EXAMPLE_H
|
||||
|
||||
@ADDR_DEFINE@
|
||||
|
||||
#endif /* @DRVNAME@_EXAMPLE_H */
|
||||
+313
@@ -0,0 +1,313 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : @STACK_SIZE@;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : @HEAP_SIZE@;
|
||||
|
||||
_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
|
||||
_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
|
||||
_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
|
||||
|
||||
@MEMORY_SECTION@
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_vector_table)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
KEEP (*(.vectors))
|
||||
*(.boot)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu_warning)
|
||||
*(.gcc_execpt_table)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.ARM.extab)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
} > @DDR@
|
||||
|
||||
.init (ALIGN(64)) : {
|
||||
KEEP (*(.init))
|
||||
} > @DDR@
|
||||
|
||||
.fini (ALIGN(64)) : {
|
||||
KEEP (*(.fini))
|
||||
} > @DDR@
|
||||
|
||||
.interp : {
|
||||
KEEP (*(.interp))
|
||||
} > @DDR@
|
||||
|
||||
.note-ABI-tag : {
|
||||
KEEP (*(.note-ABI-tag))
|
||||
} > @DDR@
|
||||
|
||||
.rodata : {
|
||||
. = ALIGN(64);
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.rodata1 : {
|
||||
. = ALIGN(64);
|
||||
__rodata1_start = .;
|
||||
*(.rodata1)
|
||||
*(.rodata1.*)
|
||||
__rodata1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata2 : {
|
||||
. = ALIGN(64);
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
__sdata2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss2 : {
|
||||
. = ALIGN(64);
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data : {
|
||||
. = ALIGN(64);
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.jcr)
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
__data_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data1 : {
|
||||
. = ALIGN(64);
|
||||
__data1_start = .;
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
__data1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > @DDR@
|
||||
|
||||
.got1 : {
|
||||
*(.got1)
|
||||
} > @DDR@
|
||||
|
||||
.got2 : {
|
||||
*(.got2)
|
||||
} > @DDR@
|
||||
|
||||
.ctors : {
|
||||
. = ALIGN(64);
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.dtors : {
|
||||
. = ALIGN(64);
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
___DTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.fixup : {
|
||||
__fixup_start = .;
|
||||
*(.fixup)
|
||||
__fixup_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > @DDR@
|
||||
|
||||
.eh_framehdr : {
|
||||
__eh_framehdr_start = .;
|
||||
*(.eh_framehdr)
|
||||
__eh_framehdr_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > @DDR@
|
||||
|
||||
.mmu_tbl0 (ALIGN(4096)) : {
|
||||
__mmu_tbl0_start = .;
|
||||
*(.mmu_tbl0)
|
||||
__mmu_tbl0_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.mmu_tbl1 (ALIGN(4096)) : {
|
||||
__mmu_tbl1_start = .;
|
||||
*(.mmu_tbl1)
|
||||
__mmu_tbl1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.mmu_tbl2 (ALIGN(4096)) : {
|
||||
__mmu_tbl2_start = .;
|
||||
*(.mmu_tbl2)
|
||||
__mmu_tbl2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidix.*.*)
|
||||
__exidx_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.preinit_array : {
|
||||
. = ALIGN(64);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(SORT(.preinit_array.*)))
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.init_array : {
|
||||
. = ALIGN(64);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.fini_array : {
|
||||
. = ALIGN(64);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.drvcfg_sec : {
|
||||
. = ALIGN(8);
|
||||
__drvcfgsecdata_start = .;
|
||||
KEEP (*(.drvcfg_sec))
|
||||
__drvcfgsecdata_end = .;
|
||||
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.attributes : {
|
||||
__ARM.attributes_start = .;
|
||||
*(.ARM.attributes)
|
||||
__ARM.attributes_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata : {
|
||||
. = ALIGN(64);
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
. = ALIGN(64);
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
. = ALIGN(64);
|
||||
__sbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tdata : {
|
||||
. = ALIGN(64);
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tbss : {
|
||||
. = ALIGN(64);
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
. = ALIGN(64);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(64);
|
||||
__bss_end__ = .;
|
||||
} > @DDR@
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(64);
|
||||
_heap = .;
|
||||
HeapBase = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
HeapLimit = .;
|
||||
} > @DDR@
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
. = ALIGN(64);
|
||||
_el3_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
__el3_stack = .;
|
||||
_el2_stack_end = .;
|
||||
. += _EL2_STACK_SIZE;
|
||||
. = ALIGN(64);
|
||||
__el2_stack = .;
|
||||
_el1_stack_end = .;
|
||||
. += _EL1_STACK_SIZE;
|
||||
. = ALIGN(64);
|
||||
__el1_stack = .;
|
||||
_el0_stack_end = .;
|
||||
. += _EL0_STACK_SIZE;
|
||||
. = ALIGN(64);
|
||||
__el0_stack = .;
|
||||
} > @DDR@
|
||||
|
||||
|
||||
_end = .;
|
||||
}
|
||||
+281
@@ -0,0 +1,281 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : @STACK_SIZE@;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : @HEAP_SIZE@;
|
||||
|
||||
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
|
||||
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
|
||||
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
|
||||
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
|
||||
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
|
||||
|
||||
@MEMORY_SECTION@
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_vector_table)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
KEEP (*(.vectors))
|
||||
*(.boot)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu_warning)
|
||||
*(.gcc_execpt_table)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.vfp11_veneer)
|
||||
*(.ARM.extab)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
*(.note.gnu.build-id)
|
||||
} > @DDR@
|
||||
|
||||
.init : {
|
||||
KEEP (*(.init))
|
||||
} > @DDR@
|
||||
|
||||
.fini : {
|
||||
KEEP (*(.fini))
|
||||
} > @DDR@
|
||||
|
||||
.rodata : {
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.rodata1 : {
|
||||
__rodata1_start = .;
|
||||
*(.rodata1)
|
||||
*(.rodata1.*)
|
||||
__rodata1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata2 : {
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
__sdata2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss2 : {
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data : {
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.jcr)
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
__data_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data1 : {
|
||||
__data1_start = .;
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
__data1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > @DDR@
|
||||
|
||||
.ctors : {
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.dtors : {
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
___DTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.fixup : {
|
||||
__fixup_start = .;
|
||||
*(.fixup)
|
||||
__fixup_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > @DDR@
|
||||
|
||||
.eh_framehdr : {
|
||||
__eh_framehdr_start = .;
|
||||
*(.eh_framehdr)
|
||||
__eh_framehdr_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > @DDR@
|
||||
|
||||
.mmu_tbl (ALIGN(16384)) : {
|
||||
__mmu_tbl_start = .;
|
||||
*(.mmu_tbl)
|
||||
__mmu_tbl_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidix.*.*)
|
||||
__exidx_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.preinit_array : {
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(SORT(.preinit_array.*)))
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.init_array : {
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.fini_array : {
|
||||
__fini_array_start = .;
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.drvcfg_sec : {
|
||||
. = ALIGN(8);
|
||||
__drvcfgsecdata_start = .;
|
||||
KEEP (*(.drvcfg_sec))
|
||||
__drvcfgsecdata_end = .;
|
||||
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.attributes : {
|
||||
__ARM.attributes_start = .;
|
||||
*(.ARM.attributes)
|
||||
__ARM.attributes_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata : {
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
__sbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tdata : {
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tbss : {
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
__bss_start = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
__bss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
HeapBase = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
HeapLimit = .;
|
||||
} > @DDR@
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
_stack = .;
|
||||
__stack = _stack;
|
||||
. = ALIGN(16);
|
||||
_irq_stack_end = .;
|
||||
. += _IRQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__irq_stack = .;
|
||||
_supervisor_stack_end = .;
|
||||
. += _SUPERVISOR_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__supervisor_stack = .;
|
||||
_abort_stack_end = .;
|
||||
. += _ABORT_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__abort_stack = .;
|
||||
_fiq_stack_end = .;
|
||||
. += _FIQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__fiq_stack = .;
|
||||
_undef_stack_end = .;
|
||||
. += _UNDEF_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__undef_stack = .;
|
||||
} > @DDR@
|
||||
|
||||
end = .;
|
||||
}
|
||||
+208
@@ -0,0 +1,208 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : @STACK_SIZE@;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : @HEAP_SIZE@;
|
||||
|
||||
@MEMORY_SECTION@
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors.reset 0x0 : {
|
||||
KEEP (*(.vectors.reset))
|
||||
}
|
||||
|
||||
.vectors.sw_exception 0x8 : {
|
||||
KEEP (*(.vectors.sw_exception))
|
||||
}
|
||||
|
||||
.vectors.interrupt 0x10 : {
|
||||
KEEP (*(.vectors.interrupt))
|
||||
}
|
||||
|
||||
.vectors.hw_exception 0x20 : {
|
||||
KEEP (*(.vectors.hw_exception))
|
||||
}
|
||||
|
||||
.text : {
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.note.gnu.build-id)
|
||||
} > @DDR@
|
||||
|
||||
.init : {
|
||||
KEEP (*(.init))
|
||||
} > @DDR@
|
||||
|
||||
.fini : {
|
||||
KEEP (*(.fini))
|
||||
} > @DDR@
|
||||
|
||||
.ctors : {
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.dtors : {
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
PROVIDE(__DTOR_END__ = .);
|
||||
PROVIDE(___DTORS_END___ = .);
|
||||
} > @DDR@
|
||||
|
||||
.drvcfg_sec : {
|
||||
. = ALIGN(8);
|
||||
__drvcfgsecdata_start = .;
|
||||
KEEP (*(.drvcfg_sec))
|
||||
__drvcfgsecdata_end = .;
|
||||
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
|
||||
} > @DDR@
|
||||
|
||||
.rodata : {
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata2 : {
|
||||
. = ALIGN(8);
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
. = ALIGN(8);
|
||||
__sdata2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss2 : {
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data : {
|
||||
. = ALIGN(4);
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
__data_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > @DDR@
|
||||
|
||||
.got1 : {
|
||||
*(.got1)
|
||||
} > @DDR@
|
||||
|
||||
.got2 : {
|
||||
*(.got2)
|
||||
} > @DDR@
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > @DDR@
|
||||
|
||||
.jcr : {
|
||||
*(.jcr)
|
||||
} > @DDR@
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > @DDR@
|
||||
|
||||
.sdata : {
|
||||
. = ALIGN(8);
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
. = ALIGN(8);
|
||||
__sbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tdata : {
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tbss : {
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
_heap = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_stack = .;
|
||||
__stack = _stack;
|
||||
} > @DDR@
|
||||
|
||||
_end = .;
|
||||
}
|
||||
+295
@@ -0,0 +1,295 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : @STACK_SIZE@;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : @HEAP_SIZE@;
|
||||
|
||||
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
|
||||
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
|
||||
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
|
||||
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
|
||||
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
|
||||
|
||||
@MEMORY_SECTION@
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_boot)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors : {
|
||||
KEEP (*(.vectors))
|
||||
*(.boot)
|
||||
} > psu_r5_0_atcm_MEM_0
|
||||
|
||||
.bootdata : {
|
||||
*(.bootdata)
|
||||
} > psu_r5_0_atcm_MEM_0
|
||||
|
||||
.text : {
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu_warning)
|
||||
*(.gcc_execpt_table)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.vfp11_veneer)
|
||||
*(.ARM.extab)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
} > @DDR@
|
||||
|
||||
.init : {
|
||||
KEEP (*(.init))
|
||||
} > @DDR@
|
||||
|
||||
.fini : {
|
||||
KEEP (*(.fini))
|
||||
} > @DDR@
|
||||
|
||||
.interp : {
|
||||
KEEP (*(.interp))
|
||||
} > @DDR@
|
||||
|
||||
.note-ABI-tag : {
|
||||
KEEP (*(.note-ABI-tag))
|
||||
} > @DDR@
|
||||
|
||||
.rodata : {
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.rodata1 : {
|
||||
__rodata1_start = .;
|
||||
*(.rodata1)
|
||||
*(.rodata1.*)
|
||||
__rodata1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata2 : {
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
__sdata2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss2 : {
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data : {
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.jcr)
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
__data_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data1 : {
|
||||
__data1_start = .;
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
__data1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > @DDR@
|
||||
|
||||
.ctors : {
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.dtors : {
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
___DTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.fixup : {
|
||||
__fixup_start = .;
|
||||
*(.fixup)
|
||||
__fixup_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > @DDR@
|
||||
|
||||
.eh_framehdr : {
|
||||
__eh_framehdr_start = .;
|
||||
*(.eh_framehdr)
|
||||
__eh_framehdr_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > @DDR@
|
||||
|
||||
.mmu_tbl (ALIGN(16384)) : {
|
||||
__mmu_tbl_start = .;
|
||||
*(.mmu_tbl)
|
||||
__mmu_tbl_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidix.*.*)
|
||||
__exidx_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.preinit_array : {
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(SORT(.preinit_array.*)))
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.init_array : {
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.fini_array : {
|
||||
__fini_array_start = .;
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.drvcfg_sec : {
|
||||
. = ALIGN(8);
|
||||
__drvcfgsecdata_start = .;
|
||||
KEEP (*(.drvcfg_sec))
|
||||
__drvcfgsecdata_end = .;
|
||||
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.attributes : {
|
||||
__ARM.attributes_start = .;
|
||||
*(.ARM.attributes)
|
||||
__ARM.attributes_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata : {
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
__sbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tdata : {
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tbss : {
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > @DDR@
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
HeapBase = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
HeapLimit = .;
|
||||
} > @DDR@
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
_stack = .;
|
||||
__stack = _stack;
|
||||
. = ALIGN(16);
|
||||
_irq_stack_end = .;
|
||||
. += _IRQ_STACK_SIZE;
|
||||
__irq_stack = .;
|
||||
_supervisor_stack_end = .;
|
||||
. += _SUPERVISOR_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__supervisor_stack = .;
|
||||
_abort_stack_end = .;
|
||||
. += _ABORT_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__abort_stack = .;
|
||||
_fiq_stack_end = .;
|
||||
. += _FIQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__fiq_stack = .;
|
||||
_undef_stack_end = .;
|
||||
. += _UNDEF_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__undef_stack = .;
|
||||
} > @DDR@
|
||||
|
||||
end = .;
|
||||
}
|
||||
+295
@@ -0,0 +1,295 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : @STACK_SIZE@;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : @HEAP_SIZE@;
|
||||
|
||||
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
|
||||
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
|
||||
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
|
||||
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
|
||||
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
|
||||
|
||||
@MEMORY_SECTION@
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_vector_table)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors : {
|
||||
KEEP (*(.vectors))
|
||||
*(.boot)
|
||||
} > psx_r52_tcm_alias
|
||||
|
||||
.bootdata : {
|
||||
*(.bootdata)
|
||||
} > psx_r52_tcm_alias
|
||||
|
||||
.text : {
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu_warning)
|
||||
*(.gcc_execpt_table)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.vfp11_veneer)
|
||||
*(.ARM.extab)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
} > @DDR@
|
||||
|
||||
.init : {
|
||||
KEEP (*(.init))
|
||||
} > @DDR@
|
||||
|
||||
.fini : {
|
||||
KEEP (*(.fini))
|
||||
} > @DDR@
|
||||
|
||||
.interp : {
|
||||
KEEP (*(.interp))
|
||||
} > @DDR@
|
||||
|
||||
.note-ABI-tag : {
|
||||
KEEP (*(.note-ABI-tag))
|
||||
} > @DDR@
|
||||
|
||||
.rodata : {
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.rodata1 : {
|
||||
__rodata1_start = .;
|
||||
*(.rodata1)
|
||||
*(.rodata1.*)
|
||||
__rodata1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata2 : {
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
__sdata2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss2 : {
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data : {
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.jcr)
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
__data_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data1 : {
|
||||
__data1_start = .;
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
__data1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > @DDR@
|
||||
|
||||
.ctors : {
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.dtors : {
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
___DTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.fixup : {
|
||||
__fixup_start = .;
|
||||
*(.fixup)
|
||||
__fixup_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > @DDR@
|
||||
|
||||
.eh_framehdr : {
|
||||
__eh_framehdr_start = .;
|
||||
*(.eh_framehdr)
|
||||
__eh_framehdr_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > @DDR@
|
||||
|
||||
.mmu_tbl (ALIGN(16384)) : {
|
||||
__mmu_tbl_start = .;
|
||||
*(.mmu_tbl)
|
||||
__mmu_tbl_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidix.*.*)
|
||||
__exidx_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.preinit_array : {
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(SORT(.preinit_array.*)))
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.init_array : {
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.fini_array : {
|
||||
__fini_array_start = .;
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.drvcfg_sec : {
|
||||
. = ALIGN(8);
|
||||
__drvcfgsecdata_start = .;
|
||||
KEEP (*(.drvcfg_sec))
|
||||
__drvcfgsecdata_end = .;
|
||||
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.attributes : {
|
||||
__ARM.attributes_start = .;
|
||||
*(.ARM.attributes)
|
||||
__ARM.attributes_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata : {
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
__sbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tdata : {
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tbss : {
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > @DDR@
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
HeapBase = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
HeapLimit = .;
|
||||
} > @DDR@
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
_stack = .;
|
||||
__stack = _stack;
|
||||
. = ALIGN(16);
|
||||
_irq_stack_end = .;
|
||||
. += _IRQ_STACK_SIZE;
|
||||
__irq_stack = .;
|
||||
_supervisor_stack_end = .;
|
||||
. += _SUPERVISOR_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__supervisor_stack = .;
|
||||
_abort_stack_end = .;
|
||||
. += _ABORT_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__abort_stack = .;
|
||||
_fiq_stack_end = .;
|
||||
. += _FIQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__fiq_stack = .;
|
||||
_undef_stack_end = .;
|
||||
. += _UNDEF_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__undef_stack = .;
|
||||
} > @DDR@
|
||||
|
||||
end = .;
|
||||
}
|
||||
+295
@@ -0,0 +1,295 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : @STACK_SIZE@;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : @HEAP_SIZE@;
|
||||
|
||||
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
|
||||
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
|
||||
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
|
||||
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
|
||||
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
|
||||
|
||||
@MEMORY_SECTION@
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_boot)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors : {
|
||||
KEEP (*(.vectors))
|
||||
*(.boot)
|
||||
} > psv_r5_0_atcm_MEM_0
|
||||
|
||||
.bootdata : {
|
||||
*(.bootdata)
|
||||
} > psv_r5_0_atcm_MEM_0
|
||||
|
||||
.text : {
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu_warning)
|
||||
*(.gcc_execpt_table)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.vfp11_veneer)
|
||||
*(.ARM.extab)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
} > @DDR@
|
||||
|
||||
.init : {
|
||||
KEEP (*(.init))
|
||||
} > @DDR@
|
||||
|
||||
.fini : {
|
||||
KEEP (*(.fini))
|
||||
} > @DDR@
|
||||
|
||||
.interp : {
|
||||
KEEP (*(.interp))
|
||||
} > @DDR@
|
||||
|
||||
.note-ABI-tag : {
|
||||
KEEP (*(.note-ABI-tag))
|
||||
} > @DDR@
|
||||
|
||||
.rodata : {
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.rodata1 : {
|
||||
__rodata1_start = .;
|
||||
*(.rodata1)
|
||||
*(.rodata1.*)
|
||||
__rodata1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata2 : {
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
__sdata2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss2 : {
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data : {
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.jcr)
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
__data_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.data1 : {
|
||||
__data1_start = .;
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
__data1_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > @DDR@
|
||||
|
||||
.ctors : {
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.dtors : {
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
___DTORS_END___ = .;
|
||||
} > @DDR@
|
||||
|
||||
.fixup : {
|
||||
__fixup_start = .;
|
||||
*(.fixup)
|
||||
__fixup_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > @DDR@
|
||||
|
||||
.eh_framehdr : {
|
||||
__eh_framehdr_start = .;
|
||||
*(.eh_framehdr)
|
||||
__eh_framehdr_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > @DDR@
|
||||
|
||||
.mmu_tbl (ALIGN(16384)) : {
|
||||
__mmu_tbl_start = .;
|
||||
*(.mmu_tbl)
|
||||
__mmu_tbl_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidix.*.*)
|
||||
__exidx_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.preinit_array : {
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(SORT(.preinit_array.*)))
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.init_array : {
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.fini_array : {
|
||||
__fini_array_start = .;
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.drvcfg_sec : {
|
||||
. = ALIGN(8);
|
||||
__drvcfgsecdata_start = .;
|
||||
KEEP (*(.drvcfg_sec))
|
||||
__drvcfgsecdata_end = .;
|
||||
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
|
||||
} > @DDR@
|
||||
|
||||
.ARM.attributes : {
|
||||
__ARM.attributes_start = .;
|
||||
*(.ARM.attributes)
|
||||
__ARM.attributes_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sdata : {
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
__sbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tdata : {
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.tbss : {
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > @DDR@
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > @DDR@
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
HeapBase = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
HeapLimit = .;
|
||||
} > @DDR@
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
_stack = .;
|
||||
__stack = _stack;
|
||||
. = ALIGN(16);
|
||||
_irq_stack_end = .;
|
||||
. += _IRQ_STACK_SIZE;
|
||||
__irq_stack = .;
|
||||
_supervisor_stack_end = .;
|
||||
. += _SUPERVISOR_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__supervisor_stack = .;
|
||||
_abort_stack_end = .;
|
||||
. += _ABORT_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__abort_stack = .;
|
||||
_fiq_stack_end = .;
|
||||
. += _FIQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__fiq_stack = .;
|
||||
_undef_stack_end = .;
|
||||
. += _UNDEF_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__undef_stack = .;
|
||||
} > @DDR@
|
||||
|
||||
end = .;
|
||||
}
|
||||
@@ -0,0 +1,299 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
|
||||
|
||||
_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
|
||||
|
||||
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
|
||||
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
|
||||
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
|
||||
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
|
||||
|
||||
/* Define Memories in the system */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
|
||||
ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
|
||||
}
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_vector_table)
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
*(.vectors)
|
||||
*(.boot)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu_warning)
|
||||
*(.gcc_execpt_table)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.vfp11_veneer)
|
||||
*(.ARM.extab)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.note.gnu.build-id : {
|
||||
KEEP (*(.note.gnu.build-id))
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.init : {
|
||||
KEEP (*(.init))
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.fini : {
|
||||
KEEP (*(.fini))
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.rodata : {
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.rodata1 : {
|
||||
__rodata1_start = .;
|
||||
*(.rodata1)
|
||||
*(.rodata1.*)
|
||||
__rodata1_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.sdata2 : {
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
__sdata2_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.sbss2 : {
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.data : {
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.jcr)
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
__data_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.data1 : {
|
||||
__data1_start = .;
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
__data1_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.ctors : {
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.dtors : {
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
___DTORS_END___ = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.fixup : {
|
||||
__fixup_start = .;
|
||||
*(.fixup)
|
||||
__fixup_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.eh_framehdr : {
|
||||
__eh_framehdr_start = .;
|
||||
*(.eh_framehdr)
|
||||
__eh_framehdr_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.mmu_tbl (ALIGN(0x4000)): {
|
||||
__mmu_tbl_start = .;
|
||||
*(.mmu_tbl)
|
||||
__mmu_tbl_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidix.*.*)
|
||||
__exidx_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.preinit_array : {
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(SORT(.preinit_array.*)))
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.init_array : {
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.fini_array : {
|
||||
__fini_array_start = .;
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.rsa_ac : {
|
||||
. = ALIGN(64);
|
||||
__rsa_ac_start = .;
|
||||
. += _RSA_AC_SIZE;
|
||||
__rsa_ac_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.ARM.attributes : {
|
||||
__ARM.attributes_start = .;
|
||||
*(.ARM.attributes)
|
||||
__ARM.attributes_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.sdata : {
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
__sbss_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.tdata : {
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.tbss : {
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
__bss_start = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
__bss_end = .;
|
||||
__bss_end__ = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.drvcfg_sec : {
|
||||
. = ALIGN(8);
|
||||
__drvcfgsecdata_start = .;
|
||||
KEEP (*(.drvcfg_sec))
|
||||
__drvcfgsecdata_end = .;
|
||||
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
HeapBase = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
HeapLimit = .;
|
||||
} > ps7_ram_0_S_AXI_BASEADDR
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
_stack = .;
|
||||
__stack = _stack;
|
||||
. = ALIGN(16);
|
||||
_irq_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
__irq_stack = .;
|
||||
_supervisor_stack_end = .;
|
||||
. += _SUPERVISOR_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__supervisor_stack = .;
|
||||
_abort_stack_end = .;
|
||||
. += _ABORT_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__abort_stack = .;
|
||||
_fiq_stack_end = .;
|
||||
. += _FIQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__fiq_stack = .;
|
||||
_undef_stack_end = .;
|
||||
. += _UNDEF_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__undef_stack = .;
|
||||
} > ps7_ram_1_S_AXI_BASEADDR
|
||||
|
||||
_end = .;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,484 @@
|
||||
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
|
||||
* All rights reserved.
|
||||
*
|
||||
* This package is an SSL implementation written
|
||||
* by Eric Young (eay@cryptsoft.com).
|
||||
* The implementation was written so as to conform with Netscapes SSL.
|
||||
*
|
||||
* This library is free for commercial and non-commercial use as long as
|
||||
* the following conditions are adhered to. The following conditions
|
||||
* apply to all code found in this distribution, be it the RC4, RSA,
|
||||
* lhash, DES, etc., code; not just the SSL code. The SSL documentation
|
||||
* included with this distribution is covered by the same copyright terms
|
||||
* except that the holder is Tim Hudson (tjh@cryptsoft.com).
|
||||
*
|
||||
* Copyright remains Eric Young's, and as such any Copyright notices in
|
||||
* the code are not to be removed.
|
||||
* If this package is used in a product, Eric Young should be given attribution
|
||||
* as the author of the parts of the library used.
|
||||
* This can be in the form of a textual message at program startup or
|
||||
* in documentation (online or textual) provided with the package.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* "This product includes cryptographic software written by
|
||||
* Eric Young (eay@cryptsoft.com)"
|
||||
* The word 'cryptographic' can be left out if the routines from the library
|
||||
* being used are not cryptographic related :-).
|
||||
* 4. If you include any Windows specific code (or a derivative thereof) from
|
||||
* the apps directory (application code) you must include an acknowledgement:
|
||||
* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* The licence and distribution terms for any publicly available version or
|
||||
* derivative of this code cannot be changed. i.e. this code cannot simply be
|
||||
* copied and put under another distribution licence
|
||||
* [including the GNU Public Licence.]
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file md5.c
|
||||
*
|
||||
* Contains code to calculate checksum using md5 algorithm
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 5.00a sgd 05/17/13 Initial release
|
||||
*
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************** Include Files *********************************/
|
||||
|
||||
#include "md5.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the memory
|
||||
*
|
||||
* @param dest
|
||||
*
|
||||
* @param ch
|
||||
*
|
||||
* @param count
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
inline void * MD5Memset( void *dest, int ch, u32 count )
|
||||
{
|
||||
register char *dst8 = (char*)dest;
|
||||
|
||||
while( count-- )
|
||||
*dst8++ = ch;
|
||||
|
||||
return dest;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function copy the memory
|
||||
*
|
||||
* @param dest
|
||||
*
|
||||
* @param ch
|
||||
*
|
||||
* @param count
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
inline void * MD5Memcpy( void *dest, const void *src,
|
||||
u32 count, boolean doByteSwap )
|
||||
{
|
||||
register char * dst8 = (char*)dest;
|
||||
register char * src8 = (char*)src;
|
||||
|
||||
if( doByteSwap == FALSE ) {
|
||||
while( count-- )
|
||||
*dst8++ = *src8++;
|
||||
} else {
|
||||
count /= sizeof( u32 );
|
||||
|
||||
while( count-- ) {
|
||||
dst8[ 0 ] = src8[ 3 ];
|
||||
dst8[ 1 ] = src8[ 2 ];
|
||||
dst8[ 2 ] = src8[ 1 ];
|
||||
dst8[ 3 ] = src8[ 0 ];
|
||||
|
||||
dst8 += 4;
|
||||
src8 += 4;
|
||||
}
|
||||
}
|
||||
|
||||
return dest;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function is the core of the MD5 algorithm,
|
||||
* this alters an existing MD5 hash to
|
||||
* reflect the addition of 16 longwords of new data. MD5Update blocks
|
||||
* the data and converts bytes into longwords for this routine.
|
||||
*
|
||||
* Use binary integer part of the sine of integers (Radians) as constants.
|
||||
* Calculated as:
|
||||
*
|
||||
* for( i = 0; i < 63; i++ )
|
||||
* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
|
||||
*
|
||||
* Following number is the per-round shift amount.
|
||||
*
|
||||
* @param dest
|
||||
*
|
||||
* @param ch
|
||||
*
|
||||
* @param count
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
void MD5Transform( u32 *buffer, u32 *intermediate )
|
||||
{
|
||||
register u32 a, b, c, d;
|
||||
|
||||
a = buffer[ 0 ];
|
||||
b = buffer[ 1 ];
|
||||
c = buffer[ 2 ];
|
||||
d = buffer[ 3 ];
|
||||
|
||||
MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
|
||||
MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
|
||||
MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
|
||||
MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
|
||||
MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
|
||||
MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
|
||||
MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
|
||||
MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
|
||||
MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
|
||||
MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
|
||||
MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
|
||||
MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
|
||||
MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
|
||||
MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
|
||||
MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
|
||||
MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
|
||||
|
||||
MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
|
||||
MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
|
||||
MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
|
||||
MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
|
||||
MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
|
||||
MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
|
||||
MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
|
||||
MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
|
||||
MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
|
||||
MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
|
||||
MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
|
||||
MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
|
||||
MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
|
||||
MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
|
||||
MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
|
||||
MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
|
||||
|
||||
MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
|
||||
MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
|
||||
MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
|
||||
MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
|
||||
MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
|
||||
MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
|
||||
MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
|
||||
MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
|
||||
MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
|
||||
MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
|
||||
MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
|
||||
MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
|
||||
MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
|
||||
MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
|
||||
MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
|
||||
MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
|
||||
|
||||
MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
|
||||
MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
|
||||
MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
|
||||
MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
|
||||
MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
|
||||
MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
|
||||
MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
|
||||
MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
|
||||
MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
|
||||
MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
|
||||
MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
|
||||
MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
|
||||
MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
|
||||
MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
|
||||
MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
|
||||
MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
|
||||
|
||||
buffer[ 0 ] += a;
|
||||
buffer[ 1 ] += b;
|
||||
buffer[ 2 ] += c;
|
||||
buffer[ 3 ] += d;
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function Start MD5 accumulation
|
||||
* Set bit count to 0 and buffer to mysterious initialization constants
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
inline void MD5Init( MD5Context *context )
|
||||
{
|
||||
|
||||
context->buffer[ 0 ] = 0x67452301;
|
||||
context->buffer[ 1 ] = 0xefcdab89;
|
||||
context->buffer[ 2 ] = 0x98badcfe;
|
||||
context->buffer[ 3 ] = 0x10325476;
|
||||
|
||||
context->bits[ 0 ] = 0;
|
||||
context->bits[ 1 ] = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function updates context to reflect the concatenation of another
|
||||
* buffer full of bytes
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
inline void MD5Update( MD5Context *context, u8 *buffer,
|
||||
u32 len, boolean doByteSwap )
|
||||
{
|
||||
register u32 temp;
|
||||
register u8 * p;
|
||||
|
||||
/*
|
||||
* Update bitcount
|
||||
*/
|
||||
|
||||
temp = context->bits[ 0 ];
|
||||
|
||||
if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
|
||||
/*
|
||||
* Carry from low to high
|
||||
*/
|
||||
context->bits[ 1 ]++;
|
||||
}
|
||||
|
||||
context->bits[ 1 ] += len >> 29;
|
||||
|
||||
/*
|
||||
* Bytes already in shsInfo->data
|
||||
*/
|
||||
|
||||
temp = ( temp >> 3 ) & 0x3f;
|
||||
|
||||
/*
|
||||
* Handle any leading odd-sized chunks
|
||||
*/
|
||||
|
||||
if( temp ) {
|
||||
p = (u8 *)context->intermediate + temp;
|
||||
|
||||
temp = MD5_SIGNATURE_BYTE_SIZE - temp;
|
||||
|
||||
if( len < temp ) {
|
||||
MD5Memcpy( p, buffer, len, doByteSwap );
|
||||
return;
|
||||
}
|
||||
|
||||
MD5Memcpy( p, buffer, temp, doByteSwap );
|
||||
|
||||
MD5Transform( context->buffer, (u32 *)context->intermediate );
|
||||
|
||||
buffer += temp;
|
||||
len -= temp;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Process data in 64-byte, 512 bit, chunks
|
||||
*/
|
||||
|
||||
while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
|
||||
MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
|
||||
doByteSwap );
|
||||
|
||||
MD5Transform( context->buffer, (u32 *)context->intermediate );
|
||||
|
||||
buffer += MD5_SIGNATURE_BYTE_SIZE;
|
||||
len -= MD5_SIGNATURE_BYTE_SIZE;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle any remaining bytes of data
|
||||
*/
|
||||
MD5Memcpy( context->intermediate, buffer, len, doByteSwap );
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function final wrap-up - pad to 64-byte boundary with the bit pattern
|
||||
* 1 0* (64-bit count of bits processed, MSB-first
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
inline void MD5Final( MD5Context *context, u8 *digest,
|
||||
boolean doByteSwap )
|
||||
{
|
||||
u32 count;
|
||||
u8 * p;
|
||||
|
||||
/*
|
||||
* Compute number of bytes mod 64
|
||||
*/
|
||||
count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
|
||||
|
||||
/*
|
||||
* Set the first char of padding to 0x80. This is safe since there is
|
||||
* always at least one byte free
|
||||
*/
|
||||
p = context->intermediate + count;
|
||||
*p++ = 0x80;
|
||||
|
||||
/*
|
||||
* Bytes of padding needed to make 64 bytes
|
||||
*/
|
||||
count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
|
||||
|
||||
/*
|
||||
* Pad out to 56 mod 64
|
||||
*/
|
||||
if( count < 8 ) {
|
||||
/*
|
||||
* Two lots of padding: Pad the first block to 64 bytes
|
||||
*/
|
||||
MD5Memset( p, 0, count );
|
||||
|
||||
MD5Transform( context->buffer, (u32 *)context->intermediate );
|
||||
|
||||
/*
|
||||
* Now fill the next block with 56 bytes
|
||||
*/
|
||||
MD5Memset( context->intermediate, 0, 56 );
|
||||
} else {
|
||||
/*
|
||||
* Pad block to 56 bytes
|
||||
*/
|
||||
MD5Memset( p, 0, count - 8 );
|
||||
}
|
||||
|
||||
/*
|
||||
* Append length in bits and transform
|
||||
*/
|
||||
( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
|
||||
( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
|
||||
|
||||
MD5Transform( context->buffer, (u32 *)context->intermediate );
|
||||
|
||||
/*
|
||||
* Now return the digest
|
||||
*/
|
||||
MD5Memcpy( digest, context->buffer, 16, doByteSwap );
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
|
||||
* 'input'. 'digest' must have enough space to hold 16 bytes
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @param
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
|
||||
{
|
||||
MD5Context context;
|
||||
|
||||
MD5Init( &context );
|
||||
|
||||
MD5Update( &context, input, len, doByteSwap );
|
||||
|
||||
MD5Final( &context, digest, doByteSwap );
|
||||
}
|
||||
@@ -0,0 +1,94 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file md5.h
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 5.00a sgd 05/17/13 Initial release
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___MD5_H___
|
||||
#define ___MD5_H___
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define MD5_SIGNATURE_BYTE_SIZE 64
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef u8 boolean;
|
||||
typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
|
||||
|
||||
struct MD5Context
|
||||
{
|
||||
u32 buffer[ 4 ];
|
||||
u32 bits[ 2 ];
|
||||
signature intermediate;
|
||||
};
|
||||
typedef struct MD5Context MD5Context;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/*
|
||||
* The four core functions - F1 is optimized somewhat
|
||||
*/
|
||||
#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
|
||||
#define F2( x, y, z ) F1( z, x, y )
|
||||
#define F3( x, y, z ) ( x ^ y ^ z )
|
||||
#define F4( x, y, z ) ( y ^ ( x | ~z ) )
|
||||
|
||||
|
||||
/*
|
||||
* This is the central step in the MD5 algorithm
|
||||
*/
|
||||
#define MD5_STEP( f, w, x, y, z, data, s ) \
|
||||
( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void * MD5Memset( void *dest, int ch, u32 count );
|
||||
|
||||
void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
|
||||
|
||||
void MD5Transform( u32 *buffer, u32 *intermediate );
|
||||
|
||||
void MD5Init( MD5Context *context );
|
||||
|
||||
void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
|
||||
|
||||
void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
|
||||
|
||||
void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* ___MD5_H___ */
|
||||
@@ -0,0 +1,274 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file nand.c
|
||||
*
|
||||
* Contains code for the NAND FLASH functionality. Bad Block management
|
||||
* is simple: skip the bad blocks and keep going.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 01/10/10 Initial release
|
||||
* 2.00a mb 25/05/12 fsbl changes for standalone bsp based
|
||||
* 3.00a sgd 30/01/13 Code cleanup
|
||||
* 5.00a sgd 17/05/13 Support for Multi Boot
|
||||
* 21.2 ng 07/25/23 Add SDT support
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xparameters.h"
|
||||
#include "fsbl.h"
|
||||
#if defined(XPAR_PS7_NAND_0_BASEADDR) || defined(XPAR_XNANDPS_0_FLASHBASE)
|
||||
#include "nand.h"
|
||||
#include "xnandps_bbm.h"
|
||||
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#ifndef SDT
|
||||
#define NAND_DEVICE XPAR_XNANDPS_0_DEVICE_ID
|
||||
#else
|
||||
#define NAND_DEVICE XPAR_XNANDPS_0_BASEADDR
|
||||
#endif
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
|
||||
u64 Offset,
|
||||
u32 Length);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern u32 FlashReadBaseAddress;
|
||||
extern u32 FlashOffsetAddress;
|
||||
|
||||
XNandPs *NandInstPtr;
|
||||
XNandPs NandInstance; /* XNand Instance. */
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function initializes the controller for the NAND FLASH interface.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the controller initializes correctly
|
||||
* - XST_FAILURE if the controller fails to initializes correctly
|
||||
*
|
||||
* @note none.
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 InitNand(void)
|
||||
{
|
||||
|
||||
u32 Status;
|
||||
XNandPs_Config *ConfigPtr;
|
||||
|
||||
/*
|
||||
* Set up pointers to instance and the config structure
|
||||
*/
|
||||
NandInstPtr = &NandInstance;
|
||||
|
||||
/*
|
||||
* Initialize the flash driver.
|
||||
*/
|
||||
ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE);
|
||||
|
||||
if (ConfigPtr == NULL) {
|
||||
fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr,
|
||||
ConfigPtr->SmcBase,ConfigPtr->FlashBase);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_GENERAL,"NAND initialization failed \n \r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up base address for access
|
||||
*/
|
||||
FlashReadBaseAddress = XPS_NAND_BASEADDR;
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n",
|
||||
NandInstPtr->Geometry.FlashWidth);
|
||||
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n",
|
||||
Status);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* set up the FLASH access pointers
|
||||
*/
|
||||
fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function provides the NAND FLASH interface for the Simplified header
|
||||
* functionality. This function handles bad blocks.
|
||||
*
|
||||
* The source address is the absolute good address, bad blocks are skipped
|
||||
* without incrementing the source address.
|
||||
*
|
||||
* @param SourceAddress is address in FLASH data space, absolute good address
|
||||
* @param DestinationAddress is address in OCM data space
|
||||
*
|
||||
* @return XST_SUCCESS if the transfer completes correctly
|
||||
* XST_FAILURE if the transfer fails to completes correctly
|
||||
*
|
||||
* @note none.
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
|
||||
{
|
||||
u32 ActLen;
|
||||
u32 BlockOffset;
|
||||
u32 Block;
|
||||
u32 Status;
|
||||
u32 BytesLeft = LengthBytes;
|
||||
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
|
||||
u8 *BufPtr = (u8 *)DestinationAddress;
|
||||
u32 ReadLen;
|
||||
u32 BlockReadLen;
|
||||
u32 Offset;
|
||||
u32 TmpAddress = 0 ;
|
||||
u32 BlockCount = 0;
|
||||
u32 BadBlocks = 0;
|
||||
|
||||
/*
|
||||
* First get bad blocks before the source address
|
||||
*/
|
||||
while (TmpAddress < SourceAddress) {
|
||||
while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) ==
|
||||
XST_SUCCESS) {
|
||||
BlockCount ++;
|
||||
BadBlocks ++;
|
||||
}
|
||||
|
||||
TmpAddress += BlockSize;
|
||||
BlockCount ++;
|
||||
}
|
||||
|
||||
Offset = SourceAddress + BadBlocks * BlockSize;
|
||||
|
||||
/*
|
||||
* Calculate the actual length including bad blocks
|
||||
*/
|
||||
ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes);
|
||||
|
||||
/*
|
||||
* Check if the actual length cross flash size
|
||||
*/
|
||||
if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
while (BytesLeft > 0) {
|
||||
BlockOffset = Offset & (BlockSize - 1);
|
||||
Block = (Offset & ~(BlockSize - 1))/BlockSize;
|
||||
BlockReadLen = BlockSize - BlockOffset;
|
||||
|
||||
Status = XNandPs_IsBlockBad(NandInstPtr, Block);
|
||||
if (Status == XST_SUCCESS) {
|
||||
/* Move to next block */
|
||||
Offset += BlockReadLen;
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if we cross block boundary
|
||||
*/
|
||||
if (BytesLeft < BlockReadLen) {
|
||||
ReadLen = BytesLeft;
|
||||
} else {
|
||||
ReadLen = BlockReadLen;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read from the NAND flash
|
||||
*/
|
||||
Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return Status;
|
||||
}
|
||||
BytesLeft -= ReadLen;
|
||||
Offset += ReadLen;
|
||||
BufPtr += ReadLen;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function returns the length including bad blocks from a given offset and
|
||||
* length.
|
||||
*
|
||||
* @param NandInstPtr is the pointer to the XNandPs instance.
|
||||
* @param Offset is the flash data address to read from.
|
||||
* @param Length is number of bytes to read.
|
||||
*
|
||||
* @return
|
||||
* - Return actual length including bad blocks.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
|
||||
u64 Offset,
|
||||
u32 Length)
|
||||
{
|
||||
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
|
||||
u32 CurBlockLen;
|
||||
u32 CurBlock;
|
||||
u32 Status;
|
||||
u32 TempLen = 0;
|
||||
u32 ActLen = 0;
|
||||
|
||||
while (TempLen < Length) {
|
||||
CurBlockLen = BlockSize - (Offset & (BlockSize - 1));
|
||||
CurBlock = (Offset & ~(BlockSize - 1))/BlockSize;
|
||||
|
||||
/*
|
||||
* Check if the block is bad
|
||||
*/
|
||||
Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock);
|
||||
if (Status != XST_SUCCESS) {
|
||||
/* Good Block */
|
||||
TempLen += CurBlockLen;
|
||||
}
|
||||
ActLen += CurBlockLen;
|
||||
Offset += CurBlockLen;
|
||||
if (Offset >= NandInstPtr->Geometry.DeviceSize) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ActLen;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,67 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file nand.h
|
||||
*
|
||||
* This file contains the interface for the NAND FLASH functionality
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 01/10/10 Initial release
|
||||
* 2.00a mb 30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
|
||||
* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
|
||||
* 21.2 ng 07/25/23 Add SDT support
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___NAND_H___
|
||||
#define ___NAND_H___
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
|
||||
#if defined(XPAR_PS7_NAND_0_BASEADDR) || defined(XPAR_XNANDPS_0_FLASHBASE)
|
||||
|
||||
#include "xnandps.h"
|
||||
#include "xnandps_bbm.h"
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
u32 InitNand(void);
|
||||
|
||||
u32 NandAccess( u32 SourceAddress,
|
||||
u32 DestinationAddress,
|
||||
u32 LengthWords);
|
||||
#endif
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* ___NAND_H___ */
|
||||
|
||||
@@ -0,0 +1,118 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file nor.c
|
||||
*
|
||||
* Contains code for the NOR FLASH functionality.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 01/10/10 Initial release
|
||||
* 2.00a mb 25/05/12 mio init removed
|
||||
* 3.00a sgd 30/01/13 Code cleanup
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "fsbl.h"
|
||||
#include "nor.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern u32 FlashReadBaseAddress;
|
||||
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function initializes the controller for the NOR FLASH interface.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void InitNor(void)
|
||||
{
|
||||
|
||||
/*
|
||||
* Set up the base address for access
|
||||
*/
|
||||
FlashReadBaseAddress = XPS_NOR_BASEADDR;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function provides the NOR FLASH interface for the Simplified header
|
||||
* functionality.
|
||||
*
|
||||
* @param SourceAddress is address in FLASH data space
|
||||
* @param DestinationAddress is address in OCM data space
|
||||
* @param LengthBytes is the data length to transfer in bytes
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the write completes correctly
|
||||
* - XST_FAILURE if the write fails to completes correctly
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
|
||||
{
|
||||
u32 Data;
|
||||
u32 Count;
|
||||
u32 *SourceAddr;
|
||||
u32 *DestAddr;
|
||||
u32 LengthWords;
|
||||
|
||||
/*
|
||||
* check for non-word tail
|
||||
* add bytes to cover the end
|
||||
*/
|
||||
if ((LengthBytes%4) != 0){
|
||||
|
||||
LengthBytes += (4 - (LengthBytes & 0x00000003));
|
||||
}
|
||||
|
||||
LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
|
||||
|
||||
SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
|
||||
DestAddr = (u32 *)(DestinationAddress);
|
||||
|
||||
/*
|
||||
* Word transfers, endianism isn't an issue
|
||||
*/
|
||||
for (Count=0; Count < LengthWords; Count++){
|
||||
|
||||
Data = Xil_In32((u32)(SourceAddr++));
|
||||
Xil_Out32((u32)(DestAddr++), Data);
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file nor.h
|
||||
*
|
||||
* This file contains the interface for the NOR FLASH functionality
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 01/10/10 Initial release
|
||||
* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___NOR_H___
|
||||
#define ___NOR_H___
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
void InitNor(void);
|
||||
|
||||
u32 NorAccess( u32 SourceAddress,
|
||||
u32 DestinationAddress,
|
||||
u32 LengthBytes);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* ___NOR_H___ */
|
||||
|
||||
@@ -0,0 +1,799 @@
|
||||
/*****************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file pcap.c
|
||||
*
|
||||
* Contains code for enabling and accessing the PCAP
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 02/10/10 Initial release
|
||||
* 2.00a jz 05/28/11 Add SD support
|
||||
* 2.00a mb 25/05/12 using the EDK provided devcfg driver
|
||||
* Nand/SD encryption and review comments
|
||||
* 3.00a mb 16/08/12 Added the poll function
|
||||
* Removed the FPGA_RST_CTRL define
|
||||
* Added the flag for NON PS instantiated bitstream
|
||||
* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
|
||||
* fabric_init()
|
||||
* Fix for CR#689026 - FSBL doesn't hold PL resets active
|
||||
* during bit download
|
||||
* Fix for CR#699475 - FSBL functionality is broken and
|
||||
* its not able to boot in QSPI/NAND
|
||||
* bootmode
|
||||
* Fix for CR#705664 - FSBL fails to decrypt the
|
||||
* bitstream when the image is AES
|
||||
* encrypted using non-zero key value
|
||||
* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
|
||||
* changelogs in FSBL
|
||||
* 7.00a kc 10/25/13 Fix for CR#724620 - How to handle PCAP_MODE after
|
||||
* bitstream configuration
|
||||
* Fix for CR#726178 - FabricInit() PROG_B is kept active
|
||||
* for 5mS.
|
||||
* Fix for CR#731839 - FSBL has to check the
|
||||
* HMAC error status after decryption
|
||||
* 12/04/13 Fix for CR#764382 - How to handle PCAP_MODE after
|
||||
* bitstream configuration - PCAP_MODE
|
||||
* and PCAP_PR bits are not modified
|
||||
* 8.00a kc 2/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
|
||||
* is not proper
|
||||
* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
|
||||
* 13.00a ssc 04/10/15 Fix for CR#846899 - Corrected logic to clear
|
||||
* DMA done count
|
||||
* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
|
||||
* In pcap.c/pcap.h/main.h,
|
||||
* Fabric Initialization sequence
|
||||
* is modified to check the PL power
|
||||
* before sequence starts and checking
|
||||
* INIT_B reset status twice in case
|
||||
* of failure.
|
||||
* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
|
||||
* In pcap.c, check pl power
|
||||
* through MCTRL register for
|
||||
* 3.0 and later versions of silicon.
|
||||
* 21.1 ng 07/13/23 Add SDT support
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "pcap.h"
|
||||
#include "nand.h" /* For NAND geometry information */
|
||||
#include "fsbl.h"
|
||||
#include "image_mover.h" /* For MoveImage */
|
||||
#include "xparameters.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xdevcfg.h"
|
||||
#include "sleep.h"
|
||||
#ifndef SDT
|
||||
#include "xtime_l.h"
|
||||
#else
|
||||
#include "xiltimer.h"
|
||||
#endif
|
||||
#ifdef XPAR_XWDTPS_0_BASEADDR
|
||||
#include "xwdtps.h"
|
||||
#endif
|
||||
/************************** Constant Definitions *****************************/
|
||||
/*
|
||||
* The following constants map to the XPAR parameters created in the
|
||||
* xparameters.h file. They are only defined here such that a user can easily
|
||||
* change all the needed parameters in one place.
|
||||
*/
|
||||
|
||||
#ifndef SDT
|
||||
#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
|
||||
#else
|
||||
#define DCFG_DEVICE_ID XPAR_XDEVCFG_0_BASEADDR
|
||||
#endif
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
/* Devcfg driver instance */
|
||||
static XDcfg DcfgInstance;
|
||||
XDcfg *DcfgInstPtr;
|
||||
extern u32 Silicon_Version;
|
||||
#ifdef XPAR_XWDTPS_0_BASEADDR
|
||||
extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function transfer data using PCAP
|
||||
*
|
||||
* @param SourceDataPtr is a pointer to where the data is read from
|
||||
* @param DestinationDataPtr is a pointer to where the data is written to
|
||||
* @param SourceLength is the length of the data to be moved in words
|
||||
* @param DestinationLength is the length of the data to be moved in words
|
||||
* @param SecureTransfer indicated the encryption key location, 0 for
|
||||
* non-encrypted
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the transfer is successful
|
||||
* - XST_FAILURE if the transfer fails
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
|
||||
u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
|
||||
{
|
||||
u32 Status;
|
||||
u32 IntrStsReg;
|
||||
u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
|
||||
|
||||
/*
|
||||
* Check for secure transfer
|
||||
*/
|
||||
if (SecureTransfer) {
|
||||
PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
|
||||
}
|
||||
|
||||
#ifdef FSBL_PERF
|
||||
XTime tXferCur = 0;
|
||||
FsblGetGlobalTime(&tXferCur);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Clear the PCAP status registers
|
||||
*/
|
||||
Status = ClearPcapStatus();
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
#ifdef XPAR_XWDTPS_0_BASEADDR
|
||||
/*
|
||||
* Prevent WDT reset
|
||||
*/
|
||||
XWdtPs_RestartWdt(&Watchdog);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PCAP single DMA transfer setup
|
||||
*/
|
||||
SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
|
||||
DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
|
||||
|
||||
/*
|
||||
* Transfer using Device Configuration
|
||||
*/
|
||||
Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
|
||||
SourceLength,
|
||||
(u8 *)DestinationDataPtr,
|
||||
DestinationLength, PcapTransferType);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dump the PCAP registers
|
||||
*/
|
||||
PcapDumpRegisters();
|
||||
|
||||
/*
|
||||
* Poll for the DMA done
|
||||
*/
|
||||
Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
|
||||
|
||||
/*
|
||||
* Check for errors
|
||||
*/
|
||||
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
||||
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
|
||||
fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* For Performance measurement
|
||||
*/
|
||||
#ifdef FSBL_PERF
|
||||
XTime tXferEnd = 0;
|
||||
fsbl_printf(DEBUG_GENERAL,"Time taken is ");
|
||||
FsblMeasurePerfTime(tXferCur,tXferEnd);
|
||||
#endif
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function loads PL partition using PCAP
|
||||
*
|
||||
* @param SourceDataPtr is a pointer to where the data is read from
|
||||
* @param DestinationDataPtr is a pointer to where the data is written to
|
||||
* @param SourceLength is the length of the data to be moved in words
|
||||
* @param DestinationLength is the length of the data to be moved in words
|
||||
* @param SecureTransfer indicated the encryption key location, 0 for
|
||||
* non-encrypted
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the transfer is successful
|
||||
* - XST_FAILURE if the transfer fails
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
|
||||
u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
|
||||
{
|
||||
u32 Status;
|
||||
u32 IntrStsReg;
|
||||
u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
|
||||
|
||||
/*
|
||||
* Check for secure transfer
|
||||
*/
|
||||
if (SecureTransfer) {
|
||||
PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
|
||||
}
|
||||
|
||||
#ifdef FSBL_PERF
|
||||
XTime tXferCur = 0;
|
||||
FsblGetGlobalTime(&tXferCur);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Clear the PCAP status registers
|
||||
*/
|
||||
Status = ClearPcapStatus();
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* For Bitstream case destination address will be 0xFFFFFFFF
|
||||
*/
|
||||
DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
|
||||
|
||||
/*
|
||||
* New Bitstream download initialization sequence
|
||||
*/
|
||||
Status = FabricInit();
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
|
||||
#ifdef XPAR_XWDTPS_0_BASEADDR
|
||||
/*
|
||||
* Prevent WDT reset
|
||||
*/
|
||||
XWdtPs_RestartWdt(&Watchdog);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PCAP single DMA transfer setup
|
||||
*/
|
||||
SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
|
||||
DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
|
||||
|
||||
/*
|
||||
* Transfer using Device Configuration
|
||||
*/
|
||||
Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
|
||||
SourceLength,
|
||||
(u8 *)DestinationDataPtr,
|
||||
DestinationLength, PcapTransferType);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Dump the PCAP registers
|
||||
*/
|
||||
PcapDumpRegisters();
|
||||
|
||||
|
||||
/*
|
||||
* Poll for the DMA done
|
||||
*/
|
||||
Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
|
||||
|
||||
/*
|
||||
* Poll for FPGA Done
|
||||
*/
|
||||
Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
|
||||
|
||||
/*
|
||||
* Check for errors
|
||||
*/
|
||||
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
||||
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
|
||||
fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* For Performance measurement
|
||||
*/
|
||||
#ifdef FSBL_PERF
|
||||
XTime tXferEnd = 0;
|
||||
fsbl_printf(DEBUG_GENERAL,"Time taken is ");
|
||||
FsblMeasurePerfTime(tXferCur,tXferEnd);
|
||||
#endif
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function Initializes the PCAP driver.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the pcap driver initialization is successful
|
||||
* - XST_FAILURE if the pcap driver initialization fails
|
||||
*
|
||||
* @note none
|
||||
*
|
||||
****************************************************************************/
|
||||
int InitPcap(void)
|
||||
{
|
||||
XDcfg_Config *ConfigPtr;
|
||||
int Status = XST_SUCCESS;
|
||||
DcfgInstPtr = &DcfgInstance;
|
||||
|
||||
/*
|
||||
* Initialize the Device Configuration Interface driver.
|
||||
*/
|
||||
ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
|
||||
|
||||
Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
|
||||
ConfigPtr->BaseAddr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function programs the Fabric for use.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the Fabric initialization is successful
|
||||
* - XST_FAILURE if the Fabric initialization fails
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 FabricInit(void)
|
||||
{
|
||||
u32 PcapReg;
|
||||
u32 PcapCtrlRegVal;
|
||||
u32 StatusReg;
|
||||
u32 MctrlReg;
|
||||
u32 PcfgInit;
|
||||
u32 TimerExpired=0;
|
||||
XTime tCur=0;
|
||||
XTime tEnd=0;
|
||||
|
||||
|
||||
/*
|
||||
* Set Level Shifters DT618760 - PS to PL enabling
|
||||
*/
|
||||
Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
|
||||
fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n",
|
||||
Xil_In32(PS_LVL_SHFTR_EN));
|
||||
|
||||
/*
|
||||
* Get DEVCFG controller settings
|
||||
*/
|
||||
PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
|
||||
XDCFG_CTRL_OFFSET);
|
||||
|
||||
/*
|
||||
* Check the PL power status
|
||||
*/
|
||||
if(Silicon_Version >= SILICON_VERSION_3)
|
||||
{
|
||||
MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr);
|
||||
|
||||
if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) !=
|
||||
XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK)
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Setting PCFG_PROG_B signal to high
|
||||
*/
|
||||
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
|
||||
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
|
||||
|
||||
/*
|
||||
* Check for AES source key
|
||||
*/
|
||||
PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
|
||||
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
|
||||
/*
|
||||
* 5msec delay
|
||||
*/
|
||||
usleep(5000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setting PCFG_PROG_B signal to low
|
||||
*/
|
||||
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
|
||||
(PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
|
||||
|
||||
/*
|
||||
* Check for AES source key
|
||||
*/
|
||||
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
|
||||
/*
|
||||
* 5msec delay
|
||||
*/
|
||||
usleep(5000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Polling the PCAP_INIT status for Reset or timeout
|
||||
*/
|
||||
|
||||
XTime_GetTime(&tCur);
|
||||
do
|
||||
{
|
||||
PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
|
||||
XDCFG_STATUS_PCFG_INIT_MASK);
|
||||
if(PcfgInit == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
XTime_GetTime(&tEnd);
|
||||
if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
|
||||
{
|
||||
TimerExpired = 1;
|
||||
}
|
||||
|
||||
} while(!TimerExpired);
|
||||
|
||||
if(TimerExpired == 1)
|
||||
{
|
||||
TimerExpired = 0;
|
||||
/*
|
||||
* Came here due to expiration and PCAP_INIT is set.
|
||||
* Retry PCFG_PROG_B High -> Low again
|
||||
*/
|
||||
|
||||
/*
|
||||
* Setting PCFG_PROG_B signal to high
|
||||
*/
|
||||
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
|
||||
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
|
||||
|
||||
/*
|
||||
* Check for AES source key
|
||||
*/
|
||||
PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
|
||||
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
|
||||
/*
|
||||
* 5msec delay
|
||||
*/
|
||||
usleep(5000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setting PCFG_PROG_B signal to low
|
||||
*/
|
||||
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
|
||||
(PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
|
||||
|
||||
/*
|
||||
* Check for AES source key
|
||||
*/
|
||||
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
|
||||
/*
|
||||
* 5msec delay
|
||||
*/
|
||||
usleep(5000);
|
||||
}
|
||||
/*
|
||||
* Polling the PCAP_INIT status for Reset or timeout (second iteration)
|
||||
*/
|
||||
|
||||
XTime_GetTime(&tCur);
|
||||
do
|
||||
{
|
||||
PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
|
||||
XDCFG_STATUS_PCFG_INIT_MASK);
|
||||
if(PcfgInit == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
XTime_GetTime(&tEnd);
|
||||
if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
|
||||
{
|
||||
TimerExpired = 1;
|
||||
}
|
||||
|
||||
} while(!TimerExpired);
|
||||
|
||||
if(TimerExpired == 1)
|
||||
{
|
||||
/*
|
||||
* Came here due to PCAP_INIT is not getting reset
|
||||
* for PCFG_PROG_B signal High -> Low
|
||||
*/
|
||||
fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Setting PCFG_PROG_B signal to high
|
||||
*/
|
||||
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
|
||||
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
|
||||
|
||||
/*
|
||||
* Polling the PCAP_INIT status for Set
|
||||
*/
|
||||
while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
|
||||
XDCFG_STATUS_PCFG_INIT_MASK));
|
||||
|
||||
/*
|
||||
* Get Device configuration status
|
||||
*/
|
||||
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
|
||||
fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg);
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function Clears the PCAP status registers.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the pcap status registers are cleared
|
||||
* - XST_FAILURE if errors are there
|
||||
* - XST_DEVICE_BUSY if Pcap device is busy
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 ClearPcapStatus(void)
|
||||
{
|
||||
|
||||
u32 StatusReg;
|
||||
u32 IntStatusReg;
|
||||
|
||||
/*
|
||||
* Clear it all, so if Boot ROM comes back, it can proceed
|
||||
*/
|
||||
XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
|
||||
|
||||
/*
|
||||
* Get PCAP Interrupt Status Register
|
||||
*/
|
||||
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
||||
if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
|
||||
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
|
||||
IntStatusReg);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the PCAP status register for DMA status
|
||||
*/
|
||||
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg);
|
||||
|
||||
/*
|
||||
* If the queue is full, return w/ XST_DEVICE_BUSY
|
||||
*/
|
||||
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
|
||||
XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
|
||||
return XST_DEVICE_BUSY;
|
||||
}
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
|
||||
|
||||
/*
|
||||
* There are unacknowledged DMA commands outstanding
|
||||
*/
|
||||
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
|
||||
XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
|
||||
|
||||
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
||||
|
||||
if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
|
||||
XDCFG_IXR_DMA_DONE_MASK){
|
||||
/*
|
||||
* Error state, transfer cannot occur
|
||||
*/
|
||||
fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
else {
|
||||
/*
|
||||
* clear out the status
|
||||
*/
|
||||
XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
|
||||
XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg |
|
||||
XDCFG_STATUS_DMA_DONE_CNT_MASK);
|
||||
}
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function prints PCAP register status.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
* @note none
|
||||
*
|
||||
****************************************************************************/
|
||||
void PcapDumpRegisters (void) {
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
|
||||
fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n",
|
||||
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
|
||||
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function Polls for the DMA done or FPGA done.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if polling for DMA/FPGA done is successful
|
||||
* - XST_FAILURE if polling for DMA/FPGA done fails
|
||||
*
|
||||
* @note none
|
||||
*
|
||||
****************************************************************************/
|
||||
int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
|
||||
{
|
||||
int Count = MaxCount;
|
||||
u32 IntrStsReg = 0;
|
||||
|
||||
/*
|
||||
* poll for the DMA done
|
||||
*/
|
||||
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
||||
while ((IntrStsReg & MaskValue) !=
|
||||
MaskValue) {
|
||||
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
|
||||
Count -=1;
|
||||
|
||||
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
|
||||
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
|
||||
IntrStsReg);
|
||||
PcapDumpRegisters();
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
if(!Count) {
|
||||
fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
if (Count > (MAX_COUNT-100)) {
|
||||
fsbl_printf(DEBUG_GENERAL,".");
|
||||
}
|
||||
}
|
||||
|
||||
fsbl_printf(DEBUG_GENERAL,"\n\r");
|
||||
|
||||
XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,89 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file pcap.h
|
||||
*
|
||||
* This file contains the interface for intiializing and accessing the PCAP
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 02/10/10 Initial release
|
||||
* 2.00a mb 16/08/12 Added the macros and function prototypes
|
||||
* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
|
||||
* Fabric Initialization sequence is modified to check
|
||||
* the PL power before sequence starts and checking INIT_B
|
||||
* reset status twice in case of failure.
|
||||
* 21.2 ng 07/13/23 Add SDT support
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___PCAP_H___
|
||||
#define ___PCAP_H___
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xdevcfg.h"
|
||||
|
||||
#ifndef SDT
|
||||
#include "xtime_l.h"
|
||||
#else
|
||||
#include "xiltimer.h"
|
||||
#endif
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
/* Multiboot register offset mask */
|
||||
#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF
|
||||
#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000
|
||||
/*Miscellaneous Control Register mask*/
|
||||
#define XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK 0x00000100
|
||||
#define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000)
|
||||
|
||||
#define PCAP_LAST_TRANSFER 1
|
||||
#define MAX_COUNT 1000000000
|
||||
#define LVL_PL_PS 0x0000000F
|
||||
#define LVL_PS_PL 0x0000000A
|
||||
|
||||
/* Fix for #672779 */
|
||||
#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \
|
||||
XDCFG_IXR_AXI_RTO_MASK | \
|
||||
XDCFG_IXR_AXI_RERR_MASK | \
|
||||
XDCFG_IXR_RX_FIFO_OV_MASK | \
|
||||
XDCFG_IXR_DMA_CMD_ERR_MASK |\
|
||||
XDCFG_IXR_DMA_Q_OV_MASK | \
|
||||
XDCFG_IXR_P2D_LEN_ERR_MASK |\
|
||||
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
|
||||
|
||||
int InitPcap(void);
|
||||
void PcapDumpRegisters(void);
|
||||
u32 ClearPcapStatus(void);
|
||||
u32 FabricInit(void);
|
||||
int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
|
||||
u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
|
||||
u32 DestinationLength, u32 Flags);
|
||||
u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
|
||||
u32 DestinationLength, u32 Flags);
|
||||
/************************** Variable Definitions *****************************/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* ___PCAP_H___ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 10000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,870 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file qspi.c
|
||||
*
|
||||
* Contains code for the QSPI FLASH functionality.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 01/10/10 Initial release
|
||||
* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
|
||||
* are set
|
||||
* 4.00a sg 02/28/13 Cleanup
|
||||
* Removed LPBK_DLY_ADJ register setting code as we use
|
||||
* divisor 8
|
||||
* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
|
||||
* Dual Stack support
|
||||
* Fix for CR:721674 - FSBL- Failed to boot from Dual
|
||||
* stacked QSPI
|
||||
* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
|
||||
* changelogs in FSBL
|
||||
* Fix for CR#739711 - FSBL not able to read Large QSPI
|
||||
* (512M) in IO Mode
|
||||
* 7.00a kc 10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
|
||||
* settings for Dual parallel
|
||||
* configuration in IO mode
|
||||
* 14.0 gan 01/13/16 Fix for CR#869081 - (2016.1)FSBL picks the qspi read
|
||||
* command from LQSPI_CFG register
|
||||
* instead of hard coded read
|
||||
* command (0x6B).
|
||||
* 15.0 bsv 09/04/20 Add support for 2Gb flash parts
|
||||
* 21.1 ng 07/13/23 Add SDT support
|
||||
* 21.2 ng 07/25/23 Updated QSPI address support in SDT flow
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "qspi.h"
|
||||
#include "image_mover.h"
|
||||
|
||||
#if defined(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR) || defined(XPAR_PS7_QSPI_LINEAR_0_BASEADDR)
|
||||
#include "xqspips_hw.h"
|
||||
#include "xqspips.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*
|
||||
* The following constants map to the XPAR parameters created in the
|
||||
* xparameters.h file. They are defined here such that a user can easily
|
||||
* change all the needed parameters in one place.
|
||||
*/
|
||||
#ifndef SDT
|
||||
#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
|
||||
#define QSPI_CONNECTION_MODE (XPAR_XQSPIPS_0_QSPI_MODE)
|
||||
#define QSPI_BUS_WIDTH (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH)
|
||||
#else
|
||||
#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_BASEADDR
|
||||
#define QSPI_CONNECTION_MODE (XPAR_XQSPIPS_0_CONNECTION_MODE)
|
||||
#define QSPI_BUS_WIDTH (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following constants define the commands which may be sent to the FLASH
|
||||
* device.
|
||||
*/
|
||||
#define QUAD_READ_CMD 0x6B
|
||||
#define READ_ID_CMD 0x9F
|
||||
|
||||
#define WRITE_ENABLE_CMD 0x06
|
||||
#define BANK_REG_RD 0x16
|
||||
#define BANK_REG_WR 0x17
|
||||
/* Bank register is called Extended Address Reg in Micron */
|
||||
#define EXTADD_REG_RD 0xC8
|
||||
#define EXTADD_REG_WR 0xC5
|
||||
|
||||
#define COMMAND_OFFSET 0 /* FLASH instruction */
|
||||
#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
|
||||
#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
|
||||
#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
|
||||
#define DATA_OFFSET 4 /* Start of Data for Read/Write */
|
||||
#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
|
||||
reads */
|
||||
#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
|
||||
quad reads */
|
||||
#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
|
||||
#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
|
||||
#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
|
||||
/*
|
||||
* The following constants specify the extra bytes which are sent to the
|
||||
* FLASH on the QSPI interface, that are not data, but control information
|
||||
* which includes the command and address
|
||||
*/
|
||||
#define OVERHEAD_SIZE 4
|
||||
|
||||
/*
|
||||
* The following constants specify the max amount of data and the size of the
|
||||
* the buffer required to hold the data and overhead to transfer the data to
|
||||
* and from the FLASH.
|
||||
*/
|
||||
#define DATA_SIZE 4096
|
||||
|
||||
/*
|
||||
* The following defines are for dual flash interface.
|
||||
*/
|
||||
#define LQSPI_CR_FAST_READ 0x0000000B
|
||||
#define LQSPI_CR_FAST_DUAL_READ 0x0000003B
|
||||
#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
|
||||
#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
|
||||
address and return data */
|
||||
|
||||
#define SINGLE_QSPI_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_READ)
|
||||
|
||||
#define SINGLE_QSPI_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_DUAL_READ)
|
||||
|
||||
#define SINGLE_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_QUAD_READ)
|
||||
|
||||
#define DUAL_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
|
||||
XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
|
||||
XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_QUAD_READ)
|
||||
|
||||
#define DUAL_STACK_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_READ)
|
||||
|
||||
#define DUAL_STACK_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_DUAL_READ)
|
||||
|
||||
#define DUAL_STACK_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_QUAD_READ)
|
||||
|
||||
#define SINGLE_QSPI_IO_CONFIG_FAST_READ (LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_READ)
|
||||
|
||||
#define SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ (LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_DUAL_READ)
|
||||
|
||||
#define SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_QUAD_READ)
|
||||
|
||||
#define DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
|
||||
XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
|
||||
LQSPI_CR_1_DUMMY_BYTE | \
|
||||
LQSPI_CR_FAST_QUAD_READ)
|
||||
|
||||
#define QSPI_BUSWIDTH_ONE 0U
|
||||
#define QSPI_BUSWIDTH_TWO 1U
|
||||
#define QSPI_BUSWIDTH_FOUR 2U
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
XQspiPs QspiInstance;
|
||||
XQspiPs *QspiInstancePtr;
|
||||
u32 QspiFlashSize;
|
||||
u32 QspiFlashMake;
|
||||
extern u32 FlashReadBaseAddress;
|
||||
extern u8 LinearBootDeviceFlag;
|
||||
|
||||
/*
|
||||
* The following variables are used to read and write to the eeprom and they
|
||||
* are global to avoid having large buffers on the stack
|
||||
*/
|
||||
u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
|
||||
u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function initializes the controller for the QSPI interface.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 InitQspi(void)
|
||||
{
|
||||
XQspiPs_Config *QspiConfig;
|
||||
int Status;
|
||||
u32 ConfigCmd;
|
||||
|
||||
QspiInstancePtr = &QspiInstance;
|
||||
|
||||
/*
|
||||
* Set up the base address for access
|
||||
*/
|
||||
FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
|
||||
|
||||
/*
|
||||
* Initialize the QSPI driver so that it's ready to use
|
||||
*/
|
||||
QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
|
||||
if (NULL == QspiConfig) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
|
||||
QspiConfig->BaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set Manual Chip select options and drive HOLD_B pin high.
|
||||
*/
|
||||
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
|
||||
XQSPIPS_HOLD_B_DRIVE_OPTION);
|
||||
|
||||
/*
|
||||
* Set the prescaler for QSPI clock
|
||||
*/
|
||||
XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
|
||||
|
||||
/*
|
||||
* Assert the FLASH chip select.
|
||||
*/
|
||||
XQspiPs_SetSlaveSelect(QspiInstancePtr);
|
||||
|
||||
/*
|
||||
* Read Flash ID and extract Manufacture and Size information
|
||||
*/
|
||||
Status = FlashReadID();
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
if (QSPI_CONNECTION_MODE == SINGLE_FLASH_CONNECTION) {
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
|
||||
/*
|
||||
* For Flash size <128Mbit controller configured in linear mode
|
||||
*/
|
||||
if (QspiFlashSize <= FLASH_SIZE_16MB) {
|
||||
LinearBootDeviceFlag = 1;
|
||||
|
||||
/*
|
||||
* Enable linear mode
|
||||
*/
|
||||
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
|
||||
XQSPIPS_HOLD_B_DRIVE_OPTION);
|
||||
|
||||
switch (QSPI_BUS_WIDTH) {
|
||||
|
||||
case QSPI_BUSWIDTH_ONE:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
|
||||
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
case QSPI_BUSWIDTH_TWO:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
|
||||
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_DUAL_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
case QSPI_BUSWIDTH_FOUR:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
|
||||
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_QUAD_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Single linear read
|
||||
*/
|
||||
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
|
||||
|
||||
/*
|
||||
* Enable the controller
|
||||
*/
|
||||
XQspiPs_Enable(QspiInstancePtr);
|
||||
} else {
|
||||
|
||||
switch (QSPI_BUS_WIDTH) {
|
||||
|
||||
case QSPI_BUSWIDTH_ONE:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
|
||||
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
case QSPI_BUSWIDTH_TWO:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
|
||||
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
case QSPI_BUSWIDTH_FOUR:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
|
||||
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
/*
|
||||
* Single flash IO read
|
||||
*/
|
||||
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
|
||||
|
||||
/*
|
||||
* Enable the controller
|
||||
*/
|
||||
XQspiPs_Enable(QspiInstancePtr);
|
||||
}
|
||||
}
|
||||
|
||||
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
|
||||
/*
|
||||
* For Single Flash size <128Mbit controller configured in linear mode
|
||||
*/
|
||||
if (QspiFlashSize <= FLASH_SIZE_16MB) {
|
||||
/*
|
||||
* Setting linear access flag
|
||||
*/
|
||||
LinearBootDeviceFlag = 1;
|
||||
|
||||
/*
|
||||
* Enable linear mode
|
||||
*/
|
||||
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
|
||||
XQSPIPS_HOLD_B_DRIVE_OPTION);
|
||||
|
||||
/*
|
||||
* Dual linear read
|
||||
*/
|
||||
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_FAST_QUAD_READ);
|
||||
|
||||
/*
|
||||
* Enable the controller
|
||||
*/
|
||||
XQspiPs_Enable(QspiInstancePtr);
|
||||
} else {
|
||||
/*
|
||||
* Dual flash IO read
|
||||
*/
|
||||
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ);
|
||||
|
||||
/*
|
||||
* Enable the controller
|
||||
*/
|
||||
XQspiPs_Enable(QspiInstancePtr);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Total flash size is two time of single flash size
|
||||
*/
|
||||
QspiFlashSize = 2 * QspiFlashSize;
|
||||
}
|
||||
|
||||
/*
|
||||
* It is expected to same flash size for both chip selection
|
||||
*/
|
||||
if (QSPI_CONNECTION_MODE == DUAL_STACK_CONNECTION) {
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
|
||||
|
||||
QspiFlashSize = 2 * QspiFlashSize;
|
||||
|
||||
/*
|
||||
* Enable two flash memories on separate buses
|
||||
*/
|
||||
switch (QSPI_BUS_WIDTH) {
|
||||
|
||||
case QSPI_BUSWIDTH_ONE:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
|
||||
ConfigCmd = DUAL_STACK_CONFIG_FAST_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
case QSPI_BUSWIDTH_TWO:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
|
||||
ConfigCmd = DUAL_STACK_CONFIG_FAST_DUAL_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
case QSPI_BUSWIDTH_FOUR:
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
|
||||
ConfigCmd = DUAL_STACK_CONFIG_FAST_QUAD_READ;
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* This function reads serial FLASH ID connected to the SPI interface.
|
||||
* It then deduces the make and size of the flash and obtains the
|
||||
* connection mode to point to corresponding parameters in the flash
|
||||
* configuration table. The flash driver will function based on this and
|
||||
* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
|
||||
* Winbond 128Mbit
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 FlashReadID(void)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/*
|
||||
* Read ID in Auto mode.
|
||||
*/
|
||||
WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
|
||||
WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
|
||||
WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
|
||||
WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
|
||||
|
||||
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
|
||||
RD_ID_SIZE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
|
||||
|
||||
fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
|
||||
ReadBuffer[2],
|
||||
ReadBuffer[3]);
|
||||
|
||||
/*
|
||||
* Deduce flash make
|
||||
*/
|
||||
if (ReadBuffer[1] == MICRON_ID) {
|
||||
QspiFlashMake = MICRON_ID;
|
||||
fsbl_printf(DEBUG_INFO, "MICRON ");
|
||||
} else if(ReadBuffer[1] == SPANSION_ID) {
|
||||
QspiFlashMake = SPANSION_ID;
|
||||
fsbl_printf(DEBUG_INFO, "SPANSION ");
|
||||
} else if(ReadBuffer[1] == WINBOND_ID) {
|
||||
QspiFlashMake = WINBOND_ID;
|
||||
fsbl_printf(DEBUG_INFO, "WINBOND ");
|
||||
} else if(ReadBuffer[1] == MACRONIX_ID) {
|
||||
QspiFlashMake = MACRONIX_ID;
|
||||
fsbl_printf(DEBUG_INFO, "MACRONIX ");
|
||||
} else if(ReadBuffer[1] == ISSI_ID) {
|
||||
QspiFlashMake = ISSI_ID;
|
||||
fsbl_printf(DEBUG_INFO, "ISSI ");
|
||||
}
|
||||
|
||||
/*
|
||||
* Deduce flash Size
|
||||
*/
|
||||
if (ReadBuffer[3] == FLASH_SIZE_ID_8M) {
|
||||
QspiFlashSize = FLASH_SIZE_8M;
|
||||
fsbl_printf(DEBUG_INFO, "8M Bits\r\n");
|
||||
} else if (ReadBuffer[3] == FLASH_SIZE_ID_16M) {
|
||||
QspiFlashSize = FLASH_SIZE_16M;
|
||||
fsbl_printf(DEBUG_INFO, "16M Bits\r\n");
|
||||
} else if (ReadBuffer[3] == FLASH_SIZE_ID_32M) {
|
||||
QspiFlashSize = FLASH_SIZE_32M;
|
||||
fsbl_printf(DEBUG_INFO, "32M Bits\r\n");
|
||||
} else if (ReadBuffer[3] == FLASH_SIZE_ID_64M) {
|
||||
QspiFlashSize = FLASH_SIZE_64M;
|
||||
fsbl_printf(DEBUG_INFO, "64M Bits\r\n");
|
||||
} else if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
|
||||
QspiFlashSize = FLASH_SIZE_128M;
|
||||
fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
|
||||
} else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
|
||||
QspiFlashSize = FLASH_SIZE_256M;
|
||||
fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
|
||||
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M)
|
||||
|| (ReadBuffer[3] == MACRONIX_FLASH_1_8_V_MX66_ID_512)
|
||||
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) {
|
||||
QspiFlashSize = FLASH_SIZE_512M;
|
||||
fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
|
||||
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G)
|
||||
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) {
|
||||
QspiFlashSize = FLASH_SIZE_1G;
|
||||
fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
|
||||
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_2G)
|
||||
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_2G)) {
|
||||
QspiFlashSize = FLASH_SIZE_2G;
|
||||
fsbl_printf(DEBUG_INFO, "2G Bits\r\n");
|
||||
}
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* This function reads from the serial FLASH connected to the
|
||||
* QSPI interface.
|
||||
*
|
||||
* @param Address contains the address to read data from in the FLASH.
|
||||
* @param ByteCount contains the number of bytes to read.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void FlashRead(u32 Address, u32 ByteCount)
|
||||
{
|
||||
/*
|
||||
* Setup the write command with the specified address and data for the
|
||||
* FLASH
|
||||
*/
|
||||
u32 LqspiCrReg;
|
||||
u8 ReadCommand;
|
||||
|
||||
LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
|
||||
ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK);
|
||||
WriteBuffer[COMMAND_OFFSET] = ReadCommand;
|
||||
WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
|
||||
WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
|
||||
WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
|
||||
|
||||
ByteCount += DUMMY_SIZE;
|
||||
|
||||
/*
|
||||
* Send the read command to the FLASH to read the specified number
|
||||
* of bytes from the FLASH, send the read command and address and
|
||||
* receive the specified number of bytes of data in the data buffer
|
||||
*/
|
||||
XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
|
||||
ByteCount + OVERHEAD_SIZE);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function provides the QSPI FLASH interface for the Simplified header
|
||||
* functionality.
|
||||
*
|
||||
* @param SourceAddress is address in FLASH data space
|
||||
* @param DestinationAddress is address in DDR data space
|
||||
* @param LengthBytes is the length of the data in Bytes
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the write completes correctly
|
||||
* - XST_FAILURE if the write fails to completes correctly
|
||||
*
|
||||
* @note none.
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
|
||||
{
|
||||
u8 *BufferPtr;
|
||||
u32 Length = 0;
|
||||
u32 BankSel = 0;
|
||||
u32 LqspiCrReg;
|
||||
u32 Status;
|
||||
u8 BankSwitchFlag = 1;
|
||||
|
||||
/*
|
||||
* Linear access check
|
||||
*/
|
||||
if (LinearBootDeviceFlag == 1) {
|
||||
/*
|
||||
* Check for non-word tail, add bytes to cover the end
|
||||
*/
|
||||
if ((LengthBytes%4) != 0){
|
||||
LengthBytes += (4 - (LengthBytes & 0x00000003));
|
||||
}
|
||||
|
||||
memcpy((void*)DestinationAddress,
|
||||
(const void*)(SourceAddress + FlashReadBaseAddress),
|
||||
(size_t)LengthBytes);
|
||||
} else {
|
||||
/*
|
||||
* Non Linear access
|
||||
*/
|
||||
BufferPtr = (u8*)DestinationAddress;
|
||||
|
||||
/*
|
||||
* Dual parallel connection actual flash is half
|
||||
*/
|
||||
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
|
||||
SourceAddress = SourceAddress/2;
|
||||
}
|
||||
|
||||
while(LengthBytes > 0) {
|
||||
/*
|
||||
* Local of DATA_SIZE size used for read/write buffer
|
||||
*/
|
||||
if(LengthBytes > DATA_SIZE) {
|
||||
Length = DATA_SIZE;
|
||||
} else {
|
||||
Length = LengthBytes;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dual stack connection
|
||||
*/
|
||||
if (QSPI_CONNECTION_MODE == DUAL_STACK_CONNECTION) {
|
||||
/*
|
||||
* Get the current LQSPI configuration value
|
||||
*/
|
||||
LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
|
||||
|
||||
/*
|
||||
* Select lower or upper Flash based on sector address
|
||||
*/
|
||||
if (SourceAddress >= (QspiFlashSize/2)) {
|
||||
/*
|
||||
* Set selection to U_PAGE
|
||||
*/
|
||||
XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
|
||||
LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
|
||||
|
||||
/*
|
||||
* Subtract first flash size when accessing second flash
|
||||
*/
|
||||
SourceAddress = SourceAddress - (QspiFlashSize/2);
|
||||
|
||||
fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
|
||||
|
||||
/*
|
||||
* Assert the FLASH chip select.
|
||||
*/
|
||||
XQspiPs_SetSlaveSelect(QspiInstancePtr);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Select bank
|
||||
*/
|
||||
if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
|
||||
BankSel = SourceAddress/FLASH_SIZE_16MB;
|
||||
|
||||
fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel);
|
||||
|
||||
Status = SendBankSelect(BankSel);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
BankSwitchFlag = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* If data to be read spans beyond the current bank, then
|
||||
* calculate length in current bank else no change in length
|
||||
*/
|
||||
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
|
||||
/*
|
||||
* In dual parallel mode, check should be for half
|
||||
* the length.
|
||||
*/
|
||||
if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
|
||||
{
|
||||
Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
|
||||
/*
|
||||
* Above length calculated is for single flash
|
||||
* Length should be doubled since dual parallel
|
||||
*/
|
||||
Length = Length * 2;
|
||||
BankSwitchFlag = 1;
|
||||
}
|
||||
} else {
|
||||
if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
|
||||
{
|
||||
Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
|
||||
BankSwitchFlag = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Copying the image to local buffer
|
||||
*/
|
||||
FlashRead(SourceAddress, Length);
|
||||
|
||||
/*
|
||||
* Moving the data from local buffer to DDR destination address
|
||||
*/
|
||||
memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
|
||||
|
||||
/*
|
||||
* Updated the variables
|
||||
*/
|
||||
LengthBytes -= Length;
|
||||
|
||||
/*
|
||||
* For Dual parallel connection address increment should be half
|
||||
*/
|
||||
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
|
||||
SourceAddress += Length/2;
|
||||
} else {
|
||||
SourceAddress += Length;
|
||||
}
|
||||
|
||||
BufferPtr = (u8*)((u32)BufferPtr + Length);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset Bank selection to zero
|
||||
*/
|
||||
Status = SendBankSelect(0);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
if (QSPI_CONNECTION_MODE == DUAL_STACK_CONNECTION) {
|
||||
|
||||
/*
|
||||
* Reset selection to L_PAGE
|
||||
*/
|
||||
XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
|
||||
LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
|
||||
|
||||
fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
|
||||
|
||||
/*
|
||||
* Assert the FLASH chip select.
|
||||
*/
|
||||
XQspiPs_SetSlaveSelect(QspiInstancePtr);
|
||||
}
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* This functions selects the current bank
|
||||
*
|
||||
* @param BankSel is the bank to be selected in the flash device(s).
|
||||
*
|
||||
* @return XST_SUCCESS if bank selected
|
||||
* XST_FAILURE if selection failed
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 SendBankSelect(u8 BankSel)
|
||||
{
|
||||
u32 Status;
|
||||
|
||||
/*
|
||||
* bank select commands for Micron and Spansion are different
|
||||
* Macronix bank select is same as Micron
|
||||
*/
|
||||
if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
|
||||
/*
|
||||
* For micron command WREN should be sent first
|
||||
* except for some specific feature set
|
||||
*/
|
||||
WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
|
||||
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
|
||||
WRITE_ENABLE_CMD_SIZE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Send the Extended address register write command
|
||||
* written, no receive buffer required
|
||||
*/
|
||||
WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
|
||||
WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
|
||||
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
|
||||
BANK_SEL_SIZE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
if (QspiFlashMake == SPANSION_ID) {
|
||||
WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
|
||||
WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
|
||||
|
||||
/*
|
||||
* Send the Extended address register write command
|
||||
* written, no receive buffer required
|
||||
*/
|
||||
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
|
||||
BANK_SEL_SIZE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* For testing - Read bank to verify
|
||||
*/
|
||||
if (QspiFlashMake == SPANSION_ID) {
|
||||
WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
|
||||
WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
|
||||
|
||||
/*
|
||||
* Send the Extended address register write command
|
||||
* written, no receive buffer required
|
||||
*/
|
||||
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
|
||||
BANK_SEL_SIZE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
|
||||
WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
|
||||
WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
|
||||
|
||||
/*
|
||||
* Send the Extended address register write command
|
||||
* written, no receive buffer required
|
||||
*/
|
||||
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
|
||||
BANK_SEL_SIZE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
if (ReadBuffer[1] != BankSel) {
|
||||
fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
|
||||
ReadBuffer[1]);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,115 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file qspi.h
|
||||
*
|
||||
* This file contains the interface for the QSPI FLASH functionality
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a ecm 01/10/10 Initial release
|
||||
* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
|
||||
* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
|
||||
* Dual Stack support
|
||||
* 6.00a bsv 09/04/20 Added support for 2Gb flash parts
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___QSPI_H___
|
||||
#define ___QSPI_H___
|
||||
|
||||
#include "fsbl.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "fsbl.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define SINGLE_FLASH_CONNECTION 0
|
||||
#define DUAL_STACK_CONNECTION 1
|
||||
#define DUAL_PARALLEL_CONNECTION 2
|
||||
#define FLASH_SIZE_16MB 0x1000000
|
||||
|
||||
/*
|
||||
* Bank mask
|
||||
*/
|
||||
#define BANKMASK 0xF000000
|
||||
|
||||
/*
|
||||
* Identification of Flash
|
||||
* Micron:
|
||||
* Byte 0 is Manufacturer ID;
|
||||
* Byte 1 is first byte of Device ID - 0xBB or 0xBA
|
||||
* Byte 2 is second byte of Device ID describes flash size:
|
||||
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
|
||||
* Spansion:
|
||||
* Byte 0 is Manufacturer ID;
|
||||
* Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
|
||||
* Byte 2 is second byte of Device ID describes flash size:
|
||||
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
|
||||
*/
|
||||
|
||||
#define MICRON_ID 0x20
|
||||
#define SPANSION_ID 0x01
|
||||
#define WINBOND_ID 0xEF
|
||||
#define MACRONIX_ID 0xC2
|
||||
#define ISSI_ID 0x9D
|
||||
|
||||
#define FLASH_SIZE_ID_8M 0x14
|
||||
#define FLASH_SIZE_ID_16M 0x15
|
||||
#define FLASH_SIZE_ID_32M 0x16
|
||||
#define FLASH_SIZE_ID_64M 0x17
|
||||
#define FLASH_SIZE_ID_128M 0x18
|
||||
#define FLASH_SIZE_ID_256M 0x19
|
||||
#define FLASH_SIZE_ID_512M 0x20
|
||||
#define FLASH_SIZE_ID_1G 0x21
|
||||
#define FLASH_SIZE_ID_2G 0x22
|
||||
/* Macronix size constants are different for 512M and 1G */
|
||||
#define MACRONIX_FLASH_SIZE_ID_512M 0x1A
|
||||
#define MACRONIX_FLASH_SIZE_ID_1G 0x1B
|
||||
#define MACRONIX_FLASH_SIZE_ID_2G 0x1C
|
||||
#define MACRONIX_FLASH_1_8_V_MX66_ID_512 (0x3A)
|
||||
/*
|
||||
* Size in bytes
|
||||
*/
|
||||
#define FLASH_SIZE_8M 0x0100000
|
||||
#define FLASH_SIZE_16M 0x0200000
|
||||
#define FLASH_SIZE_32M 0x0400000
|
||||
#define FLASH_SIZE_64M 0x0800000
|
||||
#define FLASH_SIZE_128M 0x1000000
|
||||
#define FLASH_SIZE_256M 0x2000000
|
||||
#define FLASH_SIZE_512M 0x4000000
|
||||
#define FLASH_SIZE_1G 0x8000000
|
||||
#define FLASH_SIZE_2G 0x10000000
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
u32 InitQspi(void);
|
||||
|
||||
u32 QspiAccess( u32 SourceAddress,
|
||||
u32 DestinationAddress,
|
||||
u32 LengthBytes);
|
||||
|
||||
u32 FlashReadID(void);
|
||||
u32 SendBankSelect(u8 BankSel);
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* ___QSPI_H___ */
|
||||
|
||||
@@ -0,0 +1,330 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file rsa.c
|
||||
*
|
||||
* Contains code for the RSA authentication
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 4.00a sgd 02/28/13 Initial release
|
||||
* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
|
||||
* Fix for CR#724165 - Partition Header used by FSBL is
|
||||
* not authenticated
|
||||
* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
|
||||
* by Boot ROM for authenticating
|
||||
* the Partition images
|
||||
* Fix for CR#722979 - Provide customer-friendly
|
||||
* changelogs in FSBL
|
||||
* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
|
||||
* fallback unless FSBL* and FSBL are
|
||||
* identical in length
|
||||
* Fix for CR#791245 - Use of xilrsa in FSBL
|
||||
* 10.0 vns 03/18/22 Fixed CR#1125470 to authenticate the parition header buffer
|
||||
* which is being used instead of one from DDR. Modified
|
||||
* prototype of AuthenticatePartition() API
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#ifdef RSA_SUPPORT
|
||||
#include "fsbl.h"
|
||||
#include "rsa.h"
|
||||
#include "xilrsa.h"
|
||||
|
||||
#ifdef XPAR_XWDTPS_0_BASEADDR
|
||||
#include "xwdtps.h"
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
#ifdef XPAR_XWDTPS_0_BASEADDR
|
||||
extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
|
||||
#endif
|
||||
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
static u8 *PpkModular;
|
||||
static u8 *PpkModularEx;
|
||||
static u32 PpkExp;
|
||||
static u32 PpkAlreadySet=0;
|
||||
|
||||
extern u32 FsblLength;
|
||||
|
||||
void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
|
||||
{
|
||||
#ifdef FSBL_DEBUG_RSA
|
||||
int Index;
|
||||
fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
|
||||
for (Index=0;Index<Len;Index++)
|
||||
{
|
||||
fsbl_printf(DEBUG_INFO, "%02x",Buf[Index]);
|
||||
if ((Index+1)%16 == 0){
|
||||
fsbl_printf(DEBUG_INFO, "\r\n");
|
||||
}
|
||||
}
|
||||
fsbl_printf(DEBUG_INFO, "\r\n %s END\r\n",Str);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function is used to set ppk pointer to ppk in OCM
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
void SetPpk(void )
|
||||
{
|
||||
u32 PadSize;
|
||||
u8 *PpkPtr;
|
||||
|
||||
/*
|
||||
* Set PPK only if is not already set
|
||||
*/
|
||||
if(PpkAlreadySet == 0)
|
||||
{
|
||||
|
||||
/*
|
||||
* Set PpkPtr to PPK in OCM
|
||||
*/
|
||||
|
||||
/*
|
||||
* Skip FSBL Length
|
||||
*/
|
||||
PpkPtr = (u8 *)(FsblLength);
|
||||
/*
|
||||
* Skip to 64 byte Boundary
|
||||
*/
|
||||
PadSize = ((u32)PpkPtr % 64);
|
||||
if(PadSize != 0)
|
||||
{
|
||||
PpkPtr += (64 - PadSize);
|
||||
}
|
||||
|
||||
/*
|
||||
* Increment the pointer by authentication Header size
|
||||
*/
|
||||
PpkPtr += RSA_HEADER_SIZE;
|
||||
|
||||
/*
|
||||
* Increment the pointer by Magic word size
|
||||
*/
|
||||
PpkPtr += RSA_MAGIC_WORD_SIZE;
|
||||
|
||||
/*
|
||||
* Set pointer to PPK
|
||||
*/
|
||||
PpkModular = (u8 *)PpkPtr;
|
||||
PpkPtr += RSA_PPK_MODULAR_SIZE;
|
||||
PpkModularEx = (u8 *)PpkPtr;
|
||||
PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
|
||||
PpkExp = *((u32 *)PpkPtr);
|
||||
|
||||
/*
|
||||
* Setting variable to avoid resetting PPK pointers
|
||||
*/
|
||||
PpkAlreadySet=1;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function Authenticate Partition Signature
|
||||
*
|
||||
* @param AC is the pointer to authentication certificate
|
||||
* @param Hash is the pointer which holds the SHA2 digest of data
|
||||
* to be authenticated.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if Authentication passed
|
||||
* - XST_FAILURE if Authentication failed
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 AuthenticatePartition(u8 *Ac, u8* Hash)
|
||||
{
|
||||
u8 DecryptSignature[256];
|
||||
u8 HashSignature[32];
|
||||
u8 *SpkModular;
|
||||
u8 *SpkModularEx;
|
||||
u32 SpkExp;
|
||||
u8 *SignaturePtr;
|
||||
u32 Status;
|
||||
|
||||
#ifdef XPAR_XWDTPS_0_BASEADDR
|
||||
/*
|
||||
* Prevent WDT reset
|
||||
*/
|
||||
XWdtPs_RestartWdt(&Watchdog);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Point to Authentication Certificate
|
||||
*/
|
||||
SignaturePtr = (u8 *)Ac;
|
||||
|
||||
/*
|
||||
* Increment the pointer by authentication Header size
|
||||
*/
|
||||
SignaturePtr += RSA_HEADER_SIZE;
|
||||
|
||||
/*
|
||||
* Increment the pointer by Magic word size
|
||||
*/
|
||||
SignaturePtr += RSA_MAGIC_WORD_SIZE;
|
||||
|
||||
/*
|
||||
* Increment the pointer beyond the PPK
|
||||
*/
|
||||
SignaturePtr += RSA_PPK_MODULAR_SIZE;
|
||||
SignaturePtr += RSA_PPK_MODULAR_EXT_SIZE;
|
||||
SignaturePtr += RSA_PPK_EXPO_SIZE;
|
||||
|
||||
/*
|
||||
* Calculate Hash Signature
|
||||
*/
|
||||
sha_256((u8 *)SignaturePtr, (RSA_SPK_MODULAR_EXT_SIZE +
|
||||
RSA_SPK_EXPO_SIZE + RSA_SPK_MODULAR_SIZE),
|
||||
HashSignature);
|
||||
FsblPrintArray(HashSignature, 32, "SPK Hash Calculated");
|
||||
|
||||
/*
|
||||
* Extract SPK signature
|
||||
*/
|
||||
SpkModular = (u8 *)SignaturePtr;
|
||||
SignaturePtr += RSA_SPK_MODULAR_SIZE;
|
||||
SpkModularEx = (u8 *)SignaturePtr;
|
||||
SignaturePtr += RSA_SPK_MODULAR_EXT_SIZE;
|
||||
SpkExp = *((u32 *)SignaturePtr);
|
||||
SignaturePtr += RSA_SPK_EXPO_SIZE;
|
||||
|
||||
/*
|
||||
* Decrypt SPK Signature
|
||||
*/
|
||||
rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
|
||||
(RSA_NUMBER)SignaturePtr,
|
||||
(u32)PpkExp,
|
||||
(RSA_NUMBER)PpkModular,
|
||||
(RSA_NUMBER)PpkModularEx);
|
||||
FsblPrintArray(DecryptSignature, RSA_SPK_SIGNATURE_SIZE,
|
||||
"SPK Decrypted Hash");
|
||||
|
||||
|
||||
Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO, "Partition SPK Signature "
|
||||
"Authentication failed\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
SignaturePtr += RSA_SPK_SIGNATURE_SIZE;
|
||||
|
||||
/*
|
||||
* Decrypt Partition Signature
|
||||
*/
|
||||
rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
|
||||
(RSA_NUMBER)SignaturePtr,
|
||||
(u32)SpkExp,
|
||||
(RSA_NUMBER)SpkModular,
|
||||
(RSA_NUMBER)SpkModularEx);
|
||||
FsblPrintArray(DecryptSignature, RSA_PARTITION_SIGNATURE_SIZE,
|
||||
"Partition Decrypted Hash");
|
||||
|
||||
Status = RecreatePaddingAndCheck(DecryptSignature, Hash);
|
||||
if (Status != XST_SUCCESS) {
|
||||
fsbl_printf(DEBUG_INFO, "Partition Signature "
|
||||
"Authentication failed\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function recreates the and check signature
|
||||
*
|
||||
* @param Partition signature
|
||||
* @param Partition hash value which includes boot header, partition data
|
||||
* @return
|
||||
* - XST_SUCCESS if check passed
|
||||
* - XST_FAILURE if check failed
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash)
|
||||
{
|
||||
u8 T_padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
|
||||
0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
|
||||
u8 * pad_ptr = signature + 256;
|
||||
u32 pad = 256 - 3 - 19 - 32;
|
||||
u32 ii;
|
||||
|
||||
/*
|
||||
* Re-Create PKCS#1v1.5 Padding
|
||||
* MSB ----------------------------------------------------LSB
|
||||
* 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
|
||||
*/
|
||||
if (*--pad_ptr != 0x00 || *--pad_ptr != 0x01) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
for (ii = 0; ii < pad; ii++) {
|
||||
if (*--pad_ptr != 0xFF) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
if (*--pad_ptr != 0x00) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
for (ii = 0; ii < sizeof(T_padding); ii++) {
|
||||
if (*--pad_ptr != T_padding[ii]) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
for (ii = 0; ii < 32; ii++) {
|
||||
if (*--pad_ptr != hash[ii])
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,55 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file rsa.h
|
||||
*
|
||||
* This file contains the RSA algorithm functions
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 4.00a sg 02/28/13 Initial release
|
||||
* 5.0 vns 03/18/22 Modified prototype of AuthenticatePartition() API
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___RSA_H___
|
||||
#define ___RSA_H___
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
|
||||
#define RSA_PPK_MODULAR_SIZE 256
|
||||
#define RSA_PPK_MODULAR_EXT_SIZE 256
|
||||
#define RSA_PPK_EXPO_SIZE 64
|
||||
#define RSA_SPK_MODULAR_SIZE 256
|
||||
#define RSA_SPK_MODULAR_EXT_SIZE 256
|
||||
#define RSA_SPK_EXPO_SIZE 64
|
||||
#define RSA_SPK_SIGNATURE_SIZE 256
|
||||
#define RSA_PARTITION_SIGNATURE_SIZE 256
|
||||
#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */
|
||||
#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
|
||||
#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
|
||||
|
||||
void SetPpk(void );
|
||||
u32 AuthenticatePartition(u8 *Ac, u8 *Hash);
|
||||
u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___RSA_H___ */
|
||||
@@ -0,0 +1,165 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file sd.c
|
||||
*
|
||||
* Contains code for the SD card FLASH functionality.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jz 04/28/11 Initial release
|
||||
* 7.00a kc 10/18/13 Integrated SD/MMC driver
|
||||
* 12.00a ssc 12/11/14 Fix for CR# 839182
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xparameters.h"
|
||||
#include "fsbl.h"
|
||||
|
||||
#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
|
||||
|
||||
#ifndef XPAR_PS7_SD_0_S_AXI_BASEADDR
|
||||
#define XPAR_PS7_SD_0_S_AXI_BASEADDR XPAR_XSDPS_0_BASEADDR
|
||||
#endif
|
||||
|
||||
#include "xstatus.h"
|
||||
|
||||
#include "ff.h"
|
||||
#include "sd.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern u32 FlashReadBaseAddress;
|
||||
|
||||
|
||||
static FIL fil; /* File object */
|
||||
static FATFS fatfs;
|
||||
static char buffer[32];
|
||||
static char *boot_file = buffer;
|
||||
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function initializes the controller for the SD FLASH interface.
|
||||
*
|
||||
* @param filename of the file that is to be used
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the controller initializes correctly
|
||||
* - XST_FAILURE if the controller fails to initializes correctly
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 InitSD(const char *filename)
|
||||
{
|
||||
|
||||
FRESULT rc;
|
||||
TCHAR *path = "0:/"; /* Logical drive number is 0 */
|
||||
|
||||
/* Register volume work area, initialize device */
|
||||
rc = f_mount(&fatfs, path, 0);
|
||||
fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc);
|
||||
|
||||
if (rc != FR_OK) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
strcpy_rom(buffer, filename);
|
||||
boot_file = (char *)buffer;
|
||||
FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR;
|
||||
|
||||
rc = f_open(&fil, boot_file, FA_READ);
|
||||
if (rc) {
|
||||
fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function provides the SD FLASH interface for the Simplified header
|
||||
* functionality.
|
||||
*
|
||||
* @param SourceAddress is address in FLASH data space
|
||||
* @param DestinationAddress is address in OCM data space
|
||||
* @param LengthBytes is the number of bytes to move
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the write completes correctly
|
||||
* - XST_FAILURE if the write fails to completes correctly
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
|
||||
{
|
||||
|
||||
FRESULT rc; /* Result code */
|
||||
UINT br;
|
||||
|
||||
rc = f_lseek(&fil, SourceAddress);
|
||||
if (rc) {
|
||||
fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br);
|
||||
|
||||
if (rc) {
|
||||
fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc);
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
|
||||
} /* End of SDAccess */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function closes the file object
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void ReleaseSD(void) {
|
||||
|
||||
f_close(&fil);
|
||||
return;
|
||||
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file sd.h
|
||||
*
|
||||
* This file contains the interface for the Secure Digital (SD) card
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a bh 03/10/11 Initial release
|
||||
* 7.00a kc 10/18/13 Integrated SD/MMC driver
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef ___SD_H___
|
||||
#define ___SD_H___
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
|
||||
u32 InitSD(const char *);
|
||||
|
||||
u32 SDAccess( u32 SourceAddress,
|
||||
u32 DestinationAddress,
|
||||
u32 LengthWords);
|
||||
|
||||
void ReleaseSD(void);
|
||||
#endif
|
||||
/************************** Variable Definitions *****************************/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* ___SD_H___ */
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
|
||||
cmake_minimum_required(VERSION 3.15)
|
||||
project(bsp)
|
||||
find_package(common)
|
||||
|
||||
if(CMAKE_EXPORT_COMPILE_COMMANDS)
|
||||
set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES})
|
||||
set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES})
|
||||
endif()
|
||||
|
||||
ADD_DEFINITIONS(-c ${proc_extra_compiler_flags})
|
||||
include_directories(${CMAKE_BINARY_DIR}/include)
|
||||
|
||||
if (EXISTS ${metal_BINARY_DIR})
|
||||
include_directories(${metal_BINARY_DIR}/lib/include)
|
||||
endif()
|
||||
set (BSP_LIBSRC_SUBDIRS libsrc standalone xiltimer xilffs xilrsa)
|
||||
|
||||
if (SUBDIR_LIST STREQUAL "ALL")
|
||||
set (SUBDIR_LIST ${BSP_LIBSRC_SUBDIRS})
|
||||
endif()
|
||||
|
||||
foreach(entry ${SUBDIR_LIST})
|
||||
if(entry STREQUAL "libsrc")
|
||||
set (path "${CMAKE_LIBRARY_PATH}/../libsrc")
|
||||
else()
|
||||
set (path "${CMAKE_LIBRARY_PATH}/../libsrc/${entry}/src")
|
||||
endif()
|
||||
if(EXISTS ${path})
|
||||
add_subdirectory(${path})
|
||||
endif()
|
||||
endforeach()
|
||||
|
||||
+219
@@ -0,0 +1,219 @@
|
||||
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
# SPDX-License-Identifier: MIT
|
||||
|
||||
option(NON_YOCTO "Non Yocto embeddedsw FLOW" OFF)
|
||||
set(CMAKE_POLICY_DEFAULT_CMP0140 OLD)
|
||||
|
||||
set (CMAKE_INSTALL_LIBDIR "lib")
|
||||
function (collector_create name base)
|
||||
set_property (GLOBAL PROPERTY "COLLECT_${name}_LIST")
|
||||
set_property (GLOBAL PROPERTY "COLLECT_${name}_BASE" "${base}")
|
||||
endfunction (collector_create)
|
||||
|
||||
function (collector_list var name)
|
||||
get_property (_list GLOBAL PROPERTY "COLLECT_${name}_LIST")
|
||||
set (${var} "${_list}" PARENT_SCOPE)
|
||||
endfunction (collector_list)
|
||||
|
||||
function (collector_base var name)
|
||||
get_property (_base GLOBAL PROPERTY "COLLECT_${name}_BASE")
|
||||
set (${var} "${_base}" PARENT_SCOPE)
|
||||
endfunction (collector_base)
|
||||
|
||||
function (collect name)
|
||||
collector_base (_base ${name})
|
||||
string(COMPARE NOTEQUAL "${_base}" "" _is_rel)
|
||||
set (_list)
|
||||
foreach (s IN LISTS ARGN)
|
||||
if (_is_rel)
|
||||
get_filename_component (s "${s}" ABSOLUTE)
|
||||
file (RELATIVE_PATH s "${_base}" "${s}")
|
||||
endif (_is_rel)
|
||||
list (APPEND _list "${s}")
|
||||
endforeach ()
|
||||
set_property (GLOBAL APPEND PROPERTY "COLLECT_${name}_LIST" "${_list}")
|
||||
endfunction (collect)
|
||||
|
||||
function(LIST_INDEX index match PROP)
|
||||
foreach (prop ${PROP})
|
||||
if ("${prop}" STREQUAL "${match}")
|
||||
set(index ${index} PARENT_SCOPE)
|
||||
return()
|
||||
endif()
|
||||
MATH(EXPR index "${index}+1")
|
||||
endforeach()
|
||||
endfunction()
|
||||
|
||||
function(get_headers headers)
|
||||
foreach(header ${_headers})
|
||||
string(REPLACE "/" ";" PATH_LIST ${header})
|
||||
list(GET PATH_LIST -1 header)
|
||||
list(APPEND clean_headers ${CMAKE_INCLUDE_PATH}/${header})
|
||||
set(clean_headers ${clean_headers} PARENT_SCOPE)
|
||||
endforeach()
|
||||
return(${clean_headers})
|
||||
endfunction()
|
||||
|
||||
macro(subdirlist result curdir)
|
||||
file(GLOB subdirs RELATIVE ${curdir} ${curdir}/*)
|
||||
set(dirlist "")
|
||||
foreach(subdir ${subdirs})
|
||||
if(IS_DIRECTORY ${curdir}/${subdir})
|
||||
list(APPEND dirlist ${subdir})
|
||||
endif()
|
||||
endforeach()
|
||||
set(${result} ${dirlist})
|
||||
endmacro()
|
||||
|
||||
function (linker_gen path)
|
||||
if (NOT EXISTS "${CMAKE_SOURCE_DIR}/lscript.ld")
|
||||
if (NOT DEFINED STACK_SIZE)
|
||||
if("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze")
|
||||
set(STACK_SIZE 0x400)
|
||||
else()
|
||||
set(STACK_SIZE 0x2000)
|
||||
endif()
|
||||
endif()
|
||||
if (NOT DEFINED HEAP_SIZE)
|
||||
if("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze")
|
||||
set(HEAP_SIZE 0x400)
|
||||
else()
|
||||
set(HEAP_SIZE 0x2000)
|
||||
endif()
|
||||
endif()
|
||||
SET(MEM_NODE_INSTANCES "${TOTAL_MEM_CONTROLLERS}" CACHE STRING "Memory Controller")
|
||||
SET_PROPERTY(CACHE MEM_NODE_INSTANCES PROPERTY STRINGS "${TOTAL_MEM_CONTROLLERS}")
|
||||
set(CUSTOM_LINKER_FILE "None" CACHE STRING "Custom Linker Script")
|
||||
list(LENGTH MEM_NODE_INSTANCES _len)
|
||||
if (${_len} EQUAL 1)
|
||||
set(DDR ${MEM_NODE_INSTANCES})
|
||||
endif()
|
||||
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa72")
|
||||
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa78")
|
||||
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa53")
|
||||
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa53-32")
|
||||
OR ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "aarch64"))
|
||||
configure_file(${path}/lscript_a53.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
|
||||
list(APPEND LINKER_FILE_PATH ${path}/lscript_a53.ld.in)
|
||||
list(APPEND LINKER_FILE lscript_a53.ld.in)
|
||||
endif()
|
||||
|
||||
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblaze") OR
|
||||
("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "microblazeel") OR
|
||||
("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "plm_microblaze") OR
|
||||
("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "pmu_microblaze"))
|
||||
configure_file(${path}/lscript_mb.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
|
||||
list(APPEND LINKER_FILE_PATH ${path}/lscript_mb.ld.in)
|
||||
list(APPEND LINKER_FILE lscript_mb.ld.in)
|
||||
endif()
|
||||
|
||||
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexr5"))
|
||||
if("${CMAKE_MACHINE}" STREQUAL "Versal")
|
||||
configure_file(${path}/lscript_versal_r5.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
|
||||
list(APPEND LINKER_FILE_PATH ${path}/lscript_versal_r5.ld.in)
|
||||
list(APPEND LINKER_FILE lscript_versal_r5.ld.in)
|
||||
else()
|
||||
configure_file(${path}/lscript_r5.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
|
||||
list(APPEND LINKER_FILE_PATH ${path}/lscript_r5.ld.in)
|
||||
list(APPEND LINKER_FILE lscript_r5.ld.in)
|
||||
endif()
|
||||
endif()
|
||||
|
||||
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexr52"))
|
||||
configure_file(${path}/lscript_versal_net_r5.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
|
||||
list(APPEND LINKER_FILE_PATH ${path}/lscript_versal_net_r5.ld.in)
|
||||
list(APPEND LINKER_FILE lscript_versal_net_r5.ld.in)
|
||||
endif()
|
||||
|
||||
if(("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortexa9"))
|
||||
configure_file(${path}/lscript_a9.ld.in ${CMAKE_SOURCE_DIR}/lscript.ld)
|
||||
list(APPEND LINKER_FILE_PATH ${path}/lscript_a9.ld.in)
|
||||
list(APPEND LINKER_FILE lscript_a9.ld.in)
|
||||
endif()
|
||||
|
||||
if (NOT "${CUSTOM_LINKER_FILE}" STREQUAL "None")
|
||||
execute_process(COMMAND ${CMAKE_COMMAND} -E copy ${CUSTOM_LINKER_FILE} ${CMAKE_SOURCE_DIR}/)
|
||||
endif()
|
||||
if (${NON_YOCTO})
|
||||
file (REMOVE_RECURSE ${path})
|
||||
endif()
|
||||
endif()
|
||||
endfunction(linker_gen)
|
||||
|
||||
function(gen_exheader path drvname addr prefix)
|
||||
string(TOUPPER ${drvname} DRVNAME)
|
||||
set(ADDR_DEFINE "#define X${DRVNAME}_BASEADDRESS ${addr}U")
|
||||
|
||||
if (NOT ${prefix})
|
||||
set(DRVNAME X${DRVNAME})
|
||||
configure_file(${path}/example.h.in ${CMAKE_SOURCE_DIR}/${prefix}${drvname}_example.h)
|
||||
else()
|
||||
configure_file(${path}/example.h.in ${CMAKE_SOURCE_DIR}/${drvname}_example.h)
|
||||
endif()
|
||||
endfunction(gen_exheader)
|
||||
|
||||
function(gen_bspconfig)
|
||||
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetal_bspconfig_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}
|
||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/common
|
||||
RESULT_VARIABLE output)
|
||||
execute_process(COMMAND ${CMAKE_COMMAND} -E copy ${CMAKE_SOURCE_DIR}/common/MemConfig.cmake ${CMAKE_SOURCE_DIR}/MemConfig.cmake)
|
||||
endfunction(gen_bspconfig)
|
||||
|
||||
function(get_drvlist)
|
||||
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetaldrvlist_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/../../
|
||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
|
||||
RESULT_VARIABLE output)
|
||||
endfunction(get_drvlist)
|
||||
|
||||
function(gen_drvconfig drvname)
|
||||
if ("${drvname}" STREQUAL "uartps" OR
|
||||
"${drvname}" STREQUAL "uartlite" OR
|
||||
"${drvname}" STREQUAL "uartpsv")
|
||||
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetalconfig_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/${drvname}/src/ stdin
|
||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/${drvname}/src/
|
||||
RESULT_VARIABLE output)
|
||||
else()
|
||||
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetalconfig_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/${drvname}/src/
|
||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/${drvname}/src/
|
||||
RESULT_VARIABLE output)
|
||||
endif()
|
||||
endfunction(gen_drvconfig)
|
||||
|
||||
function(gen_xparams)
|
||||
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetal_xparameters_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/../../
|
||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
|
||||
RESULT_VARIABLE output)
|
||||
endfunction(gen_xparams)
|
||||
|
||||
function(gen_linker)
|
||||
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- baremetallinker_xlnx ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/
|
||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
|
||||
RESULT_VARIABLE output)
|
||||
endfunction(gen_linker)
|
||||
|
||||
function(gen_libconfig)
|
||||
execute_process(COMMAND lopper $ENV{SYSTEM_DTFILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${CMAKE_SOURCE_DIR}/ hwcmake_metadata ${CMAKE_SOURCE_DIR}/../../../../
|
||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
|
||||
RESULT_VARIABLE output)
|
||||
endfunction(gen_libconfig)
|
||||
|
||||
macro(print_elf_size size_command app_name)
|
||||
if(DEFINED ${size_command})
|
||||
add_custom_command(
|
||||
TARGET ${app_name}.elf POST_BUILD
|
||||
COMMAND ${${size_command}} --format=berkeley ${app_name}.elf
|
||||
COMMAND ${${size_command}} --format=berkeley ${app_name}.elf > ${CMAKE_BINARY_DIR}/${app_name}.elf.size
|
||||
VERBATIM)
|
||||
endif()
|
||||
endmacro()
|
||||
|
||||
function(find_project_type src_ext PROJECT_TYPE)
|
||||
set(cpp_extensions ".cpp;.cc;.CPP;.c++;.cxx")
|
||||
foreach(extension ${cpp_extensions})
|
||||
if (${extension} IN_LIST src_ext)
|
||||
set(PROJECT_TYPE "c++" PARENT_SCOPE)
|
||||
return()
|
||||
endif()
|
||||
endforeach()
|
||||
set(PROJECT_TYPE "c" PARENT_SCOPE)
|
||||
endfunction()
|
||||
@@ -0,0 +1,4 @@
|
||||
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
# SPDX-License-Identifier: MIT
|
||||
*startfile:
|
||||
%:if-exists(crti%O%s) %:if-exists(crtbegin%O%s) %:if-exists(crtinit%O%s)
|
||||
@@ -0,0 +1,96 @@
|
||||
ps7_cortexa9_0:
|
||||
standalone:
|
||||
zynq_fsbl:
|
||||
description: First Stage Bootloader (FSBL) for Zynq. The FSBL configures the FPGA with HW bit stream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/NOR/QSPI) to RAM (DDR) and starts executing it. It supports multiple partitions, and each partition can be a code image or a bit stream.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
- xilffs
|
||||
- xilrsa
|
||||
peripheral_tests:
|
||||
description: Simple test routines for all peripherals in the hardware.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
hello_world:
|
||||
description: Let's say 'Hello World' in C.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
zynq_dram_test:
|
||||
description: This application runs out of OCM and performs memory tests on Zynq DRAM. For more information about the test, refer to ZYNQ_DRAM_DIAGNOSTICS_TEST.docx, in the src directory of the application.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
empty_application:
|
||||
description: A blank C project.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
dhrystone:
|
||||
description: Dhrystone synthetic benchmark program for baremetal environment.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
lwip_tcp_perf_server:
|
||||
description: The LwIP TCP Server application is used for creating TCP server using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address when ipv6_enable is true, with MAC address 00:0a:35:00:01:02. The application creates TCP server on board and starts listening for TCP client connections. It will display client connection info and also display interim and average TCP statistics for data transfer. This application handles only 1 client connection at a time.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
lwip_udp_perf_server:
|
||||
description: The LwIP UDP Perf Server application is used for creating UDP server and measure downlink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. The application creates UDP server on board and starts listening for UDP client connections. It will display client connection information with interim and average UDP statistics for data transfer.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
memory_tests:
|
||||
description: This application tests Memory Regions present in the hardware.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
lwip_tcp_perf_client:
|
||||
description: The LwIP TCP Perf Client application is used for creating TCP client and measure TCP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address whenipv6_enable is true, with MAC address 00:0a:35:00:01:02. This application creates TCP client on board and make connection with TCP server running on host machine. It will display connection information along with interim and average TCP statistics for data transfer.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
lwip_udp_perf_client:
|
||||
description: The LwIP UDP Perf Client application is used for creating UDP client and measure UDP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. This application creates UDP client on board and make connection with UDP server running on host machine. It will display connection information along with interim and average UDP statistics for data transfer.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
lwip_echo_server:
|
||||
description: The lwIP Echo Server application provides a simple demonstration of how to use the light-weight IP stack (lwIP). This application sets up the board to use IP address 192.168.1.10 or IPv6 FE80:0:0:0:20A:35FF:FE00:102, with MAC address 00:0a:35:00:01:02. The server listens for input at port 7 and simply echoes back whatever data is sent to that port.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
rsa_auth_app:
|
||||
description: Used to RSA authenticate a user application.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
- xilrsa
|
||||
freertos:
|
||||
empty_application:
|
||||
description: A blank C project.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
freertos_lwip_tcp_perf_server:
|
||||
description: The FreeRTOS LwIP TCP Server application is used for creating TCP server using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address when ipv6_enable is true, with MAC address 00:0a:35:00:01:02. The application creates TCP server on board and starts listening for TCP client connections. It will display client connection info and also display interim and average TCP statistics for data transfer. This application handles only 1 client connection at a time.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
freertos_lwip_udp_perf_server:
|
||||
description: The FreeRTOS LwIP UDP Perf Server application is used for creating UDP server and measure downlink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. The application creates UDP server on board and starts listening for UDP client connections. It will display client connection information with interim and average UDP statistics for data transfer..
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
freertos_lwip_echo_server:
|
||||
description: The FreeRTOS lwIP Echo Server application provides a simple demonstration of how to use the light-weight IP stack (lwIP) with FreeRTOS. This application sets up the board to use IP address 192.168.1.10 or IPv6 address FE80:0:0:0:20A:35FF:FE00:102, with MAC address 00:0a:35:00:01:02. The server listens for input at port 7 and simply echoes back whatever data is sent to that port.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
freertos_lwip_tcp_perf_client:
|
||||
description: The FreeRTOS LwIP TCP Perf Client application is used for creating TCP client and measure TCP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10 and IPv6 link local address whenipv6_enable is true, with MAC address 00:0a:35:00:01:02. This application creates TCP client on board and make connection with TCP server running on host machine. It will display connection information along with interim and average TCP statistics for data transfer.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
freertos_hello_world:
|
||||
description: FreeRTOS Hello World application.
|
||||
depends_libs:
|
||||
- xiltimer
|
||||
freertos_lwip_udp_perf_client:
|
||||
description: The FreeRTOS LwIP UDP Perf Client application is used for creating UDP client and measure UDP uplink performance using light-weight IP stack (lwIP). This application sets up the board to use default IP address 192.168.1.10, with MAC address 00:0a:35:00:01:02. This application creates UDP client on board and make connection with UDP server running on host machine. It will display connection information along with interim and average UDP statistics for data transfer.
|
||||
depends_libs:
|
||||
- lwip213
|
||||
- xiltimer
|
||||
@@ -0,0 +1,323 @@
|
||||
sdt: hw_artifacts/ps7_cortexa9_0_baremetal.dts
|
||||
family: Zynq
|
||||
path: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp
|
||||
os: standalone
|
||||
os_info:
|
||||
standalone:
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/bsp/standalone_v9_0
|
||||
os_config:
|
||||
standalone:
|
||||
standalone_stdin:
|
||||
name: standalone_stdin
|
||||
permission: read_write
|
||||
type: string
|
||||
value: ps7_uart_1
|
||||
default: ps7_uart_1
|
||||
options:
|
||||
- None
|
||||
- ps7_uart_1
|
||||
- ps7_coresight_comp_0
|
||||
description: stdin peripheral
|
||||
standalone_stdout:
|
||||
name: standalone_stdout
|
||||
permission: read_write
|
||||
type: string
|
||||
value: ps7_uart_1
|
||||
default: ps7_uart_1
|
||||
options:
|
||||
- None
|
||||
- ps7_uart_1
|
||||
- ps7_coresight_comp_0
|
||||
description: stdout peripheral
|
||||
toolchain_file: cortexa9_toolchain.cmake
|
||||
specs_file: Xilinx.spec
|
||||
proc: ps7_cortexa9_0
|
||||
proc_config:
|
||||
ps7_cortexa9_0:
|
||||
proc_archiver:
|
||||
name: proc_archiver
|
||||
permission: readonly
|
||||
type: string
|
||||
value: arm-none-eabi-gcc-ar
|
||||
default: arm-none-eabi-gcc-ar
|
||||
options: []
|
||||
description: Archiver
|
||||
proc_assembler:
|
||||
name: proc_assembler
|
||||
permission: readonly
|
||||
type: string
|
||||
value: arm-none-eabi-gcc
|
||||
default: arm-none-eabi-gcc
|
||||
options: []
|
||||
description: Assembler
|
||||
proc_compiler:
|
||||
name: proc_compiler
|
||||
permission: readonly
|
||||
type: string
|
||||
value: arm-none-eabi-gcc
|
||||
default: arm-none-eabi-gcc
|
||||
options: []
|
||||
description: Compiler
|
||||
proc_compiler_flags:
|
||||
name: proc_compiler_flags
|
||||
permission: readonly
|
||||
type: string
|
||||
value: ' -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard;-c'
|
||||
default: ' -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard;-c'
|
||||
options: []
|
||||
description: Compiler Flags
|
||||
proc_extra_compiler_flags:
|
||||
name: proc_extra_compiler_flags
|
||||
permission: read_write
|
||||
type: string
|
||||
value: ' -g -Wall -Wextra -fno-tree-loop-distribute-patterns'
|
||||
default: ' -g -Wall -Wextra -fno-tree-loop-distribute-patterns'
|
||||
options: []
|
||||
description: Extra Compiler Flags
|
||||
template: zynq_fsbl
|
||||
compiler_flags: ''
|
||||
include_folder: include
|
||||
lib_folder: lib
|
||||
libsrc_folder: libsrc
|
||||
drv_info:
|
||||
mydna_read_v1_0_0: None
|
||||
ps7_afi_0: None
|
||||
ps7_afi_1: None
|
||||
ps7_afi_2: None
|
||||
ps7_afi_3: None
|
||||
ps7_coresight_comp_0:
|
||||
driver: coresightps_dcc
|
||||
ip_name: ps7_coresight_comp
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/coresightps_dcc_v1_9
|
||||
ps7_ddrc_0: None
|
||||
ps7_dev_cfg_0:
|
||||
driver: devcfg
|
||||
ip_name: ps7_dev_cfg
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/devcfg_v3_8
|
||||
ps7_dma_ns: None
|
||||
ps7_dma_s:
|
||||
driver: dmaps
|
||||
ip_name: ps7_dma
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/dmaps_v2_9
|
||||
ps7_ethernet_0:
|
||||
driver: emacps
|
||||
ip_name: ps7_ethernet
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/emacps_v3_19
|
||||
ps7_globaltimer_0: None
|
||||
ps7_gpio_0:
|
||||
driver: gpiops
|
||||
ip_name: ps7_gpio
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/gpiops_v3_12
|
||||
ps7_gpv_0: None
|
||||
ps7_intc_dist_0:
|
||||
driver: scugic
|
||||
ip_name: ps7_intc_dist
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scugic_v5_2
|
||||
ps7_iop_bus_config_0: None
|
||||
ps7_ocmc_0: None
|
||||
ps7_pl310_0: None
|
||||
ps7_pmu_0: None
|
||||
ps7_qspi_0:
|
||||
driver: qspips
|
||||
ip_name: ps7_qspi
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/qspips_v3_11
|
||||
ps7_qspi_linear_0: None
|
||||
ps7_scuc_0: None
|
||||
ps7_scutimer_0:
|
||||
driver: scutimer
|
||||
ip_name: ps7_scutimer
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scutimer_v2_5
|
||||
ps7_scuwdt_0:
|
||||
driver: scuwdt
|
||||
ip_name: ps7_scuwdt
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scuwdt_v2_5
|
||||
ps7_sd_0:
|
||||
driver: sdps
|
||||
ip_name: ps7_sdio
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sdps_v4_2
|
||||
ps7_slcr_0: None
|
||||
ps7_uart_1:
|
||||
driver: uartps
|
||||
ip_name: ps7_uart
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartps_v3_13
|
||||
ps7_xadc_0:
|
||||
driver: xadcps
|
||||
ip_name: ps7_xadc
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/xadcps_v2_7
|
||||
lib_info:
|
||||
xiltimer:
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/sw_services/xiltimer_v1_3
|
||||
xilffs:
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/sw_services/xilffs_v5_1
|
||||
examples:
|
||||
xilffs_polled_example.c: []
|
||||
xilrsa:
|
||||
path: /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/sw_services/xilrsa_v1_7
|
||||
lib_config:
|
||||
xiltimer:
|
||||
XILTIMER_en_interval_timer:
|
||||
name: XILTIMER_en_interval_timer
|
||||
permission: read_write
|
||||
type: boolean
|
||||
value: 'false'
|
||||
default: 'false'
|
||||
options:
|
||||
- 'true'
|
||||
- 'false'
|
||||
description: Enable Interval Timer
|
||||
XILTIMER_sleep_timer:
|
||||
name: XILTIMER_sleep_timer
|
||||
permission: read_write
|
||||
type: string
|
||||
value: ps7_scutimer_0
|
||||
default: ps7_scutimer_0
|
||||
options:
|
||||
- Default
|
||||
- ps7_scutimer_0
|
||||
description: This parameter is used to select specific timer for sleep functionality
|
||||
XILTIMER_tick_timer:
|
||||
name: XILTIMER_tick_timer
|
||||
permission: read_write
|
||||
type: string
|
||||
value: None
|
||||
default: None
|
||||
options:
|
||||
- None
|
||||
- ps7_scutimer_0
|
||||
description: This parameter is used to select specific timer for tick functionality
|
||||
xilffs:
|
||||
XILFFS_enable_exfat:
|
||||
name: XILFFS_enable_exfat
|
||||
permission: read_write
|
||||
type: boolean
|
||||
value: 'false'
|
||||
default: 'false'
|
||||
options:
|
||||
- 'true'
|
||||
- 'false'
|
||||
description: 0:Disable exFAT, 1:Enable exFAT(Also Enables LFN)
|
||||
XILFFS_enable_multi_partition:
|
||||
name: XILFFS_enable_multi_partition
|
||||
permission: read_write
|
||||
type: boolean
|
||||
value: 'false'
|
||||
default: 'false'
|
||||
options:
|
||||
- 'true'
|
||||
- 'false'
|
||||
description: 0:Single partition, 1:Enable multiple partition
|
||||
XILFFS_fs_interface:
|
||||
name: XILFFS_fs_interface
|
||||
permission: read_write
|
||||
type: integer
|
||||
value: '1'
|
||||
default: '1'
|
||||
options:
|
||||
- '1'
|
||||
- '2'
|
||||
description: Enables file system with selected interface. Enter 1 for SD. Enter
|
||||
2 for RAM
|
||||
XILFFS_num_logical_vol:
|
||||
name: XILFFS_num_logical_vol
|
||||
permission: read_write
|
||||
type: integer
|
||||
value: '2'
|
||||
default: '2'
|
||||
options: []
|
||||
description: Number of volumes (logical drives, from 1 to 10) to be used.
|
||||
XILFFS_ramfs_size:
|
||||
name: XILFFS_ramfs_size
|
||||
permission: read_write
|
||||
type: integer
|
||||
value: '3145728'
|
||||
default: '3145728'
|
||||
options: []
|
||||
description: RAM FS size
|
||||
XILFFS_ramfs_start_addr:
|
||||
name: XILFFS_ramfs_start_addr
|
||||
permission: read_write
|
||||
type: string
|
||||
value: ''
|
||||
default: ''
|
||||
options: []
|
||||
description: RAM FS start address
|
||||
XILFFS_read_only:
|
||||
name: XILFFS_read_only
|
||||
permission: read_write
|
||||
type: boolean
|
||||
value: 'false'
|
||||
default: 'false'
|
||||
options:
|
||||
- 'true'
|
||||
- 'false'
|
||||
description: Enables the file system in Read_Only mode if true. ZynqMP fsbl
|
||||
will set this to true
|
||||
XILFFS_set_fs_rpath:
|
||||
name: XILFFS_set_fs_rpath
|
||||
permission: read_write
|
||||
type: integer
|
||||
value: '0'
|
||||
default: '0'
|
||||
options:
|
||||
- '0'
|
||||
- '1'
|
||||
- '2'
|
||||
description: Configures relative path feature (valid values 0 to 2).
|
||||
XILFFS_use_chmod:
|
||||
name: XILFFS_use_chmod
|
||||
permission: read_write
|
||||
type: boolean
|
||||
value: 'false'
|
||||
default: 'false'
|
||||
options:
|
||||
- 'true'
|
||||
- 'false'
|
||||
description: Enables use of CHMOD functionality for changing attributes (valid
|
||||
only with read_only set to false)
|
||||
XILFFS_use_lfn:
|
||||
name: XILFFS_use_lfn
|
||||
permission: read_write
|
||||
type: integer
|
||||
value: '0'
|
||||
default: '0'
|
||||
options:
|
||||
- '0'
|
||||
- '1'
|
||||
- '2'
|
||||
- '3'
|
||||
description: 'Enables the Long File Name(LFN) support if non-zero. Disabled
|
||||
by default: 0, LFN with static working buffer: 1, Dynamic working buffer:
|
||||
2 (on stack) or 3 (on heap)'
|
||||
XILFFS_use_mkfs:
|
||||
name: XILFFS_use_mkfs
|
||||
permission: read_write
|
||||
type: boolean
|
||||
value: 'true'
|
||||
default: 'true'
|
||||
options:
|
||||
- 'true'
|
||||
- 'false'
|
||||
description: Disable(0) or Enable(1) f_mkfs function. ZynqMP fsbl will set this
|
||||
to false
|
||||
XILFFS_use_strfunc:
|
||||
name: XILFFS_use_strfunc
|
||||
permission: read_write
|
||||
type: integer
|
||||
value: '0'
|
||||
default: '0'
|
||||
options:
|
||||
- '0'
|
||||
- '1'
|
||||
- '2'
|
||||
description: Enables the string functions (valid values 0 to 2).
|
||||
XILFFS_word_access:
|
||||
name: XILFFS_word_access
|
||||
permission: read_write
|
||||
type: boolean
|
||||
value: 'true'
|
||||
default: 'true'
|
||||
options:
|
||||
- 'true'
|
||||
- 'false'
|
||||
description: Enables word access for misaligned memory access platform
|
||||
xilrsa: {}
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
# SPDX-License-Identifier: MIT
|
||||
set( CMAKE_EXPORT_COMPILE_COMMANDS ON)
|
||||
set( CMAKE_INSTALL_MESSAGE LAZY)
|
||||
set( CMAKE_C_COMPILER arm-none-eabi-gcc )
|
||||
set( CMAKE_CXX_COMPILER arm-none-eabi-g++ )
|
||||
set( CMAKE_C_COMPILER_LAUNCHER )
|
||||
set( CMAKE_CXX_COMPILER_LAUNCHER )
|
||||
set( CMAKE_ASM_COMPILER arm-none-eabi-gcc )
|
||||
set( CMAKE_AR arm-none-eabi-ar CACHE FILEPATH "Archiver" )
|
||||
set( CMAKE_SIZE arm-none-eabi-size CACHE FILEPATH "Size" )
|
||||
set( CMAKE_SYSTEM_PROCESSOR "cortexa9" )
|
||||
set( CMAKE_MACHINE "Zynq" )
|
||||
set( CMAKE_SYSTEM_NAME "Generic" )
|
||||
set( CMAKE_SPECS_FILE "$ENV{ESW_REPO}/scripts/specs/arm/Xilinx.spec" CACHE STRING "Specs file path for using CMAKE toolchain files" )
|
||||
set( TOOLCHAIN_C_FLAGS " -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" CACHE STRING "CFLAGS" )
|
||||
set( TOOLCHAIN_CXX_FLAGS " -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" CACHE STRING "CXXFLAGS" )
|
||||
set( TOOLCHAIN_ASM_FLAGS " -O2 -DSDT -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" CACHE STRING "ASM FLAGS" )
|
||||
set( TOOLCHAIN_DEP_FLAGS " -MMD -MP" CACHE STRING "Flags used by compiler to generate dependency files")
|
||||
set( TOOLCHAIN_EXTRA_C_FLAGS " -g -Wall -Wextra -fno-tree-loop-distribute-patterns" CACHE STRING "Extra CFLAGS")
|
||||
set( CMAKE_C_FLAGS_RELEASE "-DNDEBUG" CACHE STRING "Additional CFLAGS for release" )
|
||||
set( CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG" CACHE STRING "Additional CXXFLAGS for release" )
|
||||
set( CMAKE_ASM_FLAGS_RELEASE "-DNDEBUG" CACHE STRING "Additional ASM FLAGS for release" )
|
||||
set( CMAKE_C_FLAGS "${TOOLCHAIN_C_FLAGS} ${TOOLCHAIN_DEP_FLAGS} -specs=${CMAKE_SPECS_FILE} -I${CMAKE_INCLUDE_PATH}" CACHE STRING "CFLAGS")
|
||||
set( CMAKE_CXX_FLAGS "${TOOLCHAIN_CXX_FLAGS} ${TOOLCHAIN_DEP_FLAGS} -specs=${CMAKE_SPECS_FILE} -I${CMAKE_INCLUDE_PATH}" CACHE STRING "CXXFLAGS")
|
||||
set( CMAKE_ASM_FLAGS "${TOOLCHAIN_ASM_FLAGS} ${TOOLCHAIN_DEP_FLAGS} -specs=${CMAKE_SPECS_FILE} -I${CMAKE_INCLUDE_PATH}" CACHE STRING "ASMFLAGS")
|
||||
@@ -0,0 +1,2 @@
|
||||
ps7_cortexa9_0: ps7_cortexa9
|
||||
ps7_cortexa9_1: ps7_cortexa9
|
||||
+1160
File diff suppressed because it is too large
Load Diff
+10066
File diff suppressed because it is too large
Load Diff
+117
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 142857132
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 10000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+1160
File diff suppressed because it is too large
Load Diff
+1
@@ -0,0 +1 @@
|
||||
set(DRIVER_LIST common;coresightps_dcc;devcfg;dmaps;emacps;gpiops;qspips;scugic;scutimer;scuwdt;sdps;uartps;xadcps)
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
#ifndef BSPCONFIG_H
|
||||
#define BSPCONFIG_H
|
||||
|
||||
#include "xmem_config.h"
|
||||
#define XPAR_XILTIMER_ENABLED
|
||||
#include "xparameters_ps.h"
|
||||
|
||||
#if defined (__aarch64__)
|
||||
#define EL3 0
|
||||
#define EL1_NONSECURE 0
|
||||
#define HYP_GUEST 0
|
||||
#endif
|
||||
|
||||
/* #undef versal */
|
||||
/* #undef PSU_PMU */
|
||||
/* #undef PLATFORM_ZYNQMP */
|
||||
#define PLATFORM_ZYNQ
|
||||
/* #undef VERSAL_PLM */
|
||||
/* #undef VERSALNET_PLM */
|
||||
/* #undef PLATFORM_MB */
|
||||
#define XPAR_CPU_ID 0
|
||||
#define XIL_INTERRUPT
|
||||
/* #undef XPAR_STDIN_IS_UARTLITE */
|
||||
/* #undef XPAR_STDIN_IS_UARTNS550 */
|
||||
#define XPAR_STDIN_IS_UARTPS
|
||||
/* #undef XPAR_STDIN_IS_UARTPSV */
|
||||
/* #undef XPAR_STDIN_IS_CORESIGHTPS_DCC */
|
||||
#define STDIN_BASEADDRESS 0xe0001000
|
||||
#define STDOUT_BASEADDRESS 0xe0001000
|
||||
|
||||
#endif /* BSPCONFIG_H */
|
||||
+83
@@ -0,0 +1,83 @@
|
||||
/*-----------------------------------------------------------------------/
|
||||
/ Low level disk interface modlue include file (C)ChaN, 2022 /
|
||||
/-----------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _DISKIO_DEFINED
|
||||
#define _DISKIO_DEFINED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define USE_WRITE 1 /* 1: Enable disk_write function */
|
||||
#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */
|
||||
|
||||
#include "ff.h"
|
||||
#include "xil_types.h"
|
||||
|
||||
/* Status of Disk Functions */
|
||||
typedef BYTE DSTATUS;
|
||||
|
||||
/* Results of Disk Functions */
|
||||
typedef enum {
|
||||
RES_OK = 0, /* 0: Successful */
|
||||
RES_ERROR, /* 1: R/W Error */
|
||||
RES_WRPRT, /* 2: Write Protected */
|
||||
RES_NOTRDY, /* 3: Not Ready */
|
||||
RES_PARERR /* 4: Invalid Parameter */
|
||||
} DRESULT;
|
||||
|
||||
|
||||
/*---------------------------------------*/
|
||||
/* Prototypes for disk control functions */
|
||||
|
||||
|
||||
DSTATUS disk_initialize (BYTE pdrv);
|
||||
DSTATUS disk_status (BYTE pdrv);
|
||||
DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
|
||||
DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
|
||||
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
|
||||
|
||||
|
||||
/* Disk Status Bits (DSTATUS) */
|
||||
|
||||
#define STA_NOINIT 0x01U /* Drive not initialized */
|
||||
#define STA_NODISK 0x02U /* No medium in the drive */
|
||||
#define STA_PROTECT 0x04U /* Write protected */
|
||||
|
||||
|
||||
/* Command code for disk_ioctrl fucntion */
|
||||
|
||||
/* Generic command (Used by FatFs) */
|
||||
#define CTRL_SYNC 0U /* Complete pending write process (needed at FF_FS_READONLY == 0) */
|
||||
#define GET_SECTOR_COUNT 1U /* Get media size (needed at FF_USE_MKFS == 1) */
|
||||
#define GET_SECTOR_SIZE 2U /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
|
||||
#define GET_BLOCK_SIZE 3U /* Get erase block size (needed at FF_USE_MKFS == 1) */
|
||||
#define CTRL_TRIM 4U /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
|
||||
|
||||
/* Generic command (Not used by FatFs) */
|
||||
#define CTRL_POWER 5U /* Get/Set power status */
|
||||
#define CTRL_LOCK 6U /* Lock/Unlock media removal */
|
||||
#define CTRL_EJECT 7U /* Eject media */
|
||||
#define CTRL_FORMAT 8U /* Create physical format on the media */
|
||||
|
||||
/* MMC/SDC specific ioctl command */
|
||||
#define MMC_GET_TYPE 10U /* Get card type */
|
||||
#define MMC_GET_CSD 11U /* Get CSD */
|
||||
#define MMC_GET_CID 12U /* Get CID */
|
||||
#define MMC_GET_OCR 13U /* Get OCR */
|
||||
#define MMC_GET_SDSTAT 14U /* Get SD status */
|
||||
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
|
||||
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
|
||||
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
|
||||
|
||||
/* ATA/CF specific ioctl command */
|
||||
#define ATA_GET_REV 20U /* Get F/W revision */
|
||||
#define ATA_GET_MODEL 21U /* Get model name */
|
||||
#define ATA_GET_SN 22U /* Get serial number */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
+1
@@ -0,0 +1 @@
|
||||
DISTRO_FEATURES = "common coresightps-dcc devcfg dmaps emacps gpiops qspips scugic scutimer scuwdt sdps uartps xadcps"
|
||||
@@ -0,0 +1,448 @@
|
||||
/*----------------------------------------------------------------------------/
|
||||
/ FatFs - Generic FAT Filesystem module R0.15 /
|
||||
/-----------------------------------------------------------------------------/
|
||||
/
|
||||
/ Copyright (C) 2022, ChaN, all right reserved.
|
||||
/
|
||||
/ FatFs module is an open source software. Redistribution and use of FatFs in
|
||||
/ source and binary forms, with or without modification, are permitted provided
|
||||
/ that the following condition is met:
|
||||
|
||||
/ 1. Redistributions of source code must retain the above copyright notice,
|
||||
/ this condition and the following disclaimer.
|
||||
/
|
||||
/ This software is provided by the copyright holder and contributors "AS IS"
|
||||
/ and any warranties related to this software are DISCLAIMED.
|
||||
/ The copyright owner or contributors be NOT LIABLE for any damages caused
|
||||
/ by use of this software.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef FF_DEFINED
|
||||
#define FF_DEFINED 80286 /* Revision ID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "ffconf.h" /* FatFs configuration options */
|
||||
|
||||
#if FF_DEFINED != FFCONF_DEF
|
||||
#error Wrong configuration file (ffconf.h).
|
||||
#endif
|
||||
|
||||
|
||||
/* Integer types used for FatFs API */
|
||||
|
||||
#if defined(_WIN32) /* Windows VC++ (for development only) */
|
||||
#define FF_INTDEF 2
|
||||
#include <windows.h>
|
||||
typedef unsigned __int64 QWORD;
|
||||
#include <float.h>
|
||||
#define isnan(v) _isnan(v)
|
||||
#define isinf(v) (!_finite(v))
|
||||
|
||||
#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */
|
||||
#define FF_INTDEF 2
|
||||
#include <stdint.h>
|
||||
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
|
||||
typedef unsigned char BYTE; /* char must be 8-bit */
|
||||
typedef uint16_t WORD; /* 16-bit unsigned integer */
|
||||
typedef uint32_t DWORD; /* 32-bit unsigned integer */
|
||||
typedef uint64_t QWORD; /* 64-bit unsigned integer */
|
||||
typedef WORD WCHAR; /* UTF-16 character type */
|
||||
|
||||
#else /* Earlier than C99 */
|
||||
#define FF_INTDEF 1
|
||||
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
|
||||
typedef unsigned char BYTE; /* char must be 8-bit */
|
||||
typedef unsigned short WORD; /* 16-bit unsigned integer */
|
||||
typedef unsigned long DWORD; /* 32-bit unsigned integer */
|
||||
typedef WORD WCHAR; /* UTF-16 character type */
|
||||
#endif
|
||||
|
||||
|
||||
/* Type of file size and LBA variables */
|
||||
|
||||
#if FF_FS_EXFAT
|
||||
#if FF_INTDEF != 2
|
||||
#error exFAT feature wants C99 or later
|
||||
#endif
|
||||
typedef QWORD FSIZE_t;
|
||||
#if FF_LBA64
|
||||
typedef QWORD LBA_t;
|
||||
#else
|
||||
typedef DWORD LBA_t;
|
||||
#endif
|
||||
#else
|
||||
#if FF_LBA64
|
||||
#error exFAT needs to be enabled when enable 64-bit LBA
|
||||
#endif
|
||||
typedef DWORD FSIZE_t;
|
||||
typedef DWORD LBA_t;
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of path name strings on FatFs API (TCHAR) */
|
||||
|
||||
#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
|
||||
typedef WCHAR TCHAR;
|
||||
#define _T(x) L ## x
|
||||
#define _TEXT(x) L ## x
|
||||
#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
|
||||
typedef char TCHAR;
|
||||
#define _T(x) u8 ## x
|
||||
#define _TEXT(x) u8 ## x
|
||||
#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
|
||||
typedef DWORD TCHAR;
|
||||
#define _T(x) U ## x
|
||||
#define _TEXT(x) U ## x
|
||||
#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
|
||||
#error Wrong FF_LFN_UNICODE setting
|
||||
#else /* ANSI/OEM code in SBCS/DBCS */
|
||||
typedef char TCHAR;
|
||||
#define _T(x) x
|
||||
#define _TEXT(x) x
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Definitions of volume management */
|
||||
|
||||
#if FF_MULTI_PARTITION /* Multiple partition configuration */
|
||||
typedef struct {
|
||||
BYTE pd; /* Physical drive number */
|
||||
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
|
||||
} PARTITION;
|
||||
extern PARTITION VolToPart[]; /* Volume - Partition mapping table */
|
||||
#endif
|
||||
|
||||
#if FF_STR_VOLUME_ID
|
||||
#ifndef FF_VOLUME_STRS
|
||||
extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Filesystem object structure (FATFS) */
|
||||
|
||||
typedef struct {
|
||||
BYTE fs_type; /* Filesystem type (0:not mounted) */
|
||||
BYTE pdrv; /* Volume hosting physical drive */
|
||||
BYTE ldrv; /* Logical drive number (used only when FF_FS_REENTRANT) */
|
||||
BYTE n_fats; /* Number of FATs (1 or 2) */
|
||||
BYTE wflag; /* win[] status (b0:dirty) */
|
||||
BYTE fsi_flag; /* FSINFO status (b7:disabled, b0:dirty) */
|
||||
WORD id; /* Volume mount ID */
|
||||
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
|
||||
WORD csize; /* Cluster size [sectors] */
|
||||
#if FF_MAX_SS != FF_MIN_SS
|
||||
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
|
||||
#endif
|
||||
#if FF_USE_LFN
|
||||
WCHAR* lfnbuf; /* LFN working buffer */
|
||||
#endif
|
||||
#if FF_FS_EXFAT
|
||||
BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
|
||||
#endif
|
||||
#if !FF_FS_READONLY
|
||||
DWORD last_clst; /* Last allocated cluster */
|
||||
DWORD free_clst; /* Number of free clusters */
|
||||
#endif
|
||||
#if FF_FS_RPATH
|
||||
DWORD cdir; /* Current directory start cluster (0:root) */
|
||||
#if FF_FS_EXFAT
|
||||
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
|
||||
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
|
||||
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
|
||||
#endif
|
||||
#endif
|
||||
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
|
||||
DWORD fsize; /* Number of sectors per FAT */
|
||||
LBA_t volbase; /* Volume base sector */
|
||||
LBA_t fatbase; /* FAT base sector */
|
||||
LBA_t dirbase; /* Root directory base sector (FAT12/16) or cluster (FAT32/exFAT) */
|
||||
LBA_t database; /* Data base sector */
|
||||
#if FF_FS_EXFAT
|
||||
LBA_t bitbase; /* Allocation bitmap base sector */
|
||||
#endif
|
||||
LBA_t winsect; /* Current sector appearing in the win[] */
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment = 32
|
||||
BYTE win[FF_MAX_SS];
|
||||
#else
|
||||
#ifdef __aarch64__
|
||||
BYTE win[FF_MAX_SS] __attribute__ ((aligned(64))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
|
||||
#else
|
||||
BYTE win[FF_MAX_SS] __attribute__ ((aligned(32))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
|
||||
#endif
|
||||
#endif
|
||||
} FATFS;
|
||||
|
||||
|
||||
|
||||
/* Object ID and allocation information (FFOBJID) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the hosting volume of this object */
|
||||
WORD id; /* Hosting volume's mount ID */
|
||||
BYTE attr; /* Object attribute */
|
||||
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
|
||||
DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
|
||||
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
|
||||
#if FF_FS_EXFAT
|
||||
DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
|
||||
DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
|
||||
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
|
||||
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
|
||||
DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
|
||||
#endif
|
||||
#if FF_FS_LOCK
|
||||
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
|
||||
#endif
|
||||
} FFOBJID;
|
||||
|
||||
|
||||
|
||||
/* File object structure (FIL) */
|
||||
|
||||
typedef struct {
|
||||
FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
|
||||
BYTE flag; /* File status flags */
|
||||
BYTE err; /* Abort flag (error code) */
|
||||
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
|
||||
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
|
||||
LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */
|
||||
#if !FF_FS_READONLY
|
||||
LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
|
||||
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
|
||||
#endif
|
||||
#if FF_USE_FASTSEEK
|
||||
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
|
||||
#endif
|
||||
#if !FF_FS_TINY
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment = 32
|
||||
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
|
||||
#else
|
||||
#ifdef __aarch64__
|
||||
BYTE buf[FF_MAX_SS] __attribute__ ((aligned(64))); /* File private data read/write window */
|
||||
#else
|
||||
BYTE buf[FF_MAX_SS] __attribute__ ((aligned(32))); /* File private data read/write window */
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
} FIL;
|
||||
|
||||
|
||||
|
||||
/* Directory object structure (DIR) */
|
||||
|
||||
typedef struct {
|
||||
FFOBJID obj; /* Object identifier */
|
||||
DWORD dptr; /* Current read/write offset */
|
||||
DWORD clust; /* Current cluster */
|
||||
LBA_t sect; /* Current sector (0:Read operation has terminated) */
|
||||
BYTE* dir; /* Pointer to the directory item in the win[] */
|
||||
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
|
||||
#if FF_USE_LFN
|
||||
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
|
||||
#endif
|
||||
#if FF_USE_FIND
|
||||
const TCHAR* pat; /* Pointer to the name matching pattern */
|
||||
#endif
|
||||
} DIR;
|
||||
|
||||
|
||||
|
||||
/* File information structure (FILINFO) */
|
||||
|
||||
typedef struct {
|
||||
FSIZE_t fsize; /* File size */
|
||||
WORD fdate; /* Modified date */
|
||||
WORD ftime; /* Modified time */
|
||||
BYTE fattrib; /* File attribute */
|
||||
#if FF_USE_LFN
|
||||
TCHAR altname[FF_SFN_BUF + 1];/* Alternative file name */
|
||||
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
|
||||
#else
|
||||
TCHAR fname[12 + 1]; /* File name */
|
||||
#endif
|
||||
} FILINFO;
|
||||
|
||||
|
||||
|
||||
/* Format parameter structure (MKFS_PARM) */
|
||||
|
||||
typedef struct {
|
||||
BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
|
||||
BYTE n_fat; /* Number of FATs */
|
||||
UINT align; /* Data area alignment (sector) */
|
||||
UINT n_root; /* Number of root directory entries */
|
||||
DWORD au_size; /* Cluster size (byte) */
|
||||
} MKFS_PARM;
|
||||
|
||||
|
||||
|
||||
/* File function return code (FRESULT) */
|
||||
|
||||
typedef enum {
|
||||
FR_OK = 0, /* (0) Succeeded */
|
||||
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||
FR_INT_ERR, /* (2) Assertion failed */
|
||||
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||
FR_NO_FILE, /* (4) Could not find the file */
|
||||
FR_NO_PATH, /* (5) Could not find the path */
|
||||
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
|
||||
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
|
||||
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||
} FRESULT;
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* FatFs Module Application Interface */
|
||||
/*--------------------------------------------------------------*/
|
||||
|
||||
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
|
||||
FRESULT f_close (FIL* fp); /* Close an open file object */
|
||||
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
|
||||
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
|
||||
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
|
||||
FRESULT f_truncate (FIL* fp); /* Truncate the file */
|
||||
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
|
||||
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
|
||||
FRESULT f_closedir (DIR* dp); /* Close an open directory */
|
||||
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
|
||||
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
|
||||
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
|
||||
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
|
||||
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
|
||||
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
|
||||
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
|
||||
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
|
||||
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
|
||||
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
|
||||
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
|
||||
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
|
||||
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
|
||||
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
|
||||
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
|
||||
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
|
||||
FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */
|
||||
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
|
||||
FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */
|
||||
FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */
|
||||
FRESULT f_setcp (WORD cp); /* Set current code page */
|
||||
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
|
||||
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
|
||||
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
|
||||
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
|
||||
|
||||
/* Some API fucntions are implemented as macro */
|
||||
|
||||
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
|
||||
#define f_error(fp) ((fp)->err)
|
||||
#define f_tell(fp) ((fp)->fptr)
|
||||
#define f_size(fp) ((fp)->obj.objsize)
|
||||
#define f_rewind(fp) f_lseek((fp), 0)
|
||||
#define f_rewinddir(dp) f_readdir((dp), 0)
|
||||
#define f_rmdir(path) f_unlink(path)
|
||||
#define f_unmount(path) f_mount(0, path, 0)
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Additional Functions */
|
||||
/*--------------------------------------------------------------*/
|
||||
|
||||
/* RTC function (provided by user) */
|
||||
#if !FF_FS_READONLY && !FF_FS_NORTC
|
||||
DWORD get_fattime (void); /* Get current time */
|
||||
#endif
|
||||
|
||||
|
||||
/* LFN support functions (defined in ffunicode.c) */
|
||||
|
||||
#if FF_USE_LFN >= 1
|
||||
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
|
||||
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
|
||||
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
|
||||
#endif
|
||||
|
||||
|
||||
/* O/S dependent functions (samples available in ffsystem.c) */
|
||||
|
||||
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||
void* ff_memalloc (UINT msize); /* Allocate memory block */
|
||||
void ff_memfree (void* mblock); /* Free memory block */
|
||||
#endif
|
||||
#if FF_FS_REENTRANT /* Sync functions */
|
||||
int ff_mutex_create (int vol); /* Create a sync object */
|
||||
void ff_mutex_delete (int vol); /* Delete a sync object */
|
||||
int ff_mutex_take (int vol); /* Lock sync object */
|
||||
void ff_mutex_give (int vol); /* Unlock sync object */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Flags and Offset Address */
|
||||
/*--------------------------------------------------------------*/
|
||||
|
||||
/* File access mode and open method flags (3rd argument of f_open) */
|
||||
#define FA_READ 0x01
|
||||
#define FA_WRITE 0x02
|
||||
#define FA_OPEN_EXISTING 0x00
|
||||
#define FA_CREATE_NEW 0x04
|
||||
#define FA_CREATE_ALWAYS 0x08
|
||||
#define FA_OPEN_ALWAYS 0x10
|
||||
#define FA_OPEN_APPEND 0x30
|
||||
|
||||
/* Fast seek controls (2nd argument of f_lseek) */
|
||||
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
|
||||
|
||||
/* Format options (2nd argument of f_mkfs) */
|
||||
#define FM_FAT 0x01
|
||||
#define FM_FAT32 0x02
|
||||
#define FM_EXFAT 0x04
|
||||
#define FM_ANY 0x07
|
||||
#define FM_SFD 0x08
|
||||
|
||||
/* Filesystem type (FATFS.fs_type) */
|
||||
#define FS_FAT12 1
|
||||
#define FS_FAT16 2
|
||||
#define FS_FAT32 3
|
||||
#define FS_EXFAT 4
|
||||
|
||||
/* File attribute bits for directory entry (FILINFO.fattrib) */
|
||||
#define AM_RDO 0x01 /* Read only */
|
||||
#define AM_HID 0x02 /* Hidden */
|
||||
#define AM_SYS 0x04 /* System */
|
||||
#define AM_DIR 0x10 /* Directory */
|
||||
#define AM_ARC 0x20 /* Archive */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* FF_DEFINED */
|
||||
+401
@@ -0,0 +1,401 @@
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Configurations of FatFs Module
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FFCONF_DEF 80286 /* Revision ID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef SDT
|
||||
#include "xilffs_config.h"
|
||||
#else
|
||||
#include "xparameters.h"
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Function Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef FILE_SYSTEM_READ_ONLY
|
||||
#define FF_FS_READONLY 1 /* 1:Read only */
|
||||
#else
|
||||
#define FF_FS_READONLY 0 /* 0:Read/Write */
|
||||
#endif
|
||||
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
|
||||
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
|
||||
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
|
||||
/ and optional writing functions as well. */
|
||||
|
||||
|
||||
#define FF_FS_MINIMIZE 0
|
||||
/* This option defines minimization level to remove some basic API functions.
|
||||
/
|
||||
/ 0: Basic functions are fully enabled.
|
||||
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
|
||||
/ are removed.
|
||||
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
|
||||
/ 3: f_lseek() function is removed in addition to 2. */
|
||||
|
||||
|
||||
#if FILE_SYSTEM_USE_STRFUNC == 0
|
||||
#define FF_USE_STRFUNC 0 /* 0:Disable */
|
||||
#elif FILE_SYSTEM_USE_STRFUNC == 1
|
||||
#define FF_USE_STRFUNC 1 /* 1:Enable */
|
||||
#elif FILE_SYSTEM_USE_STRFUNC == 2
|
||||
#define FF_USE_STRFUNC 2 /* 2:Enable */
|
||||
#endif
|
||||
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
|
||||
/
|
||||
/ 0: Disable string functions.
|
||||
/ 1: Enable without LF-CRLF conversion.
|
||||
/ 2: Enable with LF-CRLF conversion. */
|
||||
|
||||
|
||||
#define FF_USE_FIND 0
|
||||
/* This option switches filtered directory read functions, f_findfirst() and
|
||||
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
|
||||
|
||||
#ifdef FILE_SYSTEM_USE_MKFS
|
||||
#define FF_USE_MKFS 1 /* 1:Enable */
|
||||
#else
|
||||
#define FF_USE_MKFS 0 /* 0:Disable */
|
||||
#endif
|
||||
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FASTSEEK 0
|
||||
/* This option switches fast seek function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_EXPAND 0
|
||||
/* This option switches f_expand function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#ifdef FILE_SYSTEM_USE_CHMOD
|
||||
#define FF_USE_CHMOD 1 /* 1:Enable */
|
||||
#else
|
||||
#define FF_USE_CHMOD 0 /* 0:Disable */
|
||||
#endif
|
||||
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
|
||||
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
|
||||
|
||||
|
||||
#define FF_USE_LABEL 0
|
||||
/* This option switches volume label functions, f_getlabel() and f_setlabel().
|
||||
/ (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FORWARD 0
|
||||
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_STRFUNC 0
|
||||
#define FF_PRINT_LLI 1
|
||||
#define FF_PRINT_FLOAT 1
|
||||
#define FF_STRF_ENCODE 3
|
||||
/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and
|
||||
/ f_printf().
|
||||
/
|
||||
/ 0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect.
|
||||
/ 1: Enable without LF-CRLF conversion.
|
||||
/ 2: Enable with LF-CRLF conversion.
|
||||
/
|
||||
/ FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2
|
||||
/ makes f_printf() support floating point argument. These features want C99 or later.
|
||||
/ When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character
|
||||
/ encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE
|
||||
/ to be read/written via those functions.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP
|
||||
/ 1: Unicode in UTF-16LE
|
||||
/ 2: Unicode in UTF-16BE
|
||||
/ 3: Unicode in UTF-8
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Locale and Namespace Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_CODE_PAGE 932
|
||||
/* This option specifies the OEM code page to be used on the target system.
|
||||
/ Incorrect code page setting can cause a file open failure.
|
||||
/
|
||||
/ 437 - U.S.
|
||||
/ 720 - Arabic
|
||||
/ 737 - Greek
|
||||
/ 771 - KBL
|
||||
/ 775 - Baltic
|
||||
/ 850 - Latin 1
|
||||
/ 852 - Latin 2
|
||||
/ 855 - Cyrillic
|
||||
/ 857 - Turkish
|
||||
/ 860 - Portuguese
|
||||
/ 861 - Icelandic
|
||||
/ 862 - Hebrew
|
||||
/ 863 - Canadian French
|
||||
/ 864 - Arabic
|
||||
/ 865 - Nordic
|
||||
/ 866 - Russian
|
||||
/ 869 - Greek 2
|
||||
/ 932 - Japanese (DBCS)
|
||||
/ 936 - Simplified Chinese (DBCS)
|
||||
/ 949 - Korean (DBCS)
|
||||
/ 950 - Traditional Chinese (DBCS)
|
||||
/ 0 - Include all code pages above and configured by f_setcp()
|
||||
*/
|
||||
|
||||
|
||||
#ifdef FILE_SYSTEM_USE_LFN
|
||||
#define FF_USE_LFN FILE_SYSTEM_USE_LFN /* 0 to 3 */
|
||||
#else
|
||||
#define FF_USE_LFN 0 /* 0 to 3 */
|
||||
#endif
|
||||
#define FF_MAX_LFN 255
|
||||
/* The FF_USE_LFN switches the support for LFN (long file name).
|
||||
/
|
||||
/ 0: Disable LFN. FF_MAX_LFN has no effect.
|
||||
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
|
||||
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||
/
|
||||
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
|
||||
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
|
||||
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
|
||||
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
|
||||
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
|
||||
/ specification.
|
||||
/ When use stack for the working buffer, take care on stack overflow. When use heap
|
||||
/ memory for the working buffer, memory management functions, ff_memalloc() and
|
||||
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
|
||||
|
||||
|
||||
#define FF_LFN_UNICODE 0
|
||||
/* This option switches the character encoding on the API when LFN is enabled.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP (TCHAR = char)
|
||||
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
|
||||
/ 2: Unicode in UTF-8 (TCHAR = char)
|
||||
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
|
||||
/
|
||||
/ Also behavior of string I/O functions will be affected by this option.
|
||||
/ When LFN is not enabled, this option has no effect. */
|
||||
|
||||
|
||||
#define FF_LFN_BUF 255
|
||||
#define FF_SFN_BUF 12
|
||||
/* This set of options defines size of file name members in the FILINFO structure
|
||||
/ which is used to read out directory items. These values should be suffcient for
|
||||
/ the file names to read. The maximum possible length of the read file name depends
|
||||
/ on character encoding. When LFN is not enabled, these options have no effect. */
|
||||
|
||||
|
||||
#if FILE_SYSTEM_SET_FS_RPATH == 0
|
||||
#define FF_FS_RPATH 0U
|
||||
#elif FILE_SYSTEM_SET_FS_RPATH == 1
|
||||
#define FF_FS_RPATH 1U
|
||||
#elif FILE_SYSTEM_SET_FS_RPATH == 2
|
||||
#define FF_FS_RPATH 2U
|
||||
#endif
|
||||
/* This option configures support for relative path.
|
||||
/
|
||||
/ 0: Disable relative path and remove related functions.
|
||||
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
|
||||
/ 2: f_getcwd() function is available in addition to 1.
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Drive/Volume Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#if FILE_SYSTEM_NUM_LOGIC_VOL == 1
|
||||
#define FF_VOLUMES 1U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 2
|
||||
#define FF_VOLUMES 2U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 3
|
||||
#define FF_VOLUMES 3U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 4
|
||||
#define FF_VOLUMES 4U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 5
|
||||
#define FF_VOLUMES 5U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 6
|
||||
#define FF_VOLUMES 6U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 7
|
||||
#define FF_VOLUMES 7U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 8
|
||||
#define FF_VOLUMES 8U
|
||||
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 9
|
||||
#define FF_VOLUMES 9U
|
||||
#else
|
||||
#define FF_VOLUMES 10U
|
||||
#endif
|
||||
/* Number of volumes (logical drives) to be used. (1-10) */
|
||||
|
||||
|
||||
#define FF_STR_VOLUME_ID 0
|
||||
#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
|
||||
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
|
||||
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
|
||||
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
|
||||
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
|
||||
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
|
||||
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
|
||||
/ not defined, a user defined volume string table is needed as:
|
||||
/
|
||||
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
|
||||
*/
|
||||
|
||||
|
||||
#ifdef FILE_SYSTEM_MULTI_PARTITION
|
||||
#define FF_MULTI_PARTITION 1 /* 1:Enable multiple partition */
|
||||
#else
|
||||
#define FF_MULTI_PARTITION 0 /* 0:Single partition */
|
||||
#endif
|
||||
/* This option switches support for multiple volumes on the physical drive.
|
||||
/ By default (0), each logical drive number is bound to the same physical drive
|
||||
/ number and only an FAT volume found on the physical drive will be mounted.
|
||||
/ When this function is enabled (1), each logical drive number can be bound to
|
||||
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
|
||||
/ function will be available. */
|
||||
|
||||
|
||||
#define FF_MIN_SS 512
|
||||
#define FF_MAX_SS 512
|
||||
/* This set of options configures the range of sector size to be supported. (512,
|
||||
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
|
||||
/ harddisk, but a larger value may be required for on-board flash memory and some
|
||||
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
|
||||
/ for variable sector size mode and disk_ioctl() function needs to implement
|
||||
/ GET_SECTOR_SIZE command. */
|
||||
|
||||
|
||||
#define FF_LBA64 0
|
||||
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
|
||||
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
|
||||
|
||||
|
||||
#define FF_MIN_GPT 0x10000000
|
||||
/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and
|
||||
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
|
||||
|
||||
|
||||
#ifdef FILE_SYSTEM_USE_TRIM
|
||||
#define FF_USE_TRIM 1
|
||||
#else
|
||||
#define FF_USE_TRIM 0
|
||||
#endif
|
||||
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
|
||||
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
|
||||
/ disk_ioctl() function. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ System Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_FS_TINY 0
|
||||
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
|
||||
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
|
||||
/ Instead of private sector buffer eliminated from the file object, common sector
|
||||
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
|
||||
|
||||
|
||||
#ifdef FILE_SYSTEM_FS_EXFAT
|
||||
#define FF_FS_EXFAT 1
|
||||
#else
|
||||
#define FF_FS_EXFAT 0
|
||||
#endif
|
||||
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
|
||||
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
|
||||
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
|
||||
|
||||
|
||||
#define FF_FS_NORTC 0
|
||||
#define FF_NORTC_MON 1
|
||||
#define FF_NORTC_MDAY 1
|
||||
#define FF_NORTC_YEAR 2022
|
||||
/* The option FF_FS_NORTC switches timestamp feature. If the system does not have
|
||||
/ an RTC or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable the
|
||||
/ timestamp feature. Every object modified by FatFs will have a fixed timestamp
|
||||
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
|
||||
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
|
||||
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
|
||||
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
|
||||
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
|
||||
|
||||
|
||||
#define FF_FS_NOFSINFO 0
|
||||
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
|
||||
/ option, and f_getfree() function at the first time after volume mount will force
|
||||
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
|
||||
/
|
||||
/ bit0=0: Use free cluster count in the FSINFO if available.
|
||||
/ bit0=1: Do not trust free cluster count in the FSINFO.
|
||||
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
|
||||
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
|
||||
*/
|
||||
|
||||
|
||||
#define FF_FS_LOCK 0
|
||||
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
|
||||
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
|
||||
/ is 1.
|
||||
/
|
||||
/ 0: Disable file lock function. To avoid volume corruption, application program
|
||||
/ should avoid illegal open, remove and rename to the open objects.
|
||||
/ >0: Enable file lock function. The value defines how many files/sub-directories
|
||||
/ can be opened simultaneously under file lock control. Note that the file
|
||||
/ lock control is independent of re-entrancy. */
|
||||
|
||||
|
||||
#define FF_FS_REENTRANT 0
|
||||
#define FF_FS_TIMEOUT 1000
|
||||
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
|
||||
/ module itself. Note that regardless of this option, file access to different
|
||||
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
|
||||
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
|
||||
/ to the same volume is under control of this featuer.
|
||||
/
|
||||
/ 0: Disable re-entrancy. FF_FS_TIMEOUT have no effect.
|
||||
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
|
||||
/ ff_mutex_create(), ff_mutex_delete(), ff_mutex_take() and ff_mutex_give()
|
||||
/ function, must be added to the project. Samples are available in ffsystem.c.
|
||||
/
|
||||
/ The FF_FS_TIMEOUT defines timeout period in unit of O/S time tick.
|
||||
*/
|
||||
#ifdef FILE_SYSTEM_WORD_ACCESS
|
||||
#define FF_WORD_ACCESS 1
|
||||
#else
|
||||
#define FF_WORD_ACCESS 0
|
||||
#endif
|
||||
/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
|
||||
/ which access method is used to the word data on the FAT volume.
|
||||
/
|
||||
/ 0: Byte-by-byte access. Always compatible with all platforms.
|
||||
/ 1: Word access. Do not choose this unless under both the following conditions.
|
||||
/
|
||||
/ * Address misaligned memory access is always allowed for ALL instructions.
|
||||
/ * Byte order on the memory is little-endian.
|
||||
/
|
||||
/ If it is the case, FF_WORD_ACCESS can also be set to 1 to improve performance and
|
||||
/ reduce code size. Following table shows an example of some processor types.
|
||||
/
|
||||
/ ARM7TDMI 0 ColdFire 0 V850E 0
|
||||
/ Cortex-M3 0 Z80 0/1 V850ES 0/1
|
||||
/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
|
||||
/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
|
||||
/ AVR32 0 RL78 0 R32C 0
|
||||
/ PIC18 0/1 SH-2 0 M16C 0/1
|
||||
/ PIC24 0 H8S 0 MSP430 0
|
||||
/ PIC32 0 H8/300H 0 x86 0/1
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*--- End of configuration options ---*/
|
||||
+84
@@ -0,0 +1,84 @@
|
||||
mydna_read_v1_0_0:
|
||||
- mydna_read_v1_0
|
||||
- None
|
||||
ps7_afi_0:
|
||||
- ps7_afi
|
||||
- None
|
||||
ps7_afi_1:
|
||||
- ps7_afi
|
||||
- None
|
||||
ps7_afi_2:
|
||||
- ps7_afi
|
||||
- None
|
||||
ps7_afi_3:
|
||||
- ps7_afi
|
||||
- None
|
||||
ps7_coresight_comp_0:
|
||||
- ps7_coresight_comp
|
||||
- coresightps_dcc
|
||||
ps7_ddrc_0:
|
||||
- ps7_ddrc
|
||||
- None
|
||||
ps7_dev_cfg_0:
|
||||
- ps7_dev_cfg
|
||||
- devcfg
|
||||
ps7_dma_ns:
|
||||
- ps7_dma
|
||||
- None
|
||||
ps7_dma_s:
|
||||
- ps7_dma
|
||||
- dmaps
|
||||
ps7_ethernet_0:
|
||||
- ps7_ethernet
|
||||
- emacps
|
||||
ps7_globaltimer_0:
|
||||
- ps7_globaltimer
|
||||
- None
|
||||
ps7_gpio_0:
|
||||
- ps7_gpio
|
||||
- gpiops
|
||||
ps7_gpv_0:
|
||||
- ps7_gpv
|
||||
- None
|
||||
ps7_intc_dist_0:
|
||||
- ps7_intc_dist
|
||||
- scugic
|
||||
ps7_iop_bus_config_0:
|
||||
- ps7_iop_bus_config
|
||||
- None
|
||||
ps7_ocmc_0:
|
||||
- ps7_ocmc
|
||||
- None
|
||||
ps7_pl310_0:
|
||||
- ps7_pl310
|
||||
- None
|
||||
ps7_pmu_0:
|
||||
- ps7_pmu
|
||||
- None
|
||||
ps7_qspi_0:
|
||||
- ps7_qspi
|
||||
- qspips
|
||||
ps7_qspi_linear_0:
|
||||
- ps7_qspi_linear
|
||||
- None
|
||||
ps7_scuc_0:
|
||||
- ps7_scuc
|
||||
- None
|
||||
ps7_scutimer_0:
|
||||
- ps7_scutimer
|
||||
- scutimer
|
||||
ps7_scuwdt_0:
|
||||
- ps7_scuwdt
|
||||
- scuwdt
|
||||
ps7_sd_0:
|
||||
- ps7_sdio
|
||||
- sdps
|
||||
ps7_slcr_0:
|
||||
- ps7_slcr
|
||||
- None
|
||||
ps7_uart_1:
|
||||
- ps7_uart
|
||||
- uartps
|
||||
ps7_xadc_0:
|
||||
- ps7_xadc
|
||||
- xadcps
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
|
||||
PACKAGECONFIG[common] = "${RECIPE_SYSROOT}/usr/lib/libcommon.a,,common,,"
|
||||
PACKAGECONFIG[coresightps-dcc] = "${RECIPE_SYSROOT}/usr/lib/libcoresightps_dcc.a,,coresightps-dcc,,"
|
||||
PACKAGECONFIG[devcfg] = "${RECIPE_SYSROOT}/usr/lib/libdevcfg.a,,devcfg,,"
|
||||
PACKAGECONFIG[dmaps] = "${RECIPE_SYSROOT}/usr/lib/libdmaps.a,,dmaps,,"
|
||||
PACKAGECONFIG[emacps] = "${RECIPE_SYSROOT}/usr/lib/libemacps.a,,emacps,,"
|
||||
PACKAGECONFIG[gpiops] = "${RECIPE_SYSROOT}/usr/lib/libgpiops.a,,gpiops,,"
|
||||
PACKAGECONFIG[qspips] = "${RECIPE_SYSROOT}/usr/lib/libqspips.a,,qspips,,"
|
||||
PACKAGECONFIG[scugic] = "${RECIPE_SYSROOT}/usr/lib/libscugic.a,,scugic,,"
|
||||
PACKAGECONFIG[scutimer] = "${RECIPE_SYSROOT}/usr/lib/libscutimer.a,,scutimer,,"
|
||||
PACKAGECONFIG[scuwdt] = "${RECIPE_SYSROOT}/usr/lib/libscuwdt.a,,scuwdt,,"
|
||||
PACKAGECONFIG[sdps] = "${RECIPE_SYSROOT}/usr/lib/libsdps.a,,sdps,,"
|
||||
PACKAGECONFIG[uartps] = "${RECIPE_SYSROOT}/usr/lib/libuartps.a,,uartps,,"
|
||||
PACKAGECONFIG[xadcps] = "${RECIPE_SYSROOT}/usr/lib/libxadcps.a,,xadcps,,"
|
||||
@@ -0,0 +1,87 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2021 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file sleep.h
|
||||
*
|
||||
* This header file contains sleep related APIs.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY :
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.0 adk 24/11/21 Initial release.
|
||||
* 1.2 adk 22/12/22 Fixed doxygen style and indentation issues.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef SLEEP_H
|
||||
#define SLEEP_H
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro polls an address periodically until a condition is met or till the
|
||||
* timeout occurs.
|
||||
* The minimum timeout for calling this macro is 100us. If the timeout is less
|
||||
* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
|
||||
* If the timeout is not a multiple of 100us, it waits for a timeout of
|
||||
* the next usec value which is a multiple of 100us.
|
||||
*
|
||||
* @param IO_func - accessor function to read the register contents.
|
||||
* Depends on the register width.
|
||||
* @param ADDR - Address to be polled
|
||||
* @param VALUE - variable to read the value
|
||||
* @param COND - Condition to checked (usually involves VALUE)
|
||||
* @param TIMEOUT_US - timeout in micro seconds
|
||||
*
|
||||
* @return
|
||||
* - 0 - when the condition is met
|
||||
* - 1 - when the condition is not met till the timeout period
|
||||
*
|
||||
* @note none
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
|
||||
( { \
|
||||
u64 timeout = TIMEOUT_US/100; \
|
||||
if(TIMEOUT_US%100!=0) \
|
||||
timeout++; \
|
||||
for(;;) { \
|
||||
VALUE = IO_func(ADDR); \
|
||||
if(COND) \
|
||||
break; \
|
||||
else { \
|
||||
usleep(100); \
|
||||
timeout--; \
|
||||
if(timeout==0) \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
(timeout>0) ? 0 : -1; \
|
||||
} )
|
||||
|
||||
void usleep(unsigned long useconds);
|
||||
void sleep(unsigned int seconds);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,97 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file smc.h
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 1.00a sdm 11/03/09 Initial release.
|
||||
* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
|
||||
* as smc.c is removed
|
||||
* </pre>
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*@cond nocomments
|
||||
*/
|
||||
|
||||
#ifndef SMC_H /* prevent circular inclusions */
|
||||
#define SMC_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/* Memory controller configuration register offset */
|
||||
#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
|
||||
#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
|
||||
#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
|
||||
#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
|
||||
#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
|
||||
#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
|
||||
#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
|
||||
#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
|
||||
#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
|
||||
|
||||
/* Chip select configuration register offset */
|
||||
#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
|
||||
#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
|
||||
#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
|
||||
#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
|
||||
#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
|
||||
#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
|
||||
#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
|
||||
#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
|
||||
|
||||
/* User configuration register offset */
|
||||
#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
|
||||
#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
|
||||
|
||||
/* Integration test register offset */
|
||||
#define XSMCPSS_IT_OFFSET 0xE00U
|
||||
|
||||
/* ID configuration register offset */
|
||||
#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
|
||||
#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
|
||||
#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
|
||||
#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
|
||||
#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
|
||||
#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
|
||||
#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
|
||||
#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* SMC_H */
|
||||
|
||||
/**
|
||||
*@endcond
|
||||
*/
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file vectors.h
|
||||
*
|
||||
* This file contains the C level vector prototypes for the ARM Cortex A9 core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
|
||||
* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
|
||||
* 8.0 sk 03/02/22 Update _VECTORS_H_ with VECTORS_H_ to fix misra_c_
|
||||
* 2012_rule_21_1 violation.
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef VECTORS_H_
|
||||
#define VECTORS_H_
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void FIQInterrupt(void);
|
||||
void IRQInterrupt(void);
|
||||
#if !defined (__aarch64__)
|
||||
void SWInterrupt(void);
|
||||
void DataAbortInterrupt(void);
|
||||
void PrefetchAbortInterrupt(void);
|
||||
void UndefinedException(void);
|
||||
#else
|
||||
void SynchronousInterrupt(void);
|
||||
void SErrorInterrupt(void);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* protection macro */
|
||||
+582
@@ -0,0 +1,582 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xadcps.h
|
||||
* @addtogroup Overview
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* The XAdcPs driver supports the Xilinx XADC/ADC device.
|
||||
*
|
||||
* The XADC/ADC device has the following features:
|
||||
* - 10-bit, 200-KSPS (kilo samples per second)
|
||||
* Analog-to-Digital Converter (ADC)
|
||||
* - Monitoring of on-chip supply voltages and temperature
|
||||
* - 1 dedicated differential analog-input pair and
|
||||
* 16 auxiliary differential analog-input pairs
|
||||
* - Automatic alarms based on user defined limits for the on-chip
|
||||
* supply voltages and temperature
|
||||
* - Automatic Channel Sequencer, programmable averaging, programmable
|
||||
* acquisition time for the external inputs, unipolar or differential
|
||||
* input selection for the external inputs
|
||||
* - Inbuilt Calibration
|
||||
* - Optional interrupt request generation
|
||||
*
|
||||
*
|
||||
* The user should refer to the hardware device specification for detailed
|
||||
* information about the device.
|
||||
*
|
||||
* This header file contains the prototypes of driver functions that can
|
||||
* be used to access the XADC/ADC device.
|
||||
*
|
||||
*
|
||||
* <b> XADC Channel Sequencer Modes </b>
|
||||
*
|
||||
* The XADC Channel Sequencer supports the following operating modes:
|
||||
*
|
||||
* - <b> Default </b>: This is the default mode after power up.
|
||||
* In this mode of operation the XADC operates in
|
||||
* a sequence mode, monitoring the on chip sensors:
|
||||
* Temperature, VCCINT, and VCCAUX.
|
||||
* - <b> One pass through sequence </b>: In this mode the XADC
|
||||
* converts the channels enabled in the Sequencer Channel Enable
|
||||
* registers for a single pass and then stops.
|
||||
* - <b> Continuous cycling of sequence </b>: In this mode the XADC
|
||||
* converts the channels enabled in the Sequencer Channel Enable
|
||||
* registers continuously.
|
||||
* - <b> Single channel mode</b>: In this mode the XADC Channel
|
||||
* Sequencer is disabled and the XADC operates in a
|
||||
* Single Channel Mode.
|
||||
* The XADC can operate either in a Continuous or Event
|
||||
* driven sampling mode in the single channel mode.
|
||||
* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
|
||||
* Sequencer will automatically sequence through eight fixed pairs
|
||||
* of auxiliary analog input channels for simulataneous conversion.
|
||||
* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
|
||||
* is used to implement a fixed monitoring mode similar to the
|
||||
* default mode but the alarm fucntions ar eenabled.
|
||||
* The second ADC (B) is available to be used with external analog
|
||||
* input channels only.
|
||||
*
|
||||
* Read the XADC spec for more information about the sequencer modes.
|
||||
*
|
||||
* <b> Initialization and Configuration </b>
|
||||
*
|
||||
* The device driver enables higher layer software (e.g., an application) to
|
||||
* communicate to the XADC/ADC device.
|
||||
*
|
||||
* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
|
||||
* device. The user needs to first call the XAdcPs_LookupConfig() API which
|
||||
* returns the Configuration structure pointer which is passed as a parameter to
|
||||
* the XAdcPs_CfgInitialize() API.
|
||||
*
|
||||
*
|
||||
* <b>Interrupts</b>
|
||||
*
|
||||
* The XADC/ADC device supports interrupt driven mode and the default
|
||||
* operation mode is polling mode.
|
||||
*
|
||||
* The interrupt mode is available only if hardware is configured to support
|
||||
* interrupts.
|
||||
*
|
||||
* This driver does not provide a Interrupt Service Routine (ISR) for the device.
|
||||
* It is the responsibility of the application to provide one if needed. Refer to
|
||||
* the interrupt example provided with this driver for details on using the
|
||||
* device in interrupt mode.
|
||||
*
|
||||
*
|
||||
* <b> Virtual Memory </b>
|
||||
*
|
||||
* This driver supports Virtual Memory. The RTOS is responsible for calculating
|
||||
* the correct device base address in Virtual Memory space.
|
||||
*
|
||||
*
|
||||
* <b> Threads </b>
|
||||
*
|
||||
* This driver is not thread safe. Any needs for threads or thread mutual
|
||||
* exclusion must be satisfied by the layer above this driver.
|
||||
*
|
||||
*
|
||||
* <b> Asserts </b>
|
||||
*
|
||||
* Asserts are used within all Xilinx drivers to enforce constraints on argument
|
||||
* values. Asserts can be turned off on a system-wide basis by defining, at
|
||||
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
|
||||
* is recommended that users leave asserts on during development.
|
||||
*
|
||||
*
|
||||
* <b> Building the driver </b>
|
||||
*
|
||||
* The XAdcPs driver is composed of several source files. This allows the user
|
||||
* to build and link only those parts of the driver that are necessary.
|
||||
*
|
||||
* <b> Limitations of the driver </b>
|
||||
*
|
||||
* XADC/ADC device can be accessed through the JTAG port and the PLB
|
||||
* interface. The driver implementation does not support the simultaneous access
|
||||
* of the device by both these interfaces. The user has to care of this situation
|
||||
* in the user application code.
|
||||
*
|
||||
* <br><br>
|
||||
*
|
||||
* <pre>
|
||||
*
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ----- -------- -----------------------------------------------------
|
||||
* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
|
||||
* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
|
||||
* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
|
||||
* in xadcps.c to fix CR #693371
|
||||
* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
|
||||
* CR#749687
|
||||
* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
|
||||
* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
|
||||
* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
|
||||
* functions.
|
||||
* Modified Assert for XAdcPs_SetSingleChParams in
|
||||
* xadcps.c to fix CR #807563.
|
||||
* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
|
||||
* xadcps.c (CR#854437).
|
||||
* ms 01/23/17 Added xil_printf statement in main function for all
|
||||
* examples to ensure that "Successfully ran" and "Failed"
|
||||
* strings are available in all examples. This is a fix
|
||||
* for CR-965028.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/05/17 Modified Comment lines in functions of xadcps
|
||||
* examples to recognize it as documentation block
|
||||
* for doxygen generation.
|
||||
* 2.3 mn 07/09/18 Fix Doxygen warning
|
||||
* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
|
||||
* aad 12/17/20 Added missing function declarations and removed
|
||||
* functions with no definitions.
|
||||
* 2.7 cog 07/24/23 Added support for SDT flow
|
||||
*
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef XADCPS_H /* Prevent circular inclusions */
|
||||
#define XADCPS_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xstatus.h"
|
||||
#include "xadcps_hw.h"
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
|
||||
/**
|
||||
* @name Indexes for the different channels.
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */
|
||||
#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */
|
||||
#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */
|
||||
#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */
|
||||
#define XADCPS_CH_VREFP 0x4U /**< VREFP */
|
||||
#define XADCPS_CH_VREFN 0x5U /**< VREFN */
|
||||
#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */
|
||||
#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */
|
||||
#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */
|
||||
#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */
|
||||
#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
|
||||
#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
|
||||
#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
|
||||
#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */
|
||||
#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**
|
||||
* @name Indexes for reading the Calibration Coefficient Data.
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */
|
||||
#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */
|
||||
#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**
|
||||
* @name Indexes for reading the Minimum/Maximum Measurement Data.
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */
|
||||
#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */
|
||||
#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */
|
||||
#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */
|
||||
#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */
|
||||
#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */
|
||||
#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */
|
||||
#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */
|
||||
#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */
|
||||
#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */
|
||||
#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */
|
||||
#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */
|
||||
#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */
|
||||
#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**
|
||||
* @name Alarm Threshold(Limit) Register (ATR) indexes.
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */
|
||||
#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */
|
||||
#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */
|
||||
#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */
|
||||
#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */
|
||||
#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */
|
||||
#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */
|
||||
#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */
|
||||
#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */
|
||||
#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
|
||||
#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
|
||||
#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
|
||||
#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
|
||||
#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
|
||||
#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
|
||||
#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**
|
||||
* @name Averaging to be done for the channels.
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */
|
||||
#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */
|
||||
#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */
|
||||
#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**
|
||||
* @name Channel Sequencer Modes of operation
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */
|
||||
#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */
|
||||
#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */
|
||||
#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */
|
||||
#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */
|
||||
#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @name Power Down Modes
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */
|
||||
#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */
|
||||
#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */
|
||||
/*@}*/
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the XADC/ADC
|
||||
* device.
|
||||
*/
|
||||
typedef struct {
|
||||
#ifndef SDT
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
#else
|
||||
char *Name;
|
||||
#endif
|
||||
u32 BaseAddress; /**< Device base address */
|
||||
} XAdcPs_Config;
|
||||
|
||||
|
||||
/**
|
||||
* The driver's instance data. The user is required to allocate a variable
|
||||
* of this type for every XADC/ADC device in the system. A pointer to
|
||||
* a variable of this type is then passed to the driver API functions.
|
||||
*/
|
||||
typedef struct {
|
||||
XAdcPs_Config Config; /**< XAdcPs_Config of current device */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
|
||||
} XAdcPs;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro checks if the XADC device is in Event Sampling mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XAdcPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if the device is in Event Sampling Mode.
|
||||
* - FALSE if the device is in Continuous Sampling Mode.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
|
||||
(((XAdcPs_ReadInternalReg(InstancePtr, \
|
||||
XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
|
||||
TRUE : FALSE))
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro checks if the XADC device is in External Mux mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XAdcPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if the device is in External Mux Mode.
|
||||
* - FALSE if the device is NOT in External Mux Mode.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
|
||||
(((XAdcPs_ReadInternalReg(InstancePtr, \
|
||||
XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
|
||||
TRUE : FALSE))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro converts XADC Raw Data to Temperature(centigrades).
|
||||
*
|
||||
* @param AdcData is the Raw ADC Data from XADC.
|
||||
*
|
||||
* @return The Temperature in centigrades.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* float XAdcPs_RawToTemperature(u32 AdcData);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_RawToTemperature(AdcData) \
|
||||
((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro converts XADC/ADC Raw Data to Voltage(volts).
|
||||
*
|
||||
* @param AdcData is the XADC/ADC Raw Data.
|
||||
*
|
||||
* @return The Voltage in volts.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* float XAdcPs_RawToVoltage(u32 AdcData);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_RawToVoltage(AdcData) \
|
||||
((((float)(AdcData))* (3.0f))/65536.0f)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
|
||||
*
|
||||
* @param Temperature is the Temperature in centigrades to be
|
||||
* converted to XADC/ADC Raw Data.
|
||||
*
|
||||
* @return The XADC/ADC Raw Data.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* int XAdcPs_TemperatureToRaw(float Temperature);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_TemperatureToRaw(Temperature) \
|
||||
((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro converts Voltage in Volts to XADC/ADC Raw Data.
|
||||
*
|
||||
* @param Voltage is the Voltage in volts to be converted to
|
||||
* XADC/ADC Raw Data.
|
||||
*
|
||||
* @return The XADC/ADC Raw Data.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* int XAdcPs_VoltageToRaw(float Voltage);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_VoltageToRaw(Voltage) \
|
||||
((int)((Voltage)*65536.0f/3.0f))
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro is used for writing to the XADC Registers using the
|
||||
* command FIFO.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XAdcPs instance.
|
||||
* @param Data is the value to be written to XADC register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_WriteFifo(InstancePtr, Data) \
|
||||
XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
|
||||
XADCPS_CMDFIFO_OFFSET, Data);
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro is used for reading from the XADC Registers using the
|
||||
* data FIFO.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XAdcPs instance.
|
||||
*
|
||||
* @return Data read from the FIFO
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XAdcPs_ReadFifo(InstancePtr) \
|
||||
XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
|
||||
XADCPS_RDFIFO_OFFSET);
|
||||
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* Functions in xadcps_sinit.c
|
||||
*/
|
||||
#ifndef SDT
|
||||
XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
|
||||
#else
|
||||
XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Functions in xadcps.c
|
||||
*/
|
||||
int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
|
||||
XAdcPs_Config *ConfigPtr,
|
||||
u32 EffectiveAddr);
|
||||
|
||||
void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
|
||||
u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
|
||||
|
||||
u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
|
||||
u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_Reset(XAdcPs *InstancePtr);
|
||||
|
||||
u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
|
||||
|
||||
u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
|
||||
|
||||
u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
|
||||
|
||||
void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
|
||||
u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
|
||||
|
||||
int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
|
||||
u8 Channel,
|
||||
int IncreaseAcqCycles,
|
||||
int IsEventMode,
|
||||
int IsDifferentialMode);
|
||||
|
||||
|
||||
void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
|
||||
u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
|
||||
u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
|
||||
u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
|
||||
u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
|
||||
|
||||
int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
|
||||
u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
|
||||
|
||||
int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
|
||||
u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
|
||||
|
||||
int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
|
||||
u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
|
||||
|
||||
int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
|
||||
u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
|
||||
u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
|
||||
|
||||
void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
|
||||
void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
|
||||
|
||||
int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
|
||||
|
||||
void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
|
||||
|
||||
void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
|
||||
|
||||
u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
|
||||
|
||||
/**
|
||||
* Functions in xadcps_selftest.c
|
||||
*/
|
||||
int XAdcPs_SelfTest(XAdcPs *InstancePtr);
|
||||
|
||||
/**
|
||||
* Functions in xadcps_intr.c
|
||||
*/
|
||||
void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
|
||||
void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
|
||||
u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
|
||||
|
||||
u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
|
||||
void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* End of protection macro. */
|
||||
/** @} */
|
||||
+478
@@ -0,0 +1,478 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xadcps_hw.h
|
||||
* @addtogroup Overview
|
||||
* @{
|
||||
*
|
||||
* This header file contains identifiers and basic driver functions (or
|
||||
* macros) that can be used to access the XADC device through the Device
|
||||
* Config Interface of the Zynq.
|
||||
*
|
||||
*
|
||||
* Refer to the device specification for more information about this driver.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
*
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ----- -------- -----------------------------------------------------
|
||||
* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
|
||||
* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
|
||||
* CR#749687
|
||||
* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef XADCPS_HW_H /* Prevent circular inclusions */
|
||||
#define XADCPS_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
|
||||
/**@name Register offsets of XADC in the Device Config
|
||||
*
|
||||
* The following constants provide access to each of the registers of the
|
||||
* XADC device.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */
|
||||
#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */
|
||||
#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */
|
||||
#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */
|
||||
#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */
|
||||
#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */
|
||||
#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */
|
||||
|
||||
/* @} */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/** @name XADC Config Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */
|
||||
#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */
|
||||
#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */
|
||||
#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */
|
||||
#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */
|
||||
#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */
|
||||
#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between
|
||||
* successive commands */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name XADC Interrupt Status/Mask Register Bit definitions
|
||||
*
|
||||
* The definitions are same for the Interrupt Status Register and
|
||||
* Interrupt Mask Register. They are defined only once.
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */
|
||||
#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
|
||||
#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
|
||||
#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */
|
||||
#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */
|
||||
#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */
|
||||
#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */
|
||||
#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */
|
||||
#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */
|
||||
#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */
|
||||
#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */
|
||||
#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */
|
||||
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name XADC Miscellaneous Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */
|
||||
#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */
|
||||
#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */
|
||||
#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */
|
||||
#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */
|
||||
#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */
|
||||
#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */
|
||||
#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name XADC Miscellaneous Control Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */
|
||||
#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */
|
||||
/* @} */
|
||||
|
||||
|
||||
/**@name Internal Register offsets of the XADC
|
||||
*
|
||||
* The following constants provide access to each of the internal registers of
|
||||
* the XADC device.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*
|
||||
* XADC Internal Channel Registers
|
||||
*/
|
||||
#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */
|
||||
#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */
|
||||
#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */
|
||||
#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */
|
||||
#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */
|
||||
#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */
|
||||
#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */
|
||||
#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */
|
||||
#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */
|
||||
#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */
|
||||
#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */
|
||||
#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */
|
||||
#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */
|
||||
|
||||
/*
|
||||
* XADC External Channel Registers
|
||||
*/
|
||||
#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */
|
||||
#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */
|
||||
#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */
|
||||
#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */
|
||||
#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */
|
||||
#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */
|
||||
#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */
|
||||
#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */
|
||||
#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */
|
||||
#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */
|
||||
#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */
|
||||
#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */
|
||||
#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */
|
||||
#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */
|
||||
#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */
|
||||
#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */
|
||||
|
||||
/*
|
||||
* XADC Registers for Maximum/Minimum data captured for the
|
||||
* on chip Temperature/VCCINT/VCCAUX data.
|
||||
*/
|
||||
#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */
|
||||
#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */
|
||||
#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */
|
||||
#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */
|
||||
#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */
|
||||
#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */
|
||||
#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */
|
||||
#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */
|
||||
#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */
|
||||
#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */
|
||||
#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */
|
||||
#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */
|
||||
#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */
|
||||
#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */
|
||||
/* Undefined 0x2F to 0x3E */
|
||||
#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */
|
||||
|
||||
/*
|
||||
* XADC Configuration Registers
|
||||
*/
|
||||
#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */
|
||||
#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */
|
||||
#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */
|
||||
|
||||
/* Test Registers 0x43 to 0x47 */
|
||||
|
||||
/*
|
||||
* XADC Sequence Registers
|
||||
*/
|
||||
#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */
|
||||
#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */
|
||||
#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */
|
||||
#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */
|
||||
#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */
|
||||
#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */
|
||||
#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */
|
||||
#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */
|
||||
|
||||
/*
|
||||
* XADC Alarm Threshold/Limit Registers (ATR)
|
||||
*/
|
||||
#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */
|
||||
#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */
|
||||
#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */
|
||||
#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */
|
||||
#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */
|
||||
#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */
|
||||
#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */
|
||||
#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */
|
||||
#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */
|
||||
#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */
|
||||
#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */
|
||||
#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */
|
||||
#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */
|
||||
#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */
|
||||
#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */
|
||||
#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */
|
||||
|
||||
/* Undefined 0x60 to 0x7F */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @name Configuration Register 0 (CFR0) mask(s)
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */
|
||||
#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */
|
||||
#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */
|
||||
#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */
|
||||
#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */
|
||||
#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */
|
||||
#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */
|
||||
#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */
|
||||
#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */
|
||||
#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/
|
||||
* Continuous mode selection
|
||||
*/
|
||||
#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */
|
||||
#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* @name Configuration Register 1 (CFR1) mask(s)
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */
|
||||
#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */
|
||||
#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */
|
||||
#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */
|
||||
#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */
|
||||
#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */
|
||||
#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */
|
||||
#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */
|
||||
#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */
|
||||
#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
|
||||
#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */
|
||||
#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */
|
||||
#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */
|
||||
#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power
|
||||
Supply Gain/Offset
|
||||
Enable */
|
||||
#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power
|
||||
Supply Offset Enable */
|
||||
#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
|
||||
Offset Enable */
|
||||
#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset
|
||||
Enable */
|
||||
#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */
|
||||
#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */
|
||||
#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */
|
||||
#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */
|
||||
#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */
|
||||
#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* @name Configuration Register 2 (CFR2) mask(s)
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**<Clock Divisor bit Mask */
|
||||
#define XADCPS_CFR2_CD_SHIFT 8U /**<Num of shift on division */
|
||||
#define XADCPS_CFR2_CD_MIN 8U /**<Minimum value of divisor */
|
||||
#define XADCPS_CFR2_CD_MAX 255U /**<Maximum value of divisor */
|
||||
|
||||
#define XADCPS_CFR2_CD_MIN 8U /**<Minimum value of divisor */
|
||||
#define XADCPS_CFR2_PD_MASK 0x0030U /**<Power Down Mask */
|
||||
#define XADCPS_CFR2_PD_XADC_MASK 0x0030U /**<Power Down XADC Mask */
|
||||
#define XADCPS_CFR2_PD_ADC1_MASK 0x0020U /**<Power Down ADC1 Mask */
|
||||
#define XADCPS_CFR2_PD_SHIFT 4U /**<Power Down Shift */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* @name Sequence Register (SEQ) Bit Definitions
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_SEQ_CH_CALIB 0x00000001U /**< ADC Calibration Channel */
|
||||
#define XADCPS_SEQ_CH_VCCPINT 0x00000020U /**< VCCPINT, Zynq Only */
|
||||
#define XADCPS_SEQ_CH_VCCPAUX 0x00000040U /**< VCCPAUX, Zynq Only */
|
||||
#define XADCPS_SEQ_CH_VCCPDRO 0x00000080U /**< VCCPDRO, Zynq Only */
|
||||
#define XADCPS_SEQ_CH_TEMP 0x00000100U /**< On Chip Temperature Channel */
|
||||
#define XADCPS_SEQ_CH_VCCINT 0x00000200U /**< VCCINT Channel */
|
||||
#define XADCPS_SEQ_CH_VCCAUX 0x00000400U /**< VCCAUX Channel */
|
||||
#define XADCPS_SEQ_CH_VPVN 0x00000800U /**< VP/VN analog inputs Channel */
|
||||
#define XADCPS_SEQ_CH_VREFP 0x00001000U /**< VREFP Channel */
|
||||
#define XADCPS_SEQ_CH_VREFN 0x00002000U /**< VREFN Channel */
|
||||
#define XADCPS_SEQ_CH_VBRAM 0x00004000U /**< VBRAM Channel, 7 series */
|
||||
#define XADCPS_SEQ_CH_AUX00 0x00010000U /**< 1st Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX01 0x00020000U /**< 2nd Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX02 0x00040000U /**< 3rd Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX03 0x00080000U /**< 4th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX04 0x00100000U /**< 5th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX05 0x00200000U /**< 6th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX06 0x00400000U /**< 7th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX07 0x00800000U /**< 8th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX08 0x01000000U /**< 9th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX09 0x02000000U /**< 10th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX10 0x04000000U /**< 11th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX11 0x08000000U /**< 12th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX12 0x10000000U /**< 13th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX13 0x20000000U /**< 14th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX14 0x40000000U /**< 15th Aux Channel */
|
||||
#define XADCPS_SEQ_CH_AUX15 0x80000000U /**< 16th Aux Channel */
|
||||
|
||||
#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1U /**< Mask for the valid channels */
|
||||
#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
|
||||
|
||||
#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0U /**< Mask for the valid channels */
|
||||
#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
|
||||
|
||||
#define XADCPS_SEQ04_CH_VALID_MASK 0x0800U /**< Mask for the valid channels */
|
||||
#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
|
||||
|
||||
#define XADCPS_SEQ06_CH_VALID_MASK 0x0800U /**< Mask for the valid channels */
|
||||
#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
|
||||
|
||||
|
||||
#define XADCPS_SEQ_CH_AUX_SHIFT 16U /**< Shift for the Aux Channel */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* @name OT Upper Alarm Threshold Register Bit Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000FU /**< Mask for OT enable */
|
||||
#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0U /**< Mask for OT value */
|
||||
#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4U /**< Shift for OT value */
|
||||
#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003U /**< Value for OT enable */
|
||||
#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFFU /**< Max OT value */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**
|
||||
* @name JTAG DRP Bit Definitions
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_JTAG_DATA_MASK 0x0000FFFFU /**< Mask for the Data */
|
||||
#define XADCPS_JTAG_ADDR_MASK 0x03FF0000U /**< Mask for the Addr */
|
||||
#define XADCPS_JTAG_ADDR_SHIFT 16U /**< Shift for the Addr */
|
||||
#define XADCPS_JTAG_CMD_MASK 0x3C000000U /**< Mask for the Cmd */
|
||||
#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000U /**< Mask for CMD Write */
|
||||
#define XADCPS_JTAG_CMD_READ_MASK 0x04000000U /**< Mask for CMD Read */
|
||||
#define XADCPS_JTAG_CMD_SHIFT 26U /**< Shift for the Cmd */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/** @name Unlock Register Definitions
|
||||
* @{
|
||||
*/
|
||||
#define XADCPS_UNLK_OFFSET 0x034U /**< Unlock Register */
|
||||
#define XADCPS_UNLK_VALUE 0x757BDF0DU /**< Unlock Value */
|
||||
|
||||
/* @} */
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read a register of the XADC device. This macro provides register
|
||||
* access to all registers using the register offsets defined above.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset is the offset of the register to read.
|
||||
*
|
||||
* @return The contents of the register.
|
||||
*
|
||||
* @note C-style Signature:
|
||||
* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
|
||||
(Xil_In32((BaseAddress) + (RegOffset)))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write a register of the XADC device. This macro provides
|
||||
* register access to all registers using the register offsets defined above.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset is the offset of the register to write.
|
||||
* @param Data is the value to write to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style Signature:
|
||||
* void XAdcPs_WriteReg(u32 BaseAddress,
|
||||
* u32 RegOffset,u32 Data)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
|
||||
(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Formats the data to be written to the the XADC registers.
|
||||
*
|
||||
* @param RegOffset is the offset of the Register
|
||||
* @param Data is the data to be written to the Register if it is
|
||||
* a write.
|
||||
* @param ReadWrite specifies whether it is a Read or a Write.
|
||||
* Use 0 for Read, 1 for Write.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style Signature:
|
||||
* void XAdcPs_FormatWriteData(u32 RegOffset,
|
||||
* u16 Data, int ReadWrite)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \
|
||||
((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
|
||||
((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \
|
||||
(Data & XADCPS_JTAG_DATA_MASK))
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* End of protection macro. */
|
||||
/** @} */
|
||||
+113
@@ -0,0 +1,113 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xbasic_types.h
|
||||
*
|
||||
*
|
||||
* @note Dummy File for backwards compatibility
|
||||
*
|
||||
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
|
||||
* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
|
||||
* 7.0 aru 02/06/19 Included stdint.h and stddef.h
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
*@cond nocomments
|
||||
*/
|
||||
|
||||
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
|
||||
#define XBASIC_TYPES_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/** @name Legacy types
|
||||
* Deprecated legacy types.
|
||||
* @{
|
||||
*/
|
||||
typedef uint8_t Xuint8; /**< unsigned 8-bit */
|
||||
typedef char Xint8; /**< signed 8-bit */
|
||||
typedef uint16_t Xuint16; /**< unsigned 16-bit */
|
||||
typedef short Xint16; /**< signed 16-bit */
|
||||
typedef uint32_t Xuint32; /**< unsigned 32-bit */
|
||||
typedef long Xint32; /**< signed 32-bit */
|
||||
typedef float Xfloat32; /**< 32-bit floating point */
|
||||
typedef double Xfloat64; /**< 64-bit double precision FP */
|
||||
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
|
||||
|
||||
#if !defined __XUINT64__
|
||||
typedef struct
|
||||
{
|
||||
Xuint32 Upper;
|
||||
Xuint32 Lower;
|
||||
} Xuint64;
|
||||
#endif
|
||||
|
||||
/** @name New types
|
||||
* New simple types.
|
||||
* @{
|
||||
*/
|
||||
#ifndef __KERNEL__
|
||||
#ifndef XIL_TYPES_H
|
||||
typedef Xuint32 u32;
|
||||
typedef Xuint16 u16;
|
||||
typedef Xuint8 u8;
|
||||
#endif
|
||||
#else
|
||||
#include <linux/types.h>
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
# define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
# define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
|
||||
* Please use NULL, TRUE and FALSE
|
||||
*/
|
||||
#define XNULL NULL
|
||||
#define XTRUE TRUE
|
||||
#define XFALSE FALSE
|
||||
|
||||
/*
|
||||
* This file is deprecated and users
|
||||
* should use xil_types.h and xil_assert.h\n\r
|
||||
*/
|
||||
#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
|
||||
#warning Please refer the Standalone BSP UG647 for further details
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
|
||||
/**
|
||||
*@endcond
|
||||
*/
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
#ifndef XCOMMON_DRV_CONFIG_H_
|
||||
#define XCOMMON_DRV_CONFIG_H_
|
||||
|
||||
#define XPAR_SCUGIC
|
||||
|
||||
#endif
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xcoresightpsdcc.h
|
||||
* @addtogroup coresightps_dcc Overview
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* CoreSight driver component.
|
||||
*
|
||||
* The coresight is a part of debug communication channel (DCC) group. Jtag UART
|
||||
* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
|
||||
* ARM target in XSDB console before running the jtag terminal command. Using the
|
||||
* coresight driver component, the output stream can be directed to a log file.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ----- -------- -----------------------------------------------
|
||||
* 1.00 kvn 02/14/15 First release
|
||||
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
|
||||
* kvn 08/18/15 Modified Makefile according to compiler changes.
|
||||
* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
|
||||
* for MB BSPs. Instead it throws up a warning. This
|
||||
* fixes the CR#953056.
|
||||
* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
|
||||
#define XCORESIGHTPSDCC_H /* by using protection macros */
|
||||
#ifndef __MICROBLAZE__
|
||||
#include <xil_types.h>
|
||||
|
||||
void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
|
||||
|
||||
u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
|
||||
#endif
|
||||
#endif
|
||||
/** @} */
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
#ifndef XIL_XCORTEXA9_H_ /* prevent circular inclusions */
|
||||
#define XIL_XCORTEXA9_H_ /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
typedef struct {
|
||||
u32 CpuFreq;
|
||||
} XCortexa9_Config;
|
||||
|
||||
#endif /* XIL_XCORTEXA9_H_ */
|
||||
+18
@@ -0,0 +1,18 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
#ifndef XIL_XCORTEXA9_CONFIG_H_ /* prevent circular inclusions */
|
||||
#define XIL_XCORTEXA9_CONFIG_H_ /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xcortexa9.h"
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
extern XCortexa9_Config XCortexa9_ConfigTable;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
#define XGet_CpuFreq() XCortexa9_ConfigTable.CpuFreq
|
||||
#endif /* XIL_XCORTEXA9_CONFIG_H_ */
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef XDEBUG
|
||||
#define XDEBUG
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "xil_printf.h"
|
||||
|
||||
#if defined(DEBUG) && !defined(NDEBUG)
|
||||
|
||||
#ifndef XDEBUG_WARNING
|
||||
#define XDEBUG_WARNING
|
||||
#warning DEBUG is enabled
|
||||
#endif
|
||||
|
||||
int printf(const char *format, ...);
|
||||
|
||||
#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
|
||||
#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
|
||||
#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
|
||||
|
||||
#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */
|
||||
#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */
|
||||
#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */
|
||||
#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */
|
||||
|
||||
#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */
|
||||
#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */
|
||||
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */
|
||||
|
||||
|
||||
#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
|
||||
|
||||
#define xdbg_stmnt(x) x
|
||||
|
||||
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
|
||||
* macros that accept variable number of arguments
|
||||
*/
|
||||
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
|
||||
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
|
||||
#else /* ANSI Syntax */
|
||||
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
|
||||
#endif
|
||||
|
||||
#define xdbg_exception_printf(type, ...) (((type) & xdbg_current_types) ? xil_printf (__VA_ARGS__) : 0)
|
||||
|
||||
#else /* defined(DEBUG) && !defined(NDEBUG) */
|
||||
|
||||
#define xdbg_stmnt(x) /**< Debug statement */
|
||||
|
||||
/* See VxWorks comments above */
|
||||
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
|
||||
#define xdbg_printf(type, args...)
|
||||
#else /* ANSI Syntax */
|
||||
#define xdbg_printf(...) /**< Debug printf */
|
||||
#endif
|
||||
#endif /* defined(DEBUG) && !defined(NDEBUG) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* XDEBUG */
|
||||
+393
@@ -0,0 +1,393 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdevcfg.h
|
||||
* @addtogroup devcfg Overview
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* The is the main header file for the Device Configuration Interface of the Zynq
|
||||
* device. The device configuration interface has three main functionality.
|
||||
* 1. AXI-PCAP
|
||||
* 2. Security Policy
|
||||
* 3. XADC
|
||||
* This current version of the driver supports only the AXI-PCAP and Security
|
||||
* Policy blocks. There is a separate driver for XADC.
|
||||
*
|
||||
* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
|
||||
* DMA embedded in the AXI PCAP provides the master interface to
|
||||
* the Device configuration block for any DMA transfers. The data transfer can
|
||||
* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
|
||||
* RAM/DDR/peripheral memory).
|
||||
*
|
||||
* The current driver only supports the downloading the FPGA bitstream and
|
||||
* readback of the decrypted image (sort of loopback).
|
||||
* The driver does not know what information needs to be written to the FPGA to
|
||||
* readback FPGA configuration register or memory data. The application above the
|
||||
* driver should take care of creating the data that needs to be downloaded to
|
||||
* the FPGA so that the bitstream can be readback.
|
||||
* This driver also does not support the reading of the internal registers of the
|
||||
* PCAP. The driver has no knowledge of the PCAP internals.
|
||||
*
|
||||
* <b> Initialization and Configuration </b>
|
||||
*
|
||||
* The device driver enables higher layer software (e.g., an application) to
|
||||
* communicate with the Device Configuration device.
|
||||
*
|
||||
* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
|
||||
* Interface. The user needs to first call the XDcfg_LookupConfig() API which
|
||||
* returns the Configuration structure pointer which is passed as a parameter to
|
||||
* the XDcfg_CfgInitialize() API.
|
||||
*
|
||||
* <b>Interrupts</b>
|
||||
* The Driver implements an interrupt handler to support the interrupts provided
|
||||
* by this interface.
|
||||
*
|
||||
* <b> Threads </b>
|
||||
*
|
||||
* This driver is not thread safe. Any needs for threads or thread mutual
|
||||
* exclusion must be satisfied by the layer above this driver.
|
||||
*
|
||||
* <b> Asserts </b>
|
||||
*
|
||||
* Asserts are used within all Xilinx drivers to enforce constraints on argument
|
||||
* values. Asserts can be turned off on a system-wide basis by defining, at
|
||||
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
|
||||
* is recommended that users leave asserts on during development.
|
||||
*
|
||||
* <b> Building the driver </b>
|
||||
*
|
||||
* The XDcfg driver is composed of several source files. This allows the user
|
||||
* to build and link only those parts of the driver that are necessary.
|
||||
*
|
||||
* <br><br>
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a hvm 02/07/11 First release
|
||||
* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
|
||||
* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
|
||||
* APIs is words (32 bit) and not bytes.
|
||||
* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
|
||||
* to add information that 2 LSBs of the Source/Destination
|
||||
* address when equal to 2�b01 indicate the last DMA command
|
||||
* of an overall transfer.
|
||||
* Destination Address passed to this API for secure transfers
|
||||
* instead of using 0xFFFFFFFF for CR 662197. This issue was
|
||||
* resulting in the failure of secure transfers of
|
||||
* non-bitstream images.
|
||||
* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
|
||||
* set the mask instead of oring it with the
|
||||
* value read from the interrupt status register
|
||||
* Added defines for the PS Version bits,
|
||||
* removed the FIFO Flush bits from the
|
||||
* Miscellaneous Control Reg.
|
||||
* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
|
||||
* and XDcfg_SelectPcapInterface APIs for CR 643295
|
||||
* The user has to call the XDcfg_SelectIcapInterface API
|
||||
* for the PL reconfiguration using AXI HwIcap.
|
||||
* Updated the XDcfg_Transfer API to clear the
|
||||
* QUARTER_PCAP_RATE_EN bit in the control register for
|
||||
* non secure writes for CR 675543.
|
||||
* 2.02a nm 01/31/13 Fixed CR# 679335.
|
||||
* Added Setting and Clearing the internal PCAP loopback.
|
||||
* Removed code for enabling/disabling AES engine as BootROM
|
||||
* locks down this setting.
|
||||
* Fixed CR# 681976.
|
||||
* Skip Checking the PCFG_INIT in case of non-secure DMA
|
||||
* loopback.
|
||||
* Fixed CR# 699558.
|
||||
* XDcfg_Transfer fails to transfer data in loopback mode.
|
||||
* Fixed CR# 701348.
|
||||
* Peripheral test fails with Running
|
||||
* DcfgSelfTestExample() in SECURE bootmode.
|
||||
* 2.03a nm 04/19/13 Fixed CR# 703728.
|
||||
* Updated the register definitions as per the latest TRM
|
||||
* version UG585 (v1.4) November 16, 2012.
|
||||
* 3.0 adk 10/12/13 Updated as per the New Tcl API's
|
||||
* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
|
||||
* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
|
||||
* updated driver code with != instead of ==,
|
||||
* while checking for Interrupt Status with DMA and
|
||||
* PCAP Done Mask
|
||||
* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
* XDCFG_INT_STS_OFFSET) &
|
||||
* XDCFG_IXR_D_P_DONE_MASK) !=
|
||||
* XDCFG_IXR_D_P_DONE_MASK);
|
||||
* A new example has been added to read back the
|
||||
* configuration registers from the PL region.
|
||||
* xdevcfg_reg_readback_example.c
|
||||
* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/10/17 Modified filename tag in interrupt and polled examples
|
||||
* to include them in doxygen examples.
|
||||
* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
|
||||
* definitions of devcfg in xparameters.h
|
||||
* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
|
||||
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XDCFG_H /* prevent circular inclusions */
|
||||
#define XDCFG_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xdevcfg_hw.h"
|
||||
#include "xstatus.h"
|
||||
#include "xil_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/* Types of PCAP transfers */
|
||||
|
||||
#define XDCFG_NON_SECURE_PCAP_WRITE 1
|
||||
#define XDCFG_SECURE_PCAP_WRITE 2
|
||||
#define XDCFG_PCAP_READBACK 3
|
||||
#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
|
||||
#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
/**
|
||||
* The handler data type allows the user to define a callback function to
|
||||
* respond to interrupt events in the system. This function is executed
|
||||
* in interrupt context, so amount of processing should be minimized.
|
||||
*
|
||||
* @param CallBackRef is the callback reference passed in by the upper
|
||||
* layer when setting the callback functions, and passed back to
|
||||
* the upper layer when the callback is invoked. Its type is
|
||||
* unimportant to the driver component, so it is a void pointer.
|
||||
* @param Status is the Interrupt status of the XDcfg device.
|
||||
*/
|
||||
typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
typedef struct {
|
||||
#ifndef SDT
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
#else
|
||||
char *Name;
|
||||
#endif
|
||||
u32 BaseAddr; /**< Base address of the device */
|
||||
#ifdef SDT
|
||||
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
|
||||
* trigger type and level flags */
|
||||
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
|
||||
* Parent base address */
|
||||
#endif
|
||||
} XDcfg_Config;
|
||||
|
||||
/**
|
||||
* The XDcfg driver instance data.
|
||||
*/
|
||||
typedef struct {
|
||||
XDcfg_Config Config; /**< Hardware Configuration */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
u32 IsStarted; /**< Device Configuration Interface
|
||||
* is running
|
||||
*/
|
||||
XDcfg_IntrHandler StatusHandler; /* Event handler function */
|
||||
void *CallBackRef; /* Callback reference for event handler */
|
||||
} XDcfg;
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Unlock the Device Config Interface block.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of XDcfg driver.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XDcfg_Unlock(XDcfg* InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XDcfg_Unlock(InstancePtr) \
|
||||
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
|
||||
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
|
||||
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Get the version number of the PS from the Miscellaneous Control Register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of XDcfg driver.
|
||||
*
|
||||
* @return Version of the PS.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XDcfg_GetPsVersion(InstancePtr) \
|
||||
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XDCFG_MCTRL_OFFSET)) & \
|
||||
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
|
||||
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
|
||||
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the multiboot config register value.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of XDcfg driver.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XDcfg_ReadMultiBootConfig(InstancePtr) \
|
||||
XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XDCFG_MULTIBOOT_ADDR_OFFSET)
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Selects ICAP interface for reconfiguration after the initial configuration
|
||||
* of the PL.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of XDcfg driver.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XDcfg_SelectIcapInterface(InstancePtr) \
|
||||
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
|
||||
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
|
||||
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Selects PCAP interface for reconfiguration after the initial configuration
|
||||
* of the PL.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of XDcfg driver.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XDcfg_SelectPcapInterface(InstancePtr) \
|
||||
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
|
||||
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
|
||||
| XDCFG_CTRL_PCAP_PR_MASK))
|
||||
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*
|
||||
* Lookup configuration in xdevcfg_sinit.c.
|
||||
*/
|
||||
#ifndef SDT
|
||||
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
|
||||
#else
|
||||
XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Selftest function in xdevcfg_selftest.c
|
||||
*/
|
||||
int XDcfg_SelfTest(XDcfg *InstancePtr);
|
||||
|
||||
/*
|
||||
* Interface functions in xdevcfg.c
|
||||
*/
|
||||
int XDcfg_CfgInitialize(XDcfg *InstancePtr,
|
||||
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
|
||||
|
||||
void XDcfg_EnablePCAP(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_DisablePCAP(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
|
||||
|
||||
void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
|
||||
|
||||
u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
|
||||
|
||||
u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
|
||||
|
||||
u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
|
||||
|
||||
u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
|
||||
|
||||
u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
|
||||
|
||||
u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
|
||||
|
||||
u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
|
||||
u32 SrcWordLength, u32 DestWordLength);
|
||||
|
||||
u32 XDcfg_Transfer(XDcfg *InstancePtr,
|
||||
void *SourcePtr, u32 SrcWordLength,
|
||||
void *DestPtr, u32 DestWordLength,
|
||||
u32 TransferType);
|
||||
|
||||
/*
|
||||
* Interrupt related function prototypes implemented in xdevcfg_intr.c
|
||||
*/
|
||||
void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
|
||||
|
||||
void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
|
||||
|
||||
u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
|
||||
|
||||
u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
|
||||
|
||||
void XDcfg_InterruptHandler(XDcfg *InstancePtr);
|
||||
|
||||
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
|
||||
void *CallBackRef);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
+371
@@ -0,0 +1,371 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdevcfg_hw.h
|
||||
* @addtogroup devcfg Overview
|
||||
* @{
|
||||
*
|
||||
* This file contains the hardware interface to the Device Config Interface.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a hvm 02/07/11 First release
|
||||
* 2.01a nm 08/01/12 Added defines for the PS Version bits,
|
||||
* removed the FIFO Flush bits from the
|
||||
* Miscellaneous Control Reg
|
||||
* 2.03a nm 04/19/13 Fixed CR# 703728.
|
||||
* Updated the register definitions as per the latest TRM
|
||||
* version UG585 (v1.4) November 16, 2012.
|
||||
* 2.04a kpc 10/07/13 Added function prototype.
|
||||
* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
|
||||
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XDCFG_HW_H /* prevent circular inclusions */
|
||||
#define XDCFG_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Register Map
|
||||
* Offsets of registers from the start of the device
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
|
||||
#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
|
||||
#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
|
||||
#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
|
||||
#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
|
||||
#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
|
||||
#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
|
||||
#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
|
||||
#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
|
||||
#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
|
||||
#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
|
||||
#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
|
||||
#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
|
||||
#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
|
||||
#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
|
||||
|
||||
/* @} */
|
||||
|
||||
/** @name Control Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
|
||||
* Secure Reset
|
||||
*/
|
||||
#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
|
||||
* Reset FPGA
|
||||
*/
|
||||
#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
|
||||
#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
|
||||
#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
|
||||
#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
|
||||
* to FPGA every 4 PCAP
|
||||
* cycles
|
||||
*/
|
||||
#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
|
||||
#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
|
||||
#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
|
||||
#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
|
||||
#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
|
||||
#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
|
||||
#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
|
||||
* Status mask
|
||||
*/
|
||||
#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
|
||||
* Debug Enable
|
||||
*/
|
||||
#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
|
||||
* Debug Enable
|
||||
*/
|
||||
#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
|
||||
* Enable
|
||||
*/
|
||||
#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
|
||||
* Enable
|
||||
*/
|
||||
#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
|
||||
|
||||
/* @} */
|
||||
|
||||
/** @name Lock register bit definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
|
||||
#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
|
||||
#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
|
||||
#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
|
||||
* USER_MODE
|
||||
*/
|
||||
#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
|
||||
* security config
|
||||
* including: DAP_En,
|
||||
* DBGEN,,
|
||||
* NIDEN, SPNIEN
|
||||
*/
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/** @name Config Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
|
||||
* Threshold Mask
|
||||
*/
|
||||
#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
|
||||
* Mask
|
||||
*/
|
||||
#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
|
||||
* clock edge
|
||||
*/
|
||||
#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
|
||||
* clock edge
|
||||
*/
|
||||
#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
|
||||
* increment mask
|
||||
*/
|
||||
#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
|
||||
* address increment
|
||||
* mask
|
||||
*/
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Interrupt Status/Mask Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
|
||||
* HIZ
|
||||
*/
|
||||
#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
|
||||
* done
|
||||
*/
|
||||
#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
|
||||
#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
|
||||
* configuration
|
||||
*/
|
||||
#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
|
||||
* reset
|
||||
*/
|
||||
#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
|
||||
* or Data or response
|
||||
* timeout
|
||||
*/
|
||||
#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
|
||||
* error
|
||||
*/
|
||||
#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
|
||||
* response timeout
|
||||
*/
|
||||
#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
|
||||
* error
|
||||
*/
|
||||
#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
|
||||
#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
|
||||
* threshold */
|
||||
#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
|
||||
* threshold */
|
||||
#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
|
||||
#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
|
||||
* overflow
|
||||
*/
|
||||
#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
|
||||
#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
|
||||
* transfers Done
|
||||
*/
|
||||
#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
|
||||
* length error
|
||||
*/
|
||||
#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
|
||||
#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
|
||||
#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
|
||||
#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
|
||||
#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
|
||||
#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
|
||||
* of Init Signal
|
||||
*/
|
||||
#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
|
||||
* of Init Signal
|
||||
*/
|
||||
#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
|
||||
XDCFG_IXR_AXI_WERR_MASK | \
|
||||
XDCFG_IXR_AXI_RTO_MASK | \
|
||||
XDCFG_IXR_AXI_RERR_MASK | \
|
||||
XDCFG_IXR_RX_FIFO_OV_MASK | \
|
||||
XDCFG_IXR_DMA_CMD_ERR_MASK |\
|
||||
XDCFG_IXR_DMA_Q_OV_MASK | \
|
||||
XDCFG_IXR_P2D_LEN_ERR_MASK |\
|
||||
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
|
||||
|
||||
|
||||
#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
|
||||
|
||||
|
||||
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Status Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
|
||||
* Queue full
|
||||
*/
|
||||
#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
|
||||
* Queue empty
|
||||
*/
|
||||
#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
|
||||
* completed DMA
|
||||
* transfers
|
||||
*/
|
||||
#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
|
||||
#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
|
||||
|
||||
#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
|
||||
* during HIZ
|
||||
*/
|
||||
#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
|
||||
* done
|
||||
*/
|
||||
#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
|
||||
#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
|
||||
* config
|
||||
*/
|
||||
#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
|
||||
* POR Status
|
||||
*/
|
||||
#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
|
||||
* access
|
||||
*/
|
||||
#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
|
||||
* reset status
|
||||
*/
|
||||
#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
|
||||
* Status
|
||||
*/
|
||||
#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
|
||||
/**< BBRAM key
|
||||
* disable
|
||||
*/
|
||||
#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
|
||||
* Enable Status
|
||||
*/
|
||||
#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
|
||||
* Disable
|
||||
* status
|
||||
*/
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name DMA Source/Destination Transfer Length Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
|
||||
/** @name Miscellaneous Control Register Bit definitions
|
||||
* @{
|
||||
*/
|
||||
#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
|
||||
#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
|
||||
#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
|
||||
/* @} */
|
||||
|
||||
/** @name FIFO Threshold Bit definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
|
||||
#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
|
||||
#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
|
||||
#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
|
||||
/* @}*/
|
||||
|
||||
|
||||
/* Miscellaneous constant values */
|
||||
#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
|
||||
#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
|
||||
#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
|
||||
* address
|
||||
*/
|
||||
#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the given register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the device
|
||||
* @param RegOffset is the register offset to be read
|
||||
*
|
||||
* @return The 32-bit value of the register
|
||||
*
|
||||
* @note C-style signature:
|
||||
* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XDcfg_ReadReg(BaseAddr, RegOffset) \
|
||||
Xil_In32((BaseAddr) + (RegOffset))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write to the given register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the device
|
||||
* @param RegOffset is the register offset to be written
|
||||
* @param Data is the 32-bit value to write to the register
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddr) + (RegOffset), (Data))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
/*
|
||||
* Perform reset operation to the devcfg interface
|
||||
*/
|
||||
void XDcfg_ResetHw(u32 BaseAddr);
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
+347
@@ -0,0 +1,347 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xdmaps.h
|
||||
* @addtogroup dmaps Overview
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ----------------------------------------------
|
||||
* 1.00 hbm 08/19/10 First Release
|
||||
* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
|
||||
* the maximum number of channels.
|
||||
* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
|
||||
* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
|
||||
* Added the tcl file to automatically generate the
|
||||
* xparameters.h
|
||||
* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
|
||||
* header from the xdmaps.h file to xdmaps.c file
|
||||
* Other cleanup for coding guidelines and CR 657109
|
||||
* and CR 657898
|
||||
* The xdmaps_example_no_intr.c example is removed
|
||||
* as it is using interrupts and is similar to
|
||||
* the interrupt example - CR 652477
|
||||
* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
|
||||
* 1.04a nm 10/22/2012 Fixed CR# 681671.
|
||||
* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
|
||||
* with -Wall and -Wextra option in bsp.
|
||||
* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
|
||||
* function description.
|
||||
* Fixed CR# 704396. Removed unused variables
|
||||
* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
|
||||
* function.
|
||||
* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
|
||||
* Removed the PDBG prints. By default they were always
|
||||
* defined out and never used. The PDBG is non-standard for
|
||||
* Xilinx drivers and no other driver does something similar.
|
||||
* Since there is no easy way to fix compilation issues with
|
||||
* the IARCC compiler around PDBG, it is better to remove it.
|
||||
* Users can always use xil_printfs if they want to debug.
|
||||
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
|
||||
* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
|
||||
* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
|
||||
* linker error for IAR compiler
|
||||
* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
|
||||
* examples to ensure that "Successfully ran" and "Failed"
|
||||
* strings are available in all examples. This is a fix
|
||||
* for CR-965028.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
|
||||
* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
|
||||
* to static inline to avoid the linkage conflict for IAR compiler.
|
||||
* 2.9 aj 11/07/23 Added support for system device tree
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef XDMAPS_H /* prevent circular inclusions */
|
||||
#define XDMAPS_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#include "xdmaps_hw.h"
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
typedef struct {
|
||||
#ifndef SDT
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
#else
|
||||
char *Name;
|
||||
#endif
|
||||
u32 BaseAddress; /**< Base address of device (IPIF) */
|
||||
|
||||
#ifdef SDT
|
||||
u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12]
|
||||
* trigger type and level flags */
|
||||
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
|
||||
* Parent base address */
|
||||
#endif
|
||||
} XDmaPs_Config;
|
||||
|
||||
|
||||
/** DMA channle control structure. It's for AXI bus transaction.
|
||||
* This struct will be translated into a 32-bit channel control register value.
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int EndianSwapSize; /**< Endian swap size. */
|
||||
unsigned int DstCacheCtrl; /**< Destination cache control */
|
||||
unsigned int DstProtCtrl; /**< Destination protection control */
|
||||
unsigned int DstBurstLen; /**< Destination burst length */
|
||||
unsigned int DstBurstSize; /**< Destination burst size */
|
||||
unsigned int DstInc; /**< Destination incrementing or fixed
|
||||
* address */
|
||||
unsigned int SrcCacheCtrl; /**< Source cache control */
|
||||
unsigned int SrcProtCtrl; /**< Source protection control */
|
||||
unsigned int SrcBurstLen; /**< Source burst length */
|
||||
unsigned int SrcBurstSize; /**< Source burst size */
|
||||
unsigned int SrcInc; /**< Source incrementing or fixed
|
||||
* address */
|
||||
} XDmaPs_ChanCtrl;
|
||||
|
||||
/** DMA block descriptor stucture.
|
||||
*/
|
||||
typedef struct {
|
||||
u32 SrcAddr; /**< Source starting address */
|
||||
u32 DstAddr; /**< Destination starting address */
|
||||
unsigned int Length; /**< Number of bytes for the block */
|
||||
} XDmaPs_BD;
|
||||
|
||||
/**
|
||||
* A DMA command consisits of a channel control struct, a block descriptor,
|
||||
* a user defined program, a pointer pointing to generated DMA program, and
|
||||
* execution result.
|
||||
*
|
||||
*/
|
||||
typedef struct {
|
||||
XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
|
||||
XDmaPs_BD BD; /**< Together with SgLength field,
|
||||
* it's a scatter-gather list.
|
||||
*/
|
||||
void *UserDmaProg; /**< If user wants the driver to
|
||||
* execute their own DMA program,
|
||||
* this field points to the DMA
|
||||
* program.
|
||||
*/
|
||||
int UserDmaProgLength; /**< The length of user defined
|
||||
* DMA program.
|
||||
*/
|
||||
|
||||
void *GeneratedDmaProg; /**< The DMA program genreated
|
||||
* by the driver. This field will be
|
||||
* set if a user invokes the DMA
|
||||
* program generation function. Or
|
||||
* the DMA command is finished and
|
||||
* a user informs the driver not to
|
||||
* release the program buffer.
|
||||
* This field has two purposes, one
|
||||
* is to ask the driver to generate
|
||||
* a DMA program while the DMAC is
|
||||
* performaning DMA transactions. The
|
||||
* other purpose is to debug the
|
||||
* driver.
|
||||
*/
|
||||
int GeneratedDmaProgLength; /**< The length of the DMA program
|
||||
* generated by the driver
|
||||
*/
|
||||
int DmaStatus; /**< 0 on success, otherwise error code
|
||||
*/
|
||||
u32 ChanFaultType; /**< Channel fault type in case of fault
|
||||
*/
|
||||
u32 ChanFaultPCAddr; /**< Channel fault PC address
|
||||
*/
|
||||
} XDmaPs_Cmd;
|
||||
|
||||
/**
|
||||
* It's the done handler a user can set for a channel
|
||||
*/
|
||||
typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
|
||||
XDmaPs_Cmd *DmaCmd,
|
||||
void *CallbackRef);
|
||||
|
||||
/**
|
||||
* It's the fault handler a user can set for a channel
|
||||
*/
|
||||
typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
|
||||
XDmaPs_Cmd *DmaCmd,
|
||||
void *CallbackRef);
|
||||
|
||||
#define XDMAPS_MAX_CHAN_BUFS 2
|
||||
#define XDMAPS_CHAN_BUF_LEN 128
|
||||
|
||||
/**
|
||||
* The XDmaPs_ProgBuf is the struct for a DMA program buffer.
|
||||
*/
|
||||
typedef struct {
|
||||
char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
|
||||
* content */
|
||||
unsigned Len; /**< The actual length of the DMA
|
||||
* program in bytes. */
|
||||
int Allocated; /**< A tag indicating whether the
|
||||
* buffer is allocated or not */
|
||||
} XDmaPs_ProgBuf;
|
||||
|
||||
/**
|
||||
* The XDmaPs_ChannelData is a struct to book keep individual channel of
|
||||
* the DMAC.
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned DevId; /**< Device id indicating which DMAC */
|
||||
unsigned ChanId; /**< Channel number of the DMAC */
|
||||
XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
|
||||
program buffers*/
|
||||
XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
|
||||
void *DoneRef; /**< Done interrupt callback data */
|
||||
XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
|
||||
XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
|
||||
* This field is for debugging purpose
|
||||
*/
|
||||
int HoldDmaProg; /**< A tag indicating whether to hold the
|
||||
* DMA program after the DMA is done.
|
||||
*/
|
||||
|
||||
} XDmaPs_ChannelData;
|
||||
|
||||
/**
|
||||
* The XDmaPs driver instance data structure. A pointer to an instance data
|
||||
* structure is passed around by functions to refer to a specific driver
|
||||
* instance.
|
||||
*/
|
||||
typedef struct {
|
||||
XDmaPs_Config Config; /**< Configuration data structure */
|
||||
int IsReady; /**< Device is Ready */
|
||||
int CacheLength; /**< icache length */
|
||||
XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
|
||||
void *FaultRef; /**< fault call back data */
|
||||
XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
|
||||
/**<
|
||||
* channel data
|
||||
*/
|
||||
} XDmaPs;
|
||||
|
||||
/*
|
||||
* Functions implemented in xdmaps.c
|
||||
*/
|
||||
int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
|
||||
XDmaPs_Config *Config,
|
||||
u32 EffectiveAddr);
|
||||
|
||||
int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
|
||||
XDmaPs_Cmd *Cmd,
|
||||
int HoldDmaProg);
|
||||
|
||||
int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
|
||||
int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
|
||||
XDmaPs_Cmd *Cmd);
|
||||
int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
|
||||
XDmaPs_Cmd *Cmd);
|
||||
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
|
||||
|
||||
|
||||
int XDmaPs_ResetManager(XDmaPs *InstPtr);
|
||||
int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
|
||||
|
||||
|
||||
int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
|
||||
unsigned Channel,
|
||||
XDmaPsDoneHandler DoneHandler,
|
||||
void *CallbackRef);
|
||||
|
||||
int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
|
||||
XDmaPsFaultHandler FaultHandler,
|
||||
void *CallbackRef);
|
||||
|
||||
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
|
||||
int XDmaPs_Instr_DMARMB(char *DmaProg);
|
||||
int XDmaPs_Instr_DMAWMB(char *DmaProg);
|
||||
|
||||
/**
|
||||
* To avoid linkage error,modify all inline functions from extern
|
||||
* inline to static inline for IAR compiler
|
||||
*/
|
||||
#ifdef __ICCARM__
|
||||
static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
|
||||
static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
|
||||
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
|
||||
u32 Imm, unsigned int Ns);
|
||||
static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
|
||||
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
|
||||
unsigned LoopIterations);
|
||||
static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
|
||||
static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
|
||||
static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
|
||||
static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
|
||||
static INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
|
||||
static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
|
||||
static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Driver done interrupt service routines for the channels.
|
||||
* We need this done ISR mainly because the driver needs to release the
|
||||
* DMA program buffer. This is the one that connects the GIC
|
||||
*/
|
||||
void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
|
||||
void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
|
||||
void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
|
||||
void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
|
||||
void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
|
||||
void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
|
||||
void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
|
||||
void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
|
||||
|
||||
/**
|
||||
* Driver fault interrupt service routine
|
||||
*/
|
||||
void XDmaPs_FaultISR(XDmaPs *InstPtr);
|
||||
|
||||
|
||||
/*
|
||||
* Static loopup function implemented in xdmaps_sinit.c
|
||||
*/
|
||||
#ifndef SDT
|
||||
XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
|
||||
#else
|
||||
XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress);
|
||||
u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress);
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* self-test functions in xdmaps_selftest.c
|
||||
*/
|
||||
int XDmaPs_SelfTest(XDmaPs *InstPtr);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
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Reference in New Issue
Block a user