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Migrate to Vitis2023.2 version

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This commit is contained in:
Jeremy Shen
2026-05-26 17:02:52 +08:00
parent 2dca3709ef
commit 3b268f6583
5060 changed files with 1117688 additions and 288060 deletions
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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define ZYNQMP_DPDMA_VIDEO0 0
#define ZYNQMP_DPDMA_VIDEO1 1
#define ZYNQMP_DPDMA_VIDEO2 2
#define ZYNQMP_DPDMA_GRAPHICS 3
#define ZYNQMP_DPDMA_AUDIO0 4
#define ZYNQMP_DPDMA_AUDIO1 5
#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/gpio/gpio.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for most GPIO bindings.
*
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_GPIO_GPIO_H
#define _DT_BINDINGS_GPIO_GPIO_H
/* Bit 0 express polarity */
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
/* Bit 1 express single-endedness */
#define GPIO_PUSH_PULL 0
#define GPIO_SINGLE_ENDED 2
/* Bit 2 express Open drain or open source */
#define GPIO_LINE_OPEN_SOURCE 0
#define GPIO_LINE_OPEN_DRAIN 4
/*
* Open Drain/Collector is the combination of single-ended open drain interface.
* Open Source/Emitter is the combination of single-ended open source interface.
*/
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
/* Bit 3 express GPIO suspend/resume and reset persistence */
#define GPIO_PERSISTENT 0
#define GPIO_TRANSITORY 8
/* Bit 4 express pull up */
#define GPIO_PULL_UP 16
/* Bit 5 express pull down */
#define GPIO_PULL_DOWN 32
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/input/input.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for most input bindings.
*
* Most input bindings include key code, matrix key code format.
* In most cases, key code and matrix key code format uses
* the standard values/macro defined in this header.
*/
#ifndef _DT_BINDINGS_INPUT_INPUT_H
#define _DT_BINDINGS_INPUT_INPUT_H
/*
* Device properties and quirks
*/
#define INPUT_PROP_POINTER 0x00 /* needs a pointer */
#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
#define INPUT_PROP_MAX 0x1f
#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)
/*
* Event types
*/
#define EV_SYN 0x00
#define EV_KEY 0x01
#define EV_REL 0x02
#define EV_ABS 0x03
#define EV_MSC 0x04
#define EV_SW 0x05
#define EV_LED 0x11
#define EV_SND 0x12
#define EV_REP 0x14
#define EV_FF 0x15
#define EV_PWR 0x16
#define EV_FF_STATUS 0x17
#define EV_MAX 0x1f
#define EV_CNT (EV_MAX+1)
/*
* Synchronization events.
*/
#define SYN_REPORT 0
#define SYN_CONFIG 1
#define SYN_MT_REPORT 2
#define SYN_DROPPED 3
#define SYN_MAX 0xf
#define SYN_CNT (SYN_MAX+1)
/*
* Keys and buttons
*
* Most of the keys/buttons are modeled after USB HUT 1.12
* (see http://www.usb.org/developers/hidpage).
* Abbreviations in the comments:
* AC - Application Control
* AL - Application Launch Button
* SC - System Control
*/
#define KEY_RESERVED 0
#define KEY_ESC 1
#define KEY_1 2
#define KEY_2 3
#define KEY_3 4
#define KEY_4 5
#define KEY_5 6
#define KEY_6 7
#define KEY_7 8
#define KEY_8 9
#define KEY_9 10
#define KEY_0 11
#define KEY_MINUS 12
#define KEY_EQUAL 13
#define KEY_BACKSPACE 14
#define KEY_TAB 15
#define KEY_Q 16
#define KEY_W 17
#define KEY_E 18
#define KEY_R 19
#define KEY_T 20
#define KEY_Y 21
#define KEY_U 22
#define KEY_I 23
#define KEY_O 24
#define KEY_P 25
#define KEY_LEFTBRACE 26
#define KEY_RIGHTBRACE 27
#define KEY_ENTER 28
#define KEY_LEFTCTRL 29
#define KEY_A 30
#define KEY_S 31
#define KEY_D 32
#define KEY_F 33
#define KEY_G 34
#define KEY_H 35
#define KEY_J 36
#define KEY_K 37
#define KEY_L 38
#define KEY_SEMICOLON 39
#define KEY_APOSTROPHE 40
#define KEY_GRAVE 41
#define KEY_LEFTSHIFT 42
#define KEY_BACKSLASH 43
#define KEY_Z 44
#define KEY_X 45
#define KEY_C 46
#define KEY_V 47
#define KEY_B 48
#define KEY_N 49
#define KEY_M 50
#define KEY_COMMA 51
#define KEY_DOT 52
#define KEY_SLASH 53
#define KEY_RIGHTSHIFT 54
#define KEY_KPASTERISK 55
#define KEY_LEFTALT 56
#define KEY_SPACE 57
#define KEY_CAPSLOCK 58
#define KEY_F1 59
#define KEY_F2 60
#define KEY_F3 61
#define KEY_F4 62
#define KEY_F5 63
#define KEY_F6 64
#define KEY_F7 65
#define KEY_F8 66
#define KEY_F9 67
#define KEY_F10 68
#define KEY_NUMLOCK 69
#define KEY_SCROLLLOCK 70
#define KEY_KP7 71
#define KEY_KP8 72
#define KEY_KP9 73
#define KEY_KPMINUS 74
#define KEY_KP4 75
#define KEY_KP5 76
#define KEY_KP6 77
#define KEY_KPPLUS 78
#define KEY_KP1 79
#define KEY_KP2 80
#define KEY_KP3 81
#define KEY_KP0 82
#define KEY_KPDOT 83
#define KEY_ZENKAKUHANKAKU 85
#define KEY_102ND 86
#define KEY_F11 87
#define KEY_F12 88
#define KEY_RO 89
#define KEY_KATAKANA 90
#define KEY_HIRAGANA 91
#define KEY_HENKAN 92
#define KEY_KATAKANAHIRAGANA 93
#define KEY_MUHENKAN 94
#define KEY_KPJPCOMMA 95
#define KEY_KPENTER 96
#define KEY_RIGHTCTRL 97
#define KEY_KPSLASH 98
#define KEY_SYSRQ 99
#define KEY_RIGHTALT 100
#define KEY_LINEFEED 101
#define KEY_HOME 102
#define KEY_UP 103
#define KEY_PAGEUP 104
#define KEY_LEFT 105
#define KEY_RIGHT 106
#define KEY_END 107
#define KEY_DOWN 108
#define KEY_PAGEDOWN 109
#define KEY_INSERT 110
#define KEY_DELETE 111
#define KEY_MACRO 112
#define KEY_MUTE 113
#define KEY_VOLUMEDOWN 114
#define KEY_VOLUMEUP 115
#define KEY_POWER 116 /* SC System Power Down */
#define KEY_KPEQUAL 117
#define KEY_KPPLUSMINUS 118
#define KEY_PAUSE 119
#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
#define KEY_KPCOMMA 121
#define KEY_HANGEUL 122
#define KEY_HANGUEL KEY_HANGEUL
#define KEY_HANJA 123
#define KEY_YEN 124
#define KEY_LEFTMETA 125
#define KEY_RIGHTMETA 126
#define KEY_COMPOSE 127
#define KEY_STOP 128 /* AC Stop */
#define KEY_AGAIN 129
#define KEY_PROPS 130 /* AC Properties */
#define KEY_UNDO 131 /* AC Undo */
#define KEY_FRONT 132
#define KEY_COPY 133 /* AC Copy */
#define KEY_OPEN 134 /* AC Open */
#define KEY_PASTE 135 /* AC Paste */
#define KEY_FIND 136 /* AC Search */
#define KEY_CUT 137 /* AC Cut */
#define KEY_HELP 138 /* AL Integrated Help Center */
#define KEY_MENU 139 /* Menu (show menu) */
#define KEY_CALC 140 /* AL Calculator */
#define KEY_SETUP 141
#define KEY_SLEEP 142 /* SC System Sleep */
#define KEY_WAKEUP 143 /* System Wake Up */
#define KEY_FILE 144 /* AL Local Machine Browser */
#define KEY_SENDFILE 145
#define KEY_DELETEFILE 146
#define KEY_XFER 147
#define KEY_PROG1 148
#define KEY_PROG2 149
#define KEY_WWW 150 /* AL Internet Browser */
#define KEY_MSDOS 151
#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
#define KEY_SCREENLOCK KEY_COFFEE
#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */
#define KEY_DIRECTION KEY_ROTATE_DISPLAY
#define KEY_CYCLEWINDOWS 154
#define KEY_MAIL 155
#define KEY_BOOKMARKS 156 /* AC Bookmarks */
#define KEY_COMPUTER 157
#define KEY_BACK 158 /* AC Back */
#define KEY_FORWARD 159 /* AC Forward */
#define KEY_CLOSECD 160
#define KEY_EJECTCD 161
#define KEY_EJECTCLOSECD 162
#define KEY_NEXTSONG 163
#define KEY_PLAYPAUSE 164
#define KEY_PREVIOUSSONG 165
#define KEY_STOPCD 166
#define KEY_RECORD 167
#define KEY_REWIND 168
#define KEY_PHONE 169 /* Media Select Telephone */
#define KEY_ISO 170
#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
#define KEY_HOMEPAGE 172 /* AC Home */
#define KEY_REFRESH 173 /* AC Refresh */
#define KEY_EXIT 174 /* AC Exit */
#define KEY_MOVE 175
#define KEY_EDIT 176
#define KEY_SCROLLUP 177
#define KEY_SCROLLDOWN 178
#define KEY_KPLEFTPAREN 179
#define KEY_KPRIGHTPAREN 180
#define KEY_NEW 181 /* AC New */
#define KEY_REDO 182 /* AC Redo/Repeat */
#define KEY_F13 183
#define KEY_F14 184
#define KEY_F15 185
#define KEY_F16 186
#define KEY_F17 187
#define KEY_F18 188
#define KEY_F19 189
#define KEY_F20 190
#define KEY_F21 191
#define KEY_F22 192
#define KEY_F23 193
#define KEY_F24 194
#define KEY_PLAYCD 200
#define KEY_PAUSECD 201
#define KEY_PROG3 202
#define KEY_PROG4 203
#define KEY_DASHBOARD 204 /* AL Dashboard */
#define KEY_SUSPEND 205
#define KEY_CLOSE 206 /* AC Close */
#define KEY_PLAY 207
#define KEY_FASTFORWARD 208
#define KEY_BASSBOOST 209
#define KEY_PRINT 210 /* AC Print */
#define KEY_HP 211
#define KEY_CAMERA 212
#define KEY_SOUND 213
#define KEY_QUESTION 214
#define KEY_EMAIL 215
#define KEY_CHAT 216
#define KEY_SEARCH 217
#define KEY_CONNECT 218
#define KEY_FINANCE 219 /* AL Checkbook/Finance */
#define KEY_SPORT 220
#define KEY_SHOP 221
#define KEY_ALTERASE 222
#define KEY_CANCEL 223 /* AC Cancel */
#define KEY_BRIGHTNESSDOWN 224
#define KEY_BRIGHTNESSUP 225
#define KEY_MEDIA 226
#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
outputs (Monitor/LCD/TV-out/etc) */
#define KEY_KBDILLUMTOGGLE 228
#define KEY_KBDILLUMDOWN 229
#define KEY_KBDILLUMUP 230
#define KEY_SEND 231 /* AC Send */
#define KEY_REPLY 232 /* AC Reply */
#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
#define KEY_SAVE 234 /* AC Save */
#define KEY_DOCUMENTS 235
#define KEY_BATTERY 236
#define KEY_BLUETOOTH 237
#define KEY_WLAN 238
#define KEY_UWB 239
#define KEY_UNKNOWN 240
#define KEY_VIDEO_NEXT 241 /* drive next video source */
#define KEY_VIDEO_PREV 242 /* drive previous video source */
#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual
brightness control is off,
rely on ambient */
#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO
#define KEY_DISPLAY_OFF 245 /* display device to off state */
#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */
#define KEY_WIMAX KEY_WWAN
#define KEY_RFKILL 247 /* Key that controls all radios */
#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
/* Code 255 is reserved for special needs of AT keyboard driver */
#define BTN_MISC 0x100
#define BTN_0 0x100
#define BTN_1 0x101
#define BTN_2 0x102
#define BTN_3 0x103
#define BTN_4 0x104
#define BTN_5 0x105
#define BTN_6 0x106
#define BTN_7 0x107
#define BTN_8 0x108
#define BTN_9 0x109
#define BTN_MOUSE 0x110
#define BTN_LEFT 0x110
#define BTN_RIGHT 0x111
#define BTN_MIDDLE 0x112
#define BTN_SIDE 0x113
#define BTN_EXTRA 0x114
#define BTN_FORWARD 0x115
#define BTN_BACK 0x116
#define BTN_TASK 0x117
#define BTN_JOYSTICK 0x120
#define BTN_TRIGGER 0x120
#define BTN_THUMB 0x121
#define BTN_THUMB2 0x122
#define BTN_TOP 0x123
#define BTN_TOP2 0x124
#define BTN_PINKIE 0x125
#define BTN_BASE 0x126
#define BTN_BASE2 0x127
#define BTN_BASE3 0x128
#define BTN_BASE4 0x129
#define BTN_BASE5 0x12a
#define BTN_BASE6 0x12b
#define BTN_DEAD 0x12f
#define BTN_GAMEPAD 0x130
#define BTN_SOUTH 0x130
#define BTN_A BTN_SOUTH
#define BTN_EAST 0x131
#define BTN_B BTN_EAST
#define BTN_C 0x132
#define BTN_NORTH 0x133
#define BTN_X BTN_NORTH
#define BTN_WEST 0x134
#define BTN_Y BTN_WEST
#define BTN_Z 0x135
#define BTN_TL 0x136
#define BTN_TR 0x137
#define BTN_TL2 0x138
#define BTN_TR2 0x139
#define BTN_SELECT 0x13a
#define BTN_START 0x13b
#define BTN_MODE 0x13c
#define BTN_THUMBL 0x13d
#define BTN_THUMBR 0x13e
#define BTN_DIGI 0x140
#define BTN_TOOL_PEN 0x140
#define BTN_TOOL_RUBBER 0x141
#define BTN_TOOL_BRUSH 0x142
#define BTN_TOOL_PENCIL 0x143
#define BTN_TOOL_AIRBRUSH 0x144
#define BTN_TOOL_FINGER 0x145
#define BTN_TOOL_MOUSE 0x146
#define BTN_TOOL_LENS 0x147
#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
#define BTN_TOUCH 0x14a
#define BTN_STYLUS 0x14b
#define BTN_STYLUS2 0x14c
#define BTN_TOOL_DOUBLETAP 0x14d
#define BTN_TOOL_TRIPLETAP 0x14e
#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
#define BTN_WHEEL 0x150
#define BTN_GEAR_DOWN 0x150
#define BTN_GEAR_UP 0x151
#define KEY_OK 0x160
#define KEY_SELECT 0x161
#define KEY_GOTO 0x162
#define KEY_CLEAR 0x163
#define KEY_POWER2 0x164
#define KEY_OPTION 0x165
#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
#define KEY_TIME 0x167
#define KEY_VENDOR 0x168
#define KEY_ARCHIVE 0x169
#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
#define KEY_CHANNEL 0x16b
#define KEY_FAVORITES 0x16c
#define KEY_EPG 0x16d
#define KEY_PVR 0x16e /* Media Select Home */
#define KEY_MHP 0x16f
#define KEY_LANGUAGE 0x170
#define KEY_TITLE 0x171
#define KEY_SUBTITLE 0x172
#define KEY_ANGLE 0x173
#define KEY_ZOOM 0x174
#define KEY_MODE 0x175
#define KEY_KEYBOARD 0x176
#define KEY_SCREEN 0x177
#define KEY_PC 0x178 /* Media Select Computer */
#define KEY_TV 0x179 /* Media Select TV */
#define KEY_TV2 0x17a /* Media Select Cable */
#define KEY_VCR 0x17b /* Media Select VCR */
#define KEY_VCR2 0x17c /* VCR Plus */
#define KEY_SAT 0x17d /* Media Select Satellite */
#define KEY_SAT2 0x17e
#define KEY_CD 0x17f /* Media Select CD */
#define KEY_TAPE 0x180 /* Media Select Tape */
#define KEY_RADIO 0x181
#define KEY_TUNER 0x182 /* Media Select Tuner */
#define KEY_PLAYER 0x183
#define KEY_TEXT 0x184
#define KEY_DVD 0x185 /* Media Select DVD */
#define KEY_AUX 0x186
#define KEY_MP3 0x187
#define KEY_AUDIO 0x188 /* AL Audio Browser */
#define KEY_VIDEO 0x189 /* AL Movie Browser */
#define KEY_DIRECTORY 0x18a
#define KEY_LIST 0x18b
#define KEY_MEMO 0x18c /* Media Select Messages */
#define KEY_CALENDAR 0x18d
#define KEY_RED 0x18e
#define KEY_GREEN 0x18f
#define KEY_YELLOW 0x190
#define KEY_BLUE 0x191
#define KEY_CHANNELUP 0x192 /* Channel Increment */
#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
#define KEY_FIRST 0x194
#define KEY_LAST 0x195 /* Recall Last */
#define KEY_AB 0x196
#define KEY_NEXT 0x197
#define KEY_RESTART 0x198
#define KEY_SLOW 0x199
#define KEY_SHUFFLE 0x19a
#define KEY_BREAK 0x19b
#define KEY_PREVIOUS 0x19c
#define KEY_DIGITS 0x19d
#define KEY_TEEN 0x19e
#define KEY_TWEN 0x19f
#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
#define KEY_GAMES 0x1a1 /* Media Select Games */
#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
#define KEY_EDITOR 0x1a6 /* AL Text Editor */
#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
#define KEY_DATABASE 0x1aa /* AL Database App */
#define KEY_NEWS 0x1ab /* AL Newsreader */
#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE
#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
#define KEY_LOGOFF 0x1b1 /* AL Logoff */
#define KEY_DOLLAR 0x1b2
#define KEY_EURO 0x1b3
#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
#define KEY_FRAMEFORWARD 0x1b5
#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
#define KEY_IMAGES 0x1ba /* AL Image Browser */
#define KEY_DEL_EOL 0x1c0
#define KEY_DEL_EOS 0x1c1
#define KEY_INS_LINE 0x1c2
#define KEY_DEL_LINE 0x1c3
#define KEY_FN 0x1d0
#define KEY_FN_ESC 0x1d1
#define KEY_FN_F1 0x1d2
#define KEY_FN_F2 0x1d3
#define KEY_FN_F3 0x1d4
#define KEY_FN_F4 0x1d5
#define KEY_FN_F5 0x1d6
#define KEY_FN_F6 0x1d7
#define KEY_FN_F7 0x1d8
#define KEY_FN_F8 0x1d9
#define KEY_FN_F9 0x1da
#define KEY_FN_F10 0x1db
#define KEY_FN_F11 0x1dc
#define KEY_FN_F12 0x1dd
#define KEY_FN_1 0x1de
#define KEY_FN_2 0x1df
#define KEY_FN_D 0x1e0
#define KEY_FN_E 0x1e1
#define KEY_FN_F 0x1e2
#define KEY_FN_S 0x1e3
#define KEY_FN_B 0x1e4
#define KEY_BRL_DOT1 0x1f1
#define KEY_BRL_DOT2 0x1f2
#define KEY_BRL_DOT3 0x1f3
#define KEY_BRL_DOT4 0x1f4
#define KEY_BRL_DOT5 0x1f5
#define KEY_BRL_DOT6 0x1f6
#define KEY_BRL_DOT7 0x1f7
#define KEY_BRL_DOT8 0x1f8
#define KEY_BRL_DOT9 0x1f9
#define KEY_BRL_DOT10 0x1fa
#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
#define KEY_NUMERIC_1 0x201 /* and other keypads */
#define KEY_NUMERIC_2 0x202
#define KEY_NUMERIC_3 0x203
#define KEY_NUMERIC_4 0x204
#define KEY_NUMERIC_5 0x205
#define KEY_NUMERIC_6 0x206
#define KEY_NUMERIC_7 0x207
#define KEY_NUMERIC_8 0x208
#define KEY_NUMERIC_9 0x209
#define KEY_NUMERIC_STAR 0x20a
#define KEY_NUMERIC_POUND 0x20b
#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */
#define KEY_NUMERIC_B 0x20d
#define KEY_NUMERIC_C 0x20e
#define KEY_NUMERIC_D 0x20f
#define KEY_CAMERA_FOCUS 0x210
#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
#define KEY_TOUCHPAD_ON 0x213
#define KEY_TOUCHPAD_OFF 0x214
#define KEY_CAMERA_ZOOMIN 0x215
#define KEY_CAMERA_ZOOMOUT 0x216
#define KEY_CAMERA_UP 0x217
#define KEY_CAMERA_DOWN 0x218
#define KEY_CAMERA_LEFT 0x219
#define KEY_CAMERA_RIGHT 0x21a
#define KEY_ATTENDANT_ON 0x21b
#define KEY_ATTENDANT_OFF 0x21c
#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
#define BTN_DPAD_UP 0x220
#define BTN_DPAD_DOWN 0x221
#define BTN_DPAD_LEFT 0x222
#define BTN_DPAD_RIGHT 0x223
#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */
#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */
#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */
#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */
#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */
#define KEY_APPSELECT 0x244 /* AL Select Task/Application */
#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */
#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */
#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */
#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */
#define KEY_KBDINPUTASSIST_PREV 0x260
#define KEY_KBDINPUTASSIST_NEXT 0x261
#define KEY_KBDINPUTASSIST_PREVGROUP 0x262
#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263
#define KEY_KBDINPUTASSIST_ACCEPT 0x264
#define KEY_KBDINPUTASSIST_CANCEL 0x265
#define BTN_TRIGGER_HAPPY 0x2c0
#define BTN_TRIGGER_HAPPY1 0x2c0
#define BTN_TRIGGER_HAPPY2 0x2c1
#define BTN_TRIGGER_HAPPY3 0x2c2
#define BTN_TRIGGER_HAPPY4 0x2c3
#define BTN_TRIGGER_HAPPY5 0x2c4
#define BTN_TRIGGER_HAPPY6 0x2c5
#define BTN_TRIGGER_HAPPY7 0x2c6
#define BTN_TRIGGER_HAPPY8 0x2c7
#define BTN_TRIGGER_HAPPY9 0x2c8
#define BTN_TRIGGER_HAPPY10 0x2c9
#define BTN_TRIGGER_HAPPY11 0x2ca
#define BTN_TRIGGER_HAPPY12 0x2cb
#define BTN_TRIGGER_HAPPY13 0x2cc
#define BTN_TRIGGER_HAPPY14 0x2cd
#define BTN_TRIGGER_HAPPY15 0x2ce
#define BTN_TRIGGER_HAPPY16 0x2cf
#define BTN_TRIGGER_HAPPY17 0x2d0
#define BTN_TRIGGER_HAPPY18 0x2d1
#define BTN_TRIGGER_HAPPY19 0x2d2
#define BTN_TRIGGER_HAPPY20 0x2d3
#define BTN_TRIGGER_HAPPY21 0x2d4
#define BTN_TRIGGER_HAPPY22 0x2d5
#define BTN_TRIGGER_HAPPY23 0x2d6
#define BTN_TRIGGER_HAPPY24 0x2d7
#define BTN_TRIGGER_HAPPY25 0x2d8
#define BTN_TRIGGER_HAPPY26 0x2d9
#define BTN_TRIGGER_HAPPY27 0x2da
#define BTN_TRIGGER_HAPPY28 0x2db
#define BTN_TRIGGER_HAPPY29 0x2dc
#define BTN_TRIGGER_HAPPY30 0x2dd
#define BTN_TRIGGER_HAPPY31 0x2de
#define BTN_TRIGGER_HAPPY32 0x2df
#define BTN_TRIGGER_HAPPY33 0x2e0
#define BTN_TRIGGER_HAPPY34 0x2e1
#define BTN_TRIGGER_HAPPY35 0x2e2
#define BTN_TRIGGER_HAPPY36 0x2e3
#define BTN_TRIGGER_HAPPY37 0x2e4
#define BTN_TRIGGER_HAPPY38 0x2e5
#define BTN_TRIGGER_HAPPY39 0x2e6
#define BTN_TRIGGER_HAPPY40 0x2e7
/* We avoid low common keys in module aliases so they don't get huge. */
#define KEY_MIN_INTERESTING KEY_MUTE
#define KEY_MAX 0x2ff
#define KEY_CNT (KEY_MAX+1)
/*
* Relative axes
*/
#define REL_X 0x00
#define REL_Y 0x01
#define REL_Z 0x02
#define REL_RX 0x03
#define REL_RY 0x04
#define REL_RZ 0x05
#define REL_HWHEEL 0x06
#define REL_DIAL 0x07
#define REL_WHEEL 0x08
#define REL_MISC 0x09
#define REL_MAX 0x0f
#define REL_CNT (REL_MAX+1)
/*
* Absolute axes
*/
#define ABS_X 0x00
#define ABS_Y 0x01
#define ABS_Z 0x02
#define ABS_RX 0x03
#define ABS_RY 0x04
#define ABS_RZ 0x05
#define ABS_THROTTLE 0x06
#define ABS_RUDDER 0x07
#define ABS_WHEEL 0x08
#define ABS_GAS 0x09
#define ABS_BRAKE 0x0a
#define ABS_HAT0X 0x10
#define ABS_HAT0Y 0x11
#define ABS_HAT1X 0x12
#define ABS_HAT1Y 0x13
#define ABS_HAT2X 0x14
#define ABS_HAT2Y 0x15
#define ABS_HAT3X 0x16
#define ABS_HAT3Y 0x17
#define ABS_PRESSURE 0x18
#define ABS_DISTANCE 0x19
#define ABS_TILT_X 0x1a
#define ABS_TILT_Y 0x1b
#define ABS_TOOL_WIDTH 0x1c
#define ABS_VOLUME 0x20
#define ABS_MISC 0x28
#define ABS_MT_SLOT 0x2f /* MT slot being modified */
#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */
#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */
#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */
#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */
#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */
#define ABS_MT_POSITION_X 0x35 /* Center X touch position */
#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */
#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */
#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */
#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */
#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */
#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */
#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */
#define ABS_MAX 0x3f
#define ABS_CNT (ABS_MAX+1)
/*
* Switch events
*/
#define SW_LID 0x00 /* set = lid shut */
#define SW_TABLET_MODE 0x01 /* set = tablet mode */
#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */
#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any"
set = radio enabled */
#define SW_RADIO SW_RFKILL_ALL /* deprecated */
#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */
#define SW_DOCK 0x05 /* set = plugged into dock */
#define SW_LINEOUT_INSERT 0x06 /* set = inserted */
#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */
#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */
#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */
#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */
#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */
#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */
#define SW_LINEIN_INSERT 0x0d /* set = inserted */
#define SW_MUTE_DEVICE 0x0e /* set = device disabled */
#define SW_MAX 0x0f
#define SW_CNT (SW_MAX+1)
/*
* Misc events
*/
#define MSC_SERIAL 0x00
#define MSC_PULSELED 0x01
#define MSC_GESTURE 0x02
#define MSC_RAW 0x03
#define MSC_SCAN 0x04
#define MSC_TIMESTAMP 0x05
#define MSC_MAX 0x07
#define MSC_CNT (MSC_MAX+1)
/*
* LEDs
*/
#define LED_NUML 0x00
#define LED_CAPSL 0x01
#define LED_SCROLLL 0x02
#define LED_COMPOSE 0x03
#define LED_KANA 0x04
#define LED_SLEEP 0x05
#define LED_SUSPEND 0x06
#define LED_MUTE 0x07
#define LED_MISC 0x08
#define LED_MAIL 0x09
#define LED_CHARGING 0x0a
#define LED_MAX 0x0f
#define LED_CNT (LED_MAX+1)
/*
* Autorepeat values
*/
#define REP_DELAY 0x00
#define REP_PERIOD 0x01
#define REP_MAX 0x01
#define REP_CNT (REP_MAX+1)
/*
* Sounds
*/
#define SND_CLICK 0x00
#define SND_BELL 0x01
#define SND_TONE 0x02
#define SND_MAX 0x07
#define SND_CNT (SND_MAX+1)
#define MATRIX_KEY(row, col, code) \
((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
#endif /* _DT_BINDINGS_INPUT_INPUT_H */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/interrupt-controller/irq.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for most IRQ bindings.
*
* Most IRQ bindings include a flags cell as part of the IRQ specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISING 1
#define IRQ_TYPE_EDGE_FALLING 2
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/net/mscc-phy-vsc8531.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Device Tree constants for Microsemi VSC8531 PHY
*
* Author: Nagaraju Lakkaraju
*
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _DT_BINDINGS_MSCC_VSC8531_H
#define _DT_BINDINGS_MSCC_VSC8531_H
/* PHY LED Modes */
#define VSC8531_LINK_ACTIVITY 0
#define VSC8531_LINK_1000_ACTIVITY 1
#define VSC8531_LINK_100_ACTIVITY 2
#define VSC8531_LINK_10_ACTIVITY 3
#define VSC8531_LINK_100_1000_ACTIVITY 4
#define VSC8531_LINK_10_1000_ACTIVITY 5
#define VSC8531_LINK_10_100_ACTIVITY 6
#define VSC8584_LINK_100FX_1000X_ACTIVITY 7
#define VSC8531_DUPLEX_COLLISION 8
#define VSC8531_COLLISION 9
#define VSC8531_ACTIVITY 10
#define VSC8584_100FX_1000X_ACTIVITY 11
#define VSC8531_AUTONEG_FAULT 12
#define VSC8531_SERIAL_MODE 13
#define VSC8531_FORCE_LED_OFF 14
#define VSC8531_FORCE_LED_ON 15
#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0
#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1
#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2
#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3
#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4
#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5
#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6
#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/net/ti-dp83867.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Device Tree constants for the Texas Instruments DP83867 PHY
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* Copyright: (C) 2015 Texas Instruments, Inc.
*/
#ifndef _DT_BINDINGS_TI_DP83867_H
#define _DT_BINDINGS_TI_DP83867_H
/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
/* RGMIIDCTL internal delay for rx and tx */
#define DP83867_RGMIIDCTL_250_PS 0x0
#define DP83867_RGMIIDCTL_500_PS 0x1
#define DP83867_RGMIIDCTL_750_PS 0x2
#define DP83867_RGMIIDCTL_1_NS 0x3
#define DP83867_RGMIIDCTL_1_25_NS 0x4
#define DP83867_RGMIIDCTL_1_50_NS 0x5
#define DP83867_RGMIIDCTL_1_75_NS 0x6
#define DP83867_RGMIIDCTL_2_00_NS 0x7
#define DP83867_RGMIIDCTL_2_25_NS 0x8
#define DP83867_RGMIIDCTL_2_50_NS 0x9
#define DP83867_RGMIIDCTL_2_75_NS 0xa
#define DP83867_RGMIIDCTL_3_00_NS 0xb
#define DP83867_RGMIIDCTL_3_25_NS 0xc
#define DP83867_RGMIIDCTL_3_50_NS 0xd
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
/* IO_MUX_CFG - Clock output selection */
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
#define DP83867_CLK_O_SEL_REF_CLK 0xC
/* Special flag to indicate clock should be off */
#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/phy/phy.h
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/*
*
* This header provides constants for the phy framework
*
* Copyright (C) 2014 STMicroelectronics
* Author: Gabriel Fernandez <gabriel.fernandez@st.com>
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef _DT_BINDINGS_PHY
#define _DT_BINDINGS_PHY
#define PHY_NONE 0
#define PHY_TYPE_SATA 1
#define PHY_TYPE_PCIE 2
#define PHY_TYPE_USB2 3
#define PHY_TYPE_USB3 4
#define PHY_TYPE_UFS 5
#define PHY_TYPE_DP 6
#define PHY_TYPE_XPCS 7
#define PHY_TYPE_SGMII 8
#define PHY_TYPE_QSGMII 9
#endif /* _DT_BINDINGS_PHY */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* MIO pin configuration defines for Xilinx ZynqMP
*
* Copyright (C) 2020-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
/* Bit value for different voltage levels */
#define IO_STANDARD_LVCMOS33 0
#define IO_STANDARD_LVCMOS18 1
/* Bit values for Slew Rates */
#define SLEW_RATE_FAST 0
#define SLEW_RATE_SLOW 1
/* Bit values for Pin drive strength */
#define DRIVE_STRENGTH_2MA 2
#define DRIVE_STRENGTH_4MA 4
#define DRIVE_STRENGTH_8MA 8
#define DRIVE_STRENGTH_12MA 12
#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-versal-net-power.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_NET_POWER_H
#define _DT_BINDINGS_VERSAL_NET_POWER_H
#include "xlnx-versal-power.h"
#define PM_DEV_USB_1 (0x182240D7U)
#define PM_DEV_FPD_SWDT_0 (0x182240DBU)
#define PM_DEV_FPD_SWDT_1 (0x182240DCU)
#define PM_DEV_FPD_SWDT_2 (0x182240DDU)
#define PM_DEV_FPD_SWDT_3 (0x182240DEU)
/* Remove Versal specific node IDs */
#undef PM_DEV_RPU0_0
#undef PM_DEV_RPU0_1
#undef PM_DEV_OCM_0
#undef PM_DEV_OCM_1
#undef PM_DEV_OCM_2
#undef PM_DEV_OCM_3
#undef PM_DEV_TCM_0_A
#undef PM_DEV_TCM_1_A
#undef PM_DEV_TCM_0_B
#undef PM_DEV_TCM_1_B
#undef PM_DEV_SWDT_FPD
#undef PM_DEV_AI
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-versal-power.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_POWER_H
#define _DT_BINDINGS_VERSAL_POWER_H
#define PM_DEV_RPU0_0 (0x18110005U)
#define PM_DEV_RPU0_1 (0x18110006U)
#define PM_DEV_OCM_0 (0x18314007U)
#define PM_DEV_OCM_1 (0x18314008U)
#define PM_DEV_OCM_2 (0x18314009U)
#define PM_DEV_OCM_3 (0x1831400aU)
#define PM_DEV_TCM_0_A (0x1831800bU)
#define PM_DEV_TCM_0_B (0x1831800cU)
#define PM_DEV_TCM_1_A (0x1831800dU)
#define PM_DEV_TCM_1_B (0x1831800eU)
#define PM_DEV_USB_0 (0x18224018U)
#define PM_DEV_GEM_0 (0x18224019U)
#define PM_DEV_GEM_1 (0x1822401aU)
#define PM_DEV_SPI_0 (0x1822401bU)
#define PM_DEV_SPI_1 (0x1822401cU)
#define PM_DEV_I2C_0 (0x1822401dU)
#define PM_DEV_I2C_1 (0x1822401eU)
#define PM_DEV_I2C_PMC (0x1822402dU)
#define PM_DEV_CAN_FD_0 (0x1822401fU)
#define PM_DEV_CAN_FD_1 (0x18224020U)
#define PM_DEV_UART_0 (0x18224021U)
#define PM_DEV_UART_1 (0x18224022U)
#define PM_DEV_GPIO (0x18224023U)
#define PM_DEV_TTC_0 (0x18224024U)
#define PM_DEV_TTC_1 (0x18224025U)
#define PM_DEV_TTC_2 (0x18224026U)
#define PM_DEV_TTC_3 (0x18224027U)
#define PM_DEV_SWDT_FPD (0x18224029U)
#define PM_DEV_OSPI (0x1822402aU)
#define PM_DEV_QSPI (0x1822402bU)
#define PM_DEV_GPIO_PMC (0x1822402cU)
#define PM_DEV_SDIO_0 (0x1822402eU)
#define PM_DEV_SDIO_1 (0x1822402fU)
#define PM_DEV_RTC (0x18224034U)
#define PM_DEV_ADMA_0 (0x18224035U)
#define PM_DEV_ADMA_1 (0x18224036U)
#define PM_DEV_ADMA_2 (0x18224037U)
#define PM_DEV_ADMA_3 (0x18224038U)
#define PM_DEV_ADMA_4 (0x18224039U)
#define PM_DEV_ADMA_5 (0x1822403aU)
#define PM_DEV_ADMA_6 (0x1822403bU)
#define PM_DEV_ADMA_7 (0x1822403cU)
#define PM_DEV_AI (0x18224072U)
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-versal-regnode.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_REGNODE_H
#define _DT_BINDINGS_VERSAL_REGNODE_H
#define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U)
#define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U)
#define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U)
#define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U)
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/power/xlnx-zynqmp-power.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
#define _DT_BINDINGS_ZYNQMP_POWER_H
#define PD_RPU 6
#define PD_RPU_0 7
#define PD_RPU_1 8
#define PD_OCM_0 11
#define PD_OCM_1 12
#define PD_OCM_2 13
#define PD_OCM_3 14
#define PD_TCM_0_A 15
#define PD_TCM_0_B 16
#define PD_TCM_1_A 17
#define PD_TCM_1_B 18
#define PD_USB_0 22
#define PD_USB_1 23
#define PD_TTC_0 24
#define PD_TTC_1 25
#define PD_TTC_2 26
#define PD_TTC_3 27
#define PD_SATA 28
#define PD_ETH_0 29
#define PD_ETH_1 30
#define PD_ETH_2 31
#define PD_ETH_3 32
#define PD_UART_0 33
#define PD_UART_1 34
#define PD_SPI_0 35
#define PD_SPI_1 36
#define PD_I2C_0 37
#define PD_I2C_1 38
#define PD_SD_0 39
#define PD_SD_1 40
#define PD_DP 41
#define PD_GDMA 42
#define PD_ADMA 43
#define PD_NAND 44
#define PD_QSPI 45
#define PD_GPIO 46
#define PD_CAN_0 47
#define PD_CAN_1 48
#define PD_GPU 58
#define PD_PCIE 59
#define PD_PL 69
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/reset/xlnx-versal-net-resets.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H
#define _DT_BINDINGS_VERSAL_NET_RESETS_H
#include "xlnx-versal-resets.h"
#define VERSAL_RST_USB_1 (0xC1040C6U)
/* Remove Versal specific reset IDs */
#undef VERSAL_RST_ACPU_0_POR
#undef VERSAL_RST_ACPU_1_POR
#undef VERSAL_RST_OCM2_POR
#undef VERSAL_RST_APU
#undef VERSAL_RST_ACPU_0
#undef VERSAL_RST_ACPU_1
#undef VERSAL_RST_ACPU_L2
#undef VERSAL_RST_RPU_ISLAND
#undef VERSAL_RST_RPU_AMBA
#undef VERSAL_RST_R5_0
#undef VERSAL_RST_R5_1
#undef VERSAL_RST_OCM2_RST
#undef VERSAL_RST_I2C_PMC
#undef VERSAL_RST_I2C_0
#undef VERSAL_RST_I2C_1
#undef VERSAL_RST_SWDT_FPD
#undef VERSAL_RST_SWDT_LPD
#undef VERSAL_RST_USB
#undef VERSAL_RST_DPC
#undef VERSAL_RST_DBG_TRACE
#undef VERSAL_RST_DBG_TSTMP
#undef VERSAL_RST_RPU0_DBG
#undef VERSAL_RST_RPU1_DBG
#undef VERSAL_RST_HSDP
#undef VERSAL_RST_CPMDBG
#undef VERSAL_RST_PCIE_CFG
#undef VERSAL_RST_PCIE_CORE0
#undef VERSAL_RST_PCIE_CORE1
#undef VERSAL_RST_PCIE_DMA
#undef VERSAL_RST_L2_0
#undef VERSAL_RST_L2_1
#undef VERSAL_RST_ADDR_REMAP
#undef VERSAL_RST_CPI0
#undef VERSAL_RST_CPI1
#undef VERSAL_RST_XRAM
#undef VERSAL_RST_AIE_ARRAY
#undef VERSAL_RST_AIE_SHIM
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/reset/xlnx-versal-resets.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_VERSAL_RESETS_H
#define _DT_BINDINGS_VERSAL_RESETS_H
#define VERSAL_RST_PMC_POR (0xc30c001U)
#define VERSAL_RST_PMC (0xc410002U)
#define VERSAL_RST_PS_POR (0xc30c003U)
#define VERSAL_RST_PL_POR (0xc30c004U)
#define VERSAL_RST_NOC_POR (0xc30c005U)
#define VERSAL_RST_FPD_POR (0xc30c006U)
#define VERSAL_RST_ACPU_0_POR (0xc30c007U)
#define VERSAL_RST_ACPU_1_POR (0xc30c008U)
#define VERSAL_RST_OCM2_POR (0xc30c009U)
#define VERSAL_RST_PS_SRST (0xc41000aU)
#define VERSAL_RST_PL_SRST (0xc41000bU)
#define VERSAL_RST_NOC (0xc41000cU)
#define VERSAL_RST_NPI (0xc41000dU)
#define VERSAL_RST_SYS_RST_1 (0xc41000eU)
#define VERSAL_RST_SYS_RST_2 (0xc41000fU)
#define VERSAL_RST_SYS_RST_3 (0xc410010U)
#define VERSAL_RST_FPD (0xc410011U)
#define VERSAL_RST_PL0 (0xc410012U)
#define VERSAL_RST_PL1 (0xc410013U)
#define VERSAL_RST_PL2 (0xc410014U)
#define VERSAL_RST_PL3 (0xc410015U)
#define VERSAL_RST_APU (0xc410016U)
#define VERSAL_RST_ACPU_0 (0xc410017U)
#define VERSAL_RST_ACPU_1 (0xc410018U)
#define VERSAL_RST_ACPU_L2 (0xc410019U)
#define VERSAL_RST_ACPU_GIC (0xc41001aU)
#define VERSAL_RST_RPU_ISLAND (0xc41001bU)
#define VERSAL_RST_RPU_AMBA (0xc41001cU)
#define VERSAL_RST_R5_0 (0xc41001dU)
#define VERSAL_RST_R5_1 (0xc41001eU)
#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU)
#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U)
#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U)
#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U)
#define VERSAL_RST_SYSMON_LPD (0xc410023U)
#define VERSAL_RST_PDMA_RST1 (0xc410024U)
#define VERSAL_RST_PDMA_RST0 (0xc410025U)
#define VERSAL_RST_ADMA (0xc410026U)
#define VERSAL_RST_TIMESTAMP (0xc410027U)
#define VERSAL_RST_OCM (0xc410028U)
#define VERSAL_RST_OCM2_RST (0xc410029U)
#define VERSAL_RST_IPI (0xc41002aU)
#define VERSAL_RST_SBI (0xc41002bU)
#define VERSAL_RST_LPD (0xc41002cU)
#define VERSAL_RST_QSPI (0xc10402dU)
#define VERSAL_RST_OSPI (0xc10402eU)
#define VERSAL_RST_SDIO_0 (0xc10402fU)
#define VERSAL_RST_SDIO_1 (0xc104030U)
#define VERSAL_RST_I2C_PMC (0xc104031U)
#define VERSAL_RST_GPIO_PMC (0xc104032U)
#define VERSAL_RST_GEM_0 (0xc104033U)
#define VERSAL_RST_GEM_1 (0xc104034U)
#define VERSAL_RST_SPARE (0xc104035U)
#define VERSAL_RST_USB_0 (0xc104036U)
#define VERSAL_RST_UART_0 (0xc104037U)
#define VERSAL_RST_UART_1 (0xc104038U)
#define VERSAL_RST_SPI_0 (0xc104039U)
#define VERSAL_RST_SPI_1 (0xc10403aU)
#define VERSAL_RST_CAN_FD_0 (0xc10403bU)
#define VERSAL_RST_CAN_FD_1 (0xc10403cU)
#define VERSAL_RST_I2C_0 (0xc10403dU)
#define VERSAL_RST_I2C_1 (0xc10403eU)
#define VERSAL_RST_GPIO_LPD (0xc10403fU)
#define VERSAL_RST_TTC_0 (0xc104040U)
#define VERSAL_RST_TTC_1 (0xc104041U)
#define VERSAL_RST_TTC_2 (0xc104042U)
#define VERSAL_RST_TTC_3 (0xc104043U)
#define VERSAL_RST_SWDT_FPD (0xc104044U)
#define VERSAL_RST_SWDT_LPD (0xc104045U)
#define VERSAL_RST_USB (0xc104046U)
#define VERSAL_RST_DPC (0xc208047U)
#define VERSAL_RST_PMCDBG (0xc208048U)
#define VERSAL_RST_DBG_TRACE (0xc208049U)
#define VERSAL_RST_DBG_FPD (0xc20804aU)
#define VERSAL_RST_DBG_TSTMP (0xc20804bU)
#define VERSAL_RST_RPU0_DBG (0xc20804cU)
#define VERSAL_RST_RPU1_DBG (0xc20804dU)
#define VERSAL_RST_HSDP (0xc20804eU)
#define VERSAL_RST_DBG_LPD (0xc20804fU)
#define VERSAL_RST_CPM_POR (0xc30c050U)
#define VERSAL_RST_CPM (0xc410051U)
#define VERSAL_RST_CPMDBG (0xc208052U)
#define VERSAL_RST_PCIE_CFG (0xc410053U)
#define VERSAL_RST_PCIE_CORE0 (0xc410054U)
#define VERSAL_RST_PCIE_CORE1 (0xc410055U)
#define VERSAL_RST_PCIE_DMA (0xc410056U)
#define VERSAL_RST_CMN (0xc410057U)
#define VERSAL_RST_L2_0 (0xc410058U)
#define VERSAL_RST_L2_1 (0xc410059U)
#define VERSAL_RST_ADDR_REMAP (0xc41005aU)
#define VERSAL_RST_CPI0 (0xc41005bU)
#define VERSAL_RST_CPI1 (0xc41005cU)
#define VERSAL_RST_XRAM (0xc30c05dU)
#define VERSAL_RST_AIE_ARRAY (0xc10405eU)
#define VERSAL_RST_AIE_SHIM (0xc10405fU)
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/include/dt-bindings/reset/xlnx-zynqmp-resets.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*/
#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
#define _DT_BINDINGS_ZYNQMP_RESETS_H
#define ZYNQMP_RESET_PCIE_CFG 0
#define ZYNQMP_RESET_PCIE_BRIDGE 1
#define ZYNQMP_RESET_PCIE_CTRL 2
#define ZYNQMP_RESET_DP 3
#define ZYNQMP_RESET_SWDT_CRF 4
#define ZYNQMP_RESET_AFI_FM5 5
#define ZYNQMP_RESET_AFI_FM4 6
#define ZYNQMP_RESET_AFI_FM3 7
#define ZYNQMP_RESET_AFI_FM2 8
#define ZYNQMP_RESET_AFI_FM1 9
#define ZYNQMP_RESET_AFI_FM0 10
#define ZYNQMP_RESET_GDMA 11
#define ZYNQMP_RESET_GPU_PP1 12
#define ZYNQMP_RESET_GPU_PP0 13
#define ZYNQMP_RESET_GPU 14
#define ZYNQMP_RESET_GT 15
#define ZYNQMP_RESET_SATA 16
#define ZYNQMP_RESET_ACPU3_PWRON 17
#define ZYNQMP_RESET_ACPU2_PWRON 18
#define ZYNQMP_RESET_ACPU1_PWRON 19
#define ZYNQMP_RESET_ACPU0_PWRON 20
#define ZYNQMP_RESET_APU_L2 21
#define ZYNQMP_RESET_ACPU3 22
#define ZYNQMP_RESET_ACPU2 23
#define ZYNQMP_RESET_ACPU1 24
#define ZYNQMP_RESET_ACPU0 25
#define ZYNQMP_RESET_DDR 26
#define ZYNQMP_RESET_APM_FPD 27
#define ZYNQMP_RESET_SOFT 28
#define ZYNQMP_RESET_GEM0 29
#define ZYNQMP_RESET_GEM1 30
#define ZYNQMP_RESET_GEM2 31
#define ZYNQMP_RESET_GEM3 32
#define ZYNQMP_RESET_QSPI 33
#define ZYNQMP_RESET_UART0 34
#define ZYNQMP_RESET_UART1 35
#define ZYNQMP_RESET_SPI0 36
#define ZYNQMP_RESET_SPI1 37
#define ZYNQMP_RESET_SDIO0 38
#define ZYNQMP_RESET_SDIO1 39
#define ZYNQMP_RESET_CAN0 40
#define ZYNQMP_RESET_CAN1 41
#define ZYNQMP_RESET_I2C0 42
#define ZYNQMP_RESET_I2C1 43
#define ZYNQMP_RESET_TTC0 44
#define ZYNQMP_RESET_TTC1 45
#define ZYNQMP_RESET_TTC2 46
#define ZYNQMP_RESET_TTC3 47
#define ZYNQMP_RESET_SWDT_CRL 48
#define ZYNQMP_RESET_NAND 49
#define ZYNQMP_RESET_ADMA 50
#define ZYNQMP_RESET_GPIO 51
#define ZYNQMP_RESET_IOU_CC 52
#define ZYNQMP_RESET_TIMESTAMP 53
#define ZYNQMP_RESET_RPU_R50 54
#define ZYNQMP_RESET_RPU_R51 55
#define ZYNQMP_RESET_RPU_AMBA 56
#define ZYNQMP_RESET_OCM 57
#define ZYNQMP_RESET_RPU_PGE 58
#define ZYNQMP_RESET_USB0_CORERESET 59
#define ZYNQMP_RESET_USB1_CORERESET 60
#define ZYNQMP_RESET_USB0_HIBERRESET 61
#define ZYNQMP_RESET_USB1_HIBERRESET 62
#define ZYNQMP_RESET_USB0_APB 63
#define ZYNQMP_RESET_USB1_APB 64
#define ZYNQMP_RESET_IPI 65
#define ZYNQMP_RESET_APM_LPD 66
#define ZYNQMP_RESET_RTC 67
#define ZYNQMP_RESET_SYSMON 68
#define ZYNQMP_RESET_AFI_FM6 69
#define ZYNQMP_RESET_LPD_SWDT 70
#define ZYNQMP_RESET_FPD 71
#define ZYNQMP_RESET_RPU_DBG1 72
#define ZYNQMP_RESET_RPU_DBG0 73
#define ZYNQMP_RESET_DBG_LPD 74
#define ZYNQMP_RESET_DBG_FPD 75
#define ZYNQMP_RESET_APLL 76
#define ZYNQMP_RESET_DPLL 77
#define ZYNQMP_RESET_VPLL 78
#define ZYNQMP_RESET_IOPLL 79
#define ZYNQMP_RESET_RPLL 80
#define ZYNQMP_RESET_GPO3_PL_0 81
#define ZYNQMP_RESET_GPO3_PL_1 82
#define ZYNQMP_RESET_GPO3_PL_2 83
#define ZYNQMP_RESET_GPO3_PL_3 84
#define ZYNQMP_RESET_GPO3_PL_4 85
#define ZYNQMP_RESET_GPO3_PL_5 86
#define ZYNQMP_RESET_GPO3_PL_6 87
#define ZYNQMP_RESET_GPO3_PL_7 88
#define ZYNQMP_RESET_GPO3_PL_8 89
#define ZYNQMP_RESET_GPO3_PL_9 90
#define ZYNQMP_RESET_GPO3_PL_10 91
#define ZYNQMP_RESET_GPO3_PL_11 92
#define ZYNQMP_RESET_GPO3_PL_12 93
#define ZYNQMP_RESET_GPO3_PL_13 94
#define ZYNQMP_RESET_GPO3_PL_14 95
#define ZYNQMP_RESET_GPO3_PL_15 96
#define ZYNQMP_RESET_GPO3_PL_16 97
#define ZYNQMP_RESET_GPO3_PL_17 98
#define ZYNQMP_RESET_GPO3_PL_18 99
#define ZYNQMP_RESET_GPO3_PL_19 100
#define ZYNQMP_RESET_GPO3_PL_20 101
#define ZYNQMP_RESET_GPO3_PL_21 102
#define ZYNQMP_RESET_GPO3_PL_22 103
#define ZYNQMP_RESET_GPO3_PL_23 104
#define ZYNQMP_RESET_GPO3_PL_24 105
#define ZYNQMP_RESET_GPO3_PL_25 106
#define ZYNQMP_RESET_GPO3_PL_26 107
#define ZYNQMP_RESET_GPO3_PL_27 108
#define ZYNQMP_RESET_GPO3_PL_28 109
#define ZYNQMP_RESET_GPO3_PL_29 110
#define ZYNQMP_RESET_GPO3_PL_30 111
#define ZYNQMP_RESET_GPO3_PL_31 112
#define ZYNQMP_RESET_RPU_LS 113
#define ZYNQMP_RESET_PS_ONLY 114
#define ZYNQMP_RESET_PL 115
#define ZYNQMP_RESET_PS_PL0 116
#define ZYNQMP_RESET_PS_PL1 117
#define ZYNQMP_RESET_PS_PL2 118
#define ZYNQMP_RESET_PS_PL3 119
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/pcw.dtsi
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&ps7_cortexa9_0 {
xlnx,rable = <0>;
xlnx,i-cache-size = <0x8000>;
xlnx,d-cache-line-size = <20>;
xlnx,i-cache-line-size = <20>;
xlnx,cpu-1x-clk-freq-hz = <111111115>;
xlnx,ip-name = "ps7_cortexa9";
xlnx,num-cores = <2>;
xlnx,d-cache-size = <0x8000>;
xlnx,cpu-clk-freq-hz = <666666687>;
bus-handle = <&amba>;
};
&ps7_cortexa9_1 {
xlnx,rable = <0>;
xlnx,i-cache-size = <0x8000>;
xlnx,d-cache-line-size = <20>;
xlnx,i-cache-line-size = <20>;
xlnx,cpu-1x-clk-freq-hz = <111111115>;
xlnx,ip-name = "ps7_cortexa9";
xlnx,d-cache-size = <0x8000>;
xlnx,cpu-clk-freq-hz = <666666687>;
bus-handle = <&amba>;
};
&amba {
ps7_pmu_0: ps7_pmu@f8891000 {
xlnx,rable = <0>;
xlnx,pmu1-s-axi-highaddr = <0xF8893FFF>;
compatible = "xlnx,ps7-pmu-1.00.a";
status = "okay";
xlnx,ip-name = "ps7_pmu";
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
xlnx,pmu1-s-axi-baseaddr = <0xF8893000>;
xlnx,name = "ps7_pmu_0";
};
ps7_qspi_linear_0: ps7_qspi_linear@fc000000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-qspi-linear-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_qspi_linear";
reg = <0xfc000000 0x1000000>;
xlnx,name = "ps7_qspi_linear_0";
};
ps7_ddr_0: ps7_ddr@100000 {
compatible = "xlnx,ps7-ddr-1.00.a";
xlnx,s-axi-hp1-baseaddr = <0x0fffffff>;
xlnx,s-axi-hp3-baseaddr = <0x0fffffff>;
xlnx,rable = <0>;
xlnx,ip-name = "ps7_ddr";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
reg = <0x00100000 0x3ff00000>;
xlnx,s-axi-hp1-highaddr = <0x0fffffff>;
xlnx,s-axi-hp3-highaddr = <0x0fffffff>;
xlnx,s-axi-hp0-baseaddr = <0x0fffffff>;
xlnx,s-axi-hp2-baseaddr = <0x0fffffff>;
status = "okay";
xlnx,s-axi-hp0-highaddr = <0x0fffffff>;
xlnx,s-axi-hp2-highaddr = <0x0fffffff>;
xlnx,name = "ps7_ddr_0";
};
ps7_ocmc_0: ps7_ocmc@f800c000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-ocmc-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ocmc";
reg = <0xf800c000 0x1000>;
xlnx,name = "ps7_ocmc_0";
};
ps7_gpv_0: ps7_gpv@f8900000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-gpv-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_gpv";
reg = <0xf8900000 0x100000>;
xlnx,name = "ps7_gpv_0";
};
ps7_scuc_0: ps7_scuc@f8f00000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-scuc-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_scuc";
reg = <0xf8f00000 0xfd>;
xlnx,name = "ps7_scuc_0";
};
ps7_iop_bus_config_0: ps7_iop_bus_config@e0200000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-iop-bus-config-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_iop_bus_config";
reg = <0xe0200000 0x1000>;
xlnx,name = "ps7_iop_bus_config_0";
};
ps7_ram_0: ps7_ram@0 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-ram-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ram";
reg = <0x00000000 0x30000>;
xlnx,name = "ps7_ram_0";
};
ps7_ram_1: ps7_ram@ffff0000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-ram-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ram";
reg = <0xffff0000 0xfe00>;
xlnx,name = "ps7_ram_1";
};
ps7_dma_ns: ps7_dma@f8004000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-dma-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_dma";
xlnx,is-secure;
reg = <0xf8004000 0x1000>;
xlnx,name = "ps7_dma_ns";
};
ps7_afi_0: ps7_afi@f8008000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf8008000 0x1000>;
xlnx,name = "ps7_afi_0";
};
ps7_afi_1: ps7_afi@f8009000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf8009000 0x1000>;
xlnx,name = "ps7_afi_1";
};
ps7_afi_2: ps7_afi@f800a000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf800a000 0x1000>;
xlnx,name = "ps7_afi_2";
};
ps7_afi_3: ps7_afi@f800b000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-afi-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_afi";
reg = <0xf800b000 0x1000>;
xlnx,name = "ps7_afi_3";
};
ps7_m_axi_gp0: ps7_m_axi_gp@40000000 {
xlnx,rable = <0>;
compatible = "xlnx,ps7-m-axi-gp-1.00.a";
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_m_axi_gp";
reg = <0x40000000 0x40000000>;
xlnx,name = "ps7_m_axi_gp0";
};
};
&uart1 {
xlnx,rable = <0>;
status = "okay";
xlnx,clock-freq = <100000000>;
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,has-modem = <0>;
xlnx,ip-name = "ps7_uart";
cts-override;
port-number = <0>;
xlnx,uart-clk-freq-hz = <100000000>;
xlnx,name = "ps7_uart_1";
};
&qspi {
xlnx,qspi-clk-freq-hz = <142857132>;
xlnx,rable = <0>;
xlnx,bus-width = <2>;
xlnx,ip-name = "ps7_qspi";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
spi-rx-bus-width = <4>;
xlnx,connection-mode = <0>;
spi-tx-bus-width = <4>;
status = "okay";
qspi-fbclk = <0>;
xlnx,clock-freq = <142857132>;
xlnx,fb-clk = <1>;
xlnx,qspi-mode = <0>;
xlnx,name = "ps7_qspi_0";
xlnx,qspi-bus-width = <2>;
is-dual = <0>;
};
&gem0 {
xlnx,has-mdio = <1>;
phy-mode = "rgmii-id";
xlnx,enet-slcr-1000mbps-div0 = <8>;
xlnx,enet-slcr-10mbps-div0 = <8>;
xlnx,rable = <0>;
xlnx,enet-slcr-1000mbps-div1 = <1>;
xlnx,enet-slcr-10mbps-div1 = <50>;
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_ethernet";
xlnx,eth-mode = <1>;
xlnx,enet-clk-freq-hz = <125000000>;
xlnx,enet-slcr-100mbps-div0 = <8>;
xlnx,ptp-enet-clock = <0x69f6bcb>;
local-mac-address = [ 00 0a 23 00 00 00 ];
status = "okay";
xlnx,enet-slcr-100mbps-div1 = <5>;
xlnx,name = "ps7_ethernet_0";
};
&sdhci0 {
xlnx,rable = <0>;
xlnx,has-power = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_sdio";
xlnx,sdio-clk-freq-hz = <50000000>;
xlnx,has-wp = <1>;
xlnx,has-cd = <1>;
xlnx,name = "ps7_sd_0";
};
&gpio0 {
xlnx,rable = <0>;
xlnx,mio-gpio-mask = <0x5600>;
status = "okay";
gpio-mask-high = <0>;
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,emio-gpio-width = <33>;
xlnx,ip-name = "ps7_gpio";
gpio-mask-low = <22016>;
emio-gpio-width = <0x21>;
xlnx,name = "ps7_gpio_0";
};
&mc {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ddr-clk-freq-hz = <533333374>;
xlnx,ip-name = "ps7_ddrc";
xlnx,has-ecc = <0>;
xlnx,name = "ps7_ddrc_0";
};
&devcfg {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_dev_cfg";
xlnx,name = "ps7_dev_cfg_0";
};
&adc {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_xadc";
xlnx,name = "ps7_xadc_0";
};
&coresight {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_coresight_comp";
xlnx,name = "ps7_coresight_comp_0";
};
&global_timer {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_globaltimer";
xlnx,name = "ps7_globaltimer_0";
};
&L2 {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_pl310";
xlnx,name = "ps7_pl310_0";
};
&dmac_s {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_dma";
xlnx,is-secure;
xlnx,name = "ps7_dma_s";
};
&intc {
xlnx,rable = <0>;
status = "okay";
xlnx,ppi-s-axi-baseaddr = <0xF8F01000>;
xlnx,irq-f2p-mode = "DIRECT";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_intc_dist";
xlnx,ppi-s-axi-highaddr = <0xF8F01FFF>;
xlnx,name = "ps7_intc_dist_0";
};
&scutimer {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_scutimer";
xlnx,name = "ps7_scutimer_0";
};
&scuwdt {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_scuwdt";
xlnx,name = "ps7_scuwdt_0";
};
&slcr {
xlnx,rable = <0>;
status = "okay";
xlnx,interconnect-s-axi-masters = "ps7_cortexa9_0.M_AXI_DP , & , ps7_cortexa9_1.M_AXI_DP";
xlnx,ip-name = "ps7_slcr";
xlnx,name = "ps7_slcr_0";
};
&clkc {
fclk-enable = <0x1>;
ps-clk-frequency = <33333333>;
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/pl.dtsi
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/ {
amba_pl: amba_pl {
ranges;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
mydna_read_v1_0_0: mydna_read_v1_0@43c00000 {
xlnx,s00-axi-data-width = <32>;
xlnx,rable = <0>;
compatible = "xlnx,mydna-read-v1-0-1.0";
status = "okay";
clock-names = "s00_axi_aclk";
xlnx,s00-axi-addr-width = <4>;
xlnx,ip-name = "mydna_read_v1_0";
xlnx,edk-iptype = "PERIPHERAL";
reg = <0x43c00000 0x10000>;
clocks = <&clkc 15>;
xlnx,name = "mydna_read_v1_0_0";
};
};
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/ps7_init.c
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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/ps7_init.h
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/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.c
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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.h
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/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/skeleton.dtsi
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/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value. The bootloader will typically populate the memory
* node.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
memory { device_type = "memory"; reg = <0 0>; };
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/system-top.dts
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/dts-v1/;
#include "zynq-7000.dtsi"
#include "pl.dtsi"
#include "pcw.dtsi"
/ {
device_id = "7z035";
slrcount = <1>;
ps7_ddr_0_memory: memory@00100000 {
compatible = "xlnx,ps7-ddr-1.00.a";
device_type = "memory";
reg = <0x00100000 0x3ff00000>;
};
ps7_ram_0_memory: memory@0 {
compatible = "xlnx,ps7-ram-1.00.a";
device_type = "memory";
reg = <0x0 0x30000>;
};
ps7_ram_1_memory: memory@ffff0000 {
compatible = "xlnx,ps7-ram-1.00.a";
device_type = "memory";
reg = <0xffff0000 0xfe00>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart1;
spi0 = &qspi;
serial1 = &coresight;
ethernet0 = &gem0;
};
cpus_a9: cpus-a9@0 {
compatible = "cpus,cluster";
address-map = <0xf0000000 &amba 0xf0000000 0x10000000>,
<0x00100000 &ps7_ddr_0_memory 0x00100000 0x3ff00000>,
<0x0 &ps7_ram_0_memory 0x0 0x30000>,
<0xffff0000 &ps7_ram_1_memory 0xffff0000 0xfe00>,
<0x43c00000 &mydna_read_v1_0_0 0x43c00000 0x10000>,
<0xf8008000 &ps7_afi_0 0xf8008000 0x1000>,
<0xf8009000 &ps7_afi_1 0xf8009000 0x1000>,
<0xf800a000 &ps7_afi_2 0xf800a000 0x1000>,
<0xf800b000 &ps7_afi_3 0xf800b000 0x1000>,
<0xf8800000 &coresight 0xf8800000 0x100000>,
<0xf8006000 &mc 0xf8006000 0x1000>,
<0xf8007000 &devcfg 0xf8007000 0x100>,
<0xf8004000 &ps7_dma_ns 0xf8004000 0x1000>,
<0xf8003000 &dmac_s 0xf8003000 0x1000>,
<0xe000b000 &gem0 0xe000b000 0x1000>,
<0xf8f00200 &global_timer 0xf8f00200 0x100>,
<0xe000a000 &gpio0 0xe000a000 0x1000>,
<0xf8900000 &ps7_gpv_0 0xf8900000 0x100000>,
<0xf8f01000 &intc 0xf8f01000 0x1000>,
<0xe0200000 &ps7_iop_bus_config_0 0xe0200000 0x1000>,
<0xf8f02000 &L2 0xf8f02000 0x1000>,
<0xf800c000 &ps7_ocmc_0 0xf800c000 0x1000>,
<0xf8891000 &ps7_pmu_0 0xf8891000 0x1000>,
<0xe000d000 &qspi 0xe000d000 0x1000>,
<0xfc000000 &ps7_qspi_linear_0 0xfc000000 0x1000000>,
<0xf8f00000 &ps7_scuc_0 0xf8f00000 0xfd>,
<0xf8f00600 &scutimer 0xf8f00600 0x20>,
<0xf8f00620 &scuwdt 0xf8f00620 0xe0>,
<0xe0100000 &sdhci0 0xe0100000 0x1000>,
<0xf8000000 &slcr 0xf8000000 0x1000>,
<0xe0001000 &uart1 0xe0001000 0x1000>,
<0xf8007100 &adc 0xf8007100 0x21>;
#ranges-address-cells = <0x1>;
#ranges-size-cells = <0x1>;
};
};
2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/system_wrapper.bit
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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/hw/sdt/zynq-7000.dtsi
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011-2022 Xilinx, Inc.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-7000";
model = "Xilinx Zynq";
cpus_a9: cpus-a9@0 {
#address-cells = <1>;
#size-cells = <0>;
ps7_cortexa9_0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
clocks = <&clkc 3>;
clock-latency = <1000>;
cpu0-supply = <&regulator_vccpint>;
operating-points = <
666667 1000000
333334 1000000
>;
};
ps7_cortexa9_1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
clocks = <&clkc 3>;
};
};
fpga_full: fpga-full {
compatible = "fpga-region";
fpga-mgr = <&devcfg>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&intc>;
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
regulator_vccpint: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
};
in-ports {
/* replicator input port */
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port>;
};
};
};
};
amba: axi {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
adc: adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 12>;
};
can0: can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 19>, <&clkc 36>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0 28 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 20>, <&clkc 37>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0 51 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
clocks = <&clkc 42>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>;
};
i2c0: i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 38>;
clock-frequency = <400000>;
interrupt-parent = <&intc>;
interrupts = <0 25 4>;
reg = <0xe0004000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 39>;
clock-frequency = <400000>;
interrupt-parent = <&intc>;
interrupts = <0 48 4>;
reg = <0xe0005000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
intc: interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xF8F01000 0x1000>,
<0xF8F00100 0x100>;
};
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
interrupts = <0 2 4>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
mc: memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocm: sram@fffc0000 {
compatible = "mmio-sram";
reg = <0xfffc0000 0x10000>;
};
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 23>, <&clkc 40>;
clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
interrupt-parent = <&intc>;
};
uart1: serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 24>, <&clkc 41>;
clock-names = "uart_clk", "pclk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
interrupt-parent = <&intc>;
};
spi0: spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 49 4>;
clocks = <&clkc 26>, <&clkc 35>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
qspi: spi@e000d000 {
compatible = "xlnx,zynq-qspi-1.0";
reg = <0xe000d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
clocks = <&clkc 10>, <&clkc 43>;
clock-names = "ref_clk", "pclk";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gem0: ethernet@e000b000 {
compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gem1: ethernet@e000c000 {
compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
smcc: memory-controller@e000e000 {
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
reg = <0xe000e000 0x0001000>;
status = "disabled";
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 18 4>;
nfc0: nand-controller@0,0 {
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
status = "disabled";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
nor0: flash@1,0 {
status = "disabled";
compatible = "cfi-flash";
reg = <1 0 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
sdhci0: mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 21>, <&clkc 32>;
interrupt-parent = <&intc>;
interrupts = <0 24 4>;
reg = <0xe0100000 0x1000>;
};
sdhci1: mmc@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 22>, <&clkc 33>;
interrupt-parent = <&intc>;
interrupts = <0 47 4>;
reg = <0xe0101000 0x1000>;
};
slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
"dma", "usb0_aper", "usb1_aper", "gem0_aper",
"gem1_aper", "sdio0_aper", "sdio1_aper",
"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
"dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
};
rstc: rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <1>;
syscon = <&slcr>;
};
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
};
};
dmac_s: dma-controller@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
/*
* interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
* "dma4", "dma5", "dma6", "dma7";
*/
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>;
#dma-cells = <1>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0 8 4>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
};
efuse: efuse@f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
global_timer: timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <1 11 0x301>;
interrupt-parent = <&intc>;
clocks = <&clkc 4>;
};
ttc0: timer@f8001000 {
interrupt-parent = <&intc>;
interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8001000 0x1000>;
};
ttc1: timer@f8002000 {
interrupt-parent = <&intc>;
interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8002000 0x1000>;
};
scutimer: timer@f8f00600 {
interrupt-parent = <&intc>;
interrupts = <1 13 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
};
scuwdt: scuwatchdog@f8f00620 {
interrupt-parent = <&intc>;
interrupts = <1 14 4>;
compatible = "xlnx,ps7-scuwdt-1.00.a";
reg = <0xf8f00620 0xe0>;
};
usb0: usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 28>;
interrupt-parent = <&intc>;
interrupts = <0 21 4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
};
usb1: usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 29>;
interrupt-parent = <&intc>;
interrupts = <0 44 4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog0: watchdog@f8005000 {
clocks = <&clkc 45>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <&intc>;
interrupts = <0 9 1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
coresight: coresight@f8800000 {
compatible = "xlnx,ps7-coresight-comp-1.00.a";
status = "disabled";
reg = <0xf8800000 0x100000>;
};
etb@f8801000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0xf8801000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
tpiu@f8803000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0xf8803000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
funnel@f8804000 {
compatible = "arm,coresight-static-funnel", "arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
/* funnel output ports */
out-ports {
port {
funnel_out_port: endpoint {
remote-endpoint =
<&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
funnel0_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel0_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel0_in_port2: endpoint {
};
};
/* The other input ports are not connect to anything */
};
};
ptm@f889c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&ps7_cortexa9_0>;
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&ps7_cortexa9_1>;
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel0_in_port1>;
};
};
};
};
};
};