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Migrate to Vitis2023.2 version

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This commit is contained in:
Jeremy Shen
2026-05-26 17:02:52 +08:00
parent 2dca3709ef
commit 3b268f6583
5060 changed files with 1117688 additions and 288060 deletions
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2.FW/CPLD3/tb_RelayConTop.sv
+13 -16
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@@ -43,14 +43,13 @@ module tb_RelayConTop;
reg i_mosi;
reg i_cs;
// Flow control (CPLD3 top uses typo: i_wvaild)
// Flow control (CPLD3 top module uses typo: i_wvaild)
reg i_rready;
reg i_wvaild;
// Status outputs (monitored by testbench)
// Note: CPLD3 uses typo name o_rvaild for the rvalid output
wire o_miso;
wire o_rvaild;
wire o_rvalid;
wire o_wready;
wire o_err;
wire o_con_done;
@@ -61,7 +60,7 @@ module tb_RelayConTop;
//==========================================================================
// DUT instantiation - CPLD3 specific pin names
// Note: CPLD3 top module ports: i_wvaild (typo), o_rvaild (typo), o_con_done (correct)
// Note: CPLD3 top module port: i_wvaild (typo), o_rvalid (correct)
//==========================================================================
RelayConTop DUT (
.i_sys_clk (i_sys_clk),
@@ -70,7 +69,7 @@ module tb_RelayConTop;
.i_mosi (i_mosi),
.i_cs (i_cs),
.o_miso (o_miso),
.o_rvaild (o_rvaild),
.o_rvalid (o_rvalid),
.i_rready (i_rready),
.i_wvaild (i_wvaild),
.o_wready (o_wready),
@@ -337,13 +336,11 @@ module tb_RelayConTop;
tb_assert(o_wready === 1'b1,
"o_wready is HIGH after reset (SPI ready)", "");
// IDENT register: CPLD3 == 1, version 1.0.0
// Bug: uses || (logical OR) instead of | (bitwise OR), result = 24'h000001
// Reg_file.v:37: 24'h800000|| 12'b0001_0000_0000
// IDENT register: CPLD3=bit23, version=1.0.0 = 24'h800100
spi_read(mk_read(7'd0), r_ident);
r_ident = r_ident[23:0];
tb_assert(r_ident === 24'h000001,
"IDENT register returns 24'h000001 (known || bug)", "");
tb_assert(r_ident === 24'h800100,
"IDENT register returns 24'h800100 (CPLD3, v1.0.0)", "");
// PMU_RC should be 4'b1111 after reset (CPLD_Con initializes to 1111)
tb_assert(o_PMU_RC === 4'b1111,
@@ -576,9 +573,9 @@ module tb_RelayConTop;
// 5a. DC_Slot1: PMU_RC = 4'b0001 (select PMU 1)
// DC_Slot1 = PMU mode, V mode, Rload=3, Ch=3
// = (0<<23) | (0<<22) | (3<<17) | (3<<1) | 1 = 24'h006007
// = (0<<23) | (0<<22) | (3<<17) | (3<<1) | 1 = 24'h060007
$display(" DC Slot1: PMU_RC = 0001 (select PMU1)");
spi_write(mk_write(7'd6, 24'h006007));
spi_write(mk_write(7'd6, 24'h060007));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -590,9 +587,9 @@ module tb_RelayConTop;
// 5b. DC_Slot2: PMU_RC = 4'b0010 (select PMU 2)
// DC_Slot2 = PMU mode, V mode, Rload=5, Ch=19
// = (0<<23) | (0<<22) | (5<<17) | (19<<1) | 1 = 24'h00A027
// = (0<<23) | (0<<22) | (5<<17) | (19<<1) | 1 = 24'h0A0027
$display(" DC Slot2: PMU_RC = 0010 (select PMU2)");
spi_write(mk_write(7'd7, 24'h00A027));
spi_write(mk_write(7'd7, 24'h0A0027));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -604,9 +601,9 @@ module tb_RelayConTop;
// 5c. DC_Slot3: PMU_RC = 4'b0100 (select PMU 3)
// DC_Slot3 = PMU mode, V mode, Rload=10, Ch=27
// = (0<<23) | (0<<22) | (10<<17) | (27<<1) | 1 = 24'h014037
// = (0<<23) | (0<<22) | (10<<17) | (27<<1) | 1 = 24'h140037
$display(" DC Slot3: PMU_RC = 0100 (select PMU3)");
spi_write(mk_write(7'd8, 24'h014037));
spi_write(mk_write(7'd8, 24'h140037));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);