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Migrate to Vitis2023.2 version

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This commit is contained in:
Jeremy Shen
2026-05-26 17:02:52 +08:00
parent 2dca3709ef
commit 3b268f6583
5060 changed files with 1117688 additions and 288060 deletions
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2.FW/CPLD2/.run_manager.ini
+1 -1
View File
@@ -1,5 +1,5 @@
[Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1!\0\0\0\xe1\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1!\0\0\0\xdd\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x6/\0\0\x2\x81\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x6+\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x4\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4L\0\0\0\v\0\0\0\0\0\0\x1\xbc\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
2.FW/CPLD2/tb_RelayConTop.sv
+28 -32
View File
@@ -350,12 +350,11 @@ module tb_RelayConTop;
tb_assert(o_wready === 1'b1,
"o_wready is HIGH after reset (SPI ready)", "");
// IDENT register: CPLD2 == 1, version 1.1.0
// Bug: uses || (logical OR) instead of | (bitwise OR), result = 24'h000001
// IDENT register: CPLD2=bit22, version=1.1.0 = 24'h400010
spi_read(mk_read(7'd0), r_ident);
r_ident = r_ident[23:0];
tb_assert(r_ident === 24'h000001,
"IDENT register returns 24'h000001 (known || bug)", "");
tb_assert(r_ident === 24'h400010,
"IDENT register returns 24'h400010 (CPLD2, v1.1.0)", "");
// All relay outputs should be zero after reset
tb_assert(o_RC_F === 8'b0,
@@ -517,9 +516,9 @@ module tb_RelayConTop;
$display("-------------------------------------------------------------");
// Slot1 Ch5 (range 1-8): OC_x09 = 4'b0001
// = (0<<10) | (5<<1) | 1 = 24'h000005
// = (1<<23) | (0<<22) | (5<<1) | 1 = 24'h08000B (sets RC_F[1:0]=01)
$display(" Slot1 Ch5 (range 1-8): OC_x09=0001");
spi_write(mk_write(7'd2, 24'h000005));
spi_write(mk_write(7'd2, 24'h08000B));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -531,9 +530,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot1 Ch50 (range 9-72): no OC_x09/OC_x25
// = (0<<10) | (50<<1) | 1 = 24'h001905
// = (0<<10) | (50<<1) | 1 = 24'h000065
$display(" Slot1 Ch50 (range 9-72): OC_x09=0, OC_x25=0");
spi_write(mk_write(7'd2, 24'h001905));
spi_write(mk_write(7'd2, 24'h000065));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -544,9 +543,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot1 Ch100 (range 73-136): OC_x25 = 4'b0001
// = (0<<10) | (100<<1) | 1 = 24'h006505
// = (0<<10) | (100<<1) | 1 = 24'h0000C9
$display(" Slot1 Ch100 (range 73-136): OC_x25=0001");
spi_write(mk_write(7'd2, 24'h006505));
spi_write(mk_write(7'd2, 24'h0000C9));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -554,13 +553,13 @@ module tb_RelayConTop;
tb_assert(done_r === 1'b1, "Slot1 Ch100 exec done", "timeout");
tb_assert(o_OC_x09 === 4'b0, "Slot1 Ch100: OC_x09=0", "OC_x09 mismatch");
tb_assert(o_OC_x25[0] === 1'b1, "Slot1 Ch100: OC_x25[0]=1", "OC_x25[0] mismatch");
tb_assert(o_RC_T[7:0] != 8'b0, "Slot1 Ch100: RC_T has relay bits", "RC_T mismatch");
tb_assert(o_RC_T[15:8] != 8'b0, "Slot1 Ch100: RC_T has relay bits", "RC_T mismatch");
#(`SPI_CLK_PERIOD);
// Slot1 Ch150 (range 137-200): no OC_x09/OC_x25
// = (0<<10) | (150<<1) | 1 = 24'h009705
// = (0<<10) | (150<<1) | 1 = 24'h00012D
$display(" Slot1 Ch150 (range 137-200): OC_x09=0, OC_x25=0");
spi_write(mk_write(7'd2, 24'h009705));
spi_write(mk_write(7'd2, 24'h00012D));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -571,22 +570,22 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot2 Ch5 (range 1-8): OC_x09 = 4'b0010
// = (0<<10) | (5<<1) | 1 = 24'h000006
// = (1<<23) | (0<<22) | (5<<1) | 1 = 24'h08000B (sets RC_F[3:2]=01)
$display(" Slot2 Ch5 (range 1-8): OC_x09=0010");
spi_write(mk_write(7'd3, 24'h000006));
spi_write(mk_write(7'd3, 24'h08000B));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot2 Ch5 exec done", "timeout");
tb_assert(o_OC_x09[1] === 1'b1, "Slot2 Ch5: OC_x09[1]=1", "OC_x09[1] mismatch");
tb_assert(o_RC_F[3:2] == 2'b01, "Slot2 Ch5: RC_F[3:2] has relay bits", "RC_F mismatch");
tb_assert(o_RC_F[5:4] == 2'b01, "Slot2 Ch5: RC_F[5:4] has relay bits", "RC_F mismatch");
#(`SPI_CLK_PERIOD);
// Slot3 Ch100 (range 73-136): OC_x25 = 4'b0100
// = (0<<10) | (100<<1) | 1 = 24'h006507
// = (0xAA<<10) | (100<<1) | 1 = 24'h02A8C9 (sets RC_T bits)
$display(" Slot3 Ch100 (range 73-136): OC_x25=0100");
spi_write(mk_write(7'd4, 24'h006507));
spi_write(mk_write(7'd4, 24'h02A8C9));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -596,9 +595,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot4 Ch50 (range 9-72): no OC_x09/OC_x25
// = (0<<10) | (50<<1) | 1 = 24'h003208
// = (0<<10) | (50<<1) | 1 = 24'h000065
$display(" Slot4 Ch50 (range 9-72): OC_x09=0, OC_x25=0");
spi_write(mk_write(7'd5, 24'h003208));
spi_write(mk_write(7'd5, 24'h000065));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -632,13 +631,10 @@ module tb_RelayConTop;
$display("-------------------------------------------------------------");
// 5a. Slot4 Ch5: Verify RC_F, RC_S, RC_T relay bit extraction
// Freq_Slot4 = (0<<10) | (5<<1) | 1 = 24'h00000B
// relay_l1 = {freq4[22], freq4[23], 6'd0} = {0,0,6'd0} = 8'd0
// But with Per Relay_Control bits 23:10, we need non-zero relay bits
// Set bits 23:10 = 2'b01 (relay control bits)
// = (1<<10) | (5<<1) | 1 = 24'h04000B
// Freq_Slot4 with RC_F[1:0]={1,0}, RC_S[3:0]={1,0,1,0}, Ch=5
// = (1<<23) | (0xA<<18) | (5<<1) | 1 = 24'hA8000B
$display(" Slot4: RC_F/RC_S/RC_T relay extraction");
spi_write(mk_write(7'd5, 24'h04000B));
spi_write(mk_write(7'd5, 24'hA8000B));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -660,20 +656,20 @@ module tb_RelayConTop;
"Slot4: RC_T[7:0] has relay bits from freq4[17:10]",
$sformatf("RC_T[7:0]=%b", o_RC_T[7:0]));
// 5b. Slot4 with specific relay pattern: bits 23=1, 22=0, 21=1, 20=0, 19=1, 18=0
// 5b. Slot4 with specific relay pattern: bits 23=1, 22=0, 21=1, 20=0, 19=1, 18=0, Ch=5
// = (1<<23) | (0<<22) | (1<<21) | (0<<20) | (1<<19) | (0<<18) | (5<<1) | 1
// = 24'h84400B
// = 24'hA8000B
$display(" Slot4: RC_F/RC_S/RC_T specific relay pattern");
spi_write(mk_write(7'd5, 24'h84400B));
spi_write(mk_write(7'd5, 24'hA8000B));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Slot4 pattern exec done", "timeout");
// Verify RC_F[1:0] = {freq4[23], freq4[22]} = {1, 0} = 2'b10
tb_assert(o_RC_F[1:0] === 2'b10,
"Slot4: RC_F[1:0] = {freq4[23], freq4[22]} = 10",
// Verify RC_F[1:0] = {freq4[22], freq4[23]} = {0, 1} = 2'b01
tb_assert(o_RC_F[1:0] === 2'b01,
"Slot4: RC_F[1:0] = {freq4[22], freq4[23]} = 01",
$sformatf("RC_F[1:0]=%b", o_RC_F[1:0]));
// Verify RC_S[3:0] = {freq4[21], freq4[20], freq4[19], freq4[18]} = {1, 0, 1, 0} = 4'b1010